diff --git a/src/main/scala/vexiiriscv/Generate.scala b/src/main/scala/vexiiriscv/Generate.scala
index 268cd0e6..1a01a246 100644
--- a/src/main/scala/vexiiriscv/Generate.scala
+++ b/src/main/scala/vexiiriscv/Generate.scala
@@ -25,34 +25,7 @@ object Generate extends App {
   sc.addTransformationPhase(new MultiPortWritesSymplifier)
   val report = sc.generateVerilog {
     val plugins = param.plugins()
-    val regions = ArrayBuffer[PmaRegion](
-      new PmaRegionImpl(
-        mapping = SizeMapping(0x80000000l, 0x80000000l),
-        isMain = true,
-        isExecutable = true,
-        transfers = M2sTransfers(
-          get = SizeRange.all,
-          putFull = SizeRange.all,
-        )
-      ),
-      new PmaRegionImpl(
-        mapping = SizeMapping(0x10000000l, 0x10000000l),
-        isMain = false,
-        isExecutable = true,
-        transfers = M2sTransfers(
-          get = SizeRange.all,
-          putFull = SizeRange.all,
-        )
-      )
-    )
-    plugins.foreach {
-      case p: FetchCachelessPlugin => p.regions.load(regions)
-      case p: LsuCachelessPlugin => p.regions.load(regions)
-      case p: FetchL1Plugin => p.regions.load(regions)
-      case p: LsuPlugin => p.ioRegions.load(regions)
-      case p: LsuL1Plugin => p.regions.load(regions)
-      case _ =>
-    }
+    ParamSimple.setPma(plugins)
     VexiiRiscv(plugins)
   }
 }
diff --git a/src/test/scala/vexiiriscv/scratchpad/Synt.scala b/src/test/scala/vexiiriscv/scratchpad/Synt.scala
index 37d03c3b..3e7d95d7 100644
--- a/src/test/scala/vexiiriscv/scratchpad/Synt.scala
+++ b/src/test/scala/vexiiriscv/scratchpad/Synt.scala
@@ -17,7 +17,7 @@ object IntegrationSynthBench extends App{
 
   def add(param : ParamSimple, name : String) = {
     rtls += Rtl(sc.generateVerilog {
-      Rtl.ffIo(VexiiRiscv(param.plugins()).setDefinitionName(if(name.isEmpty) param.getName() else name))
+      Rtl.ffIo(VexiiRiscv(ParamSimple.setPma(param.plugins())).setDefinitionName(if(name.isEmpty) param.getName() else name))
     })
   }
 
@@ -27,75 +27,81 @@ object IntegrationSynthBench extends App{
     add(p, postfix)
   }
 
-//  add(""){ p =>
-//    p.regFileSync = false
-//    p.withMul = false
-//    p.withDiv = false
-//  }
+  add(""){ p =>
+    p.regFileSync = false
+    p.withMul = false
+    p.withDiv = false
+  }
+  add("") { p =>
+    p.regFileSync = false
+    p.withMul = false
+    p.withDiv = false
+    p.withIterativeShift = true
+  }
 //  add("") { p =>
 //    p.regFileSync = false
 //    p.withMul = false
 //    p.withDiv = false
 //    p.withLsuL1 = true
 //  }
-  add("") { p =>
-    import p._
-    decoders = 1
-    lanes = 1
-    regFileSync = false
-    withGShare = false
-    withBtb = false
-    withRas = false
-    withMul = false
-    withDiv = false
-    withLateAlu = false
-    allowBypassFrom = 0
-    relaxedBranch = true
-    relaxedShift = false
-    relaxedSrc = true
-    performanceCounters = 0
-    privParam.withSupervisor = true
-    privParam.withUser = true
-    withMmu = false
-    withRva = true
-    withRvc = false
-    withAlignerBuffer = withRvc
-    withFetchL1 = true
-    withLsuL1 = true
-    xlen = 32
-    lsuL1Sets = 64
-    lsuL1Ways = 1
-    withLsuBypass = false
-  }
-  add("") { p =>
-    import p._
-    decoders = 1
-    lanes = 1
-    regFileSync = false
-    withGShare = true
-    withBtb = true
-    withRas = true
-    withMul = false
-    withDiv = false
-    withLateAlu = false
-    allowBypassFrom = 0
-    relaxedBranch = true
-    relaxedShift = false
-    relaxedSrc = true
-    performanceCounters = 0
-    privParam.withSupervisor = true
-    privParam.withUser = true
-    withMmu = false
-    withRva = true
-    withRvc = false
-    withAlignerBuffer = withRvc
-    withFetchL1 = true
-    withLsuL1 = true
-    xlen = 32
-    lsuL1Sets = 64
-    lsuL1Ways = 1
-    withLsuBypass = false
-  }
+//  add("") { p =>
+//    import p._
+//    decoders = 1
+//    lanes = 1
+//    regFileSync = false
+//    withGShare = false
+//    withBtb = false
+//    withRas = false
+//    withMul = false
+//    withDiv = false
+//    withLateAlu = false
+//    allowBypassFrom = 0
+//    relaxedBranch = true
+//    relaxedShift = false
+//    relaxedSrc = true
+//    performanceCounters = 0
+//    privParam.withSupervisor = true
+//    privParam.withUser = true
+//    withMmu = false
+//    withRva = true
+//    withRvc = false
+//    withAlignerBuffer = withRvc
+//    withFetchL1 = true
+//    withLsuL1 = true
+//    xlen = 32
+//    lsuL1Sets = 64
+//    lsuL1Ways = 1
+//    withLsuBypass = false
+//  }
+//  add("") { p =>
+//    import p._
+//    decoders = 1
+//    lanes = 1
+//    regFileSync = false
+//    withGShare = true
+//    withBtb = true
+//    withRas = true
+//    withMul = false
+//    withDiv = false
+//    withLateAlu = false
+//    allowBypassFrom = 0
+//    relaxedBranch = true
+//    relaxedShift = false
+//    relaxedSrc = true
+//    performanceCounters = 0
+//    privParam.withSupervisor = true
+//    privParam.withUser = true
+//    withMmu = false
+//    withRva = true
+//    withRvc = false
+//    withAlignerBuffer = withRvc
+//    withFetchL1 = true
+//    withLsuL1 = true
+//    xlen = 32
+//    lsuL1Sets = 64
+//    lsuL1Ways = 1
+//    withLsuBypass = false
+//  }
 //  add("") { p =>
 //    p.regFileSync = false
 //    p.withMul = false
@@ -281,4 +287,11 @@ Artix 7 -> 177 Mhz 2091 LUT 1590 FF
 rv32iasu_d1_l1_rfa_fl1_lsul1xW1xS64_bp0_btb_ras_gshare_rsrc ->
 Artix 7 -> 87 Mhz 2169 LUT 1810 FF
 Artix 7 -> 119 Mhz 2333 LUT 1824 FF
+
+rv32i_d1_l1_rfa_rsrc ->
+Artix 7 -> 90 Mhz 1153 LUT 933 FF
+Artix 7 -> 193 Mhz 1236 LUT 935 FF
+rv32i_d1_l1_rfa_rsrc_isft ->
+Artix 7 -> 90 Mhz 1108 LUT 972 FF
+Artix 7 -> 187 Mhz 1218 LUT 974 FF
  */
\ No newline at end of file