Got dual core to run linux in litex

src/main/scala/vexiiriscv/execute/lsu/LsuCachelessBridge.scala

@@ -64,13 +64,14 @@ class LsuCachelessBusToTilelink(up : LsuCachelessBus, hashWidth : Int) extends A
 class LsuCachelessTileLinkPlugin(node : bus.tilelink.fabric.Node, hashWidth : Int = 8) extends FiberPlugin {
   val logic = during build new Area{
     val lsucp = host[LsuCachelessPlugin]
+
+    node.m2s.forceParameters(lsucp.busParam.toTilelinkM2s(LsuCachelessTileLinkPlugin.this))
+    node.s2m.supported.load(S2mSupport.none())
+
     lsucp.logic.bus.setAsDirectionLess()
 
     val bridge = new LsuCachelessBusToTilelink(lsucp.logic.bus, hashWidth)
     master(bridge.down)
-
-    node.m2s.forceParameters(bridge.m2sParam)
-    node.s2m.supported.load(S2mSupport.none())
     node.bus.component.rework(node.bus << bridge.down)
   }
 }
@@ -80,13 +81,13 @@ class LsuCachelessTileLinkPlugin(node : bus.tilelink.fabric.Node, hashWidth : In
 class LsuTileLinkPlugin(node : bus.tilelink.fabric.Node, hashWidth : Int = 8) extends FiberPlugin {
   val logic = during build new Area{
     val lsucp = host[LsuPlugin]
-    lsucp.logic.bus.setAsDirectionLess()
 
+    node.m2s.forceParameters(lsucp.busParam.toTilelinkM2s(LsuTileLinkPlugin.this))
+    node.s2m.supported.load(S2mSupport.none())
+
+    lsucp.logic.bus.setAsDirectionLess()
     val bridge = new LsuCachelessBusToTilelink(lsucp.logic.bus, hashWidth)
     master(bridge.down)
-
-    node.m2s.forceParameters(bridge.m2sParam)
-    node.s2m.supported.load(S2mSupport.none())
     node.bus.component.rework(node.bus << bridge.down)
   }
 }

src/main/scala/vexiiriscv/execute/lsu/LsuCachelessPlugin.scala

@@ -39,6 +39,16 @@ class LsuCachelessPlugin(var layer : LaneLayer,
   override def accessWake: Bits = B(0)
   override def getLsuCachelessBus(): LsuCachelessBus = logic.bus
 
+  def bufferSize = joinAt - forkAt + 1
+  def busParam = LsuCachelessBusParam(
+    addressWidth = Global.PHYSICAL_WIDTH,
+    dataWidth = Riscv.LSLEN,
+    hartIdWidth = Global.HART_ID_WIDTH,
+    uopIdWidth = Decode.UOP_ID_WIDTH,
+    withAmo = withAmo,
+    pendingMax = bufferSize
+  )
+
   val logic = during setup new Area{
     val elp = host.find[ExecuteLanePlugin](_.laneName == layer.laneName)
     val ifp = host.find[IntFormatPlugin](_.laneName == layer.laneName)
@@ -102,16 +112,7 @@ class LsuCachelessPlugin(var layer : LaneLayer,
     val forkCtrl = elp.execute(forkAt)
     val joinCtrl = elp.execute(joinAt)
     val wbCtrl = elp.execute(wbAt)
-    val bufferSize = joinAt-forkAt+1
-
-    val busParam = LsuCachelessBusParam(
-      addressWidth = Global.PHYSICAL_WIDTH,
-      dataWidth = Riscv.LSLEN,
-      hartIdWidth = Global.HART_ID_WIDTH,
-      uopIdWidth = Decode.UOP_ID_WIDTH,
-      withAmo = withAmo,
-      pendingMax = bufferSize
-    )
+
     val bus = master(LsuCachelessBus(busParam)).simPublic()
 
     accessRetainer.await()

src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala

@@ -1,7 +1,7 @@
 package vexiiriscv.execute.lsu
 
 import spinal.core._
-import spinal.core.fiber.{Handle, Retainer}
+import spinal.core.fiber.{Handle, Retainer, soon}
 import spinal.core.sim.SimDataPimper
 import spinal.lib._
 import spinal.lib.misc.Plru
@@ -136,6 +136,7 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
     LINE_BYTES.set(lineSize)
     lockPort.set(LockPort())
     ackUnlock.set(False)
+    WRITEBACK_BUSY.soon()
 
     elaborationRetainer.await()
 

src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala

@@ -56,6 +56,15 @@ class LsuPlugin(var layer : LaneLayer,
 
   override def getLsuCachelessBus(): LsuCachelessBus = logic.bus
 
+  def busParam = LsuCachelessBusParam(
+    addressWidth = Global.PHYSICAL_WIDTH,
+    dataWidth = Riscv.LSLEN,
+    hartIdWidth = Global.HART_ID_WIDTH,
+    uopIdWidth = Decode.UOP_ID_WIDTH,
+    withAmo = false, //TODO
+    pendingMax = 1
+  )
+
   val tagWidth = 6
   val SB_PTR = Payload(UInt(log2Up(storeBufferOps) + 1 bits))
   case class StoreBufferPush() extends Bundle {
@@ -128,14 +137,6 @@ class LsuPlugin(var layer : LaneLayer,
       SIZE := Decode.UOP(13 downto 12).asUInt
     }
 
-    val busParam = LsuCachelessBusParam(
-      addressWidth = Global.PHYSICAL_WIDTH,
-      dataWidth = Riscv.LSLEN,
-      hartIdWidth = Global.HART_ID_WIDTH,
-      uopIdWidth = Decode.UOP_ID_WIDTH,
-      withAmo = false, //TODO
-      pendingMax = 1
-    )
     val bus = master(LsuCachelessBus(busParam)).simPublic()
 
     accessRetainer.await()

src/main/scala/vexiiriscv/fetch/FetchL1Bridge.scala

@@ -7,14 +7,16 @@ import spinal.lib.bus.tilelink.{DebugId, S2mSupport}
 import spinal.lib.misc.plugin.FiberPlugin
 
 
-class FetchFetchL1TileLinkPlugin(node : bus.tilelink.fabric.Node) extends FiberPlugin {
+class FetchL1TileLinkPlugin(node : bus.tilelink.fabric.Node) extends FiberPlugin {
   val logic = during build new Area{
     val fcp = host[FetchL1Plugin]
-    fcp.logic.bus.setAsDirectionLess()
-    val down = fcp.logic.bus.toTilelink()
-    master(down)
-    node.m2s.forceParameters(down.p.node.m)
+
+    val memParam = fcp.getBusParameter()
+    node.m2s.forceParameters(memParam.toTileLinkM2sParameters(FetchL1TileLinkPlugin.this))
     node.s2m.supported.load(S2mSupport.none())
+
+    fcp.logic.bus.setAsDirectionLess()
+    val down = master(fcp.logic.bus.toTilelink())
     node.bus.component.rework(node.bus << down)
   }
 }

src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala

@@ -17,7 +17,7 @@ import spinal.lib.system.tag.{MemoryConnection, PMA, PmaRegion}
 import spinal.sim.{Signal, SimManagerContext}
 import vexiiriscv.{ParamSimple, VexiiRiscv}
 import vexiiriscv.execute.lsu.{LsuCachelessPlugin, LsuCachelessTileLinkPlugin, LsuL1Plugin, LsuL1TileLinkPlugin, LsuPlugin, LsuTileLinkPlugin}
-import vexiiriscv.fetch.{FetchCachelessPlugin, FetchCachelessTileLinkPlugin, FetchFetchL1TileLinkPlugin, FetchL1Plugin}
+import vexiiriscv.fetch.{FetchCachelessPlugin, FetchCachelessTileLinkPlugin, FetchL1TileLinkPlugin, FetchL1Plugin}
 import vexiiriscv.memory.AddressTranslationService
 import vexiiriscv.misc.PrivilegedPlugin
 import vexiiriscv.riscv.Riscv
@@ -67,7 +67,7 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area with
   // Add the plugins to bridge the CPU toward Tilelink
   plugins.foreach {
     case p: FetchCachelessPlugin => plugins += new FetchCachelessTileLinkPlugin(iBus)
-    case p: FetchL1Plugin => plugins += new FetchFetchL1TileLinkPlugin(iBus)
+    case p: FetchL1Plugin => plugins += new FetchL1TileLinkPlugin(iBus)
     case p: LsuCachelessPlugin => plugins += new LsuCachelessTileLinkPlugin(dBus)
     case p: LsuPlugin => plugins += new LsuTileLinkPlugin(dBus)
     case p: LsuL1Plugin => plugins += new LsuL1TileLinkPlugin(lsuL1Bus)
@@ -78,7 +78,6 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area with
   val logic = Fiber setup new Area{
     val core = VexiiRiscv(plugins)
     Fiber.awaitBuild()
-
     def getRegion(node : Node) = MemoryConnection.getMemoryTransfers(node).asInstanceOf[ArrayBuffer[PmaRegion]]
     plugins.foreach {
       case p: FetchCachelessPlugin => p.regions.load(getRegion(iBus))

src/main/scala/vexiiriscv/soc/litex/Soc.scala

@@ -51,18 +51,18 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
 
   val system = systemCd on new AreaRoot {
     val mainDataWidth = vexiiParam.memDataWidth
-
-    val withCoherency = false
-    val vexiis = for (hartId <- 0 to 0) yield new TilelinkVexiiRiscvFiber(vexiiParam.plugins(hartId))
+    val withCoherency = vexiiParam.lsuL1Coherency
+    val vexiis = for (hartId <- 0 until cpuCount) yield new TilelinkVexiiRiscvFiber(vexiiParam.plugins(hartId))
     for (vexii <- vexiis) {
+      vexii.dBus.setDownConnection(a = StreamPipe.NONE, d = StreamPipe.M2S, b = StreamPipe.NONE, c = StreamPipe.NONE, e = StreamPipe.NONE)
 //      nax.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S, b = StreamPipe.HALF, c = StreamPipe.FULL, e = StreamPipe.HALF)
 //      nax.iBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S)
 //      nax.pBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.HALF)
     }
 
-    val perfBus, ioBus = fabric.Node()
+    val cBus, ioBus = fabric.Node()
     for (vexii <- vexiis) {
-      perfBus << List(vexii.iBus, vexiiParam.fetchL1Enable.mux(vexii.lsuL1Bus, vexii.dBus))
+      cBus << List(vexii.iBus, vexiiParam.fetchL1Enable.mux(vexii.lsuL1Bus, vexii.dBus))
       if(vexiiParam.fetchL1Enable) ioBus << List(vexii.dBus)
     }
 
@@ -96,30 +96,29 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
 
     assert(!(!withCoherency && withL2))
 
-    var nonCoherent: Node = null
-
+    var perfBus: Node = null
     val direct = (!withCoherency) generate new Area{
-      nonCoherent = perfBus
+      perfBus = cBus
     }
 
-//    val hub = (withCoherency && !withL2) generate new Area {
-//      val hub = new HubFiber()
-//      hub.up << memFilter.down
-//      hub.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL)
-//      hub.down.forceDataWidth(mainDataWidth)
-//      nonCoherent = hub.down
-//    }
+    val hub = (withCoherency && !withL2) generate new Area {
+      val hub = new HubFiber()
+      hub.up << cBus
+      hub.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL)
+      hub.down.forceDataWidth(mainDataWidth)
+      perfBus = hub.down
+    }
 
-//    val l2 = (withCoherency && withL2)  generate new Area {
-//      val cache = new CacheFiber()
-//      cache.parameter.cacheWays = l2Ways
-//      cache.parameter.cacheBytes = l2Bytes
-//      cache.up << memFilter.down
-//      cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL, d = StreamPipe.FULL)
-//      cache.down.setDownConnection(d = StreamPipe.S2M)
-//      cache.down.forceDataWidth(mainDataWidth)
-//      nonCoherent = cache.down
-//    }
+    val l2 = (withCoherency && withL2) generate new Area {
+      val cache = new CacheFiber()
+      cache.parameter.cacheWays = l2Ways
+      cache.parameter.cacheBytes = l2Bytes
+      cache.up << cBus
+      cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL, d = StreamPipe.FULL)
+      cache.down.setDownConnection(d = StreamPipe.S2M)
+      cache.down.forceDataWidth(mainDataWidth)
+      perfBus = cache.down
+    }
 
     val memRegions = regions.filter(e => e.onMemory && e.isCachable)
     val axiLiteRegions = regions.filter(e => e.onPeripheral)
@@ -129,7 +128,7 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
     if (withMem) {
       toAxi4.up.forceDataWidth(litedramWidth)
       regions.filter(_.onMemory).foreach(r =>
-        toAxi4.up at r.mapping of nonCoherent
+        toAxi4.up at r.mapping of perfBus
       )
       toAxi4.down.addTag(PMA.MAIN)
       toAxi4.down.addTag(PMA.EXECUTABLE)
@@ -143,7 +142,7 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
 
     val peripheral = new Area {
       val bus = Node()
-      bus << (nonCoherent, ioBus)
+      bus << (perfBus, ioBus)
       bus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.HALF)
       bus.forceDataWidth(32)
 
@@ -270,7 +269,7 @@ object SocGen extends App{
   vexiiParam.lsuL1Enable = true
   vexiiParam.privParam.withRdTime = true
 
-  assert(new scopt.OptionParser[Unit]("NaxRiscv") {
+  assert(new scopt.OptionParser[Unit]("VexiiRiscv") {
     help("help").text("prints this usage text")
     vexiiParam.addOptions(this)
     opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
@@ -290,6 +289,8 @@ object SocGen extends App{
     }
   }.parse(args, Unit).nonEmpty)
 
+  vexiiParam.lsuL1Coherency = cpuCount > 1 || withDma
+
   val spinalConfig = SpinalConfig(inlineRom = true, targetDirectory = netlistDirectory)
   spinalConfig.addTransformationPhase(new MultiPortWritesSymplifier)
   spinalConfig.addStandardMemBlackboxing(blackboxByteEnables)
@@ -383,7 +384,9 @@ python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv  --ve
 python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv  --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --div-ipc --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-mem-data-width-min=64  --with-btb --with-ras --with-gshare --relaxed-branch --regfile-async --lsu-l1-store-buffer-slots=2 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-lsu-bypass --decoders=2 --lanes=2" --with-jtag-tap  --build --load
 
 
+
 python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv  --vexii-args="--debug-privileged" --with-jtag-tap --build --load
+export HART_COUNT=2
 /media/data2/proj/upstream/openocd_riscv_up/src/openocd -f ft2232h_breakout.cfg -f vexiiriscv_jtag.tcl
 
 python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv  --vexii-args="--debug-privileged" --with-jtag-instruction --build --load
@@ -392,4 +395,36 @@ openocd -f digilent_nexys_video.tcl -f vexiiriscv_jtag_tunneled.tcl
 
 python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv  --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4  --with-btb --with-ras --with-gshare" --with-jtag-tap  --load
 
+
+
+
+//linux ++ dual core
+make O=build/full  BR2_EXTERNAL=../config litex_vexriscv_full_defconfig
+(cd build/full/ && make -j20)
+
+litex_sim --cpu-type=vexiiriscv  --with-sdram --sdram-data-width=64 --bus-standard axi-lite --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --div-ipc --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-mem-data-width-min=64  --with-btb --with-ras --with-gshare --relaxed-branch --regfile-async --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-lsu-bypass" --cpu-count=2  --with-jtag-tap --sdram-init /media/data2/proj/vexii/litex/buildroot/rv32ima/images/boot.json
+python3 -m litex_boards.targets.digilent_nexys_video  --soc-json build/digilent_nexys_video/csr.json --cpu-type=vexiiriscv  --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --div-ipc --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-mem-data-width-min=64  --with-btb --with-ras --with-gshare --relaxed-branch --regfile-async --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-lsu-bypass" --cpu-count=2 --with-jtag-tap  --with-video-framebuffer --with-spi-sdcard --with-ethernet  --build --load
+--lsu-l1-store-buffer-slots=2 --lsu-l1-store-buffer-ops=32
+
+export HART_COUNT=2
+/media/data2/proj/upstream/openocd_riscv_up/src/openocd -f ft2232h_breakout.cfg -f vexiiriscv_jtag.tcl
+
+load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images_full/Image 0x40000000
+load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images_full/linux_2c.dtb 0x40ef0000
+load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images_full/rootfs.cpio 0x41000000
+load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000
+targets riscv.cpu.1; resume
+targets riscv.cpu.0; resume
+
+boot 0x40f00000
+
+udhcpc
+cat >> /etc/X11/xorg.conf << EOF
+> Section "Module"
+>   Load "fb"
+>   Load "shadow"
+>   Load "fbdevhw"
+> EndSection
+> EOF
+
  */