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Merge pull request #8 from bitpasta/dev_divradix2
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,133 @@ | ||
| // SPDX-FileCopyrightText: 2023 "Everybody" | ||
| // | ||
| // SPDX-License-Identifier: MIT | ||
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| package vexiiriscv.misc | ||
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| import spinal.core._ | ||
| import spinal.lib._ | ||
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| case class DivCmd(width : Int) extends Bundle{ | ||
| val a,b = UInt(width bits) | ||
| } | ||
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| case class DivRsp(width : Int) extends Bundle{ | ||
| val result = UInt(width bits) | ||
| val remain = UInt(width bits) | ||
| } | ||
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| case class DivIo(width : Int) extends Bundle{ | ||
| val flush = in Bool() | ||
| val cmd = slave Stream (DivCmd(width)) | ||
| val rsp = master Stream (DivRsp(width)) | ||
| } | ||
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| class DivComp(val width : Int) extends Component{ | ||
| val io = DivIo(width) | ||
| } | ||
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| class DivRadix(width : Int, radix : Int) extends DivComp(width) { | ||
| val radixBits = radix match { | ||
| case 2 => 1 | ||
| case 4 => 2 | ||
| } | ||
| assert(width % radixBits == 0) | ||
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| val iterations = width/radixBits | ||
| val counter = Reg(UInt(log2Up(iterations) bits)) | ||
| val busy = RegInit(False) clearWhen(io.rsp.fire) | ||
| val done = RegInit(False) setWhen(busy && counter === iterations-1) clearWhen(io.rsp.fire) | ||
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| val shifter = Reg(UInt(width bits)) | ||
| val numerator = Reg(UInt(width bits)) | ||
| val result = Reg(UInt(width bits)) | ||
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| val div1, div3 = Reg(UInt(width+radixBits bits)) | ||
| val div2 = div1 |<< 1 | ||
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| val shifted = shifter @@ numerator.takeHigh(radixBits).asUInt | ||
| val sub1 = shifted -^ div1 | ||
| val sub2 = (radix >= 4) generate shifted -^ div2 | ||
| val sub3 = (radix >= 4) generate shifted -^ div3 | ||
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| io.rsp.valid := done | ||
| io.rsp.result := result.resized | ||
| io.rsp.remain := shifter.resized | ||
| io.cmd.ready := !busy | ||
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| when(!done){ | ||
| counter := counter + 1 | ||
| val sel = CombInit(shifted) | ||
| result := result |<< radixBits | ||
| when(!sub1.msb){ | ||
| sel := sub1.resized | ||
| result(radixBits-1 downto 0) := 1 | ||
| } | ||
| if(radix >= 4) { | ||
| when(!sub2.msb) { | ||
| sel := sub2.resized | ||
| result(radixBits-1 downto 0) := 2 | ||
| } | ||
| when(!sub3.msb) { | ||
| sel := sub3.resized | ||
| result(radixBits-1 downto 0) := 3 | ||
| } | ||
| } | ||
| shifter := sel.resized | ||
| numerator := numerator |<< radixBits | ||
| } | ||
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| val sliceCount = 3 | ||
| val shiftWidth = width/(sliceCount+1) | ||
| val slices = io.cmd.a.subdivideIn(sliceCount+1 slices).tail | ||
| val slicesZero = slices.map(_ === 0) | ||
| val shiftSel = B((0 until sliceCount).map(i => slicesZero.drop(i).andR)) | ||
| val sel = OHToUInt(OHMasking.firstV2(True ## shiftSel)) | ||
| when(!busy){ | ||
| busy := io.cmd.valid | ||
| div1 := io.cmd.b.resized | ||
| if(radix >= 4) div3 := io.cmd.b +^ (io.cmd.b << 1) | ||
| result := (default -> (io.cmd.b === 0)) | ||
| switch(sel) { | ||
| for (i <- sliceCount downto 0) is(i) { | ||
| val shift = width - ((i + 1) * shiftWidth) | ||
| counter := shift / radixBits | ||
| shifter := U(io.cmd.a.takeHigh(shift)).resized | ||
| numerator := io.cmd.a |<< shift | ||
| } | ||
| } | ||
| } | ||
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| when(io.flush){ | ||
| done := False | ||
| busy := False | ||
| } | ||
| } | ||
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| object DivRadix4Tester extends App{ | ||
| import spinal.core.sim._ | ||
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| for(radix <- List(2, 4)){ | ||
| SimConfig.compile(new DivRadix(16, radix)).doSim(seed = 52){ dut => | ||
| dut.clockDomain.forkStimulus(10) | ||
| dut.io.cmd.valid #= false | ||
| dut.io.rsp.ready #= true | ||
| dut.clockDomain.waitSampling() | ||
| for (i <- 0 until 100000) { | ||
| dut.io.cmd.valid #= true | ||
| val a = dut.io.cmd.a.randomizedInt() | ||
| val b = dut.io.cmd.b.randomizedInt() | ||
| dut.io.cmd.a #= a | ||
| dut.io.cmd.b #= b | ||
| dut.clockDomain.waitSampling() | ||
| dut.io.cmd.valid #= false | ||
| dut.clockDomain.waitSamplingWhere(dut.io.rsp.valid.toBoolean) | ||
| assert(dut.io.rsp.result.toInt == a / b) | ||
| assert(dut.io.rsp.remain.toInt == a % b) | ||
| dut.clockDomain.waitSampling() | ||
| } | ||
| simSuccess() | ||
| } | ||
| } | ||
| } |
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