diff --git a/src/main/scala/vexiiriscv/fetch/FetchL1Bridge.scala b/src/main/scala/vexiiriscv/fetch/FetchL1Bridge.scala
new file mode 100644
index 00000000..c7d63f3a
--- /dev/null
+++ b/src/main/scala/vexiiriscv/fetch/FetchL1Bridge.scala
@@ -0,0 +1,20 @@
+package vexiiriscv.fetch
+
+import spinal.core._
+import spinal.lib._
+import spinal.lib.bus.tilelink
+import spinal.lib.bus.tilelink.{DebugId, S2mSupport}
+import spinal.lib.misc.plugin.FiberPlugin
+
+
+class FetchFetchL1TileLinkPlugin(node : bus.tilelink.fabric.Node) extends FiberPlugin {
+  val logic = during build new Area{
+    val fcp = host[FetchL1Plugin]
+    fcp.logic.bus.setAsDirectionLess()
+    val down = fcp.logic.bus.toTilelink()
+    master(down)
+    node.m2s.forceParameters(down.p.node.m)
+    node.s2m.supported.load(S2mSupport.none())
+    node.bus.component.rework(node.bus << down)
+  }
+}
diff --git a/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala b/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala
index 0072f35c..4e3aef7c 100644
--- a/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala
+++ b/src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala
@@ -19,8 +19,8 @@ import spinal.lib.sim.SparseMemory
 import spinal.lib.system.tag.{MemoryConnection, PMA, PmaRegion}
 import spinal.sim.{Signal, SimManagerContext}
 import vexiiriscv.{ParamSimple, VexiiRiscv}
-import vexiiriscv.execute.lsu.{LsuCachelessPlugin, LsuCachelessTileLinkPlugin}
-import vexiiriscv.fetch.{FetchCachelessPlugin, FetchCachelessTileLinkPlugin}
+import vexiiriscv.execute.lsu.{LsuCachelessPlugin, LsuCachelessTileLinkPlugin, LsuL1Plugin}
+import vexiiriscv.fetch.{FetchCachelessPlugin, FetchCachelessTileLinkPlugin, FetchFetchL1TileLinkPlugin, FetchL1Plugin}
 import vexiiriscv.memory.AddressTranslationService
 import vexiiriscv.misc.PrivilegedPlugin
 
@@ -64,6 +64,7 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area{
   // Add the plugins to bridge the CPU toward Tilelink
   plugins.foreach {
     case p: FetchCachelessPlugin => plugins += new FetchCachelessTileLinkPlugin(iBus)
+    case p: FetchL1Plugin => plugins += new FetchFetchL1TileLinkPlugin(iBus)
     case p: LsuCachelessPlugin => plugins += new LsuCachelessTileLinkPlugin(dBus)
     case _ =>
   }
@@ -73,9 +74,11 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area{
     val core = VexiiRiscv(plugins)
     Fiber.awaitBuild()
 
+    def getRegion(node : Node) = MemoryConnection.getMemoryTransfers(node).asInstanceOf[ArrayBuffer[PmaRegion]]
     plugins.foreach {
-      case p: FetchCachelessPlugin => p.regions.load(MemoryConnection.getMemoryTransfers(iBus).asInstanceOf[ArrayBuffer[PmaRegion]])
-      case p: LsuCachelessPlugin => p.regions.load(MemoryConnection.getMemoryTransfers(dBus).asInstanceOf[ArrayBuffer[PmaRegion]])
+      case p: FetchCachelessPlugin => p.regions.load(getRegion(iBus))
+      case p: FetchL1Plugin => p.regions.load(getRegion(iBus))
+      case p: LsuCachelessPlugin => p.regions.load(getRegion(dBus))
       case _ =>
     }