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Merge branch 'litex' into dev
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@Dolu1990
Dolu1990 committed Mar 28, 2024
2 parents 54e8b3a + a71baef commit b212196
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Showing 16 changed files with 655 additions and 230 deletions.
1 change: 1 addition & 0 deletions build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ def rootGen() = {
)),
scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/ext/SpinalHDL/idslplugin/target/scala-2.12/spinalhdl-idsl-plugin_2.12-$spinalVersion.jar")}",
scalacOptions += s"-Xplugin-require:idsl-plugin",
scalacOptions += "-language:reflectiveCalls",
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.2.17",
"org.yaml" % "snakeyaml" % "1.8",
Expand Down
2 changes: 1 addition & 1 deletion ext/SpinalHDL
Submodule SpinalHDL updated 2 files
+1 −0 build.sbt
+2 −2 lib/src/main/scala/spinal/lib/bus/tilelink/AxiLite4Bridge.scala
66 changes: 65 additions & 1 deletion src/main/scala/vexiiriscv/Generate.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ import vexiiriscv.decode.{Decode, DecodePipelinePlugin}
import vexiiriscv.execute.{CsrRamPlugin, ExecuteLanePlugin, SrcPlugin}
import vexiiriscv.execute.lsu._
import vexiiriscv.fetch._
import vexiiriscv.prediction.BtbPlugin
import vexiiriscv.regfile.RegFilePlugin

import scala.collection.mutable.ArrayBuffer
Expand Down Expand Up @@ -50,6 +51,10 @@ object GeneratTweeked extends App {
param.relaxedBranch = true
param.lsuStoreBufferSlots = 2
param.lsuStoreBufferOps = 32
param.withBtb = true
param.withGShare = true
param.withRas = true


val report = sc.generateVerilog {
val plugins = param.plugins()
Expand All @@ -60,10 +65,69 @@ object GeneratTweeked extends App {
report.toplevel.database.on{
// val from = report.toplevel.host[ExecuteLanePlugin].execute(0).down(Decode.UOP)
// val from = report.toplevel.host[LsuPlugin].logic.storeBuffer.slots(0).tag
val from = report.toplevel.host[DecodePipelinePlugin].ctrl(1).lane(0).up(Decode.INSTRUCTION)
// val from = report.toplevel.host[DecodePipelinePlugin].ctrl(1).lane(0).up(Decode.INSTRUCTION)
// val to = report.toplevel.host[FetchL1Plugin].logic.banks.head.read.cmd.valid
val from = report.toplevel.host[BtbPlugin].logic.readPort.rsp.head.hash
val to = report.toplevel.host[FetchL1Plugin].logic.banks.head.read.cmd.valid
// val to = report.toplevel.host[CsrRamPlugin].logic.writeLogic.port.data
println(PathTracer.impl(from, to).report())
}
}



/*
- Node((toplevel/FetchL1Plugin_logic_banks_0_read_cmd_valid : Bool))
- Node((toplevel/fetch_logic_ctrls_0_up_isReady : Bool))
- Node((toplevel/fetch_logic_ctrls_0_up_ready : Bool))
- Node((toplevel/when_CtrlLink_l151 : Bool))
- Node(| Bits)
- Node(Bits ## Bits)
- Node(Bits ## Bits)
- Node(Bits -> Bits)
- Node((toplevel/fetch_logic_ctrls_0_haltRequest_BtbPlugin_l165 : Bool))
- Node(Bool && Bool)
- Node(UInt === UInt)
- Node((toplevel/BtbPlugin_logic_readPort_cmd_payload : UInt[9 bits]))
- Node(resize(UInt,9 bits))
- Node((UInt >> Int)[30 bits])
- Node((toplevel/fetch_logic_ctrls_0_down_Fetch_WORD_PC : UInt[32 bits]))
- Node((toplevel/fetch_logic_ctrls_0_up_Fetch_WORD_PC : UInt[32 bits]))
- Node((toplevel/PcPlugin_logic_harts_0_output_payload : UInt[32 bits]))
- Node((toplevel/PcPlugin_logic_harts_0_aggregator_target_1 : UInt[32 bits]))
- Node((toplevel/PcPlugin_logic_harts_0_aggregator_target : UInt[32 bits]))
- Node((Bits -> UInt of 32 bits))
- Node((Bits | Bits)[32 bits])
- Node((Bits | Bits)[32 bits])
- Node((Bool ? Bits | Bits)[32 bits])
- Node(Bits(Int))
- Node((toplevel/PcPlugin_logic_harts_0_aggregator_oh : Bits[4 bits]))
- Node((toplevel/_zz_PcPlugin_logic_harts_0_aggregator_oh_4 : Bits[4 bits]))
- Node(Bool && Bool)
- Node((toplevel/_zz_PcPlugin_logic_harts_0_aggregator_oh_1 : Bool))
- Node(Bits(Int))
- Node((toplevel/_zz_PcPlugin_logic_harts_0_aggregator_oh : Bits[4 bits]))
- Node(Bits ## Bits)
- Node(Bits ## Bits)
- Node(Bits -> Bits)
- Node((toplevel/PcPlugin_logic_harts_0_aggregator_valids_2 : Bool))
- Node(Bool && Bool)
- Node(Bool && Bool)
- Node((toplevel/BtbPlugin_logic_pcPort_valid : Bool))
- Node((toplevel/BtbPlugin_logic_applyIt_doIt : Bool))
- Node(Bool && Bool)
- Node((toplevel/BtbPlugin_logic_applyIt_needIt : Bool))
- Node(Bool && Bool)
- Node(| Bits)
- Node((toplevel/BtbPlugin_logic_applyIt_chunksTakenOh : Bits[1 bits]))
- Node((Bits & Bits)[1 bits])
- Node((toplevel/BtbPlugin_logic_applyIt_chunksMask : Bits[1 bits]))
- Node(Bits -> Bits)
- Node(Bool && Bool)
- Node((toplevel/fetch_logic_ctrls_1_down_BtbPlugin_logic_chunksLogic_0_hitCalc_HIT : Bool))
- Node(Bool && Bool)
- Node(UInt === UInt)
- Node((toplevel/fetch_logic_ctrls_1_down_BtbPlugin_logic_chunksLogic_0_readRsp_ENTRY_hash : UInt[16 bits]))
- Node((toplevel/BtbPlugin_logic_readPort_rsp_0_hash : UInt[16 bits]))
- Node((toplevel/BtbPlugin_logic_readPort_rsp_0_hash : UInt[16 bits]))
*/
104 changes: 62 additions & 42 deletions src/main/scala/vexiiriscv/Param.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ object ParamSimple{
isExecutable = true,
transfers = M2sTransfers(
get = SizeRange.all,
putFull = SizeRange.all,
putFull = SizeRange.all
)
),
new PmaRegionImpl(
Expand All @@ -39,7 +39,7 @@ object ParamSimple{
isExecutable = true,
transfers = M2sTransfers(
get = SizeRange.all,
putFull = SizeRange.all,
putFull = SizeRange.all
)
)
)
Expand Down Expand Up @@ -90,14 +90,15 @@ class ParamSimple(){
var fetchL1Sets = 64
var fetchL1Ways = 1
var fetchL1ReducedBank = false
var fetchL1MemDataWidthMin = 32
var fetchMemDataWidthMin = 32
var lsuStoreBufferSlots = 0
var lsuStoreBufferOps = 0
var lsuL1Enable = false
var lsuL1Sets = 64
var lsuL1Ways = 1
var LsuL1RefillCount = 1
var lsuL1RefillCount = 1
var lsuL1WritebackCount = 1
var lsuMemDataWidthMin = 32
var withLsuBypass = false
var withIterativeShift = false
var divRadix = 2
Expand All @@ -111,6 +112,10 @@ class ParamSimple(){
var embeddedJtagCd: ClockDomain = null
var embeddedJtagNoTapCd: ClockDomain = null

def fetchMemDataWidth = 32*decoders max fetchMemDataWidthMin
def lsuMemDataWidth = xlen max lsuMemDataWidthMin
def memDataWidth = List(fetchMemDataWidth, lsuMemDataWidth).max

// Debug modifiers
val debugParam = sys.env.getOrElse("VEXIIRISCV_DEBUG_PARAM", "0").toInt.toBoolean
if(debugParam) {
Expand All @@ -119,41 +124,41 @@ class ParamSimple(){
regFileSync = false
allowBypassFrom = 0

// withGShare = true
// withBtb = true
// withRas = true
// relaxedBranch = true // !!
// relaxedBtb = true // !!
// fetchL1Enable = true
// fetchL1Sets = 64
// fetchL1Ways = 4
//fetchL1ReducedBank = true
//fetchL1MemDataWidthMin = 256
// lsuL1Enable = true
// lsuL1Sets = 64
// lsuL1Ways = 4
// LsuL1RefillCount = 2
// lsuL1WritebackCount = 2
// lsuStoreBufferSlots = 2
// lsuStoreBufferOps = 32
// withLsuBypass = true
withGShare = true
withBtb = true
withRas = true
relaxedBranch = true // !!
relaxedBtb = true // !!
fetchL1Enable = true
fetchL1Sets = 64
fetchL1Ways = 4
fetchL1ReducedBank = true
fetchMemDataWidthMin = 256
lsuL1Enable = true
lsuL1Sets = 64
lsuL1Ways = 4
lsuL1RefillCount = 2
lsuL1WritebackCount = 2
lsuStoreBufferSlots = 2
lsuStoreBufferOps = 32
withLsuBypass = true

// lsuForkAt = 1
divArea = false
// divRadix = 4
// decoders = 2
// lanes = 2
divRadix = 4
decoders = 2
lanes = 2
withLateAlu = true
withMul = true
withDiv = true
// withDispatcherBuffer = true
// withAlignerBuffer = true
// withRvc = true
withDispatcherBuffer = true
withAlignerBuffer = true
withRvc = true
withRva = true
withMmu = true
privParam.withSupervisor = true
privParam.withUser = true
xlen = 64
// xlen = 64


privParam.withDebug = true
Expand Down Expand Up @@ -211,8 +216,8 @@ class ParamSimple(){
r += s"l${lanes}"
r += s"disAt${dispatcherAt}"
r += regFileSync.mux("rfs","rfa") + regFileDualPortRam.mux("Dp","Mem")
if (fetchL1Enable) r += s"fl1xW${lsuL1Ways}xS${lsuL1Sets}Dwm$fetchL1MemDataWidthMin${fetchL1ReducedBank.mux("Rb", "")}" else r += s"fclF${fetchForkAt}"
if (lsuL1Enable) r += s"lsul1xW${lsuL1Ways}xS${lsuL1Sets}${withLsuBypass.mux("xBp","")}Sb${lsuStoreBufferSlots}w${lsuStoreBufferOps}" else r += s"lsuP${lsuPmaAt}F$lsuForkAt"
if (fetchL1Enable) r += s"fl1xW${lsuL1Ways}xS${lsuL1Sets}Dwm$fetchMemDataWidth${fetchL1ReducedBank.mux("Rb", "")}" else r += s"fclF${fetchForkAt}dw${fetchMemDataWidth}"
if (lsuL1Enable) r += s"lsul1xW${lsuL1Ways}xS${lsuL1Sets}${withLsuBypass.mux("xBp","")}Sb${lsuStoreBufferSlots}w${lsuStoreBufferOps}dw${lsuMemDataWidth}rc${lsuL1RefillCount}wc${lsuL1WritebackCount}" else r += s"lsuP${lsuPmaAt}F${lsuForkAt}dw$lsuMemDataWidth"
if(allowBypassFrom < 100) r += s"bp$allowBypassFrom"
if (withBtb) r += s"btbS${btbSets}H${btbHashWidth}${if(relaxedBtb)"R" else ""}"
if (withRas) r += "ras"
Expand All @@ -239,6 +244,7 @@ class ParamSimple(){
opt[Int]("lanes") action { (v, c) => lanes = v }
opt[Int]("decoder-at") action { (v, c) => decoderAt = v }
opt[Int]("dispatcher-at") action { (v, c) => dispatcherAt = v }
opt[Long]("reset-vector") unbounded() action { (v, c) => resetVector = v }
opt[Unit]("relaxed-branch") action { (v, c) => relaxedBranch = true }
opt[Unit]("relaxed-shift") action { (v, c) => relaxedShift = true }
opt[Unit]("relaxed-src") action { (v, c) => relaxedSrc = true }
Expand Down Expand Up @@ -269,14 +275,19 @@ class ParamSimple(){
opt[Int]("performance-counters") action { (v, c) => withPerformanceCounters = true; additionalPerformanceCounters = v }
opt[Unit]("with-fetch-l1") action { (v, c) => fetchL1Enable = true }
opt[Unit]("with-lsu-l1") action { (v, c) => lsuL1Enable = true }
opt[Unit]("fetch-l1") action { (v, c) => fetchL1Enable = true }
opt[Unit]("lsu-l1") action { (v, c) => lsuL1Enable = true }
opt[Int]("fetch-l1-sets") action { (v, c) => fetchL1Sets = v }
opt[Int]("fetch-l1-ways") action { (v, c) => fetchL1Ways = v }
opt[Int]("fetch-l1-mem-data-width-min") action { (v, c) => fetchL1MemDataWidthMin = v }
opt[Int]("fetch-l1-mem-data-width-min") action { (v, c) => fetchMemDataWidthMin = v }
opt[Unit]("fetch-reduced-bank") action { (v, c) => fetchL1ReducedBank = true }
opt[Int]("lsu-l1-sets") action { (v, c) => lsuL1Sets = v }
opt[Int]("lsu-l1-ways") action { (v, c) => lsuL1Ways = v }
opt[Int]("lsu-l1-store-buffer-slots") action { (v, c) => lsuStoreBufferSlots = v }
opt[Int]("lsu-l1-store-buffer-ops") action { (v, c) => lsuStoreBufferOps = v }
opt[Int]("lsu-l1-refill-count") action { (v, c) => lsuL1RefillCount = v }
opt[Int]("lsu-l1-writeback-count") action { (v, c) => lsuL1WritebackCount = v }
opt[Int]("lsu-l1-mem-data-width-min") action { (v, c) => lsuMemDataWidthMin = v }
opt[Unit]("with-lsu-bypass") action { (v, c) => withLsuBypass = true }
opt[Unit]("with-iterative-shift") action { (v, c) => withIterativeShift = true }
opt[Int]("div-radix") action { (v, c) => divRadix = v }
Expand All @@ -289,12 +300,10 @@ class ParamSimple(){
opt[Int] ("debug-triggers") action { (v, c) => privParam.debugTriggers = v }
opt[Unit]("debug-triggers-lsu") action { (v, c) => privParam.debugTriggersLsu = true }
opt[Unit]("debug-jtag-tap") action { (v, c) => embeddedJtagTap = true }


}

def plugins() = pluginsArea.plugins
def pluginsArea() = new Area {
def plugins(hartId : Int = 0) = pluginsArea(hartId).plugins
def pluginsArea(hartId : Int = 0) = new Area {
val plugins = ArrayBuffer[Hostable]()
if(withLateAlu) assert(allowBypassFrom == 0)

Expand Down Expand Up @@ -347,7 +356,7 @@ class ParamSimple(){
if(!fetchL1Enable) plugins += new fetch.FetchCachelessPlugin(
forkAt = fetchForkAt,
joinAt = fetchForkAt+1, //You can for instance allow the external memory to have more latency by changing this
wordWidth = 32*decoders,
wordWidth = fetchMemDataWidth,
translationStorageParameter = MmuStorageParameter(
levels = List(
MmuStorageLevel(
Expand Down Expand Up @@ -378,7 +387,7 @@ class ParamSimple(){
setCount = fetchL1Sets,
wayCount = fetchL1Ways,
fetchDataWidth = 32*decoders,
memDataWidth = 32*decoders max fetchL1MemDataWidthMin,
memDataWidth = fetchMemDataWidth,
reducedBankWidth = fetchL1ReducedBank,
hitsWithTranslationWays = true,
tagsReadAsync = false,
Expand Down Expand Up @@ -491,7 +500,7 @@ class ParamSimple(){
layer = early0,
withRva = withRva,
storeRs2At = withLateAlu.mux(2, 0),
storeBufferSlots =lsuStoreBufferSlots,
storeBufferSlots = lsuStoreBufferSlots,
storeBufferOps = lsuStoreBufferOps,
translationStorageParameter = MmuStorageParameter(
levels = List(
Expand Down Expand Up @@ -520,9 +529,9 @@ class ParamSimple(){
)
plugins += new LsuL1Plugin(
lane = lane0,
memDataWidth = xlen,
memDataWidth = lsuMemDataWidth,
cpuDataWidth = xlen,
refillCount = LsuL1RefillCount,
refillCount = lsuL1RefillCount,
writebackCount = lsuL1WritebackCount,
setCount = lsuL1Sets,
wayCount = lsuL1Ways,
Expand Down Expand Up @@ -558,7 +567,7 @@ class ParamSimple(){
plugins += new CsrRamPlugin()
if(withPerformanceCounters) plugins += new PerformanceCounterPlugin(additionalCounterCount = additionalPerformanceCounters)
plugins += new CsrAccessPlugin(early0, writeBackKey = if(lanes == 1) "lane0" else "lane1")
plugins += new PrivilegedPlugin(privParam, 0 until hartCount)
plugins += new PrivilegedPlugin(privParam, hartId until hartId+hartCount)
plugins += new TrapPlugin(trapAt = 2)
plugins += new EnvPlugin(early0, executeAt = 0)
if(embeddedJtagTap || embeddedJtagInstruction) plugins += new EmbeddedRiscvJtag(
Expand Down Expand Up @@ -713,3 +722,14 @@ lane micro op spec
- dontFlushFrom
*/



object OptionToPython extends App{
new scopt.OptionParser[Unit]("lol"){
new ParamSimple().addOptions(this)
for(o <- options){
println(o.name)
}
}
}

14 changes: 7 additions & 7 deletions src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ class LsuPlugin(var layer : LaneLayer,
dataWidth = Riscv.LSLEN,
hartIdWidth = Global.HART_ID_WIDTH,
uopIdWidth = Decode.UOP_ID_WIDTH,
withAmo = withRva,
withAmo = false, //TODO
pendingMax = 1
)
val bus = master(LsuCachelessBus(busParam)).simPublic()
Expand Down Expand Up @@ -417,10 +417,10 @@ class LsuPlugin(var layer : LaneLayer,
bus.cmd.fromHart := True
bus.cmd.hartId := Global.HART_ID
bus.cmd.uopId := Decode.UOP_ID
if (withRva) {
bus.cmd.amoEnable := l1.ATOMIC
bus.cmd.amoOp := UOP(31 downto 27)
}
// if (withRva) {
// bus.cmd.amoEnable := l1.ATOMIC
// bus.cmd.amoOp := UOP(31 downto 27)
// }

val rsp = bus.rsp.toStream.halfPipe()
rsp.ready := !elp.isFreezed()
Expand All @@ -446,7 +446,7 @@ class LsuPlugin(var layer : LaneLayer,
}

val READ_SHIFTED = insert(rspShifted)
val SC_MISS = insert(withRva.mux(io.doIt.mux[Bool](io.rsp.scMiss, scMiss), False))
val SC_MISS = insert(scMiss)//insert(withRva.mux(io.doIt.mux[Bool](io.rsp.scMiss, scMiss), False))


if (!Riscv.RVA.get) {
Expand Down Expand Up @@ -518,7 +518,7 @@ class LsuPlugin(var layer : LaneLayer,
trapPort.code.assignDontCare()
trapPort.arg.allowOverride() := 0

when((!pmaIo.rsp.fault).mux[Bool](io.rsp.valid && io.rsp.error, l1.FAULT)) {
when((pmaL1.rsp.fault).mux[Bool](io.rsp.valid && io.rsp.error || l1.ATOMIC, l1.FAULT)) {
lsuTrap := True
trapPort.exception := True
trapPort.code := CSR.MCAUSE_ENUM.LOAD_ACCESS_FAULT
Expand Down
8 changes: 5 additions & 3 deletions src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -305,17 +305,19 @@ class FetchL1Plugin(var translationStorageParameter: Any,
val tpk = translationPort.keys

val cmd = new pp.Fetch(readAt) {
val ra1 = pp.fetch(readAt + 1).up
val doIt = ra1.ready || !ra1.valid // Better timings than up.isReady, ra1.cancel not necessary as cancel do not collapse bubbles
for ((bank, bankId) <- banks.zipWithIndex) {
bank.read.cmd.valid := up.isReady
bank.read.cmd.valid := doIt
bank.read.cmd.payload := WORD_PC(lineRange.high downto log2Up(bankWidth / 8))
}

for((way, wayId) <- ways.zipWithIndex) {
way.read.cmd.valid := up.isReady
way.read.cmd.valid := doIt
way.read.cmd.payload := WORD_PC(lineRange)
}

plru.read.cmd.valid := up.isReady
plru.read.cmd.valid := doIt
plru.read.cmd.payload := WORD_PC(lineRange)

val PLRU_BYPASS_VALID = insert(plru.write.valid && plru.write.address === plru.read.cmd.payload)
Expand Down
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