diff --git a/build.sbt b/build.sbt index 59f2cfa9..2c8570d7 100644 --- a/build.sbt +++ b/build.sbt @@ -10,6 +10,7 @@ def rootGen() = { )), scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/ext/SpinalHDL/idslplugin/target/scala-2.12/spinalhdl-idsl-plugin_2.12-$spinalVersion.jar")}", scalacOptions += s"-Xplugin-require:idsl-plugin", + scalacOptions += "-language:reflectiveCalls", libraryDependencies ++= Seq( "org.scalatest" %% "scalatest" % "3.2.17", "org.yaml" % "snakeyaml" % "1.8", diff --git a/ext/SpinalHDL b/ext/SpinalHDL index cfcde075..c2fea9ec 160000 --- a/ext/SpinalHDL +++ b/ext/SpinalHDL @@ -1 +1 @@ -Subproject commit cfcde0752f4000b8da591d4e9f2d40866a347113 +Subproject commit c2fea9eccb9fe1f4ab0b8dd72412ec4568e880af diff --git a/src/main/scala/vexiiriscv/Generate.scala b/src/main/scala/vexiiriscv/Generate.scala index 41d62a99..41f506fe 100644 --- a/src/main/scala/vexiiriscv/Generate.scala +++ b/src/main/scala/vexiiriscv/Generate.scala @@ -11,6 +11,7 @@ import vexiiriscv.decode.{Decode, DecodePipelinePlugin} import vexiiriscv.execute.{CsrRamPlugin, ExecuteLanePlugin, SrcPlugin} import vexiiriscv.execute.lsu._ import vexiiriscv.fetch._ +import vexiiriscv.prediction.BtbPlugin import vexiiriscv.regfile.RegFilePlugin import scala.collection.mutable.ArrayBuffer @@ -50,6 +51,10 @@ object GeneratTweeked extends App { param.relaxedBranch = true param.lsuStoreBufferSlots = 2 param.lsuStoreBufferOps = 32 + param.withBtb = true + param.withGShare = true + param.withRas = true + val report = sc.generateVerilog { val plugins = param.plugins() @@ -60,10 +65,69 @@ object GeneratTweeked extends App { report.toplevel.database.on{ // val from = report.toplevel.host[ExecuteLanePlugin].execute(0).down(Decode.UOP) // val from = report.toplevel.host[LsuPlugin].logic.storeBuffer.slots(0).tag - val from = report.toplevel.host[DecodePipelinePlugin].ctrl(1).lane(0).up(Decode.INSTRUCTION) +// val from = report.toplevel.host[DecodePipelinePlugin].ctrl(1).lane(0).up(Decode.INSTRUCTION) +// val to = report.toplevel.host[FetchL1Plugin].logic.banks.head.read.cmd.valid + val from = report.toplevel.host[BtbPlugin].logic.readPort.rsp.head.hash val to = report.toplevel.host[FetchL1Plugin].logic.banks.head.read.cmd.valid // val to = report.toplevel.host[CsrRamPlugin].logic.writeLogic.port.data println(PathTracer.impl(from, to).report()) } } + + +/* +- Node((toplevel/FetchL1Plugin_logic_banks_0_read_cmd_valid : Bool)) + - Node((toplevel/fetch_logic_ctrls_0_up_isReady : Bool)) + - Node((toplevel/fetch_logic_ctrls_0_up_ready : Bool)) + - Node((toplevel/when_CtrlLink_l151 : Bool)) + - Node(| Bits) + - Node(Bits ## Bits) + - Node(Bits ## Bits) + - Node(Bits -> Bits) + - Node((toplevel/fetch_logic_ctrls_0_haltRequest_BtbPlugin_l165 : Bool)) + - Node(Bool && Bool) + - Node(UInt === UInt) + - Node((toplevel/BtbPlugin_logic_readPort_cmd_payload : UInt[9 bits])) + - Node(resize(UInt,9 bits)) + - Node((UInt >> Int)[30 bits]) + - Node((toplevel/fetch_logic_ctrls_0_down_Fetch_WORD_PC : UInt[32 bits])) + - Node((toplevel/fetch_logic_ctrls_0_up_Fetch_WORD_PC : UInt[32 bits])) + - Node((toplevel/PcPlugin_logic_harts_0_output_payload : UInt[32 bits])) + - Node((toplevel/PcPlugin_logic_harts_0_aggregator_target_1 : UInt[32 bits])) + - Node((toplevel/PcPlugin_logic_harts_0_aggregator_target : UInt[32 bits])) + - Node((Bits -> UInt of 32 bits)) + - Node((Bits | Bits)[32 bits]) + - Node((Bits | Bits)[32 bits]) + - Node((Bool ? Bits | Bits)[32 bits]) + - Node(Bits(Int)) + - Node((toplevel/PcPlugin_logic_harts_0_aggregator_oh : Bits[4 bits])) + - Node((toplevel/_zz_PcPlugin_logic_harts_0_aggregator_oh_4 : Bits[4 bits])) + - Node(Bool && Bool) + - Node((toplevel/_zz_PcPlugin_logic_harts_0_aggregator_oh_1 : Bool)) + - Node(Bits(Int)) + - Node((toplevel/_zz_PcPlugin_logic_harts_0_aggregator_oh : Bits[4 bits])) + - Node(Bits ## Bits) + - Node(Bits ## Bits) + - Node(Bits -> Bits) + - Node((toplevel/PcPlugin_logic_harts_0_aggregator_valids_2 : Bool)) + - Node(Bool && Bool) + - Node(Bool && Bool) + - Node((toplevel/BtbPlugin_logic_pcPort_valid : Bool)) + - Node((toplevel/BtbPlugin_logic_applyIt_doIt : Bool)) + - Node(Bool && Bool) + - Node((toplevel/BtbPlugin_logic_applyIt_needIt : Bool)) + - Node(Bool && Bool) + - Node(| Bits) + - Node((toplevel/BtbPlugin_logic_applyIt_chunksTakenOh : Bits[1 bits])) + - Node((Bits & Bits)[1 bits]) + - Node((toplevel/BtbPlugin_logic_applyIt_chunksMask : Bits[1 bits])) + - Node(Bits -> Bits) + - Node(Bool && Bool) + - Node((toplevel/fetch_logic_ctrls_1_down_BtbPlugin_logic_chunksLogic_0_hitCalc_HIT : Bool)) + - Node(Bool && Bool) + - Node(UInt === UInt) + - Node((toplevel/fetch_logic_ctrls_1_down_BtbPlugin_logic_chunksLogic_0_readRsp_ENTRY_hash : UInt[16 bits])) + - Node((toplevel/BtbPlugin_logic_readPort_rsp_0_hash : UInt[16 bits])) + - Node((toplevel/BtbPlugin_logic_readPort_rsp_0_hash : UInt[16 bits])) + */ \ No newline at end of file diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala index 058644a7..86c47d06 100644 --- a/src/main/scala/vexiiriscv/Param.scala +++ b/src/main/scala/vexiiriscv/Param.scala @@ -30,7 +30,7 @@ object ParamSimple{ isExecutable = true, transfers = M2sTransfers( get = SizeRange.all, - putFull = SizeRange.all, + putFull = SizeRange.all ) ), new PmaRegionImpl( @@ -39,7 +39,7 @@ object ParamSimple{ isExecutable = true, transfers = M2sTransfers( get = SizeRange.all, - putFull = SizeRange.all, + putFull = SizeRange.all ) ) ) @@ -90,14 +90,15 @@ class ParamSimple(){ var fetchL1Sets = 64 var fetchL1Ways = 1 var fetchL1ReducedBank = false - var fetchL1MemDataWidthMin = 32 + var fetchMemDataWidthMin = 32 var lsuStoreBufferSlots = 0 var lsuStoreBufferOps = 0 var lsuL1Enable = false var lsuL1Sets = 64 var lsuL1Ways = 1 - var LsuL1RefillCount = 1 + var lsuL1RefillCount = 1 var lsuL1WritebackCount = 1 + var lsuMemDataWidthMin = 32 var withLsuBypass = false var withIterativeShift = false var divRadix = 2 @@ -111,6 +112,10 @@ class ParamSimple(){ var embeddedJtagCd: ClockDomain = null var embeddedJtagNoTapCd: ClockDomain = null + def fetchMemDataWidth = 32*decoders max fetchMemDataWidthMin + def lsuMemDataWidth = xlen max lsuMemDataWidthMin + def memDataWidth = List(fetchMemDataWidth, lsuMemDataWidth).max + // Debug modifiers val debugParam = sys.env.getOrElse("VEXIIRISCV_DEBUG_PARAM", "0").toInt.toBoolean if(debugParam) { @@ -119,41 +124,41 @@ class ParamSimple(){ regFileSync = false allowBypassFrom = 0 -// withGShare = true -// withBtb = true -// withRas = true -// relaxedBranch = true // !! -// relaxedBtb = true // !! -// fetchL1Enable = true -// fetchL1Sets = 64 -// fetchL1Ways = 4 - //fetchL1ReducedBank = true - //fetchL1MemDataWidthMin = 256 -// lsuL1Enable = true -// lsuL1Sets = 64 -// lsuL1Ways = 4 -// LsuL1RefillCount = 2 -// lsuL1WritebackCount = 2 -// lsuStoreBufferSlots = 2 -// lsuStoreBufferOps = 32 -// withLsuBypass = true + withGShare = true + withBtb = true + withRas = true + relaxedBranch = true // !! + relaxedBtb = true // !! + fetchL1Enable = true + fetchL1Sets = 64 + fetchL1Ways = 4 + fetchL1ReducedBank = true + fetchMemDataWidthMin = 256 + lsuL1Enable = true + lsuL1Sets = 64 + lsuL1Ways = 4 + lsuL1RefillCount = 2 + lsuL1WritebackCount = 2 + lsuStoreBufferSlots = 2 + lsuStoreBufferOps = 32 + withLsuBypass = true // lsuForkAt = 1 divArea = false -// divRadix = 4 -// decoders = 2 -// lanes = 2 + divRadix = 4 + decoders = 2 + lanes = 2 withLateAlu = true withMul = true withDiv = true -// withDispatcherBuffer = true -// withAlignerBuffer = true -// withRvc = true + withDispatcherBuffer = true + withAlignerBuffer = true + withRvc = true withRva = true withMmu = true privParam.withSupervisor = true privParam.withUser = true - xlen = 64 +// xlen = 64 privParam.withDebug = true @@ -211,8 +216,8 @@ class ParamSimple(){ r += s"l${lanes}" r += s"disAt${dispatcherAt}" r += regFileSync.mux("rfs","rfa") + regFileDualPortRam.mux("Dp","Mem") - if (fetchL1Enable) r += s"fl1xW${lsuL1Ways}xS${lsuL1Sets}Dwm$fetchL1MemDataWidthMin${fetchL1ReducedBank.mux("Rb", "")}" else r += s"fclF${fetchForkAt}" - if (lsuL1Enable) r += s"lsul1xW${lsuL1Ways}xS${lsuL1Sets}${withLsuBypass.mux("xBp","")}Sb${lsuStoreBufferSlots}w${lsuStoreBufferOps}" else r += s"lsuP${lsuPmaAt}F$lsuForkAt" + if (fetchL1Enable) r += s"fl1xW${lsuL1Ways}xS${lsuL1Sets}Dwm$fetchMemDataWidth${fetchL1ReducedBank.mux("Rb", "")}" else r += s"fclF${fetchForkAt}dw${fetchMemDataWidth}" + if (lsuL1Enable) r += s"lsul1xW${lsuL1Ways}xS${lsuL1Sets}${withLsuBypass.mux("xBp","")}Sb${lsuStoreBufferSlots}w${lsuStoreBufferOps}dw${lsuMemDataWidth}rc${lsuL1RefillCount}wc${lsuL1WritebackCount}" else r += s"lsuP${lsuPmaAt}F${lsuForkAt}dw$lsuMemDataWidth" if(allowBypassFrom < 100) r += s"bp$allowBypassFrom" if (withBtb) r += s"btbS${btbSets}H${btbHashWidth}${if(relaxedBtb)"R" else ""}" if (withRas) r += "ras" @@ -239,6 +244,7 @@ class ParamSimple(){ opt[Int]("lanes") action { (v, c) => lanes = v } opt[Int]("decoder-at") action { (v, c) => decoderAt = v } opt[Int]("dispatcher-at") action { (v, c) => dispatcherAt = v } + opt[Long]("reset-vector") unbounded() action { (v, c) => resetVector = v } opt[Unit]("relaxed-branch") action { (v, c) => relaxedBranch = true } opt[Unit]("relaxed-shift") action { (v, c) => relaxedShift = true } opt[Unit]("relaxed-src") action { (v, c) => relaxedSrc = true } @@ -269,14 +275,19 @@ class ParamSimple(){ opt[Int]("performance-counters") action { (v, c) => withPerformanceCounters = true; additionalPerformanceCounters = v } opt[Unit]("with-fetch-l1") action { (v, c) => fetchL1Enable = true } opt[Unit]("with-lsu-l1") action { (v, c) => lsuL1Enable = true } + opt[Unit]("fetch-l1") action { (v, c) => fetchL1Enable = true } + opt[Unit]("lsu-l1") action { (v, c) => lsuL1Enable = true } opt[Int]("fetch-l1-sets") action { (v, c) => fetchL1Sets = v } opt[Int]("fetch-l1-ways") action { (v, c) => fetchL1Ways = v } - opt[Int]("fetch-l1-mem-data-width-min") action { (v, c) => fetchL1MemDataWidthMin = v } + opt[Int]("fetch-l1-mem-data-width-min") action { (v, c) => fetchMemDataWidthMin = v } opt[Unit]("fetch-reduced-bank") action { (v, c) => fetchL1ReducedBank = true } opt[Int]("lsu-l1-sets") action { (v, c) => lsuL1Sets = v } opt[Int]("lsu-l1-ways") action { (v, c) => lsuL1Ways = v } opt[Int]("lsu-l1-store-buffer-slots") action { (v, c) => lsuStoreBufferSlots = v } opt[Int]("lsu-l1-store-buffer-ops") action { (v, c) => lsuStoreBufferOps = v } + opt[Int]("lsu-l1-refill-count") action { (v, c) => lsuL1RefillCount = v } + opt[Int]("lsu-l1-writeback-count") action { (v, c) => lsuL1WritebackCount = v } + opt[Int]("lsu-l1-mem-data-width-min") action { (v, c) => lsuMemDataWidthMin = v } opt[Unit]("with-lsu-bypass") action { (v, c) => withLsuBypass = true } opt[Unit]("with-iterative-shift") action { (v, c) => withIterativeShift = true } opt[Int]("div-radix") action { (v, c) => divRadix = v } @@ -289,12 +300,10 @@ class ParamSimple(){ opt[Int] ("debug-triggers") action { (v, c) => privParam.debugTriggers = v } opt[Unit]("debug-triggers-lsu") action { (v, c) => privParam.debugTriggersLsu = true } opt[Unit]("debug-jtag-tap") action { (v, c) => embeddedJtagTap = true } - - } - def plugins() = pluginsArea.plugins - def pluginsArea() = new Area { + def plugins(hartId : Int = 0) = pluginsArea(hartId).plugins + def pluginsArea(hartId : Int = 0) = new Area { val plugins = ArrayBuffer[Hostable]() if(withLateAlu) assert(allowBypassFrom == 0) @@ -347,7 +356,7 @@ class ParamSimple(){ if(!fetchL1Enable) plugins += new fetch.FetchCachelessPlugin( forkAt = fetchForkAt, joinAt = fetchForkAt+1, //You can for instance allow the external memory to have more latency by changing this - wordWidth = 32*decoders, + wordWidth = fetchMemDataWidth, translationStorageParameter = MmuStorageParameter( levels = List( MmuStorageLevel( @@ -378,7 +387,7 @@ class ParamSimple(){ setCount = fetchL1Sets, wayCount = fetchL1Ways, fetchDataWidth = 32*decoders, - memDataWidth = 32*decoders max fetchL1MemDataWidthMin, + memDataWidth = fetchMemDataWidth, reducedBankWidth = fetchL1ReducedBank, hitsWithTranslationWays = true, tagsReadAsync = false, @@ -491,7 +500,7 @@ class ParamSimple(){ layer = early0, withRva = withRva, storeRs2At = withLateAlu.mux(2, 0), - storeBufferSlots =lsuStoreBufferSlots, + storeBufferSlots = lsuStoreBufferSlots, storeBufferOps = lsuStoreBufferOps, translationStorageParameter = MmuStorageParameter( levels = List( @@ -520,9 +529,9 @@ class ParamSimple(){ ) plugins += new LsuL1Plugin( lane = lane0, - memDataWidth = xlen, + memDataWidth = lsuMemDataWidth, cpuDataWidth = xlen, - refillCount = LsuL1RefillCount, + refillCount = lsuL1RefillCount, writebackCount = lsuL1WritebackCount, setCount = lsuL1Sets, wayCount = lsuL1Ways, @@ -558,7 +567,7 @@ class ParamSimple(){ plugins += new CsrRamPlugin() if(withPerformanceCounters) plugins += new PerformanceCounterPlugin(additionalCounterCount = additionalPerformanceCounters) plugins += new CsrAccessPlugin(early0, writeBackKey = if(lanes == 1) "lane0" else "lane1") - plugins += new PrivilegedPlugin(privParam, 0 until hartCount) + plugins += new PrivilegedPlugin(privParam, hartId until hartId+hartCount) plugins += new TrapPlugin(trapAt = 2) plugins += new EnvPlugin(early0, executeAt = 0) if(embeddedJtagTap || embeddedJtagInstruction) plugins += new EmbeddedRiscvJtag( @@ -713,3 +722,14 @@ lane micro op spec - dontFlushFrom */ + + +object OptionToPython extends App{ + new scopt.OptionParser[Unit]("lol"){ + new ParamSimple().addOptions(this) + for(o <- options){ + println(o.name) + } + } +} + diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala index 78a52486..2d6dc841 100644 --- a/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala +++ b/src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala @@ -131,7 +131,7 @@ class LsuPlugin(var layer : LaneLayer, dataWidth = Riscv.LSLEN, hartIdWidth = Global.HART_ID_WIDTH, uopIdWidth = Decode.UOP_ID_WIDTH, - withAmo = withRva, + withAmo = false, //TODO pendingMax = 1 ) val bus = master(LsuCachelessBus(busParam)).simPublic() @@ -417,10 +417,10 @@ class LsuPlugin(var layer : LaneLayer, bus.cmd.fromHart := True bus.cmd.hartId := Global.HART_ID bus.cmd.uopId := Decode.UOP_ID - if (withRva) { - bus.cmd.amoEnable := l1.ATOMIC - bus.cmd.amoOp := UOP(31 downto 27) - } +// if (withRva) { +// bus.cmd.amoEnable := l1.ATOMIC +// bus.cmd.amoOp := UOP(31 downto 27) +// } val rsp = bus.rsp.toStream.halfPipe() rsp.ready := !elp.isFreezed() @@ -446,7 +446,7 @@ class LsuPlugin(var layer : LaneLayer, } val READ_SHIFTED = insert(rspShifted) - val SC_MISS = insert(withRva.mux(io.doIt.mux[Bool](io.rsp.scMiss, scMiss), False)) + val SC_MISS = insert(scMiss)//insert(withRva.mux(io.doIt.mux[Bool](io.rsp.scMiss, scMiss), False)) if (!Riscv.RVA.get) { @@ -518,7 +518,7 @@ class LsuPlugin(var layer : LaneLayer, trapPort.code.assignDontCare() trapPort.arg.allowOverride() := 0 - when((!pmaIo.rsp.fault).mux[Bool](io.rsp.valid && io.rsp.error, l1.FAULT)) { + when((pmaL1.rsp.fault).mux[Bool](io.rsp.valid && io.rsp.error || l1.ATOMIC, l1.FAULT)) { lsuTrap := True trapPort.exception := True trapPort.code := CSR.MCAUSE_ENUM.LOAD_ACCESS_FAULT diff --git a/src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala b/src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala index 24e78570..4645e799 100644 --- a/src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala +++ b/src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala @@ -305,17 +305,19 @@ class FetchL1Plugin(var translationStorageParameter: Any, val tpk = translationPort.keys val cmd = new pp.Fetch(readAt) { + val ra1 = pp.fetch(readAt + 1).up + val doIt = ra1.ready || !ra1.valid // Better timings than up.isReady, ra1.cancel not necessary as cancel do not collapse bubbles for ((bank, bankId) <- banks.zipWithIndex) { - bank.read.cmd.valid := up.isReady + bank.read.cmd.valid := doIt bank.read.cmd.payload := WORD_PC(lineRange.high downto log2Up(bankWidth / 8)) } for((way, wayId) <- ways.zipWithIndex) { - way.read.cmd.valid := up.isReady + way.read.cmd.valid := doIt way.read.cmd.payload := WORD_PC(lineRange) } - plru.read.cmd.valid := up.isReady + plru.read.cmd.valid := doIt plru.read.cmd.payload := WORD_PC(lineRange) val PLRU_BYPASS_VALID = insert(plru.write.valid && plru.write.address === plru.read.cmd.payload) diff --git a/src/main/scala/vexiiriscv/misc/EmbeddedJtagPlugin.scala b/src/main/scala/vexiiriscv/misc/EmbeddedJtagPlugin.scala index 1f094ff3..6485cff7 100644 --- a/src/main/scala/vexiiriscv/misc/EmbeddedJtagPlugin.scala +++ b/src/main/scala/vexiiriscv/misc/EmbeddedJtagPlugin.scala @@ -77,6 +77,7 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter, /* src/openocd -f $VEXIIRISCV/src/main/tcl/openocd/vexiiriscv_sim.tcl +openocd -f src/main/tcl/openocd/vexiiriscv_sim.tcl src/openocd -f $VEXIIRISCV/src/main/tcl/openocd/vexiiriscv_sim.tcl "sleep 5000" -c "reg pc 0x80000000" -c "exit" -d3 diff --git a/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala b/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala index 825df653..24143748 100644 --- a/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala +++ b/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala @@ -25,7 +25,7 @@ object PrivilegedParam{ withSupervisor = false, withUser = false, withUserTrap = false, - withRdTime = true, + withRdTime = false, withDebug = false, vendorId = 0, archId = 5, //As spike @@ -625,6 +625,18 @@ class PrivilegedPlugin(val p : PrivilegedParam, val hartIds : Seq[Int]) extends for ((id, enable) <- m.edeleg.mapping) spec.exception += ExceptionSpec(id, List(Delegator(enable, 3))) } + + if (p.withRdTime) { + XLEN.get match { + case 32 => { + api.read(rdtime(31 downto 0), CSR.UTIME) + api.read(rdtime(63 downto 32), CSR.UTIMEH) + } + case 64 => { + api.read(rdtime, CSR.UTIME) + } + } + } } val defaultTrap = new Area { diff --git a/src/main/scala/vexiiriscv/misc/TrapPlugin.scala b/src/main/scala/vexiiriscv/misc/TrapPlugin.scala index 628347bf..4c9082a5 100644 --- a/src/main/scala/vexiiriscv/misc/TrapPlugin.scala +++ b/src/main/scala/vexiiriscv/misc/TrapPlugin.scala @@ -205,6 +205,10 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService { val validBuffer = RegNext(valid) init(False) val pendingInterrupt = validBuffer && priv.api.harts(hartId).allowInterrupts csr.int.pending setWhen(pendingInterrupt) + + when(csr.spec.interrupt.map(_.cond).orR){ + askWake(hartId) + } } @@ -417,7 +421,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService { } is(TrapReason.WFI) { wfi := True - when(interrupt.valid || api.harts(hartId).askWake) { + when(api.harts(hartId).askWake) { goto(JUMP) } } diff --git a/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala b/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala index e323190b..a74424b9 100644 --- a/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala +++ b/src/main/scala/vexiiriscv/schedule/DispatchPlugin.scala @@ -204,7 +204,7 @@ class DispatchPlugin(var dispatchAt : Int, decodeSpec += Masked(uop.uop.key) -> (v.from >= hazardUntilMax).mux(Masked.one, Masked.zero) } } - val skip = Symplify(c.ctx.uop, decodeSpec, 1).as(Bool()) //TODO verify with LsuPlugin store usage at execute id 2 + val skip = Symplify(c.ctx.uop, decodeSpec, 1).as(Bool()) for (spec <- bypassedSpecs.values) yield new Area { for (l <- spec.el.getLayers(); uop <- l.uops.values) { diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala new file mode 100644 index 00000000..75fb22fa --- /dev/null +++ b/src/main/scala/vexiiriscv/soc/litex/Soc.scala @@ -0,0 +1,395 @@ +package vexiiriscv.soc.litex + +import spinal.core.fiber.Fiber +import spinal.core._ +import spinal.lib.bus.amba4.axi.{Axi4, Axi4Config, Axi4SpecRenamer, Axi4ToTilelinkFiber} +import spinal.lib.bus.amba4.axilite.AxiLite4SpecRenamer +import spinal.lib.bus.misc.SizeMapping +import spinal.lib.bus.tilelink.coherent.{CacheFiber, HubFiber} +import spinal.lib.bus.tilelink.fabric +import spinal.lib.bus.tilelink.fabric.Node +import spinal.lib.cpu.riscv.debug.DebugModuleFiber +import spinal.lib.misc.TilelinkClintFiber +import spinal.lib.misc.plic.TilelinkPlicFiber +import spinal.lib.{Delay, Flow, ResetCtrlFiber, StreamPipe, master, slave} +import spinal.lib.system.tag.{MemoryConnection, MemoryEndpoint, MemoryTransferTag, PMA} +import vexiiriscv.ParamSimple +import vexiiriscv.compat.{EnforceSyncRamPhase, MultiPortWritesSymplifier} +import vexiiriscv.soc.TilelinkVexiiRiscvFiber +import vexiiriscv.soc.demo.DebugModuleSocFiber + +import scala.collection.mutable.ArrayBuffer + +case class LitexMemoryRegion(mapping : SizeMapping, mode : String, bus : String){ + def isExecutable = mode.contains("x") + def isCachable = mode.contains("c") + def onPeripheral = bus match { + case "m" => false + case "p" => true + } + def onMemory = !onPeripheral +} + +class SocConfig(){ + var vexiiParam = new ParamSimple() + val regions = ArrayBuffer[LitexMemoryRegion]() + var withJtagTap = false + var withJtagInstruction = false + def withDebug = withJtagInstruction || withJtagTap + var withDma = false + var mBusWidth = 64 + var l2Bytes = 0 + var l2Ways = 0 + var cpuCount = 1 + var litedramWidth = 32 +// var sharedBusWidth = 32 + def withL2 = l2Bytes > 0 +} + +class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{ + import c._ + + val system = systemCd on new AreaRoot { + val mainDataWidth = vexiiParam.memDataWidth + + val withCoherency = false + val vexiis = for (hartId <- 0 to 0) yield new TilelinkVexiiRiscvFiber(vexiiParam.plugins(hartId)) + for (vexii <- vexiis) { +// nax.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S, b = StreamPipe.HALF, c = StreamPipe.FULL, e = StreamPipe.HALF) +// nax.iBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S) +// nax.pBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.HALF) + } + + val perfBus, ioBus = fabric.Node() + for (vexii <- vexiis) { + perfBus << List(vexii.iBus, vexiiParam.fetchL1Enable.mux(vexii.lsuL1Bus, vexii.dBus)) + if(vexiiParam.fetchL1Enable) ioBus << List(vexii.dBus) + } + +// val dma = c.withDma generate new Area { +// val bus = slave( +// Axi4( +// Axi4Config( +// addressWidth = 32, +// dataWidth = mainDataWidth, +// idWidth = 4 +// ) +// ) +// ) +// +// val bridge = new Axi4ToTilelinkFiber(64, 4) +// bridge.up load bus.pipelined(ar = StreamPipe.HALF, aw = StreamPipe.HALF, w = StreamPipe.FULL, b = StreamPipe.HALF, r = StreamPipe.FULL) +// bridge.down.setDownConnection(a = StreamPipe.FULL) +// memFilter.up << bridge.down +// +// //As litex reset will release before our one, we need to ensure that we don't eat a transaction +// Fiber build { +// bridge.read.get +// bridge.write.get +// when(ClockDomain.current.isResetActive){ +// bus.ar.ready := False +// bus.aw.ready := False +// bus.w.ready := False +// } +// } +// } + + assert(!(!withCoherency && withL2)) + + var nonCoherent: Node = null + + val direct = (!withCoherency) generate new Area{ + nonCoherent = perfBus + } + +// val hub = (withCoherency && !withL2) generate new Area { +// val hub = new HubFiber() +// hub.up << memFilter.down +// hub.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL) +// hub.down.forceDataWidth(mainDataWidth) +// nonCoherent = hub.down +// } + +// val l2 = (withCoherency && withL2) generate new Area { +// val cache = new CacheFiber() +// cache.parameter.cacheWays = l2Ways +// cache.parameter.cacheBytes = l2Bytes +// cache.up << memFilter.down +// cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL, d = StreamPipe.FULL) +// cache.down.setDownConnection(d = StreamPipe.S2M) +// cache.down.forceDataWidth(mainDataWidth) +// nonCoherent = cache.down +// } + + val memRegions = regions.filter(e => e.onMemory && e.isCachable) + val axiLiteRegions = regions.filter(e => e.onPeripheral) + + val withMem = memRegions.nonEmpty + val toAxi4 = withMem generate new fabric.Axi4Bridge + if (withMem) { + toAxi4.up.forceDataWidth(litedramWidth) + regions.filter(_.onMemory).foreach(r => + toAxi4.up at r.mapping of nonCoherent + ) + toAxi4.down.addTag(PMA.MAIN) + toAxi4.down.addTag(PMA.EXECUTABLE) + for(region <- memRegions) { + toAxi4.down.addTag(new MemoryEndpoint { + override def mapping = SizeMapping(0, region.mapping.size) + }) + } + } + + + val peripheral = new Area { + val bus = Node() + bus << (nonCoherent, ioBus) + bus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.HALF) + bus.forceDataWidth(32) + + val clint = new TilelinkClintFiber() + clint.node at 0xF0010000l of bus + + val plic = new TilelinkPlicFiber() + plic.node at 0xF0C00000l of bus + + val externalInterrupts = new Area { + val port = in Bits (32 bits) + val toPlic = for (i <- 0 to 31) yield (i != 0) generate new Area { + val node = plic.createInterruptSlave(i) + node.withUps = false + node.flag := port(i) + } + } + + + for (vexii <- vexiis) { + vexii.bind(clint) + vexii.bind(plic) + } + + val toAxiLite4 = new fabric.AxiLite4Bridge + toAxiLite4.up << bus + + + + + val virtualRegions = for (region <- axiLiteRegions) yield new Area with SpinalTagReady { + def self = this + + new MemoryConnection { + override def up = toAxiLite4.down + override def down = self + override def transformers = Nil +// override def mapping = region.mapping //TODO + populate() + } + self.addTag(new MemoryEndpoint { + override def mapping = region.mapping + }) + + addTag(new MemoryTransferTag { + override def get = toAxiLite4.up.m2s.parameters.emits + }) + if (region.isCachable) addTag(PMA.MAIN) + if (region.isExecutable) addTag(PMA.EXECUTABLE) + } + } + + val mBus = withMem generate (Fiber build master(toAxi4.down.pipelined())) + val pBus = Fiber build master(peripheral.toAxiLite4.down.pipelined(ar = StreamPipe.HALF, aw = StreamPipe.HALF, w = StreamPipe.HALF, b = StreamPipe.HALF, r = StreamPipe.HALF)) + +// val debug = c.withDebug generate new Area { +// val cd = ClockDomain.current.copy(reset = in Bool()) +// val cdi = c.withJtagInstruction generate ClockDomain.external("jtag_instruction", withReset = false) +// +// val dm = cd(new DebugModuleFiber()) +// vexiis.foreach(dm.bindHart) +// val tap = c.withJtagTap generate cd(dm.withJtagTap()) +// val instruction = c.withJtagInstruction generate cdi(dm.withJtagInstruction()) +// } + + val patcher = Fiber build new Area { +// if (c.withDma) { +// Axi4SpecRenamer(dma.bus) +// dma.bridge.down.bus +// } + if (withMem) Axi4SpecRenamer(mBus.get) + AxiLite4SpecRenamer(pBus.get) + +// vexii(0).dBus.bus + + + val i = MemoryConnection.getMemoryTransfers(vexiis(0).iBus) + val d = MemoryConnection.getMemoryTransfers(vexiis(0).dBus) +// val p = MemoryConnection.getMemoryTransfers(vexiis(0).pBus) + + println(i) + +// if (withJtagTap) debug.tap.jtag.setName("jtag") +// if (withJtagInstruction) debug.instruction.setName("jtag_instruction") +// if (c.withDebug) { +// debug.dm.ndmreset.toIo().setName("debug_ndmreset") +// debug.cd.reset.setName("debug_reset") +// } + +// val tracer = master(Reg(Flow(Bits(8 bits)))) +// val trigger = False +// tracer.valid init (False) +// tracer.valid := Delay(trigger, 2) +// tracer.payload init (0) +// for (nax <- vexii) { +// nax.plugins.collectFirst { case p: CsrTracer => p } match { +// case Some(p) => when(p.logic.flowOut.valid) { +// trigger := True +// tracer.payload := p.logic.flowOut.payload +// } +// case None => +// } +// } + } + } + + val debugReset = c.withDebug generate in.Bool() + val debug = c.withDebug generate ClockDomain(systemCd.clock, debugReset)(new DebugModuleSocFiber(withJtagInstruction) { + out(dm.ndmreset) + system.vexiis.foreach(bindHart) + }) +} + + + + +object SocGen extends App{ + var netlistDirectory = "." + var netlistName = "VexiiRiscvLitex" + val socConfig = new SocConfig() + import socConfig._ + + vexiiParam.fetchL1Enable = true + vexiiParam.lsuL1Enable = true + vexiiParam.privParam.withRdTime = true + + assert(new scopt.OptionParser[Unit]("NaxRiscv") { + help("help").text("prints this usage text") + vexiiParam.addOptions(this) + opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v } + opt[String]("netlist-name") action { (v, c) => netlistName = v } + opt[Int]("litedram-width") action { (v, c) => litedramWidth = v } + opt[Int]("cpu-count") action { (v, c) => cpuCount = v } + opt[Int]("l2-bytes") action { (v, c) => l2Bytes = v } + opt[Int]("l2-ways") action { (v, c) => l2Ways = v } + opt[Unit]("with-dma") action { (v, c) => withDma = true } + opt[Unit]("with-jtag-tap") action { (v, c) => withJtagTap = true } + opt[Unit]("with-jtag-instruction") action { (v, c) => withJtagInstruction = true } + opt[Seq[String]]("memory-region") unbounded() action { (v, c) => + assert(v.length == 4, "--memory-region need 4 parameters") + val r = new LitexMemoryRegion(SizeMapping(BigInt(v(0)), BigInt(v(1))), v(2), v(3)) + regions += r + assert(!(r.onMemory && !r.isCachable), s"Region $r isn't supported by VexiiRiscv, data cache will always cache memory") + } + }.parse(args, Unit).nonEmpty) + + val spinalConfig = SpinalConfig(inlineRom = true, targetDirectory = netlistDirectory) + spinalConfig.addTransformationPhase(new MultiPortWritesSymplifier) + spinalConfig.addStandardMemBlackboxing(blackboxByteEnables) + spinalConfig.addTransformationPhase(new EnforceSyncRamPhase) + + spinalConfig.generateVerilog { + + new Soc(socConfig, ClockDomain.external("system")).setDefinitionName(netlistName) + } +} + +object PythonArgsGen extends App{ + val vexiiParam = new ParamSimple() + import vexiiParam._ + var pythonPath ="miaou.py" + assert(new scopt.OptionParser[Unit]("Vexii") { + help("help").text("prints this usage text") + vexiiParam.addOptions(this) + opt[String]("python-file") action { (v, c) => pythonPath = v } + + }.parse(args, Unit).nonEmpty) + + import java.io.PrintWriter + + new PrintWriter(pythonPath) { + write( + s""" + |VexiiRiscv.xlen = $xlen + |VexiiRiscv.with_rvc = ${withRvc.toInt} + |VexiiRiscv.with_rvm = ${(withMul && withDiv).toInt} + |""".stripMargin) + close() + } + +} + +/* +vex 1 => +Memspeed at 0x40000000 (Sequential, 8.0KiB)... + Write speed: 1.6MiB/s + Read speed: 867.6KiB/s + + +Write speed: 647.4KiB/s + Read speed: 689.3KiB/s + +Write speed: 811.9KiB/s + Read speed: 833.5KiB/s + +Write speed: 1.3MiB/s + Read speed: 833.5KiB/s + +Write speed: 1.3MiB/s + Read speed: 1.0MiB/s + + +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--allow-bypass-from=0 --debug-privileged" --with-jtag-tap --build --load +--with-video-framebuffer --with-spi-sdcard --with-ethernet + +litex_sim --cpu-type=vexiiriscv --with-sdram --sdram-data-width=64 --bus-standard axi-lite --vexii-args="--allow-bypass-from=0 --with-mul --with-div --with-rva --with-btb --with-ras --with-gshare --fetch-l1 --fetch-l1-sets=64 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-sets=64 --lsu-l1-ways=4 --lsu-l1-store-buffer-slots=2 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-supervisor --with-user --performance-counters 0 --debug-privileged --debug-triggers=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-mem-data-width-min=64" --with-jtag-tap --trace-fst --with-jtagremote + + +litex_sim --cpu-type=vexiiriscv --with-sdram --sdram-data-width=64 --bus-standard axi-lite --vexii-args="--allow-bypass-from=0 --with-mul --with-div --with-rva --with-btb --with-ras --with-gshare --fetch-l1-sets=64 --fetch-l1-ways=4 --lsu-l1-sets=64 --lsu-l1-ways=4 --lsu-l1-store-buffer-slots=2 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-supervisor --with-user --performance-counters 0" --trace-fst --sdram-init /media/data2/proj/vexii/litex/buildroot/rv32ima/images/boot.json --trace-start 120000000000000 --trace-end 122000000000000 --trace + +--sdram-init /media/data2/proj/vexii/litex/buildroot/rv32ima/images/boot.json + +--decoders=2 --lanes=2 --with-dispatcher-buffer" + +--trace +--trace-start 600000000000 +60000000000000 +--sdram-init images/sim.json + + +/media/data2/proj/upstream/openocd_riscv_up/src/openocd -f ft2232h_breakout.cfg -f vexiiriscv_jtag.tcl -c "load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images/rootfs.cpio 0x40000000" -c exit +(* MARK_DEBUG = "TRUE" *) + +// Minimal linux +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --with-rva --with-supervisor --performance-counters 0" --with-jtag-tap --load +load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images/Image 0x40000000 +load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images/rv32.dtb 0x40ef0000 +load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images/rootfs.cpio 0x41000000 +load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/images/opensbi.bin 0x40f00000 +load_image /media/data2/proj/vexii/litex/buildroot/rv32ima/opensbi/build/platform/litex/vexriscv/firmware/fw_jump.bin 0x40f00000 +resume + +//Linux++ single issue 1.77 +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --div-ipc --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-mem-data-width-min=64 --with-btb --with-ras --with-gshare --relaxed-branch --regfile-async --lsu-l1-store-buffer-slots=2 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-lsu-bypass" --with-jtag-tap --build --load + +//Linux++ dual issue +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --div-ipc --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4 --fetch-l1-mem-data-width-min=64 --lsu-l1-mem-data-width-min=64 --with-btb --with-ras --with-gshare --relaxed-branch --regfile-async --lsu-l1-store-buffer-slots=2 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 2 --lsu-l1-writeback-count 2 --with-lsu-bypass --decoders=2 --lanes=2" --with-jtag-tap --build --load + + +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--debug-privileged" --with-jtag-tap --build --load +/media/data2/proj/upstream/openocd_riscv_up/src/openocd -f ft2232h_breakout.cfg -f vexiiriscv_jtag.tcl + +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--debug-privileged" --with-jtag-instruction --build --load +openocd -f digilent_nexys_video.tcl -f vexiiriscv_jtag_tunneled.tcl + + +python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=vexiiriscv --vexii-args="--allow-bypass-from=0 --debug-privileged --with-mul --with-div --with-rva --with-supervisor --performance-counters 0 --fetch-l1 --fetch-l1-ways=4 --lsu-l1 --lsu-l1-ways=4 --with-btb --with-ras --with-gshare" --with-jtag-tap --load + + */ \ No newline at end of file diff --git a/src/main/scala/vexiiriscv/tester/TestBench.scala b/src/main/scala/vexiiriscv/tester/TestBench.scala index c44af2f9..4356e5cb 100644 --- a/src/main/scala/vexiiriscv/tester/TestBench.scala +++ b/src/main/scala/vexiiriscv/tester/TestBench.scala @@ -489,7 +489,7 @@ class TestOptions{ while(!CheckSocketPort(JtagRemote.defaultPort)){ Thread.sleep(100) } - JtagRemote(p.logic.jtag, 10*4) + JtagRemote(p.logic.jtag, 20) probe.checkLiveness = false } case _ => @@ -531,7 +531,7 @@ object TestBench extends App{ override def mapping: AddressMapping = SizeMapping(0x80000000l, 0x80000000l) override def transfers: MemoryTransfers = M2sTransfers( get = SizeRange.all, - putFull = SizeRange.all, + putFull = SizeRange.all ) override def isMain: Boolean = true override def isExecutable: Boolean = true @@ -540,7 +540,7 @@ object TestBench extends App{ override def mapping: AddressMapping = SizeMapping(0x10000000l, 0x10000000l) override def transfers: MemoryTransfers = M2sTransfers( get = SizeRange.all, - putFull = SizeRange.all, + putFull = SizeRange.all ) override def isMain: Boolean = false override def isExecutable: Boolean = true @@ -549,7 +549,7 @@ object TestBench extends App{ override def mapping: AddressMapping = SizeMapping(0x1000, 0x1000) override def transfers: MemoryTransfers = M2sTransfers( get = SizeRange.all, - putFull = SizeRange.all, + putFull = SizeRange.all ) override def isMain: Boolean = true override def isExecutable: Boolean = true diff --git a/src/main/tcl/openocd/ft2232h_breakout.cfg b/src/main/tcl/openocd/ft2232h_breakout.cfg new file mode 100644 index 00000000..54a4d82c --- /dev/null +++ b/src/main/tcl/openocd/ft2232h_breakout.cfg @@ -0,0 +1,16 @@ +interface ftdi +ftdi_device_desc "FT2232H Breakout Module" +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 + +# name signal state direction +# *DBUS0 TCK/SK (low =0) (out=1) +# *DBUS1 TDI/DO (low =0) (out=1) +# *DBUS2 TDO/DI (low =0) (in =0) +# *DBUS3 TMS/CS (high=1) (out=1) +ftdi_layout_init 0x08 0x0b + +adapter speed 200000 +ftdi_tdo_sample_edge falling + + diff --git a/src/main/tcl/openocd/vexiiriscv_jtag.tcl b/src/main/tcl/openocd/vexiiriscv_jtag.tcl index 2b138df9..f30fdc36 100644 --- a/src/main/tcl/openocd/vexiiriscv_jtag.tcl +++ b/src/main/tcl/openocd/vexiiriscv_jtag.tcl @@ -5,13 +5,10 @@ set _CHIPNAME riscv set _TARGETNAME $_CHIPNAME.cpu set cpu_count 1 -if [info exists env(NAX_COUNT)] { - set cpu_count $::env(NAX_COUNT) +if [info exists env(HART_COUNT)] { + set cpu_count $::env(HART_COUNT) } - -adapter speed 500 - jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10002FFF for {set i 0} {$i < $cpu_count} {incr i} { diff --git a/src/main/tcl/openocd/vexiiriscv_sim_tunneled.tcl b/src/main/tcl/openocd/vexiiriscv_sim_tunneled.tcl index 9e511bfd..24a03533 100644 --- a/src/main/tcl/openocd/vexiiriscv_sim_tunneled.tcl +++ b/src/main/tcl/openocd/vexiiriscv_sim_tunneled.tcl @@ -18,100 +18,5 @@ $_TARGETNAME.0 configure -work-area-phys 0x70000000 -work-area-size 10000 -work- riscv use_bscan_tunnel 6 1 init -echo "Reset halt" -reset halt +halt echo "Done" - - -#mww 0x80000000 0x01000593 -#mww 0x80000004 0x01100593 -#mww 0x80000008 0x01200593 -#mww 0x8000000c 0x01300593 -#mww 0x80000010 0x01400593 -#mww 0x80000014 0x01500593 -#bp 0x80000004 1 hw -#bp 0x80000010 1 hw -#reg pc 0x80000000 -#echo "Doing resume" -# -#resume -#echo "Wait halt" -#wait_halt -#echo "Halted" -#echo [reg pc] -#echo [reg a1] -#rbp 0x80000004 -# -#resume -#echo "Wait halt" -#wait_halt -#echo "Halted" -#echo [reg pc] -#echo [reg a1] -#rbp 0x80000010 -# -#step -#echo [reg pc] -#echo [reg a1] - -#reg hgeip -#reg hgeip -#reg hgeip -#exit - -#load_image /media/data/open/riscv/VexRiscvOoo/ext/NaxSoftware/baremetal/debugAsm/build/rv32im/debugAsm.bin 0x80000000 -#reg pc 0x80000000 -#step; step; step; step; step; step; step; step; -#echo [reg pc] -#step -#echo [reg pc] - - -#resume -#wait_halt -#echo "step of death" -#echo [reg pc] -#echo [step] -#echo [reg pc] -#echo [step] -#echo [reg pc] -#echo "death" -#echo [targets] - -#mww 0x30000000 0x11223344 -#puts [mdw 0x30000000] -#mww 0x30000000 0x12345678 -#mwb 0x30000004 0x11 -#mwb 0x30000006 0x22 -#mwb 0x30000008 0x33 -#mwb 0x3000000A 0x44 -#mww 0x3000000C 0xABCDEFFF -#puts [mdw 0x30000000] -#puts [mdw 0x30000000 4] - -#echo "Loading image" -#load_image ../VexRiscvOoo/ext/NaxSoftware/baremetal/debug/build/rv32im/debug.bin 0x80000000 -# -#echo [reg pc 0x80000000] -# -#for {set i 0} {$i < 100} {incr i} { -# step -# echo "step$i" -#} - -#step -#echo [reg pc] -# -#step -#echo [reg pc] -# -#step -#echo [reg pc] -# -#step -#echo [reg pc] -# -#exit - -echo "Ready for Remote Connections" - diff --git a/src/test/scala/vexiiriscv/scratchpad/Synt.scala b/src/test/scala/vexiiriscv/scratchpad/Synt.scala index d226b418..a2b2c52a 100644 --- a/src/test/scala/vexiiriscv/scratchpad/Synt.scala +++ b/src/test/scala/vexiiriscv/scratchpad/Synt.scala @@ -30,25 +30,25 @@ object IntegrationSynthBench extends App{ }, postfix) } - add("nothing") { p => - - } - - add("debug") { p => - p.privParam.withDebug = true - } - add("debug instr") { p => - p.privParam.withDebug = true - p.embeddedJtagInstruction = true - p.embeddedJtagCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")) - p.embeddedJtagNoTapCd = ClockDomain.external("jtag", withReset = false) - } +// add("nothing") { p => +// +// } - add("debug jtag") { p => - p.privParam.withDebug = true - p.embeddedJtagTap = true - p.embeddedJtagCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")) - } +// add("debug") { p => +// p.privParam.withDebug = true +// } +// add("debug instr") { p => +// p.privParam.withDebug = true +// p.embeddedJtagInstruction = true +// p.embeddedJtagCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")) +// p.embeddedJtagNoTapCd = ClockDomain.external("jtag", withReset = false) +// } +// +// add("debug jtag") { p => +// p.privParam.withDebug = true +// p.embeddedJtagTap = true +// p.embeddedJtagCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")) +// } // add ("fmax") { p => @@ -241,61 +241,62 @@ object IntegrationSynthBench extends App{ // p.withLateAlu = true // } -// add("fullPerf") { p => -// p.allowBypassFrom = 0 -// p.decoders = 2 -// p.lanes = 2 + add("fullPerf") { p => + p.regFileSync = false + p.allowBypassFrom = 0 + p.decoders = 2 + p.lanes = 2 // p.withDispatcherBuffer = true -// -// p.withMul = true -// p.withDiv = true -// -// p.withBtb = true -// p.withGShare = true -// p.withRas = true -// p.relaxedBranch = true -// p.relaxedBtb = true -// -//// p.privParam.withSupervisor = true; -//// p.privParam.withUser = true; -//// p.withMmu = true -// -// p.lsuL1Enable = true -// p.lsuL1Sets = 64 -// p.lsuL1Ways = 4 -// -// p.fetchL1Enable = true -// p.fetchL1Sets = 64 -// p.fetchL1Ways = 4 -// } -// add("fullPerf2") { p => -// p.allowBypassFrom = 0 -// p.decoders = 2 -// p.lanes = 2 -// p.withDispatcherBuffer = true -// -// p.withMul = true -// p.withDiv = true -// -// p.withBtb = true -// p.withGShare = true -// p.withRas = true -// p.relaxedBranch = true -// p.relaxedBtb = true -// + p.withMul = true + p.withDiv = true + + p.withBtb = true + p.withGShare = true + p.withRas = true + p.relaxedBranch = true + p.relaxedBtb = true + +// p.privParam.withSupervisor = true; +// p.privParam.withUser = true; +// p.withMmu = true + + p.lsuL1Enable = true + p.lsuL1Sets = 64 + p.lsuL1Ways = 4 + + p.fetchL1Enable = true + p.fetchL1Sets = 64 + p.fetchL1Ways = 4 + } + + add("fullPerf2") { p => + p.allowBypassFrom = 0 + p.decoders = 2 + p.lanes = 2 + p.withDispatcherBuffer = true + + p.withMul = true + p.withDiv = true + + p.withBtb = true + p.withGShare = true + p.withRas = true + p.relaxedBranch = true + p.relaxedBtb = true + // p.privParam.withSupervisor = true; // p.privParam.withUser = true; // p.withMmu = true -// -// p.lsuL1Enable = true -// p.lsuL1Sets = 64 -// p.lsuL1Ways = 4 -// -// p.fetchL1Enable = true -// p.fetchL1Sets = 64 -// p.fetchL1Ways = 4 -// } + + p.lsuL1Enable = true + p.lsuL1Sets = 64 + p.lsuL1Ways = 4 + + p.fetchL1Enable = true + p.fetchL1Sets = 64 + p.fetchL1Ways = 4 + } // def cachedPerf(p : ParamSimple): ParamSimple = { @@ -990,4 +991,11 @@ debug_jtag -> Artix 7 -> 90 Mhz 1427 LUT 1608 FF Artix 7 -> 193 Mhz 1579 LUT 1608 FF + +fullPerf -> +Artix 7 -> 87 Mhz 4354 LUT 3050 FF +Artix 7 -> 127 Mhz 4663 LUT 3061 FF +fullPerf2 -> +Artix 7 -> 90 Mhz 4308 LUT 3419 FF +Artix 7 -> 156 Mhz 4813 LUT 3593 FF */ \ No newline at end of file