Merge branch 'dev' into dolu

.github/workflows/scala.yml

@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2023 Everybody
+#
+# SPDX-License-Identifier: CC0-1.0
+
+name: Scala CI
+
+on: [push, pull_request] #push, pull_request
+
+permissions:
+  contents: read
+
+jobs:
+  build:
+
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: recursive
+
+      - name: Set up JDK 11
+        uses: actions/setup-java@v3
+        with:
+          java-version: '11'
+          distribution: 'temurin'
+
+      - name: Install packages
+        run: source .github/workflows/tools.sh && install_packages
+
+      - name: Cache pip
+        uses: actions/cache@v2
+        with:
+          path: ~/.cache/pip
+          key: ${{ runner.os }}-pip-v2
+          restore-keys: |
+            ${{ runner.os }}-pip-
+
+      - name: Cache SBT
+        uses: actions/cache@v2
+        with:
+          path: |
+            ~/.ivy2/cache
+            ~/.sbt
+          key: ${{ runner.os }}-sbt-${{ hashFiles('**/build.sbt') }}
+
+      - name: Cache tools
+        id: tools
+        uses: actions/cache@v2
+        with:
+          path: |
+            ~/tools
+          key: ${{ runner.os }}-tools_v7
+
+      - name: Setup env
+        run: echo "$HOME/tools/bin" >> $GITHUB_PATH
+
+      - name: Install cached tools
+        if: steps.tools.outputs.cache-hit != 'true'
+        run: source .github/workflows/tools.sh && install_cached
+
+      - name: Install uncached tools
+        run: source .github/workflows/tools.sh && install_uncached
+
+      - name: Compile
+        run: sbt clean compile
+
+#      - name: Test
+#        run: NAXRISCV_REGRESSION_THREAD_COUNT=1 SBT_OPTS="-Xmx2G -XX:+UseConcMarkSweepGC -XX:+CMSClassUnloadingEnabled -XX:MaxPermSize=2G -Xss2M  -Duser.timezone=GMT" sbt test

.github/workflows/tools.sh

@@ -0,0 +1,72 @@
+#!/bin/bash
+
+# SPDX-FileCopyrightText: 2023 "Everybody"
+#
+# SPDX-License-Identifier: MIT
+
+install_verilator(){
+  sudo apt-get update
+  sudo apt install -y git make autoconf g++ flex libfl-dev bison  # First time prerequisites
+  git clone http://git.veripool.org/git/verilator   # Only first time
+  unset VERILATOR_ROOT  # For bash
+  cd verilator
+  git pull        # Make sure we're up-to-date
+  git checkout v4.216
+  autoconf        # Create ./configure script
+  ./configure --prefix ~/tools
+  make -j$(nproc)
+  make install
+  cd ..
+}
+
+
+
+install_NaxSoftware(){
+  (cd $VEXIIRISCV/ext/NaxSoftware  && ./init.sh)
+}
+
+install_spike(){
+  cd $VEXIIRISCV/ext/riscv-isa-sim
+  mkdir build
+  cd build
+  ../configure --prefix=$RISCV --enable-commitlog --without-boost --without-boost-asio --without-boost-regex
+  make -j$(nproc)
+}
+
+
+install_rvls(){
+  cd $VEXIIRISCV/ext/rvls
+  make -j$(nproc)
+  cp -f build/apps/rvls.so ~/tools/rvls.so
+}
+
+
+install_elfio(){
+  git clone https://github.com/serge1/ELFIO.git
+  cd ELFIO
+  git checkout d251da09a07dff40af0b63b8f6c8ae71d2d1938d # Avoid C++17
+  sudo cp -R elfio /usr/include
+  cd ..
+}
+
+install_packages(){
+  sudo apt-get update
+  sudo apt install -y zlib1g-dev libboost-all-dev libboost-dev libasio-dev device-tree-compiler libsdl2-2.0-0 libsdl2-dev
+  install_elfio
+}
+
+install_uncached(){
+  export VEXIIRISCV=${PWD}
+  install_NaxSoftware
+
+  mkdir -p $VEXIIRISCV/ext/rvls/build/apps
+  cp -f ~/tools/rvls.so $VEXIIRISCV/ext/rvls/build/apps/rvls.so
+}
+
+install_cached(){
+  export VEXIIRISCV=${PWD}
+  mkdir -p ~/tools
+  (install_spike)
+  (install_rvls)
+  (install_verilator)
+}

README.md

@@ -10,6 +10,10 @@ VexiiRiscv is a from scratch second iteration of VexRiscv. Here are the targets
 - Cleaning implementation, especially the frontend
 - ...
 
+There is a online documentation (early stage, WIP) : 
+
+- https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Introduction/VexiiRiscv.html
+
 # Dependencies
 
 ```shell

src/main/scala/spinal/lib/misc/database/DataBase.scala

@@ -46,8 +46,10 @@ abstract class Element[T](sp: ScopeProperty[Database] = Database) extends Nameab
   def get : T = getOn(sp.get)
   def apply: T = getOn(sp.get)
   def set(value: T): Unit = set(sp.get, value)
+  def isEmpty : Boolean = isEmpty(sp.get)
 
   // private API
+  def isEmpty(db: Database) : Boolean
   def getOn(db: Database) : T
   def set(db: Database, value: T) : Unit
 }
@@ -56,6 +58,7 @@ abstract class Element[T](sp: ScopeProperty[Database] = Database) extends Nameab
 class ElementValue[T](sp : ScopeProperty[Database] = Database) extends Element[T](sp) {
   def getOn(db: Database): T = db.storageGet(this)
   def set(db: Database, value: T) = db.storageUpdate(this, value)
+  override def isEmpty(db: Database): Boolean = ???
 }
 
 // Layered with a handle to allow blocking "get"
@@ -67,6 +70,7 @@ class ElementBlocking[T](sp : ScopeProperty[Database] = Database) extends Elemen
     assert(!getHandle(db).isLoaded)
     getHandle(db).load(value)
   }
+  override def isEmpty(db: Database): Boolean = !getHandle(db).isLoaded
 }
 
 // The body provide the processing to generate the value

src/main/scala/vexiiriscv/Param.scala

@@ -31,6 +31,7 @@ class ParamSimple(){
   var withLateAlu = false
   var withMul = true
   var withDiv = true
+  var privParam = PrivilegedParam.base
   var relaxedBranch = false
   var relaxedShift = false
   var relaxedSrc = false
@@ -40,8 +41,8 @@ class ParamSimple(){
   //  Debug modifiers
   val debugParam = sys.env.getOrElse("VEXIIRISCV_DEBUG_PARAM", "0").toInt.toBoolean
   if(debugParam) {
-    decoders = 1
-    lanes = 1
+    decoders = 2
+    lanes = 2
     regFileSync = false
     withGShare = true
     withBtb = true
@@ -54,13 +55,15 @@ class ParamSimple(){
     relaxedShift = false
     relaxedSrc = true
     performanceCounters = 4
+    privParam.withSupervisor = true
+    privParam.withUser = true
   }
 
 
   def getName() : String = {
     def opt(that : Boolean, v : String) = that.mux(v, "")
     val r = new ArrayBuffer[String]()
-    r += s"rv${xlen}im"
+    r += s"rv${xlen}im${privParam.withSupervisor.mux("s","")}${privParam.withUser.mux("u","")}"
     r += s"d${decoders}"
     r += s"l${lanes}"
     r += regFileSync.mux("rfs","rfa")
@@ -87,6 +90,8 @@ class ParamSimple(){
     opt[Unit]("relaxed-src") action { (v, c) => relaxedSrc = true }
     opt[Unit]("with-mul") action { (v, c) => withMul = true }
     opt[Unit]("with-div") action { (v, c) => withDiv = true }
+    opt[Unit]("with-supervisor") action { (v, c) => privParam.withSupervisor = true; privParam.withUser = true }
+    opt[Unit]("with-user") action { (v, c) => privParam.withUser = true }
     opt[Unit]("without-mul") action { (v, c) => withMul = false }
     opt[Unit]("without-div") action { (v, c) => withDiv = false }
     opt[Unit]("with-gshare") action { (v, c) => withGShare = true }
@@ -98,11 +103,12 @@ class ParamSimple(){
     opt[Int]("performance-counters") action { (v, c) => performanceCounters = v }
   }
 
-  def plugins() = {
+  def plugins() = pluginsArea.plugins
+  def pluginsArea() = new Area {
     val plugins = ArrayBuffer[Hostable]()
     if(withLateAlu) assert(allowBypassFrom == 0)
 
-    plugins += new riscv.RiscvPlugin(xlen, rvc, hartCount)
+    plugins += new riscv.RiscvPlugin(xlen, hartCount)
     withMmu match {
       case false => plugins += new memory.StaticTranslationPlugin(32, ioRange, fetchRange)
       case true =>
@@ -209,7 +215,7 @@ class ParamSimple(){
     plugins += new CsrRamPlugin()
     plugins += new PerformanceCounterPlugin(additionalCounterCount = performanceCounters)
     plugins += new CsrAccessPlugin(early0, writeBackKey =  if(lanes == 1) "lane0" else "lane1")
-    plugins += new PrivilegedPlugin(PrivilegedParam.full, 0 until hartCount, trapAt = 2)
+    plugins += new PrivilegedPlugin(privParam, 0 until hartCount, trapAt = 2)
     plugins += new EnvPlugin(early0, executeAt = 0)
 
     if(withLateAlu) {
@@ -251,8 +257,6 @@ class ParamSimple(){
     }
 
     plugins += new WhiteboxerPlugin()
-
-    plugins
   }
 }
 

src/main/scala/vexiiriscv/execute/BarrelShifterPlugin.scala

@@ -26,8 +26,7 @@ class BarrelShifterPlugin(val layer : LaneLayer,
     awaitBuild()
     import SrcKeys._
 
-    val wb = ifp.access(formatAt)
-    implicit val _ = ifp -> wb
+    val wb = newWriteback(ifp, formatAt)
 
     //TODO why using SRC1 ? why not directly RS1 => less combinatorial path, also not sure about SRC2 is realy wort it (for only 5/ 6 bits)
     add(Rvi.SLL).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> True, SIGNED -> False)
@@ -54,7 +53,7 @@ class BarrelShifterPlugin(val layer : LaneLayer,
 
     uopRetainer.release()
 
-    val shift = new eu.Execute(shiftAt) {
+    val shift = new el.Execute(shiftAt) {
       val ss = SrcStageables
       val amplitude = srcp.SRC2(log2Up(Riscv.XLEN.get) - 1 downto 0).asUInt
       val reversed = Mux[SInt](LEFT, srcp.SRC1.reversed, srcp.SRC1)
@@ -73,7 +72,7 @@ class BarrelShifterPlugin(val layer : LaneLayer,
       SHIFT_RESULT := B(patched)
     }
 
-    val format = new eu.Execute(formatAt) {
+    val format = new el.Execute(formatAt) {
       wb.valid := SEL
       wb.payload := SHIFT_RESULT
     }

src/main/scala/vexiiriscv/execute/BranchPlugin.scala

@@ -16,7 +16,7 @@ import vexiiriscv.decode.Decode
 import vexiiriscv.fetch.{Fetch, PcPlugin}
 import vexiiriscv.misc.{PerformanceCounterService, TrapService}
 import vexiiriscv.prediction.Prediction.BRANCH_HISTORY_WIDTH
-import vexiiriscv.prediction.{FetchWordPrediction, HistoryPlugin, HistoryUser, LearnCmd, LearnService, Prediction}
+import vexiiriscv.prediction.{FetchWordPrediction, HistoryPlugin, HistoryUser, LearnCmd, LearnService, LearnSource, Prediction}
 import vexiiriscv.schedule.{DispatchPlugin, ReschedulePlugin}
 
 import scala.collection.mutable
@@ -31,10 +31,11 @@ object BranchPlugin extends AreaObject {
 class BranchPlugin(val layer : LaneLayer,
                    var aluAt : Int = 0,
                    var jumpAt: Int = 1,
-                   var wbAt: Int = 0) extends ExecutionUnitElementSimple(layer) {
+                   var wbAt: Int = 0) extends ExecutionUnitElementSimple(layer) with LearnSource {
   import BranchPlugin._
 
   def catchMissaligned = !Riscv.RVC
+  override def getLearnPort(): Option[Stream[LearnCmd]] = logic.jumpLogic.learn
 
   val logic = during setup new Logic{
     val wbp = host.find[WriteBackPlugin](_.laneName == layer.el.laneName)
@@ -79,7 +80,7 @@ class BranchPlugin(val layer : LaneLayer,
       spec.mayFlushUpTo(jumpAt)
     }
 
-    val age = eu.getExecuteAge(jumpAt)
+    val age = el.getExecuteAge(jumpAt)
     val pcPort = pcp.newJumpInterface(age, laneAgeWidth = Execute.LANE_AGE_WIDTH, aggregationPriority = 0)
     val historyPort = hp.map(_.newPort(age, Execute.LANE_AGE_WIDTH))
     val flushPort = sp.newFlushPort(age, laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
@@ -92,7 +93,7 @@ class BranchPlugin(val layer : LaneLayer,
     // leading to a simpler design.
     val withBtb = host.get[FetchWordPrediction].nonEmpty
 
-    val alu = new eu.Execute(aluAt) {
+    val alu = new el.Execute(aluAt) {
       val ss = SrcStageables
       val EQ = insert(srcp.SRC1 === srcp.SRC2)
 
@@ -136,7 +137,7 @@ class BranchPlugin(val layer : LaneLayer,
       }
     }
 
-    val jumpLogic = new eu.Execute(jumpAt) {
+    val jumpLogic = new el.Execute(jumpAt) {
       val wrongCond = withBtb.mux[Bool](Prediction.ALIGNED_JUMPED =/= alu.COND     , alu.COND )
       val needFix   = withBtb.mux[Bool](wrongCond || alu.COND && alu.btb.BAD_TARGET, wrongCond)
       val doIt = isValid && SEL && needFix
@@ -234,7 +235,7 @@ class BranchPlugin(val layer : LaneLayer,
 
     }
 
-    val wbLogic = new eu.Execute(wbAt){
+    val wbLogic = new el.Execute(wbAt){
       wb.valid := SEL && Decode.rfaKeys.get(RD).ENABLE
       wb.payload := alu.PC_FALSE.asBits.resized //PC RESIZED
     }

src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala

@@ -51,7 +51,7 @@ class CsrAccessPlugin(layer : LaneLayer,
   override def onReadHartId: UInt = apiIo.onReadHartId
   override def onReadHalt(): Unit = apiIo.onReadHalt := True
 
-  override def onReadToWriteBits: Bits = ???
+  override def onReadToWriteBits: Bits = apiIo.onReadToWriteBits
 
   override def isWriting: Bool = apiIo.isWriting
   override def onWriteHalt(): Unit = apiIo.onWriteHalt := True
@@ -177,14 +177,15 @@ class CsrAccessPlugin(layer : LaneLayer,
 
         assert(!(up(LANE_SEL) && SEL && hasCancelRequest), "CsrAccessPlugin saw forbidden select && cancel request")
         val imm = IMM(UOP)
+        val csrAddress = UOP(Const.csrRange)
         val immZero = imm.z === 0
         val srcZero = CSR_IMM ? immZero otherwise UOP(Const.rs1Range) === 0
         val csrWrite = !(CSR_MASK && srcZero)
         val csrRead = !(!CSR_MASK && !rd.ENABLE)
         val sels = grouped.map(e => e._1 -> Bool().setName("COMB_CSR_" + filterToName(e._1)))
         for ((filter, sel) <- sels) sel := (filter match {
-          case filter: Int => UOP(Const.csrRange) === filter
-          case filter: CsrListFilter => filter.mapping.map(UOP(Const.csrRange) === _).orR
+          case filter: Int => csrAddress === filter
+          case filter: CsrListFilter => filter.mapping.map(csrAddress === _).orR
         })
         val implemented = sels.values.orR
 
@@ -222,7 +223,7 @@ class CsrAccessPlugin(layer : LaneLayer,
         apiIo.onDecodeRead := csrRead
         apiIo.onDecodeWrite := csrWrite
         apiIo.onDecodeHartId := Global.HART_ID
-        apiIo.onDecodeAddress := UOP(Const.csrRange).asUInt
+        apiIo.onDecodeAddress := csrAddress.asUInt
 
         val iLogic = integrated generate new Area{
           connectRegs()