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SpinalHDL · Feb 8, 2024 · da9723d · da9723d
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commit da9723d
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diff --git a/src/main/scala/vexiiriscv/execute/BarrelShifterPlugin.scala b/src/main/scala/vexiiriscv/execute/BarrelShifterPlugin.scala
@@ -28,7 +28,6 @@ class BarrelShifterPlugin(val layer : LaneLayer,
 
     val wb = newWriteback(ifp, formatAt)
 
-    //TODO why using SRC1 ? why not directly RS1 => less combinatorial path, also not sure about SRC2 is realy wort it (for only 5/ 6 bits)
     add(Rvi.SLL).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> True, SIGNED -> False)
     add(Rvi.SRL).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> False, SIGNED -> False)
     add(Rvi.SRA).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> False, SIGNED -> True)

diff --git a/src/main/scala/vexiiriscv/execute/IterativeShiftPlugin.scala b/src/main/scala/vexiiriscv/execute/IterativeShiftPlugin.scala
@@ -51,7 +51,6 @@ class IterativeShifterPlugin(val layer: LaneLayer,
     val wb = newWriteback(ifp, formatAt)
 
     // we use RS1 directly, keep SRC1.RF source here for hazard detection
-    // TODO not sure about SRC2 is really worth it (for only 5/ 6 bits)
     add(Rvi.SLL).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> True, ARITHMETIC -> False)
     add(Rvi.SRL).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> False, ARITHMETIC -> False)
     add(Rvi.SRA).srcs(SRC1.RF, SRC2.RF).decode(LEFT -> False, ARITHMETIC -> True)