diff --git a/.gitignore b/.gitignore index c0f7f579..81903d39 100644 --- a/.gitignore +++ b/.gitignore @@ -63,3 +63,6 @@ regression/ tmp/ /archive.tar.gz *.out32 + +vnc_done +docker_xfce4.lop diff --git a/README.md b/README.md index fe07b4dc..bd2f9699 100644 --- a/README.md +++ b/README.md @@ -24,3 +24,24 @@ Here is the online documentation : A roadmap is available here : - https://github.com/SpinalHDL/VexiiRiscv/issues/1 + +# TL;DR Getting started + +The quickest way for getting started is to pull the Docker image with all the dependencies installed + +Please refer to the self contained tutorial for a comprehensive step by step instruction manual with +screenshots: https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Tutorial/index.html + +After running the generation you'll find a file named "VexiiRiscv.v" in the root +of the repository folder, which you can drag into your Quartus or whatever. + +We decided to not start covering FPGA boards because there's just too many, so it's up to you +to define your pin configuration for your specific FPGA board + +If you want to know what else you can do with sbt, please refer to the complete documentation. + +# Rebuild the Docker container + +In case you wanna rebuild leviathan's Docker container you can run + + docker build . -f docker/Dockerfile -t vexiiriscv --progress=plain diff --git a/docker/Dockerfile b/docker/Dockerfile new file mode 100644 index 00000000..ed3c18e2 --- /dev/null +++ b/docker/Dockerfile @@ -0,0 +1,97 @@ +FROM leviathanch/riscv-toolchain as build + +COPY docker/sbt.asc /root/sbt.asc + +RUN apt-get update +RUN apt install -y software-properties-common +RUN add-apt-repository -y ppa:openjdk-r/ppa +RUN apt-get update + +# Add SBT repo +RUN echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | tee /etc/apt/sources.list.d/sbt.list +RUN echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | tee /etc/apt/sources.list.d/sbt_old.list + +RUN apt-key add /root/sbt.asc +RUN apt-get update +RUN apt-get install -y \ + openjdk-21-jdk \ + sbt \ + gtkwave \ + nodejs \ + npm \ + libgtk-3-0 \ + libxss1 \ + libnss3 \ + libx11-xcb1 \ + libcanberra-gtk3-module \ + xvfb \ + x11vnc \ + xfce4 \ + git \ + make \ + autoconf \ + g++ \ + flex \ + bison \ + help2man \ + device-tree-compiler \ + libboost-all-dev \ + dbus-x11 \ + sudo \ + wget \ + gosu + +WORKDIR /root +RUN git clone https://github.com/verilator/verilator.git +WORKDIR verilator +RUN autoconf +RUN ./configure +RUN make -j2 +RUN make install +WORKDIR /root +RUN rm -rf verilator + +WORKDIR /root +RUN git clone https://github.com/serge1/ELFIO.git +WORKDIR ELFIO +RUN git checkout d251da09a07dff40af0b63b8f6c8ae71d2d1938d +RUN mkdir -p /usr/include && cp -r elfio /usr/include/elfio +RUN chown ubuntu -R /usr/include/elfio && chmod 0777 -R /usr/include/elfio +WORKDIR /root +RUN rm -rf ELFIO + +WORKDIR /root +RUN rm /root/sbt.asc +ENV DISPLAY=:1 + +COPY docker/fix_fesvr.patch /home/ubuntu/fix_fesvr.patch +RUN chown ubuntu /home/ubuntu/fix_fesvr.patch +COPY docker/setup_userspace.sh /home/ubuntu/setup_userspace.sh +COPY docker/fix_userid.sh /root/fix_userid.sh +COPY docker/init_graphics.sh /home/ubuntu/init_graphics.sh +COPY docker/Konata.desktop /usr/share/applications/Konata.desktop + +COPY docker/setup_intellij.sh /root/setup_intellij.sh + +RUN chmod 0777 /home/ubuntu/setup_userspace.sh \ + /root/fix_userid.sh \ + /home/ubuntu/init_graphics.sh + +RUN gosu ubuntu /home/ubuntu/setup_userspace.sh +RUN cd /home/ubuntu/VexiiRiscv/ext/riscv-isa-sim/build && make install + +WORKDIR /root +RUN bash /root/setup_intellij.sh +RUN rm /root/setup_intellij.sh +RUN mkdir -p /home/ubuntu/Desktop +RUN ln -s /usr/share/applications/IDEA.desktop /home/ubuntu/Desktop/IDEA.desktop +RUN ln -s /usr/share/applications/Konata.desktop /home/ubuntu/Desktop/Konata.desktop + +COPY docker/generate_verilog.sh /home/ubuntu/ +COPY docker/run_simulation.sh /home/ubuntu/ + +RUN chown ubuntu /home/ubuntu/*.sh +RUN chmod 0777 /home/ubuntu/*.sh + +WORKDIR /work +ENTRYPOINT /root/fix_userid.sh && gosu ubuntu /home/ubuntu/init_graphics.sh diff --git a/docker/Konata.desktop b/docker/Konata.desktop new file mode 100644 index 00000000..2d072db1 --- /dev/null +++ b/docker/Konata.desktop @@ -0,0 +1,11 @@ +[Desktop Entry] +Version=1.0 +Type=Application +Name=Konata +Comment=The Viewer +Exec=/bin/bash -c "cd /home/ubuntu/konata && make" +Icon= +Path=/work +Terminal=false +StartupNotify=false +GenericName=Konata Viewer diff --git a/docker/fix_fesvr.patch b/docker/fix_fesvr.patch new file mode 100644 index 00000000..f8b181e5 --- /dev/null +++ b/docker/fix_fesvr.patch @@ -0,0 +1,12 @@ +diff --git a/fesvr/device.h b/fesvr/device.h +index 1387b745..639b8374 100644 +--- a/fesvr/device.h ++++ b/fesvr/device.h +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + + class memif_t; + diff --git a/docker/fix_userid.sh b/docker/fix_userid.sh new file mode 100644 index 00000000..15144021 --- /dev/null +++ b/docker/fix_userid.sh @@ -0,0 +1,12 @@ +#!/bin/bash +nuid=$(stat -c "%u" /work) +ouid=$(id -u ubuntu) + +if [ "$nuid" -ne "$ouid" ]; then + echo "Adjusting user access rights... please wait" + usermod -u $nuid ubuntu + chown ubuntu -R /home/ubuntu +fi + +chown root /home/ubuntu/konata/node_modules/electron/dist/chrome-sandbox +chmod 4755 /home/ubuntu/konata/node_modules/electron/dist/chrome-sandbox diff --git a/docker/generate_verilog.sh b/docker/generate_verilog.sh new file mode 100644 index 00000000..3cd3cdef --- /dev/null +++ b/docker/generate_verilog.sh @@ -0,0 +1,2 @@ +#!/bin/bash +sbt "Test/runMain vexiiriscv.Generate" diff --git a/docker/init_graphics.sh b/docker/init_graphics.sh new file mode 100644 index 00000000..cb706b21 --- /dev/null +++ b/docker/init_graphics.sh @@ -0,0 +1,9 @@ +#!/bin/bash +Xvfb :1 -screen 0 1024x768x16 &> /work/xvfb.log & +until pids=$(pidof Xvfb) +do + sleep 1 +done +x11vnc -display :1 -bg -forever -nopw -quiet -xkb +touch /work/vnc_done +startxfce4 &> /work/docker_xfce4.lop diff --git a/docker/run_simulation.sh b/docker/run_simulation.sh new file mode 100644 index 00000000..a4a7d7f9 --- /dev/null +++ b/docker/run_simulation.sh @@ -0,0 +1,2 @@ +#!/bin/bash +sbt "Test/runMain vexiiriscv.tester.TestBench --with-mul --with-div --load-elf ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf --trace-all" diff --git a/docker/sbt.asc b/docker/sbt.asc new file mode 100644 index 00000000..aff595bf --- /dev/null +++ b/docker/sbt.asc @@ -0,0 +1,53 @@ +-----BEGIN PGP PUBLIC KEY BLOCK----- +Comment: Hostname: +Version: Hockeypuck 2.2 + +xsFNBFVo8ucBEADTNUhKCz/6031bXPy1EOMk3qmsRp1ZIbLNN+KGFEE02qt3/4Hd +B2QtrHu1XK/ZZfD84d/RywMj/A14ESBxqaPa4uStOBUeU38+gV05b4Y/jvJ1x4wD +kCH+FTz0HlrLpwq/UQEWTX1vTH9wLQQXDcgngs45fVdGe5RDNtvnsd1pP4rp4ZTE +jqIJl2fRLd9Jd1uNGv1s9QaLKOVHkprzhphVWil16ET5wIdwivPdi7PFFJv94gXP +gbduYZiAYUdywkXHPS18s/6qWMgKcg718rn0orC6oA+zgbUzEJYHqI2OV7HFTzMw +/m+tfifWf7dgroOMFtQi5BRzMMoeVOtDXNsOTD9gv5WhzrfyfyLUgnb+nAyH1jHH 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"$@" + +# define version (ultimate. change to 'C' for Community) +ed='C' + +# Fetch the most recent community edition URL +VERSION=$(wget "https://www.jetbrains.com/intellij-repository/releases" -qO- | grep -P -o -m 1 "(?<=https://www.jetbrains.com/intellij-repository/releases/com/jetbrains/intellij/idea/BUILD/)[^/]+(?=/)") +URL="https://download.jetbrains.com/idea/ideaI$ed-$VERSION.tar.gz" + +echo "URL: ${URL}" +echo "basename(url): $(basename ${URL})" + +# Truncate filename +FILE=$(basename ${URL}) + +echo "File: ${FILE}" + +# Download binary +wget -cO /tmp/${FILE} ${URL} --read-timeout=5 --tries=0 + +# Set directory name +DIR="${FILE%\.tar\.gz}" + +# Untar file +mkdir -p /opt/${DIR} +tar -xvzf /tmp/${FILE} -C /opt/${DIR} --strip-components=1 + +# Grab executable folder +BIN="/opt/$DIR/bin" + +# Add permissions to install directory +chmod 755 ${BIN}/idea.sh + +# Set desktop shortcut path +DESK=/usr/share/applications/IDEA.desktop + +# Add desktop shortcut +echo -e "[Desktop Entry]\nEncoding=UTF-8\nName=IntelliJ IDEA\nComment=IntelliJ IDEA\nExec=${BIN}/idea.sh\nIcon=${BIN}/idea.png\nTerminal=false\nStartupNotify=true\nType=Application" > ${DESK} +chmod 644 ${DESK} + +echo "Done." diff --git a/docker/setup_userspace.sh b/docker/setup_userspace.sh new file mode 100644 index 00000000..df95c786 --- /dev/null +++ b/docker/setup_userspace.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +cd /home/ubuntu + +git clone --recursive https://github.com/SpinalHDL/VexiiRiscv.git + +pushd VexiiRiscv/ext/riscv-isa-sim/fesvr +echo "Patching fesvr" +git apply /home/ubuntu/fix_fesvr.patch +popd + +mkdir VexiiRiscv/ext/riscv-isa-sim/build +pushd VexiiRiscv/ext/riscv-isa-sim/build +../configure --prefix=/opt/riscv --enable-commitlog --without-boost --without-boost-asio --without-boost-regex +make +popd + +pushd VexiiRiscv/ext/rvls +make +popd + +pushd VexiiRiscv +sbt update +popd + +git clone https://github.com/shioyadan/konata.git +pushd konata +npm install +popd diff --git a/log b/log deleted file mode 100644 index f8f36089..00000000 --- a/log +++ /dev/null @@ -1,1216 +0,0 @@ -[Progress] Start VexiiRiscv_rv64imsu_d1_l1_rfa_bp0_btb_ras_gshare_la_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000116] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003317] Console: colour dummy device 80x25 -[ 0.004434] printk: console [hvc0] enabled -[ 0.004434] printk: console [hvc0] enabled -[ 0.006377] printk: bootconsole [sbi0] disabled -[ 0.006377] printk: bootconsole [sbi0] disabled -[ 0.008569] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.011119] pid_max: default: 32768 minimum: 301 -[ 0.013887] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.015746] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=470655550 -INTEGER WRITE MISSMATCH DUT=c REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d1_l1_rfa_bp0_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000115] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003314] Console: colour dummy device 80x25 -[ 0.004432] printk: console [hvc0] enabled -[ 0.004432] printk: console [hvc0] enabled -[ 0.006370] printk: bootconsole [sbi0] disabled -[ 0.006370] printk: bootconsole [sbi0] disabled -[ 0.008565] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.011115] pid_max: default: 32768 minimum: 301 -[ 0.013902] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.015760] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=471451830 -INTEGER WRITE MISSMATCH DUT=39 REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d1_l1_rfa_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000123] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003501] Console: colour dummy device 80x25 -[ 0.004675] printk: console [hvc0] enabled -[ 0.004675] printk: console [hvc0] enabled -[ 0.006706] printk: bootconsole [sbi0] disabled -[ 0.006706] printk: bootconsole [sbi0] disabled -[ 0.008998] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.011684] pid_max: default: 32768 minimum: 301 -[ 0.014658] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.016612] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=485859680 -INTEGER WRITE MISSMATCH DUT=33 REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d1_l1_rfs_bp0_btb_ras_gshare_la_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000116] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003340] Console: colour dummy device 80x25 -[ 0.004465] printk: console [hvc0] enabled -[ 0.004465] printk: console [hvc0] enabled -[ 0.006420] printk: bootconsole [sbi0] disabled -[ 0.006420] printk: bootconsole [sbi0] disabled -[ 0.008632] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.011212] pid_max: default: 32768 minimum: 301 -[ 0.014045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.015923] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=469183040 -INTEGER WRITE MISSMATCH DUT=4e REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d1_l1_rfs_bp0_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000118] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003343] Console: colour dummy device 80x25 -[ 0.004471] printk: console [hvc0] enabled -[ 0.004471] printk: console [hvc0] enabled -[ 0.006433] printk: bootconsole [sbi0] disabled -[ 0.006433] printk: bootconsole [sbi0] disabled -[ 0.008641] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.011226] pid_max: default: 32768 minimum: 301 -[ 0.014062] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.015944] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=470147600 -INTEGER WRITE MISSMATCH DUT=ffffffffffffff8b REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d1_l1_rfs_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000132] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003708] Console: colour dummy device 80x25 -[ 0.004939] printk: console [hvc0] enabled -[ 0.004939] printk: console [hvc0] enabled -[ 0.007075] printk: bootconsole [sbi0] disabled -[ 0.007075] printk: bootconsole [sbi0] disabled -[ 0.009489] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.012309] pid_max: default: 32768 minimum: 301 -[ 0.015509] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.017555] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=499244700 -INTEGER WRITE MISSMATCH DUT=ffffffffffffffd6 REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d2_l2_rfa_bp0_btb_ras_gshare_la_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[Progress] Start VexiiRiscv_rv64imsu_d2_l2_rfa_bp0_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000078] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.002272] Console: colour dummy device 80x25 -[ 0.003053] printk: console [hvc0] enabled -[ 0.003053] printk: console [hvc0] enabled -[ 0.004338] printk: bootconsole [sbi0] disabled -[ 0.004338] printk: bootconsole [sbi0] disabled -[ 0.005950] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.007653] pid_max: default: 32768 minimum: 301 -[ 0.009589] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.010888] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=360996460 -INTEGER WRITE MISSMATCH DUT=6a REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d2_l2_rfs_bp0_btb_ras_gshare_la_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000080] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.002272] Console: colour dummy device 80x25 -[ 0.003054] printk: console [hvc0] enabled -[ 0.003054] printk: console [hvc0] enabled -[ 0.004343] printk: bootconsole [sbi0] disabled -[ 0.004343] printk: bootconsole [sbi0] disabled -[ 0.005968] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.007674] pid_max: default: 32768 minimum: 301 -[ 0.009631] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.010939] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=358286940 -INTEGER WRITE MISSMATCH DUT=ffffffffffffff97 REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d2_l2_rfs_bp0_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000082] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.002304] Console: colour dummy device 80x25 -[ 0.003096] printk: console [hvc0] enabled -[ 0.003096] printk: console [hvc0] enabled -[ 0.004400] printk: bootconsole [sbi0] disabled -[ 0.004400] printk: bootconsole [sbi0] disabled -[ 0.006043] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.007783] pid_max: default: 32768 minimum: 301 -[ 0.009779] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.011103] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=361517370 -INTEGER WRITE MISSMATCH DUT=ffffffffffffff97 REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) -[Progress] Start VexiiRiscv_rv64imsu_d2_l2_rfs_btb_ras_gshare_m_d_a buildroot simulation with seed 2 - -OpenSBI v0.8 - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - -Platform Name : NaxRiscv -Platform Features : timer,mfdeleg -Platform HART Count : 1 -Boot HART ID : 0 -Boot HART ISA : rv64imasu -BOOT HART Features : scounteren,mcounteren -BOOT HART PMP Count : 0 -Firmware Base : 0x80000000 -Firmware Size : 72 KB -Runtime SBI Version : 0.2 - -MIDELEG : 0x0000000000000222 -MEDELEG : 0x000000000000b109 -[ 0.000000] Linux version 5.10.1 (rawrr@rawrr) (riscv64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2020.11-rc3-8-g9ef54b7d0b) 10.2.0, GNU ld (GNU Binutils) 2.34) #8 SMP Mon Mar 14 10:26:33 CET 2022 -[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') -[ 0.000000] printk: bootconsole [sbi0] enabled -[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (8388608 bytes) -[ 0.000000] Zone ranges: -[ 0.000000] DMA32 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Normal empty -[ 0.000000] Movable zone start for each node -[ 0.000000] Early memory node ranges -[ 0.000000] node 0: [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x000000008fffffff] -[ 0.000000] software IO TLB: mapped [mem 0x000000008bc8c000-0x000000008fc8c000] (64MB) -[ 0.000000] SBI specification v0.2 detected -[ 0.000000] SBI implementation ID=0x1 Version=0x8 -[ 0.000000] SBI v0.2 TIME extension detected -[ 0.000000] SBI v0.2 IPI extension detected -[ 0.000000] SBI v0.2 RFENCE extension detected -[ 0.000000] SBI v0.2 HSM extension detected -[ 0.000000] riscv: ISA extensions aim -[ 0.000000] riscv: ELF capabilities aim -[ 0.000000] percpu: Embedded 14 pages/cpu s25560 r0 d31784 u57344 -[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 63630 -[ 0.000000] Kernel command line: rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init -[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) -[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) -[ 0.000000] Sorting __ex_table... -[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off -[ 0.000000] Memory: 173364K/258048K available (4703K kernel code, 679K rwdata, 718K rodata, 176K init, 262K bss, 84684K reserved, 0K cma-reserved) -[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 -[ 0.000000] rcu: Hierarchical RCU implementation. -[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. -[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. -[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 -[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 -[ 0.000000] riscv-intc: 64 local interrupts mapped -[ 0.000000] random: get_random_bytes called from start_kernel+0x364/0x4f8 with crng_init=0 -[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] -[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns -[ 0.000111] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns -[ 0.003075] Console: colour dummy device 80x25 -[ 0.004085] printk: console [hvc0] enabled -[ 0.004085] printk: console [hvc0] enabled -[ 0.005718] printk: bootconsole [sbi0] disabled -[ 0.005718] printk: bootconsole [sbi0] disabled -[ 0.007790] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) -[ 0.009967] pid_max: default: 32768 minimum: 301 -[ 0.012796] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[ 0.014346] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) -[Error] Simulation failed at time=423770540 -INTEGER WRITE MISSMATCH DUT=ffffffffffffffb8 REF=0 -rvls.spinal.RvlsBackend.commit(Tracer.scala:196) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1$$anonfun$apply$11.apply(VexiiRiscvProbe.scala:530) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:530) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$checkCommits$1.apply(VexiiRiscvProbe.scala:486) -scala.collection.IndexedSeqOptimized$class.foreach(IndexedSeqOptimized.scala:33) -scala.collection.mutable.ArrayOps$ofRef.foreach(ArrayOps.scala:186) -vexiiriscv.test.VexiiRiscvProbe.checkCommits(VexiiRiscvProbe.scala:486) -vexiiriscv.test.VexiiRiscvProbe$$anonfun$3.apply$mcV$sp(VexiiRiscvProbe.scala:553) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:971) -scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59) -scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) -spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:971) -spinal.core.sim.package$$anon$1.update(package.scala:196) -spinal.sim.SimManager.runWhile(SimManager.scala:324) -spinal.sim.SimManager.runAll(SimManager.scala:246) -spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:608) -spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:581) -vexiiriscv.tester.TestOptions.test(TestBench.scala:155) -vexiiriscv.tester.RegressionSingle$$anonfun$18$$anon$4$$anonfun$$lessinit$greater$1.apply$mcV$sp(Regression.scala:225) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply$mcV$sp(MultithreadedTester.scala:25) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1$$anonfun$apply$mcV$sp$2.apply(MultithreadedTester.scala:24) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withErr(Console.scala:92) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply$mcV$sp(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -spinal.lib.misc.test.AsyncJob$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(MultithreadedTester.scala:23) -scala.util.DynamicVariable.withValue(DynamicVariable.scala:58) -scala.Console$.withOut(Console.scala:65) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply$mcV$sp(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -spinal.lib.misc.test.AsyncJob$$anonfun$1.apply(MultithreadedTester.scala:22) -scala.concurrent.impl.Future$PromiseCompletingRunnable.liftedTree1$1(Future.scala:24) -scala.concurrent.impl.Future$PromiseCompletingRunnable.run(Future.scala:24) -scala.concurrent.impl.ExecutionContextImpl$AdaptedForkJoinTask.exec(ExecutionContextImpl.scala:121) -scala.concurrent.forkjoin.ForkJoinTask.doExec(ForkJoinTask.java:260) -scala.concurrent.forkjoin.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1339) -scala.concurrent.forkjoin.ForkJoinPool.runWorker(ForkJoinPool.java:1979) -scala.concurrent.forkjoin.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:107) diff --git a/run_docker.sh b/run_docker.sh new file mode 100755 index 00000000..1d099ac5 --- /dev/null +++ b/run_docker.sh @@ -0,0 +1,13 @@ +#!/bin/bash +docker pull leviathanch/vexiiriscv +container_id=$(docker run -v `pwd`:/work --privileged=true -idt leviathanch/vexiiriscv) +address=$(docker inspect \ + -f '{{range.NetworkSettings.Networks}}{{.IPAddress}}{{end}}' $container_id) +echo "Waiting for the VNC server to come up" +rm -f vnc_done +until [ -f vnc_done ] +do + sleep 1 +done +echo "Address: [$address]" +vncviewer $address diff --git a/src/main/scala/vexiiriscv/execute/MulPlugin.scala b/src/main/scala/vexiiriscv/execute/MulPlugin.scala index 5fed60e7..42fc31e0 100644 --- a/src/main/scala/vexiiriscv/execute/MulPlugin.scala +++ b/src/main/scala/vexiiriscv/execute/MulPlugin.scala @@ -192,7 +192,7 @@ class MulPlugin(val layer : LaneLayer, // case true => stage(sourceToSignal(sourcesSpec.head)).twoComplement(RESULT_IS_SIGNED) } val buffer = bufferedHigh.get generate new Area{ - val valid = RegNext(False) init (False) setWhen (isValid && !isReady && !isCancel) + val valid = RegNext(layer.lane.isFreezed()) init (False) val data = RegNext(result(XLEN, XLEN bits)) el.freezeWhen(isValid && HIGH && !valid) } diff --git a/src/main/scala/vexiiriscv/execute/cfu/CfuPlugin.scala b/src/main/scala/vexiiriscv/execute/cfu/CfuPlugin.scala index 41be2376..66675189 100644 --- a/src/main/scala/vexiiriscv/execute/cfu/CfuPlugin.scala +++ b/src/main/scala/vexiiriscv/execute/cfu/CfuPlugin.scala @@ -220,15 +220,13 @@ class CfuPlugin(val layer : LaneLayer, bus.cmd.reorder_id := 0 bus.cmd.request_id := 0 bus.cmd.raw_insn := Decode.UOP.resized - if(p.CFU_INPUTS >= 1) bus.cmd.inputs(0) := layer.lane(IntRegFile, RS1) + if(p.CFU_INPUTS >= 1) bus.cmd.inputs(0) := up(layer.lane(IntRegFile, RS1)) if(p.CFU_INPUTS >= 2) bus.cmd.inputs(1) := CFU_INPUT_2_KIND.mux[Bits]( - CfuPlugin.Input2Kind.RS -> layer.lane(IntRegFile, RS2), + CfuPlugin.Input2Kind.RS -> up(layer.lane(IntRegFile, RS2)), CfuPlugin.Input2Kind.IMM_I -> IMM(Decode.UOP).h_sext.asBits ) } val onJoin = new layer.Execute(joinAt) { - //If the CFU interface can produce a result combinatorialy and the fork stage isn't the same than the join stage - //Then it is required to add a buffer on rsp to not propagate the fork stage ready := False in the CPU pipeline. val busRspStream = bus.rsp.toFlow.toStream val rsp = busRspStream.queueLowLatency( size = joinAt-forkAt+1,