Got fetch l1 and lsu l1 to work in SoC

src/main/scala/vexiiriscv/execute/lsu/LsuCachelessBridge.scala

@@ -74,3 +74,19 @@ class LsuCachelessTileLinkPlugin(node : bus.tilelink.fabric.Node, hashWidth : In
     node.bus.component.rework(node.bus << bridge.down)
   }
 }
+
+
+
+class LsuTileLinkPlugin(node : bus.tilelink.fabric.Node, hashWidth : Int = 8) extends FiberPlugin {
+  val logic = during build new Area{
+    val lsucp = host[LsuPlugin]
+    lsucp.logic.bus.setAsDirectionLess()
+
+    val bridge = new LsuCachelessBusToTilelink(lsucp.logic.bus, hashWidth)
+    master(bridge.down)
+
+    node.m2s.forceParameters(bridge.m2sParam)
+    node.s2m.supported.load(S2mSupport.none())
+    node.bus.component.rework(node.bus << bridge.down)
+  }
+}

src/main/scala/vexiiriscv/execute/lsu/LsuL1Bridge.scala

@@ -0,0 +1,29 @@
+package vexiiriscv.execute.lsu
+
+import spinal.core._
+import spinal.lib._
+import spinal.lib.bus.tilelink
+import spinal.lib.bus.tilelink.{DebugId, S2mSupport}
+import spinal.lib.misc.plugin.FiberPlugin
+import vexiiriscv.execute.LsuL1Bus
+
+
+
+class LsuL1TileLinkPlugin(node : bus.tilelink.fabric.Node) extends FiberPlugin {
+  val logic = during setup new Area{
+    val lsucp = host[LsuL1Plugin]
+    lsucp.probeIdWidth = 0
+    lsucp.ackIdWidth = 0
+    assert(!lsucp.withCoherency)
+
+    awaitBuild()
+    lsucp.logic.bus.setAsDirectionLess()
+
+    val down = lsucp.logic.bus.toTilelink()
+    master(down)
+
+    node.m2s.forceParameters(down.p.node.m)
+    node.s2m.supported.load(S2mSupport.none())
+    node.bus.component.rework(node.bus << down)
+  }
+}

src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala

@@ -2,6 +2,7 @@ package vexiiriscv.execute.lsu
 
 import spinal.core._
 import spinal.core.fiber.Handle
+import spinal.core.sim.SimDataPimper
 import spinal.lib._
 import spinal.lib.misc.Plru
 import spinal.lib.misc.database.Database.blocking
@@ -127,7 +128,7 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
 
     assert(bankWidth <= memDataWidth)
 
-    val bus = master(LsuL1Bus(memParameter))
+    val bus = master(LsuL1Bus(memParameter)).simPublic()
 
     val WAYS_HAZARD = Payload(Bits(wayCount bits))
     val BANK_BUSY = Payload(Bits(bankCount bits))

src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala

@@ -2,6 +2,7 @@ package vexiiriscv.execute.lsu
 
 import spinal.core._
 import spinal.core.fiber.Handle
+import spinal.core.sim.SimDataPimper
 import spinal.lib._
 import spinal.lib.bus.tilelink.M2sTransfers
 import spinal.lib.fsm.{State, StateMachine}
@@ -98,7 +99,7 @@ class LsuPlugin(var layer : LaneLayer,
       withAmo = withRva,
       pendingMax = 1
     )
-    val bus = master(LsuCachelessBus(busParam))
+    val bus = master(LsuCachelessBus(busParam)).simPublic()
 
     accessRetainer.await()
     val l1 = LsuL1

src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala

@@ -19,7 +19,7 @@ import spinal.lib.sim.SparseMemory
 import spinal.lib.system.tag.{MemoryConnection, PMA, PmaRegion}
 import spinal.sim.{Signal, SimManagerContext}
 import vexiiriscv.{ParamSimple, VexiiRiscv}
-import vexiiriscv.execute.lsu.{LsuCachelessPlugin, LsuCachelessTileLinkPlugin, LsuL1Plugin}
+import vexiiriscv.execute.lsu.{LsuCachelessPlugin, LsuCachelessTileLinkPlugin, LsuL1Plugin, LsuL1TileLinkPlugin, LsuPlugin, LsuTileLinkPlugin}
 import vexiiriscv.fetch.{FetchCachelessPlugin, FetchCachelessTileLinkPlugin, FetchFetchL1TileLinkPlugin, FetchL1Plugin}
 import vexiiriscv.memory.AddressTranslationService
 import vexiiriscv.misc.PrivilegedPlugin
@@ -31,6 +31,7 @@ import scala.collection.mutable.ArrayBuffer
 class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area{
   val iBus = Node.down()
   val dBus = Node.down()
+  val lsuL1Bus = plugins.exists(_.isInstanceOf[LsuL1Plugin]) generate Node.down()
 
   val priv = plugins.collectFirst {
     case p: PrivilegedPlugin => new Area {
@@ -66,6 +67,8 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area{
     case p: FetchCachelessPlugin => plugins += new FetchCachelessTileLinkPlugin(iBus)
     case p: FetchL1Plugin => plugins += new FetchFetchL1TileLinkPlugin(iBus)
     case p: LsuCachelessPlugin => plugins += new LsuCachelessTileLinkPlugin(dBus)
+    case p: LsuPlugin => plugins += new LsuTileLinkPlugin(dBus)
+    case p: LsuL1Plugin => plugins += new LsuL1TileLinkPlugin(lsuL1Bus)
     case _ =>
   }
 
@@ -79,6 +82,8 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area{
       case p: FetchCachelessPlugin => p.regions.load(getRegion(iBus))
       case p: FetchL1Plugin => p.regions.load(getRegion(iBus))
       case p: LsuCachelessPlugin => p.regions.load(getRegion(dBus))
+      case p: LsuPlugin => p.ioRegions.load(getRegion(dBus))
+      case p: LsuL1Plugin => p.regions.load(getRegion(lsuL1Bus))
       case _ =>
     }