Improve litex SoC timings

SpinalHDL · Apr 8, 2024 · f657fa2 · f657fa2
1 parent b7dc4c1
commit f657fa2
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
@@ -54,7 +54,7 @@ class Soc(c : SocConfig, systemCd : ClockDomain) extends Component{
     val withCoherency = vexiiParam.lsuL1Coherency
     val vexiis = for (hartId <- 0 until cpuCount) yield new TilelinkVexiiRiscvFiber(vexiiParam.plugins(hartId))
     for (vexii <- vexiis) {
-      vexii.dBus.setDownConnection(a = StreamPipe.NONE, d = StreamPipe.M2S, b = StreamPipe.NONE, c = StreamPipe.NONE, e = StreamPipe.NONE)
+      vexii.dBus.setDownConnection(a = StreamPipe.NONE, d = StreamPipe.M2S, b = StreamPipe.NONE, c = StreamPipe.FULL, e = StreamPipe.NONE)
 //      nax.dBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S, b = StreamPipe.HALF, c = StreamPipe.FULL, e = StreamPipe.HALF)
 //      nax.iBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.M2S)
 //      nax.pBus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.HALF)