Add iterative shifter

[andreasWallner]

Reproduce issue with
Test/runMain vexiiriscv.tester.TestBench --load-elf ext/NaxSoftware/baremetal/coremark/build/rv32ima/coremark.elf --with-konata --with-wave --with-spike-log --with-rvls-log --decoders=2 --lanes=2 --allow-bypass-from=0 --with-btb --with-late-alu --with-mul --with-div --with-iterative-shift

[Dolu1990]

I think it is ok to wb.valid bad data (as long as the good data happen last)
So, you can do wb.valid := SEL to reduce logic to minimum

the wb interface itself is then checked for lane.valid + reschedule at the end point.

[Dolu1990]

I'm asking myself if maybe we could do a "smarter" design with the following hardware shifts :

• >> 1
• >> 8
• reverse all bits
• shift by zero case being emulated by doing 2 "reverse all bits"

That way we would have as many mux than now, but much high performance for big shifts, as we could compose shifts using the >> 8 and \ >> 1

In a more generic manner, the number of different >> X possible could be a parameter List[Int]

So, the design would be kinda much closer to the actual BarrelShifterPlugin, but over multiple cycles.

[Dolu1990]

only for 32 bits it works ^^

[Dolu1990]

Thanks :)