From 986b078f4a2c666b8a357cf6f0ed5507b373fa5d Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Tue, 27 Aug 2024 10:27:32 -0500 Subject: [PATCH 1/2] Leaving HE interrupt disabled during initial fill. This prevent un-intended interrupts, causing txCnt to exceend txLen. --- Libraries/PeriphDrivers/Source/UART/uart_revb.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index b3833007877..12bd11eb899 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -673,15 +673,18 @@ int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t *req) // Save TX Request AsyncTxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req; - MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_EN_TX_HE); + /* Leave the half empty interrupt flag cleared while we're writing */ numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt], numToWrite); - /* If we're finished writing to the TX FIFO, pend the interrupt */ if (req->txCnt == req->txLen) { + /* If we're finished writing to the TX FIFO, pend the interrupt */ NVIC_SetPendingIRQ(MXC_UART_GET_IRQ(uart_num)); + } else { + /* Else enable the half empty interrupt */ + MXC_UART_EnableInt((mxc_uart_regs_t *)(req->uart), MXC_F_UART_REVB_INT_EN_TX_HE); } } From 7337114ede86e31edd304dbb781305b9e38c7172 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Tue, 27 Aug 2024 10:39:59 -0500 Subject: [PATCH 2/2] Clarifying comment. --- Libraries/PeriphDrivers/Source/UART/uart_revb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index 12bd11eb899..14fa8856420 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -673,7 +673,7 @@ int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t *req) // Save TX Request AsyncTxRequests[MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart))] = (void *)req; - /* Leave the half empty interrupt flag cleared while we're writing */ + /* Leave the half empty interrupt disabled while we're writing */ numToWrite = MXC_UART_GetTXFIFOAvailable((mxc_uart_regs_t *)(req->uart)); numToWrite = numToWrite > (req->txLen - req->txCnt) ? req->txLen - req->txCnt : numToWrite; req->txCnt += MXC_UART_WriteTXFIFO((mxc_uart_regs_t *)(req->uart), &req->txData[req->txCnt],