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Verilog Netlist Issues #16

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emonlux opened this issue Aug 2, 2022 · 1 comment
Closed

Verilog Netlist Issues #16

emonlux opened this issue Aug 2, 2022 · 1 comment

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@emonlux
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emonlux commented Aug 2, 2022

  • \ and space char need to be removed before replication and re-inserted before composing
  • primitive_databases is set up for edf, it would be nice for the database to be more generic
    • to get the verilog netlist to insert voters the primitive_library_name has to be changed to SDN.verilog_primitives
    • temp fix - update the prim_lib_name to match verilog netlists
  • properties are not being assigned to voters when using apply_tmr_to_netlist()
@jacobdbrown4
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jacobdbrown4 commented Apr 24, 2023

With the most recent update to SpyDrNet, the first bullet point (the space at the end of Verilog) should no longer be an issue. But it is something to be aware of when using older versions of SpyDrNet.

The third bullet point is directly related to #20. A temporary fix has been made by making different voters for each netlist type. See here in the documentation. When one passes the voter type object to voter insertion, the netlist type can be passed as well (as an option in the voter object). For example:

XilinxTMRVoter(VERILOG)

will make sure the properties are in the format that Verilog netlists have.

XilinxTMRVoter()

will do the same thing but for EDIF netlists. The default type is EDIF so no parameter needed to be passed.

The same thing can be done for EBLIF netlists.

Note that the above is a fix, but not perfect. A better fix would be to make the way how SpyDrNet stores internal netlist properties more generic so netlist type does not matter. See #20.

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