diff --git a/ci-tools/fpga-image/boot.scr b/ci-tools/fpga-image/boot.scr
index b587581cb2..5262e8ec4d 100644
--- a/ci-tools/fpga-image/boot.scr
+++ b/ci-tools/fpga-image/boot.scr
@@ -1,3 +1,3 @@
 setenv bootargs "earlycon root=/dev/mmcblk0p3 rootwait console=ttyPS0,115200 console=tty1 uio_pdrv_genirq.of_id=generic-uio cma=700M overlayroot=tmpfs modprobe.blacklist=zynqmp_dpsub,i2c_mux_pca954x,i2c_cadence,ahci_ceva,raid10,raid1,raid0,raid456"
 load mmc 0:1 0x10000000 image.fit
-bootm 0x10000000 0x10000000 $fdtcontroladdr
\ No newline at end of file
+bootm 0x10000000 0x10000000 $fdtcontroladdr
diff --git a/drivers/src/soc_ifc.rs b/drivers/src/soc_ifc.rs
index e3e7d50ed6..13439343a7 100644
--- a/drivers/src/soc_ifc.rs
+++ b/drivers/src/soc_ifc.rs
@@ -515,7 +515,7 @@ impl SocIfc {
             .regs()
             .cptra_hw_config()
             .read()
-            .active_mode_en()
+            .subsystem_mode_en()
     }
 
     pub fn uds_fuse_row_granularity_64(&self) -> bool {
diff --git a/hw-model/src/lib.rs b/hw-model/src/lib.rs
index 3b2b99fc98..a05e097948 100644
--- a/hw-model/src/lib.rs
+++ b/hw-model/src/lib.rs
@@ -625,7 +625,7 @@ pub trait HwModel: SocManager {
             }
             writeln!(self.output().logger(), "ready_for_fw is high")?;
             self.cover_fw_mage(fw_image);
-            let active_mode = self.soc_ifc().cptra_hw_config().read().active_mode_en();
+            let active_mode = self.soc_ifc().cptra_hw_config().read().subsystem_mode_en();
             writeln!(
                 self.output().logger(),
                 "mode {}",
diff --git a/hw-model/src/model_fpga_realtime.rs b/hw-model/src/model_fpga_realtime.rs
index d6eecf8a43..47736d515e 100644
--- a/hw-model/src/model_fpga_realtime.rs
+++ b/hw-model/src/model_fpga_realtime.rs
@@ -6,7 +6,7 @@ use std::process::{Child, Command, Stdio};
 use std::sync::atomic::{AtomicBool, Ordering};
 use std::sync::Arc;
 use std::thread;
-use std::{env, str::FromStr};
+use std::{env, slice, str::FromStr};
 
 use bitfield::bitfield;
 use caliptra_emu_bus::{Bus, BusError, BusMmio};
@@ -32,6 +32,7 @@ pub enum OpenOcdError {
 // UIO mapping indices
 const FPGA_WRAPPER_MAPPING: usize = 0;
 const CALIPTRA_MAPPING: usize = 1;
+const ROM_MAPPING: usize = 2;
 
 // Set to core_clk cycles per ITRNG sample.
 const ITRNG_DIVISOR: u32 = 400;
@@ -151,7 +152,7 @@ impl ModelFpgaRealtime {
                 };
                 if trngfifosts.trng_fifo_full() == 0 {
                     let mut itrng_dw = 0;
-                    for i in (0..8).rev() {
+                    for i in 0..8 {
                         match itrng_nibbles.next() {
                             Some(nibble) => itrng_dw += u32::from(nibble) << (4 * i),
                             None => return,
@@ -367,6 +368,7 @@ impl HwModel for ModelFpgaRealtime {
             .map_mapping(FPGA_WRAPPER_MAPPING)
             .map_err(fmt_uio_error)? as *mut u32;
         let mmio = dev.map_mapping(CALIPTRA_MAPPING).map_err(fmt_uio_error)? as *mut u32;
+        let rom = dev.map_mapping(ROM_MAPPING).map_err(fmt_uio_error)? as *mut u8;
 
         let realtime_thread_exit_flag = Arc::new(AtomicBool::new(false));
         let realtime_thread_exit_flag2 = realtime_thread_exit_flag.clone();
@@ -436,12 +438,9 @@ impl HwModel for ModelFpgaRealtime {
         }
 
         // Write ROM image over backdoor
-        let mut rom_driver = std::fs::OpenOptions::new()
-            .write(true)
-            .open("/dev/caliptra-rom-backdoor")
-            .unwrap();
-        rom_driver.write_all(params.rom)?;
-        rom_driver.sync_all()?;
+        writeln!(m.output().logger(), "Writing ROM")?;
+        let rom_slice = unsafe { slice::from_raw_parts_mut(rom, params.rom.len()) };
+        rom_slice.copy_from_slice(params.rom);
 
         // Sometimes there's garbage in here; clean it out
         m.clear_log_fifo();
@@ -590,6 +589,7 @@ impl Drop for ModelFpgaRealtime {
         // Unmap UIO memory space so that the file lock is released
         self.unmap_mapping(self.wrapper, FPGA_WRAPPER_MAPPING);
         self.unmap_mapping(self.mmio, CALIPTRA_MAPPING);
+        self.unmap_mapping(self.mmio, ROM_MAPPING);
 
         // Close openocd
         match &mut self.openocd {
@@ -608,7 +608,7 @@ impl<'a> FpgaRealtimeBus<'a> {
         let addr = addr as usize;
         unsafe {
             match addr {
-                0x3002_0000..=0x3003_ffff => Some(self.mmio.add((addr - 0x3002_0000) / 4)),
+                0x3002_0000..=0x3003_ffff => Some(self.mmio.add((addr - 0x3000_0000) / 4)),
                 _ => None,
             }
         }
diff --git a/hw/fpga/README.md b/hw/fpga/README.md
index c6a5e3fe89..166e5fdca2 100644
--- a/hw/fpga/README.md
+++ b/hw/fpga/README.md
@@ -15,28 +15,42 @@ limitations under the License.*_<BR>
 
 # **Caliptra FPGA Guide** #
 FPGA provides a fast environment for software development and testing that uses Caliptra RTL.
-The Zynq's Programmable Logic is programmed with the Caliptra RTL and FPGA specific SoC wrapper logic including a connection to the Processing System AXI bus.
+The FPGA's Programmable Logic is programmed with the Caliptra RTL and FPGA specific SoC wrapper logic including a connection to the Processing System AXI bus.
 The Processing System ARM cores then act as the SoC Security Processor with memory mapped access to Caliptra's public register space.
 
 ![](./images/fpga_module_diagram.svg)
 
 ### Requirements: ###
  - Vivado
-   - Version v2022.2
+   - Version v2022.2 or 2024.2
+ - PetaLinux Tools
+   - Version must match Vivado
  - FPGA
-   - [ZCU104 Development Board](https://www.xilinx.com/products/boards-and-kits/zcu104.html)
+   - [VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html)
+   - VMK180 will be supported soon.
 
-### ZCU104 ###
+### Versal ###
 #### Processing system one time setup: ####
-1. Install ZCU104 SD card image
+1. Download VCK190 SD card image and install to a microSD card.
+   - Insert the SD card into the slot on top of the board. The slot below the board is for the System Controller.
    - https://ubuntu.com/download/amd-xilinx
-1. Configure SW6 to boot from SD1.
-   - Mode SW6[4:1]: OFF, OFF, OFF, ON
-     ![](./images/zynq_boot_switch.jpg)
-1. Install rustup using Unix directions: https://rustup.rs/#
+1. Configure SW1 to boot from SD1: [Image](./images/versal_boot_switch.jpg)
+   - Mode SW1[4:1]: OFF, OFF, OFF, ON
+1. Boot from the SD card. (Suggest using the serial port for initial setup)
+   - Initial credentials
+     - User: ubuntu Pass: ubuntu
+   - Install software dependencies - *Do not update the system*
+     ```shell
+     sudo apt update
+     sudo apt install make gcc
+     ```
+   - Install rustup using Unix directions: https://rustup.rs/#
+   - Consider assigning a hostname for SSH access.
 
 #### Serial port configuration: ####
-Serial port settings for connection over USB.
+The USB Type-C connecter J207 provides UART and JTAG access to the board. The first UART connection should be for the PS.
+
+Serial port settings:
  - Speed: 115200
  - Data bits: 8
  - Stop bits: 1
@@ -47,14 +61,15 @@ Serial port settings for connection over USB.
 The FPGA build process uses Vivado's batch mode to procedurally create the Vivado project using fpga_configuration.tcl.
 This script provides a number of configuration options for features that can be enabled using "-tclargs OPTION=VALUE OPTION=VALUE"
 
-| Option    | Purpose
-| ------    | -------
-| BUILD     | Automatically start building the FPGA.
-| GUI       | Open the Vivado GUI.
-| JTAG      | Assign JTAG signals to Zynq PS GPIO.
-| ITRNG     | Enable Caliptra's ITRNG.
-| CG_EN     | Removes FPGA optimizations and allows clock gating.
-| HW_LATEST | Use hw/latest instead of hw/1.0.
+| Option      | Purpose
+| ------      | -------
+| BUILD       | Automatically start building the FPGA.
+| GUI         | Open the Vivado GUI.
+| JTAG        | Assign JTAG signals to PS GPIO.
+| ITRNG       | Enable Caliptra's ITRNG.
+| CG_EN       | Removes FPGA optimizations and allows clock gating.
+| RTL_VERSION | RTL directory under hw/. latest or 1.0.
+| BOARD       | VCK190 or VMK180 (TODO: VMK180 not fully enabled)
 
  - Build FPGA image without GUI
     - `vivado -mode batch -source fpga_configuration.tcl -tclargs BUILD=TRUE`
@@ -67,60 +82,43 @@ This script provides a number of configuration options for features that can be
     - Run Synthesis: `launch_runs synth_1`
     - [Optional] Set Up Debug signals on Synthesized Design
     - Run Implementation: `launch_runs impl_1`
-    - Generate Bitstream: `write_bitstream -bin_file \tmp\caliptra_fpga`
-
-### Loading and execution Steps: ###
-[setup_fpga.sh](setup_fpga.sh) performs platform setup that is needed after each boot.
- - Disables CPU IDLE. Vivado HW Manager access during IDLE causes crashes.
- - Reduces fan speed by setting the GPIO pin connected to the fan controller FULLSPD pin to output.
-   - https://support.xilinx.com/s/question/0D52E00006iHuopSAC/zcu104-fan-running-at-max-speed?language=en_US
- - Builds and installs the rom_backdoor and io_module kernel modules.
- - Sets the clock for the FPGA logic.
- - Installs the provided FPGA image.
-
+    - Generate Device Image: `write_device_image $outputDir/caliptra_fpga`
+    - Export hardware: `write_hw_platform -fixed -include_bit -force -file $outputDir/caliptra_fpga.xsa`
+
+### Build boot.bin: ###
+ - Source PetaLinux tools from the PetaLinux installation directory.
+   `source settings.sh`
+ - Run steps from [create_boot_bin.sh](create_boot_bin.sh) to create a BOOT.BIN
+   - `./create_boot_bin.sh /path/to/caliptra_fpga_project_bd_wrapper.xsa`
+ - Copy petalinux_project/images/linux/BOOT.BIN to the boot partition as boot1900.bin
+   - If the Ubuntu image is booted, it will mount the boot partition at /boot/firmware/
+   - If boot1900.bin fails to boot the system will fallback to the default boot1901.bin
+
+### Running Caliptra tests from the FPGA: ###
 ```shell
-sudo ./hw/fpga/setup_fpga.sh caliptra_fpga.bin
-
-CPTRA_UIO_NUM=4 cargo test --features=fpga_realtime,itrng -p caliptra-test smoke_test::smoke_test
+# Install dependencies
+sudo apt update
+sudo apt install make gcc
+curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+# Clone this repo
+git clone https://github.com/chipsalliance/caliptra-sw.git
+git submodule init
+git submodule update
+# Compile and install the kernel module
+sudo ./hw/fpga/setup_fpga.sh
+
+CPTRA_UIO_NUM=0 cargo test --features=fpga_realtime,itrng -p caliptra-test smoke_test::smoke_test
 ```
 
 ### Processing System - Programmable Logic interfaces ###
-#### AXI Memory Map ####
- - SoC adapter for driving caliptra-top signals
-   - 0x80000000 - Generic Input Wires
-   - 0x80000008 - Generic Output Wires
-   - 0x80000010-0x8000002C - Deobfuscation key (256 bit)
-   - 0x80000030 - Control
-     - `[0] -> cptra_pwrgood`
-     - `[1] -> cptra_rst_b`
-     - `[3:2] -> device_lifecycle`
-     - `[4] -> debug_locked`
-   - 0x80000034 - Status
-     - `[0] <- cptra_error_fatal`
-     - `[1] <- cptra_error_non_fatal`
-     - `[2] <- ready_for_fuses`
-     - `[3] <- ready_for_fw`
-     - `[4] <- ready_for_runtime`
-   - 0x80000038 - PAUSER
-     - `[31:0] -> PAUSER to Caliptra APB`
-   - 0x80001000 - Log FIFO data. Reads pop data from FIFO.
-     - `[7:0] -> Next log character`
-     - `[8] -> Log character valid`
-   - 0x80001004 - Log FIFO register
-     - `[0] -> Log FIFO empty`
-     - `[1] -> Log FIFO full (probably overrun)`
-   - 0x80001008 - ITRNG FIFO data. Write loads data to FIFO.
-     - `[31:0] -> 32 bits of random data to be fed to itrng_data 4 bits at a time`
-   - 0x8000100C - ITRNG FIFO status.
-     - `[0] -> ITRNG FIFO empty`
-     - `[1] -> ITRNG FIFO full`
-     - `[2] -> ITRNG FIFO reset`
- - ROM Backdoor - 32K
-   - `0x82000000 - 0x82007FFF`
- - Caliptra SoC register interface
-   - `0x90000000`
-#### Interrupts ####
- - 89 - Log FIFO half full.
+[FPGA Wrapper Registers](fpga_wrapper_regs.md)
+
+#### Versal Memory Map ####
+| IP/Peripheral                       | Address size | Start address | End address |
+| :---------------------------------- | :----------- | :------------ | :---------- |
+| ROM Backdoor                        | 96 KiB       | 0xB000_0000   | 0xB001_7FFF |
+| FPGA Wrapper Registers              | 8 KiB        | 0xA401_0000   | 0xA401_1FFF |
+| Caliptra                            | 1 MiB        | 0xA410_0000   | 0xA41F_FFFF |
 
 ### JTAG debug
 Requirements:
diff --git a/hw/fpga/adams-bridge-files.tcl b/hw/fpga/adams-bridge-files.tcl
new file mode 100644
index 0000000000..1d700214d1
--- /dev/null
+++ b/hw/fpga/adams-bridge-files.tcl
@@ -0,0 +1,119 @@
+
+set adbDir $fpgaDir/../$RTL_VERSION/rtl/submodules/adams-bridge
+
+if { [file exists $adbDir/src/abr_prim/rtl/abr_prim_flop_macros.sv] == 0 } {
+    puts "ERROR: $adbDir/src/abr_prim/rtl/abr_prim_flop_macros.sv not found"
+    puts "Adam's bridge submodule may not be initialized"
+    puts "Try: git submodule update --init --recursive"
+    exit
+}
+
+add_files $adbDir/src/abr_prim/rtl/abr_prim_flop_macros.sv
+
+# Initial list from mldsa_top_tb.vf
+add_files $adbDir/src/mldsa_top/rtl/mldsa_config_defines.svh
+add_files $adbDir/src/mldsa_top/rtl/mldsa_params_pkg.sv
+add_files $adbDir/src/mldsa_top/rtl/mldsa_reg_pkg.sv
+
+add_files $adbDir/src/abr_libs/rtl/abr_sva.svh
+add_files $adbDir/src/abr_libs/rtl/abr_macros.svh
+
+add_files [ glob $adbDir/src/abr_libs/rtl/*.sv ]
+
+add_files $adbDir/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv
+add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball_pkg.sv
+add_files $adbDir/src/sample_in_ball/rtl/sib_mem.sv
+
+add_files [ glob $adbDir/src/abr_prim/rtl/*.sv ]
+add_files [ glob $adbDir/src/abr_prim/rtl/*.svh ]
+
+add_files [ glob $adbDir/src/ntt_top/rtl/*.sv ]
+add_files $adbDir/src/ntt_top/tb/ntt_ram_tdp_file.sv
+add_files $adbDir/src/ntt_top/tb/ntt_wrapper.sv
+add_files $adbDir/src/norm_check/rtl/norm_check_defines_pkg.sv
+add_files $adbDir/src/mldsa_top/tb/mldsa_top_tb.sv
+add_files $adbDir/src/rej_bounded/rtl/rej_bounded_ctrl.sv
+add_files $adbDir/src/rej_bounded/rtl/rej_bounded2.sv
+add_files $adbDir/src/rej_sampler/rtl/rej_sampler_ctrl.sv
+add_files $adbDir/src/rej_sampler/rtl/rej_sampler.sv
+add_files $adbDir/src/exp_mask/rtl/exp_mask_ctrl.sv
+add_files $adbDir/src/exp_mask/rtl/exp_mask.sv
+add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv
+add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv
+add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball.sv
+add_files $adbDir/src/abr_sha3/rtl/abr_sha3_pkg.sv
+add_files $adbDir/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv
+add_files $adbDir/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv
+add_files $adbDir/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_flop_en.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_flop_2sync.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_lfsr.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_mubi4_sync.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_diff_decode.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_slicer.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_count.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_dom_and_2share.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_reg_we_check.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_packer_fifo.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_max_tree.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_subreg_arb.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_subreg.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_intr_hw.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_onehot_check.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_mubi8_sync.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_buf.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_alert_receiver.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_flop.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_alert_sender.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_fifo_sync.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_sum_tree.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_subreg_ext.sv
+add_files $adbDir/src/abr_prim/rtl/abr_prim_edge_detector.sv
+add_files $adbDir/src/abr_sha3/rtl/abr_keccak_round.sv
+add_files $adbDir/src/abr_sha3/rtl/abr_keccak_2share.sv
+add_files $adbDir/src/abr_sha3/rtl/abr_sha3pad.sv
+add_files $adbDir/src/abr_sha3/rtl/abr_sha3.sv
+add_files $adbDir/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv
+add_files $adbDir/src/decompose/rtl/decompose_defines_pkg.sv
+add_files $adbDir/src/decompose/rtl/decompose.sv
+add_files $adbDir/src/decompose/rtl/decompose_r1_lut.sv
+add_files $adbDir/src/decompose/rtl/decompose_w1_mem.sv
+add_files $adbDir/src/decompose/rtl/decompose_mod_2gamma2.sv
+add_files $adbDir/src/decompose/rtl/decompose_ctrl.sv
+add_files $adbDir/src/decompose/rtl/decompose_w1_encode.sv
+add_files $adbDir/src/decompose/rtl/decompose_usehint.sv
+add_files $adbDir/src/sk_decode/rtl/skdecode_defines_pkg.sv
+add_files $adbDir/src/sk_encode/rtl/skencode.sv
+add_files $adbDir/src/sk_decode/rtl/skdecode_top.sv
+add_files $adbDir/src/sk_decode/rtl/skdecode_ctrl.sv
+add_files $adbDir/src/sk_decode/rtl/skdecode_s1s2_unpack.sv
+add_files $adbDir/src/sk_decode/rtl/skdecode_t0_unpack.sv
+add_files $adbDir/src/makehint/rtl/makehint_defines_pkg.sv
+add_files $adbDir/src/makehint/rtl/hintgen.sv
+add_files $adbDir/src/makehint/rtl/makehint.sv
+add_files $adbDir/src/norm_check/rtl/norm_check.sv
+add_files $adbDir/src/norm_check/rtl/norm_check_ctrl.sv
+add_files $adbDir/src/norm_check/rtl/norm_check_top.sv
+add_files $adbDir/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv
+add_files $adbDir/src/sig_encode_z/rtl/sigencode_z_top.sv
+add_files $adbDir/src/sig_encode_z/rtl/sigencode_z_unit.sv
+add_files $adbDir/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv
+add_files $adbDir/src/sigdecode_h/rtl/sigdecode_h.sv
+add_files $adbDir/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv
+add_files $adbDir/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv
+add_files $adbDir/src/sig_decode_z/rtl/sigdecode_z_top.sv
+add_files $adbDir/src/sig_decode_z/rtl/sigdecode_z_unit.sv
+add_files $adbDir/src/pk_decode/rtl/pkdecode.sv
+add_files $adbDir/src/power2round/rtl/power2round_defines_pkg.sv
+add_files $adbDir/src/power2round/rtl/power2round_top.sv
+add_files $adbDir/src/power2round/rtl/power2round_ctrl.sv
+add_files $adbDir/src/power2round/rtl/power2round_core.sv
+add_files $adbDir/src/power2round/rtl/power2round_skencode.sv
+
+add_files [ glob $adbDir/src/mldsa_top/rtl/*.sv ]
diff --git a/hw/fpga/create_boot_bin.sh b/hw/fpga/create_boot_bin.sh
new file mode 100755
index 0000000000..0983ee9d96
--- /dev/null
+++ b/hw/fpga/create_boot_bin.sh
@@ -0,0 +1,55 @@
+#!/bin/bash
+# Licensed under the Apache-2.0 license
+
+# This script generates a Versal BOOT.BIN using Petalinux.
+# When using an ubuntu image BOOT.BIN replaces boot1901.bin in the boot partition.
+
+if [[ -z $1 ]]; then
+    echo "create_boot_bin.sh [/path/to/caliptra_fpga_project_bd_wrapper.xsa]"
+    exit
+fi
+
+xsa_location=$(realpath $1)
+
+set -e
+trap '{
+  if [ $? -ne 0 ]
+  then
+    echo FAILED TO CREATE BOOT.BIN
+    exit 1
+  else
+    echo SUCCESS
+  fi  
+}' EXIT
+
+echo Deleting old project
+rm -rf petalinux_project
+echo Creating project
+petalinux-create -t project --template versal --name petalinux_project
+cd petalinux_project
+echo Adding xsa
+petalinux-config --get-hw-description $xsa_location --silentconfig
+
+echo Modifying Petalinux configuration
+# Set ROOTFS to EXT4
+sed -i 's|CONFIG_SUBSYSTEM_ROOTFS_INITRD=y|# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set|g' project-spec/configs/config
+sed -i 's|# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set|CONFIG_SUBSYSTEM_ROOTFS_EXT4=y|g' project-spec/configs/config
+sed -i 's|CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0|CONFIG_SUBSYSTEM_SDROOT_DEV="/dev/mmcblk0p2"|g' project-spec/configs/config
+sed -i 's|CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-image-minimal"||g' project-spec/configs/config
+sed -i 's|root=/dev/ram0 rw|root=/dev/mmcblk0p2 rw rootwait|g' project-spec/configs/config
+
+echo Building FW components, only device-tree depends on XSA
+petalinux-build -c device-tree
+petalinux-build -c u-boot
+petalinux-build -c arm-trusted-firmware
+petalinux-build -c plm
+petalinux-build -c psmfw
+
+echo Modify device tree for 2024.2
+dtc -I dtb -O dts -o images/linux/system.dts images/linux/system.dtb
+sed -i 's/primecell/sbsa-uart/g' images/linux/system.dts
+dtc -I dts -O dtb -o images/linux/system.dtb images/linux/system.dts
+
+echo Packaging boot files
+petalinux-package --boot --format BIN --plm --psmfw --u-boot --dtb --force
+cd ../
diff --git a/hw/fpga/create_caliptra_package.tcl b/hw/fpga/create_caliptra_package.tcl
new file mode 100644
index 0000000000..5a54e29664
--- /dev/null
+++ b/hw/fpga/create_caliptra_package.tcl
@@ -0,0 +1,100 @@
+
+# Create a project to package Caliptra.
+# Packaging Caliptra allows Vivado to recognize the APB bus as an endpoint for the memory map.
+create_project caliptra_package_project $outputDir -part $PART
+if {$BOARD eq "VCK190"} {
+  set_property board_part xilinx.com:vck190:part0:3.1 [current_project]
+}
+
+set_property verilog_define $VERILOG_OPTIONS [current_fileset]
+puts "\n\nVERILOG DEFINES: [get_property verilog_define [current_fileset]]"
+
+# Add VEER Headers
+add_files $rtlDir/src/riscv_core/veer_el2/rtl/el2_param.vh
+add_files $rtlDir/src/riscv_core/veer_el2/rtl/pic_map_auto.h
+add_files $rtlDir/src/riscv_core/veer_el2/rtl/el2_pdef.vh
+add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/include/*.svh ]
+
+# Add VEER sources
+add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/*.sv ]
+add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/*/*.sv ]
+add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/*/*.v ]
+
+# Add Adam's Bridge
+source adams-bridge-files.tcl
+
+# Add Caliptra Headers
+add_files [ glob $rtlDir/src/*/rtl/*.svh ]
+# Add Caliptra Sources
+add_files [ glob $rtlDir/src/*/rtl/*.sv ]
+add_files [ glob $rtlDir/src/*/rtl/*.v ]
+
+# Remove spi_host files that aren't used yet and are flagged as having syntax errors
+# TODO: Re-include these files when spi_host is used.
+remove_files [ glob $rtlDir/src/spi_host/rtl/*.sv ]
+
+# Add FPGA specific sources
+add_files [ glob $fpgaDir/src/*.sv]
+add_files [ glob $fpgaDir/src/*.v]
+
+# Replace RAM with FPGA block ram
+remove_files [ glob $rtlDir/src/ecc/rtl/ecc_ram_tdp_file.sv ]
+
+# TODO: Copy aes_clk_wrapper.sv to apply workaround
+file copy [ glob $rtlDir/src/aes/rtl/aes_clp_wrapper.sv ] $outputDir/aes_clk_wrapper.sv
+exec sed -i {1i `include \"kv_macros.svh\"} $outputDir/aes_clk_wrapper.sv
+remove_files [ glob $rtlDir/src/aes/rtl/aes_clp_wrapper.sv ]
+add_files $outputDir/aes_clk_wrapper.sv
+
+# Mark all Verilog sources as SystemVerilog because some of them have SystemVerilog syntax.
+set_property file_type SystemVerilog [get_files *.v]
+
+# Exception: caliptra_package_top.v needs to be Verilog to be included in a Block Diagram.
+set_property file_type Verilog [get_files  $fpgaDir/src/caliptra_package_top.v]
+
+# Add include paths
+set_property include_dirs $rtlDir/src/integration/rtl [current_fileset]
+
+
+# Set caliptra_package_top as top in case next steps fail so that the top is something useful.
+if {$APB} {
+  set_property top caliptra_package_apb_top [current_fileset]
+} else {
+  set_property top caliptra_package_axi_top [current_fileset]
+}
+
+# Create block diagram that includes an instance of caliptra_package_top
+create_bd_design "caliptra_package_bd"
+if {$APB} {
+  create_bd_cell -type module -reference caliptra_package_apb_top caliptra_package_top_0
+} else {
+  create_bd_cell -type module -reference caliptra_package_axi_top caliptra_package_top_0
+}
+save_bd_design
+close_bd_design [get_bd_designs caliptra_package_bd]
+
+# Package IP
+puts "Fileset when packaging: [current_fileset]"
+puts "\n\nVERILOG DEFINES: [get_property verilog_define [current_fileset]]"
+ipx::package_project -root_dir $caliptrapackageDir -vendor design -library user -taxonomy /UserIP -import_files
+# Infer interfaces
+ipx::infer_bus_interfaces xilinx.com:interface:apb_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interfaces xilinx.com:interface:bram_rtl:1.0 [ipx::current_core]
+ipx::add_bus_parameter MASTER_TYPE [ipx::get_bus_interfaces axi_bram -of_objects [ipx::current_core]]
+# Associate clocks to busses
+ipx::associate_bus_interfaces -busif S_AXI_WRAPPER -clock core_clk [ipx::current_core]
+ipx::associate_bus_interfaces -busif S_AXI_CALIPTRA -clock core_clk [ipx::current_core]
+ipx::associate_bus_interfaces -busif M_AXI_CALIPTRA -clock core_clk [ipx::current_core]
+ipx::associate_bus_interfaces -busif axi_bram -clock axi_bram_clk [ipx::current_core]
+# Other packager settings
+set_property name caliptra_package_top [ipx::current_core]
+set_property core_revision 1 [ipx::current_core]
+set_property PAYMENT_REQUIRED FALSE [ipx::current_core]
+ipx::update_source_project_archive -component [ipx::current_core]
+ipx::create_xgui_files [ipx::current_core]
+ipx::update_checksums [ipx::current_core]
+ipx::check_integrity [ipx::current_core]
+ipx::save_core [ipx::current_core]
+
+# Close caliptra_package_project
+close_project
diff --git a/hw/fpga/create_versal_cips.tcl b/hw/fpga/create_versal_cips.tcl
new file mode 100644
index 0000000000..b28d9275c4
--- /dev/null
+++ b/hw/fpga/create_versal_cips.tcl
@@ -0,0 +1,290 @@
+
+# Create interface ports
+set ch0_lpddr4_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:lpddr4_rtl:1.0 ch0_lpddr4_c0 ]
+
+set ch1_lpddr4_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:lpddr4_rtl:1.0 ch1_lpddr4_c0 ]
+
+set lpddr4_sma_clk1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 lpddr4_sma_clk1 ]
+set_property -dict [ list \
+  CONFIG.FREQ_HZ {200321000} \
+  ] $lpddr4_sma_clk1
+
+set ch0_lpddr4_c1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:lpddr4_rtl:1.0 ch0_lpddr4_c1 ]
+
+set ch1_lpddr4_c1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:lpddr4_rtl:1.0 ch1_lpddr4_c1 ]
+
+set lpddr4_sma_clk2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 lpddr4_sma_clk2 ]
+set_property -dict [ list \
+  CONFIG.FREQ_HZ {200321000} \
+  ] $lpddr4_sma_clk2
+
+set ddr4_dimm1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_dimm1 ]
+
+set ddr4_dimm1_sma_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_dimm1_sma_clk ]
+set_property -dict [ list \
+  CONFIG.FREQ_HZ {200000000} \
+  ] $ddr4_dimm1_sma_clk
+
+create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips ps_0
+set_property -dict [list \
+  CONFIG.DDR_MEMORY_MODE {Custom} \
+  CONFIG.DEBUG_MODE {JTAG} \
+  CONFIG.DESIGN_MODE {1} \
+  CONFIG.PS_PL_CONNECTIVITY_MODE {Custom} \
+  CONFIG.PS_PMC_CONFIG { \
+    CLOCK_MODE {Custom} \
+    DDR_MEMORY_MODE {Connectivity to DDR via NOC} \
+    DEBUG_MODE {JTAG} \
+    DESIGN_MODE {1} \
+    PMC_CRP_PL0_REF_CTRL_FREQMHZ {20} \
+    PMC_GPIO0_MIO_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 0 .. 25}}} \
+    PMC_GPIO1_MIO_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 26 .. 51}}} \
+    PMC_MIO37 {{AUX_IO 0} {DIRECTION out} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA high} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE GPIO}} \
+    PMC_OSPI_PERIPHERAL {{ENABLE 0} {IO {PMC_MIO 0 .. 11}} {MODE Single}} \
+    PMC_QSPI_COHERENCY {0} \
+    PMC_QSPI_FBCLK {{ENABLE 1} {IO {PMC_MIO 6}}} \
+    PMC_QSPI_PERIPHERAL_DATA_MODE {x4} \
+    PMC_QSPI_PERIPHERAL_ENABLE {1} \
+    PMC_QSPI_PERIPHERAL_MODE {Dual Parallel} \
+    PMC_REF_CLK_FREQMHZ {33.3333} \
+    PMC_SD1 {{CD_ENABLE 1} {CD_IO {PMC_MIO 28}} {POW_ENABLE 1} {POW_IO {PMC_MIO 51}} {RESET_ENABLE 0} {RESET_IO {PMC_MIO 12}} {WP_ENABLE 0} {WP_IO {PMC_MIO 1}}} \
+    PMC_SD1_COHERENCY {0} \
+    PMC_SD1_DATA_TRANSFER_MODE {8Bit} \
+    PMC_SD1_PERIPHERAL {{CLK_100_SDR_OTAP_DLY 0x3} {CLK_200_SDR_OTAP_DLY 0x2} {CLK_50_DDR_ITAP_DLY 0x36} {CLK_50_DDR_OTAP_DLY 0x3} {CLK_50_SDR_ITAP_DLY 0x2C} {CLK_50_SDR_OTAP_DLY 0x4} {ENABLE 1} {IO\
+{PMC_MIO 26 .. 36}}} \
+    PMC_SD1_SLOT_TYPE {SD 3.0} \
+    PMC_USE_PMC_NOC_AXI0 {1} \
+    PS_CAN1_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 40 .. 41}}} \
+    PS_CRL_CAN1_REF_CTRL_FREQMHZ {160} \
+    PS_ENET0_MDIO {{ENABLE 1} {IO {PS_MIO 24 .. 25}}} \
+    PS_ENET0_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 0 .. 11}}} \
+    PS_ENET1_PERIPHERAL {{ENABLE 1} {IO {PS_MIO 12 .. 23}}} \
+    PS_GEN_IPI0_ENABLE {1} \
+    PS_GEN_IPI0_MASTER {A72} \
+    PS_GEN_IPI1_ENABLE {1} \
+    PS_GEN_IPI2_ENABLE {1} \
+    PS_GEN_IPI3_ENABLE {1} \
+    PS_GEN_IPI4_ENABLE {1} \
+    PS_GEN_IPI5_ENABLE {1} \
+    PS_GEN_IPI6_ENABLE {1} \
+    PS_GPIO_EMIO_PERIPHERAL_ENABLE {1} \
+    PS_GPIO_EMIO_WIDTH {5} \
+    PS_HSDP_EGRESS_TRAFFIC {JTAG} \
+    PS_HSDP_INGRESS_TRAFFIC {JTAG} \
+    PS_HSDP_MODE {NONE} \
+    PS_I2C0_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 46 .. 47}}} \
+    PS_I2C1_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 44 .. 45}}} \
+    PS_MIO19 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL disable} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \
+    PS_MIO21 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL disable} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \
+    PS_MIO7 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL disable} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \
+    PS_MIO9 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL disable} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \
+    PS_NUM_FABRIC_RESETS {1} \
+    PS_PCIE_EP_RESET1_IO {None} \
+    PS_PCIE_EP_RESET2_IO {None} \
+    PS_PCIE_RESET {{ENABLE 1}} \
+    PS_PL_CONNECTIVITY_MODE {Custom} \
+    PS_UART0_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 42 .. 43}}} \
+    PS_USB3_PERIPHERAL {{ENABLE 1} {IO {PMC_MIO 13 .. 25}}} \
+    PS_USE_FPD_CCI_NOC {1} \
+    PS_USE_FPD_CCI_NOC0 {1} \
+    PS_USE_M_AXI_FPD {1} \
+    PS_USE_NOC_LPD_AXI0 {1} \
+    PS_USE_PMCPL_CLK0 {1} \
+    PS_USE_PMCPL_CLK1 {0} \
+    PS_USE_PMCPL_CLK2 {0} \
+    PS_USE_PMCPL_CLK3 {0} \
+    SMON_ALARMS {Set_Alarms_On} \
+    SMON_ENABLE_TEMP_AVERAGING {0} \
+    SMON_TEMP_AVERAGING_SAMPLES {0} \
+  } \
+] [get_bd_cells ps_0]
+#  CONFIG.PS_BOARD_INTERFACE {ps_pmc_fixed_io} \
+#  PS_BOARD_INTERFACE {ps_pmc_fixed_io} \
+
+# Create instance: axi_noc_0, and set properties
+set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_0 ]
+set_property -dict [list \
+  CONFIG.CH0_DDR4_0_BOARD_INTERFACE {ddr4_dimm1} \
+  CONFIG.MC_CHAN_REGION1 {DDR_LOW1} \
+  CONFIG.MC_SYSTEM_CLOCK {Differential} \
+  CONFIG.NUM_CLKS {6} \
+  CONFIG.NUM_MC {1} \
+  CONFIG.NUM_MCP {4} \
+  CONFIG.NUM_MI {0} \
+  CONFIG.NUM_NMI {4} \
+  CONFIG.NUM_SI {6} \
+  CONFIG.sys_clk0_BOARD_INTERFACE {ddr4_dimm1_sma_clk} \
+] $axi_noc_0
+
+
+set_property -dict [ list \
+  CONFIG.REGION {0} \
+  CONFIG.CONNECTIONS {M00_INI {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}} MC_3 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+  CONFIG.DEST_IDS {} \
+  CONFIG.NOC_PARAMS {} \
+  CONFIG.CATEGORY {ps_cci} \
+] [get_bd_intf_pins /axi_noc_0/S00_AXI]
+
+set_property -dict [ list \
+  CONFIG.REGION {0} \
+  CONFIG.CONNECTIONS {M01_INI {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}} MC_2 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+  CONFIG.DEST_IDS {} \
+  CONFIG.NOC_PARAMS {} \
+  CONFIG.CATEGORY {ps_cci} \
+] [get_bd_intf_pins /axi_noc_0/S01_AXI]
+
+set_property -dict [ list \
+  CONFIG.REGION {0} \
+  CONFIG.CONNECTIONS {M02_INI {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}} MC_0 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+  CONFIG.DEST_IDS {} \
+  CONFIG.NOC_PARAMS {} \
+  CONFIG.CATEGORY {ps_cci} \
+] [get_bd_intf_pins /axi_noc_0/S02_AXI]
+
+set_property -dict [ list \
+  CONFIG.REGION {0} \
+  CONFIG.CONNECTIONS {M03_INI {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}} MC_1 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+  CONFIG.DEST_IDS {} \
+  CONFIG.NOC_PARAMS {} \
+  CONFIG.CATEGORY {ps_cci} \
+] [get_bd_intf_pins /axi_noc_0/S03_AXI]
+
+set_property -dict [ list \
+  CONFIG.REGION {0} \
+  CONFIG.CONNECTIONS {M00_INI {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}} MC_3 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+  CONFIG.DEST_IDS {} \
+  CONFIG.NOC_PARAMS {} \
+  CONFIG.CATEGORY {ps_rpu} \
+] [get_bd_intf_pins /axi_noc_0/S04_AXI]
+
+set_property -dict [ list \
+  CONFIG.REGION {0} \
+  CONFIG.CONNECTIONS {M01_INI {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}} MC_2 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+  CONFIG.DEST_IDS {} \
+  CONFIG.NOC_PARAMS {} \
+  CONFIG.CATEGORY {ps_pmc} \
+] [get_bd_intf_pins /axi_noc_0/S05_AXI]
+
+set_property -dict [ list \
+  CONFIG.ASSOCIATED_BUSIF {S00_AXI} \
+] [get_bd_pins /axi_noc_0/aclk0]
+
+set_property -dict [ list \
+  CONFIG.ASSOCIATED_BUSIF {S01_AXI} \
+] [get_bd_pins /axi_noc_0/aclk1]
+
+set_property -dict [ list \
+  CONFIG.ASSOCIATED_BUSIF {S02_AXI} \
+] [get_bd_pins /axi_noc_0/aclk2]
+
+set_property -dict [ list \
+  CONFIG.ASSOCIATED_BUSIF {S03_AXI} \
+] [get_bd_pins /axi_noc_0/aclk3]
+
+set_property -dict [ list \
+  CONFIG.ASSOCIATED_BUSIF {S04_AXI} \
+] [get_bd_pins /axi_noc_0/aclk4]
+
+set_property -dict [ list \
+  CONFIG.ASSOCIATED_BUSIF {S05_AXI} \
+] [get_bd_pins /axi_noc_0/aclk5]
+
+# Create instance: axi_noc_mc, and set properties
+set axi_noc_mc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc axi_noc_mc ]
+set_property -dict [list \
+  CONFIG.CH0_LPDDR4_0_BOARD_INTERFACE {ch0_lpddr4_c0} \
+  CONFIG.CH0_LPDDR4_1_BOARD_INTERFACE {ch0_lpddr4_c1} \
+  CONFIG.CH1_LPDDR4_0_BOARD_INTERFACE {ch1_lpddr4_c0} \
+  CONFIG.CH1_LPDDR4_1_BOARD_INTERFACE {ch1_lpddr4_c1} \
+  CONFIG.MC_CHAN_REGION0 {DDR_CH1} \
+  CONFIG.MC_DM_WIDTH {4} \
+  CONFIG.MC_DQS_WIDTH {4} \
+  CONFIG.MC_DQ_WIDTH {32} \
+  CONFIG.MC_SYSTEM_CLOCK {Differential} \
+  CONFIG.NUM_MC {2} \
+  CONFIG.NUM_MCP {4} \
+  CONFIG.NUM_MI {0} \
+  CONFIG.NUM_NSI {4} \
+  CONFIG.NUM_SI {0} \
+  CONFIG.sys_clk0_BOARD_INTERFACE {lpddr4_sma_clk1} \
+  CONFIG.sys_clk1_BOARD_INTERFACE {lpddr4_sma_clk2} \
+] $axi_noc_mc
+
+
+set_property -dict [ list \
+  CONFIG.CONNECTIONS {MC_3 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+] [get_bd_intf_pins /axi_noc_mc/S00_INI]
+
+set_property -dict [ list \
+  CONFIG.CONNECTIONS {MC_2 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+] [get_bd_intf_pins /axi_noc_mc/S01_INI]
+
+set_property -dict [ list \
+  CONFIG.CONNECTIONS {MC_0 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+] [get_bd_intf_pins /axi_noc_mc/S02_INI]
+
+set_property -dict [ list \
+  CONFIG.CONNECTIONS {MC_1 {read_bw {100} write_bw {100} read_avg_burst {4} write_avg_burst {4} initial_boot {true}}} \
+] [get_bd_intf_pins /axi_noc_mc/S03_INI]
+
+# Create variables to adapt between PS
+set ps_m_axi ps_0/M_AXI_FPD
+set ps_pl_clk ps_0/pl0_ref_clk
+set ps_axi_aclk ps_0/m_axi_fpd_aclk
+set ps_pl_resetn ps_0/pl0_resetn
+set ps_gpio_i ps_0/LPD_GPIO_i
+set ps_gpio_o ps_0/LPD_GPIO_o
+
+# Connect DDR
+connect_bd_intf_net -intf_net axi_noc_0_CH0_DDR4_0 [get_bd_intf_ports ddr4_dimm1] [get_bd_intf_pins axi_noc_0/CH0_DDR4_0]
+connect_bd_intf_net -intf_net axi_noc_0_M00_INI [get_bd_intf_pins axi_noc_0/M00_INI] [get_bd_intf_pins axi_noc_mc/S00_INI]
+connect_bd_intf_net -intf_net axi_noc_0_M01_INI [get_bd_intf_pins axi_noc_0/M01_INI] [get_bd_intf_pins axi_noc_mc/S01_INI]
+connect_bd_intf_net -intf_net axi_noc_0_M02_INI [get_bd_intf_pins axi_noc_0/M02_INI] [get_bd_intf_pins axi_noc_mc/S02_INI]
+connect_bd_intf_net -intf_net axi_noc_0_M03_INI [get_bd_intf_pins axi_noc_0/M03_INI] [get_bd_intf_pins axi_noc_mc/S03_INI]
+connect_bd_intf_net -intf_net axi_noc_mc_CH0_LPDDR4_0 [get_bd_intf_ports ch0_lpddr4_c0] [get_bd_intf_pins axi_noc_mc/CH0_LPDDR4_0]
+connect_bd_intf_net -intf_net axi_noc_mc_CH0_LPDDR4_1 [get_bd_intf_ports ch0_lpddr4_c1] [get_bd_intf_pins axi_noc_mc/CH0_LPDDR4_1]
+connect_bd_intf_net -intf_net axi_noc_mc_CH1_LPDDR4_0 [get_bd_intf_ports ch1_lpddr4_c0] [get_bd_intf_pins axi_noc_mc/CH1_LPDDR4_0]
+connect_bd_intf_net -intf_net axi_noc_mc_CH1_LPDDR4_1 [get_bd_intf_ports ch1_lpddr4_c1] [get_bd_intf_pins axi_noc_mc/CH1_LPDDR4_1]
+connect_bd_intf_net -intf_net ddr4_dimm1_sma_clk_1 [get_bd_intf_ports ddr4_dimm1_sma_clk] [get_bd_intf_pins axi_noc_0/sys_clk0]
+connect_bd_intf_net -intf_net lpddr4_sma_clk1_1 [get_bd_intf_ports lpddr4_sma_clk1] [get_bd_intf_pins axi_noc_mc/sys_clk0]
+connect_bd_intf_net -intf_net lpddr4_sma_clk2_1 [get_bd_intf_ports lpddr4_sma_clk2] [get_bd_intf_pins axi_noc_mc/sys_clk1]
+connect_bd_intf_net -intf_net ps_0_FPD_CCI_NOC_0 [get_bd_intf_pins ps_0/FPD_CCI_NOC_0] [get_bd_intf_pins axi_noc_0/S00_AXI]
+connect_bd_intf_net -intf_net ps_0_FPD_CCI_NOC_1 [get_bd_intf_pins ps_0/FPD_CCI_NOC_1] [get_bd_intf_pins axi_noc_0/S01_AXI]
+connect_bd_intf_net -intf_net ps_0_FPD_CCI_NOC_2 [get_bd_intf_pins ps_0/FPD_CCI_NOC_2] [get_bd_intf_pins axi_noc_0/S02_AXI]
+connect_bd_intf_net -intf_net ps_0_FPD_CCI_NOC_3 [get_bd_intf_pins ps_0/FPD_CCI_NOC_3] [get_bd_intf_pins axi_noc_0/S03_AXI]
+connect_bd_intf_net -intf_net ps_0_LPD_AXI_NOC_0 [get_bd_intf_pins ps_0/LPD_AXI_NOC_0] [get_bd_intf_pins axi_noc_0/S04_AXI]
+connect_bd_intf_net -intf_net ps_0_PMC_NOC_AXI_0 [get_bd_intf_pins ps_0/PMC_NOC_AXI_0] [get_bd_intf_pins axi_noc_0/S05_AXI]
+
+# Create port connections
+connect_bd_net -net ps_0_fpd_cci_noc_axi0_clk  [get_bd_pins ps_0/fpd_cci_noc_axi0_clk] \
+[get_bd_pins axi_noc_0/aclk0]
+connect_bd_net -net ps_0_fpd_cci_noc_axi1_clk  [get_bd_pins ps_0/fpd_cci_noc_axi1_clk] \
+[get_bd_pins axi_noc_0/aclk1]
+connect_bd_net -net ps_0_fpd_cci_noc_axi2_clk  [get_bd_pins ps_0/fpd_cci_noc_axi2_clk] \
+[get_bd_pins axi_noc_0/aclk2]
+connect_bd_net -net ps_0_fpd_cci_noc_axi3_clk  [get_bd_pins ps_0/fpd_cci_noc_axi3_clk] \
+[get_bd_pins axi_noc_0/aclk3]
+connect_bd_net -net ps_0_lpd_axi_noc_clk  [get_bd_pins ps_0/lpd_axi_noc_clk] \
+[get_bd_pins axi_noc_0/aclk4]
+connect_bd_net -net ps_0_pmc_axi_noc_axi0_clk  [get_bd_pins ps_0/pmc_axi_noc_axi0_clk] \
+[get_bd_pins axi_noc_0/aclk5]
+
+# Create DRAM address segments
+assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_0] [get_bd_addr_segs axi_noc_0/S00_AXI/C3_DDR_LOW0] -force
+assign_bd_address -offset 0x000800000000 -range 0x000180000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_0] [get_bd_addr_segs axi_noc_0/S00_AXI/C3_DDR_LOW1] -force
+assign_bd_address -offset 0x050000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_0] [get_bd_addr_segs axi_noc_mc/S00_INI/C3_DDR_CH1x2] -force
+assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_1] [get_bd_addr_segs axi_noc_0/S01_AXI/C2_DDR_LOW0] -force
+assign_bd_address -offset 0x000800000000 -range 0x000180000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_1] [get_bd_addr_segs axi_noc_0/S01_AXI/C2_DDR_LOW1] -force
+assign_bd_address -offset 0x050000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_1] [get_bd_addr_segs axi_noc_mc/S01_INI/C2_DDR_CH1x2] -force
+assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_2] [get_bd_addr_segs axi_noc_0/S02_AXI/C0_DDR_LOW0] -force
+assign_bd_address -offset 0x000800000000 -range 0x000180000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_2] [get_bd_addr_segs axi_noc_0/S02_AXI/C0_DDR_LOW1] -force
+assign_bd_address -offset 0x050000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_2] [get_bd_addr_segs axi_noc_mc/S02_INI/C0_DDR_CH1x2] -force
+assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_3] [get_bd_addr_segs axi_noc_0/S03_AXI/C1_DDR_LOW0] -force
+assign_bd_address -offset 0x000800000000 -range 0x000180000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_3] [get_bd_addr_segs axi_noc_0/S03_AXI/C1_DDR_LOW1] -force
+assign_bd_address -offset 0x050000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps_0/FPD_CCI_NOC_3] [get_bd_addr_segs axi_noc_mc/S03_INI/C1_DDR_CH1x2] -force
+assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps_0/LPD_AXI_NOC_0] [get_bd_addr_segs axi_noc_0/S04_AXI/C3_DDR_LOW0] -force
+assign_bd_address -offset 0x000800000000 -range 0x000180000000 -target_address_space [get_bd_addr_spaces ps_0/LPD_AXI_NOC_0] [get_bd_addr_segs axi_noc_0/S04_AXI/C3_DDR_LOW1] -force
+assign_bd_address -offset 0x050000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps_0/LPD_AXI_NOC_0] [get_bd_addr_segs axi_noc_mc/S00_INI/C3_DDR_CH1x2] -force
+assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps_0/PMC_NOC_AXI_0] [get_bd_addr_segs axi_noc_0/S05_AXI/C2_DDR_LOW0] -force
+assign_bd_address -offset 0x000800000000 -range 0x000180000000 -target_address_space [get_bd_addr_spaces ps_0/PMC_NOC_AXI_0] [get_bd_addr_segs axi_noc_0/S05_AXI/C2_DDR_LOW1] -force
+assign_bd_address -offset 0x050000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps_0/PMC_NOC_AXI_0] [get_bd_addr_segs axi_noc_mc/S01_INI/C2_DDR_CH1x2] -force
diff --git a/hw/fpga/fpga_configuration.tcl b/hw/fpga/fpga_configuration.tcl
index 9e5f3900c6..178722c67a 100644
--- a/hw/fpga/fpga_configuration.tcl
+++ b/hw/fpga/fpga_configuration.tcl
@@ -1,22 +1,15 @@
-# Create path variables
-set fpgaDir [file dirname [info script]]
-set outputDir $fpgaDir/caliptra_build
-set packageDir $outputDir/caliptra_package
-set adapterDir $outputDir/soc_adapter_package
-# Clean and create output directory.
-file delete -force $outputDir
-file mkdir $outputDir
-file mkdir $packageDir
-file mkdir $adapterDir
 
-# Simplistic processing of command line arguments to enable different features
-# Defaults:
+# Default settings:
 set BUILD FALSE
 set GUI   FALSE
 set JTAG  TRUE
 set ITRNG TRUE
 set CG_EN FALSE
 set RTL_VERSION latest
+set BOARD VCK190
+set ITRNG TRUE
+set APB FALSE
+# Simplistic processing of command line arguments to override defaults
 foreach arg $argv {
     regexp {(.*)=(.*)} $arg fullmatch option value
     set $option "$value"
@@ -27,6 +20,16 @@ if {[info exists VERSION] == 0} {
   set VERSION [exec git rev-parse --short HEAD]
 }
 
+# Create path variables
+set fpgaDir [file dirname [info script]]
+set outputDir $fpgaDir/caliptra_build
+set caliptrapackageDir $outputDir/caliptra_package
+
+# Clean and create output directory.
+file delete -force $outputDir
+file mkdir $outputDir
+file mkdir $caliptrapackageDir
+
 # Path to rtl
 set rtlDir $fpgaDir/../$RTL_VERSION/rtl
 puts "JTAG: $JTAG"
@@ -50,149 +53,40 @@ if {$ITRNG} {
   # Add option to use Caliptra's internal TRNG instead of ETRNG
   lappend VERILOG_OPTIONS CALIPTRA_INTERNAL_TRNG
 }
+if {$APB} {
+  lappend VERILOG_OPTIONS CALIPTRA_APB
+}
+lappend VERILOG_OPTIONS FPGA_VERSION=32'h$VERSION
+# Needed to inform Adam's Bridge to use key vault params. TODO: Still need to test if this works
+lappend VERILOG_OPTIONS CALIPTRA
 
 # Start the Vivado GUI for interactive debug
 if {$GUI} {
   start_gui
 }
 
-# Create a project to package Caliptra.
-# Packaging Caliptra allows Vivado to recognize the APB bus as an endpoint for the memory map.
-create_project caliptra_package_project $outputDir -part xczu7ev-ffvc1156-2-e
-
-# Generate ROM
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name fpga_imem -dir $outputDir
-set_property -dict [list \
-  CONFIG.Memory_Type {True_Dual_Port_RAM} \
-  CONFIG.Write_Depth_A {6144} \
-  CONFIG.Write_Width_A {64} \
-  CONFIG.Write_Width_B {32} \
-  CONFIG.Use_RSTB_Pin {true} \
-  CONFIG.Byte_Size {8} \
-  CONFIG.Use_Byte_Write_Enable {true} \
-  CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-  CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
-] [get_ips fpga_imem]
-
-# Generate Mailbox RAM. 128K
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name fpga_mbox_ram -dir $outputDir
-set_property -dict [list \
-  CONFIG.Memory_Type {Single_Port_RAM} \
-  CONFIG.Write_Depth_A {32768} \
-  CONFIG.Write_Width_A {39} \
-  CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-] [get_ips fpga_mbox_ram]
-
-# Generate ECC TDP File
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name fpga_ecc_ram_tdp_file -dir $outputDir
-set_property -dict [list \
-  CONFIG.Memory_Type {True_Dual_Port_RAM} \
-  CONFIG.Write_Depth_A {64} \
-  CONFIG.Write_Width_A {384} \
-  CONFIG.Write_Width_B {384} \
-  CONFIG.Use_RSTA_Pin {true} \
-  CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-  CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
-] [get_ips fpga_ecc_ram_tdp_file]
-
-# Create FIFO for fake UART communication
-create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name log_fifo -dir $outputDir
-set_property -dict [list \
-  CONFIG.Input_Data_Width {8} \
-  CONFIG.Input_Depth {8192} \
-  CONFIG.Performance_Options {First_Word_Fall_Through} \
-  CONFIG.Full_Threshold_Assert_Value {7168} \
-  CONFIG.Programmable_Full_Type {Single_Programmable_Full_Threshold_Constant} \
-] [get_ips log_fifo]
-
-# Create FIFO for ITRNG data
-create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name itrng_fifo -dir $outputDir
-set_property -dict [list \
-  CONFIG.Input_Data_Width {32} \
-  CONFIG.Input_Depth {1024} \
-  CONFIG.Output_Data_Width {4} \
-  CONFIG.Overflow_Flag {false} \
-  CONFIG.Valid_Flag {true} \
-  CONFIG.asymmetric_port_width {true} \
-] [get_ips itrng_fifo]
-
-set_property verilog_define $VERILOG_OPTIONS [current_fileset]
-
-# Add VEER Headers
-add_files $rtlDir/src/riscv_core/veer_el2/rtl/el2_param.vh
-add_files $rtlDir/src/riscv_core/veer_el2/rtl/pic_map_auto.h
-add_files $rtlDir/src/riscv_core/veer_el2/rtl/el2_pdef.vh
-
-# Add VEER sources
-add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/*.sv ]
-add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/*/*.sv ]
-add_files [ glob $rtlDir/src/riscv_core/veer_el2/rtl/*/*.v ]
-
-# Add Caliptra Headers
-add_files [ glob $rtlDir/src/*/rtl/*.svh ]
-# Add Caliptra Sources
-add_files [ glob $rtlDir/src/*/rtl/*.sv ]
-add_files [ glob $rtlDir/src/*/rtl/*.v ]
-
-# Remove spi_host files that aren't used yet and are flagged as having syntax errors
-# TODO: Re-include these files when spi_host is used.
-remove_files [ glob $rtlDir/src/spi_host/rtl/*.sv ]
-
-# Remove Caliptra files that need to be replaced by FPGA specific versions
-# Replace RAM with FPGA block ram
-remove_files [ glob $rtlDir/src/ecc/rtl/ecc_ram_tdp_file.sv ]
-# Key Vault is very large. Replacing KV with a version with the minimum number of entries.
-remove_files [ glob $rtlDir/src/keyvault/rtl/kv_reg.sv ]
-
-# Add FPGA specific sources
-add_files [ glob $fpgaDir/src/*.sv]
-add_files [ glob $fpgaDir/src/*.v]
-
-# Mark all Verilog sources as SystemVerilog because some of them have SystemVerilog syntax.
-set_property file_type SystemVerilog [get_files *.v]
-
-# Exception: caliptra_package_top.v needs to be Verilog to be included in a Block Diagram.
-set_property file_type Verilog [get_files  $fpgaDir/src/caliptra_package_top.v]
-
-# Add include paths
-set_property include_dirs $rtlDir/src/integration/rtl [current_fileset]
+if {$BOARD eq "VCK190"} {
+  set PART xcvc1902-vsva2197-2MP-e-S
+  set BOARD_PART xilinx.com:vck190:part0:3.1
+} elseif {$BOARD eq "VMK180"} {
+  set PART xcvm1802-vsva2197-2MP-e-S
+  set BOARD_PART xilinx.com:vmk180:part0:3.1
+} else {
+  puts "Board $BOARD not supported"
+  exit
+}
 
+##### Caliptra Package #####
+source create_caliptra_package.tcl
+##### Caliptra Package #####
 
-# Set caliptra_package_top as top in case next steps fail so that the top is something useful.
-set_property top caliptra_package_top [current_fileset]
-
-# Create block diagram that includes an instance of caliptra_package_top
-create_bd_design "caliptra_package_bd"
-create_bd_cell -type module -reference caliptra_package_top caliptra_package_top_0
-save_bd_design
-close_bd_design [get_bd_designs caliptra_package_bd]
-
-# Package IP
-ipx::package_project -root_dir $packageDir -vendor design -library user -taxonomy /UserIP -import_files -set_current false
-ipx::unload_core $packageDir/component.xml
-ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $packageDir $packageDir/component.xml
-ipx::infer_bus_interfaces xilinx.com:interface:apb_rtl:1.0 [ipx::current_core]
-ipx::infer_bus_interfaces xilinx.com:interface:bram_rtl:1.0 [ipx::current_core]
-ipx::associate_bus_interfaces -busif S_AXI -clock core_clk [ipx::current_core]
-set_property core_revision 1 [ipx::current_core]
-ipx::update_source_project_archive -component [ipx::current_core]
-ipx::create_xgui_files [ipx::current_core]
-ipx::update_checksums [ipx::current_core]
-ipx::check_integrity [ipx::current_core]
-ipx::save_core [ipx::current_core]
-
-# Close temp project
-close_project
-# Close caliptra_package_project
-close_project
-
-# Packaging complete
 
 # Create a project for the SOC connections
-create_project caliptra_fpga_project $outputDir -part xczu7ev-ffvc1156-2-e
+create_project caliptra_fpga_project $outputDir -part $PART
+set_property board_part $BOARD_PART [current_project]
 
 # Include the packaged IP
-set_property  ip_repo_paths  "$packageDir $adapterDir" [current_project]
+set_property  ip_repo_paths "$caliptrapackageDir" [current_project]
 update_ip_catalog
 
 # Create SOC block design
@@ -201,25 +95,38 @@ create_bd_design "caliptra_fpga_project_bd"
 # Add Caliptra package
 create_bd_cell -type ip -vlnv design:user:caliptra_package_top:1.0 caliptra_package_top_0
 
-# Add Zynq PS
-create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps_e_0
-set_property -dict [list \
-  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
-  CONFIG.PSU__USE__IRQ0 {1} \
-  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
-  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {5} \
-] [get_bd_cells zynq_ultra_ps_e_0]
+# Add Versal PS
+source create_versal_cips.tcl
+# Connections to PS:
+# set ps_m_axi ps_0/M_AXI_FPD
+# set ps_pl_clk ps_0/pl0_ref_clk
+# set ps_axi_aclk ps_0/m_axi_fpd_aclk
+# set ps_pl_resetn ps_0/pl0_resetn
+# set ps_gpio_i ps_0/LPD_GPIO_i
+# set ps_gpio_o ps_0/LPD_GPIO_o
+
+# Create XDC file with jtag constraints
+set xdc_fd [ open $outputDir/jtag_constraints.xdc w ]
+puts $xdc_fd {create_clock -period 5000.000 -name {jtag_clk} -waveform {0.000 2500.000} [get_pins {caliptra_fpga_project_bd_i/ps_0/inst/pspmc_0/inst/PS9_inst/EMIOGPIO2O[0]}]}
+puts $xdc_fd {set_clock_groups -asynchronous -group [get_clocks {jtag_clk}]}
+close $xdc_fd
 
 # Add AXI Interconnect
-create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
-set_property CONFIG.NUM_MI {3} [get_bd_cells axi_interconnect_0]
-
-# Add AXI APB Bridge for Caliptra
-create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0
+create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_interconnect_0
 set_property -dict [list \
-  CONFIG.C_APB_NUM_SLAVES {1} \
-  CONFIG.C_M_APB_PROTOCOL {apb4} \
-] [get_bd_cells axi_apb_bridge_0]
+  CONFIG.NUM_MI {7} \
+  CONFIG.NUM_SI {4} \
+] [get_bd_cells axi_interconnect_0]
+
+if {$APB} {
+  # Add AXI APB Bridge for Caliptra 1.x
+  create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0
+  set_property -dict [list \
+    CONFIG.C_APB_NUM_SLAVES {1} \
+    CONFIG.C_M_APB_PROTOCOL {apb4} \
+  ] [get_bd_cells axi_apb_bridge_0]
+  set_property location {3 1041 439} [get_bd_cells axi_apb_bridge_0]
+}
 
 # Add AXI BRAM Controller for backdoor access to IMEM
 create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0
@@ -229,78 +136,98 @@ set_property CONFIG.SINGLE_PORT_BRAM {1} [get_bd_cells axi_bram_ctrl_0]
 create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0
 
 # Move blocks around on the block diagram. This step is optional.
-set_property location {1 177 345} [get_bd_cells zynq_ultra_ps_e_0]
+set_property location {1 177 345} [get_bd_cells ps_0]
 set_property location {2 696 373} [get_bd_cells axi_interconnect_0]
 set_property location {2 707 654} [get_bd_cells proc_sys_reset_0]
-set_property location {3 1041 439} [get_bd_cells axi_apb_bridge_0]
 set_property location {3 1151 617} [get_bd_cells axi_bram_ctrl_0]
 set_property location {4 1335 456} [get_bd_cells caliptra_package_top_0]
 
-# Create interface connections
-connect_bd_intf_net -intf_net axi_apb_bridge_0_APB_M [get_bd_intf_pins axi_apb_bridge_0/APB_M] [get_bd_intf_pins caliptra_package_top_0/s_apb]
-connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_apb_bridge_0/AXI4_LITE] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
-connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
-connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M02_AXI]
-connect_bd_intf_net [get_bd_intf_pins caliptra_package_top_0/axi_bram] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA]
+# Create AXI bus connections
+connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins $ps_m_axi]
+# Caliptra M_AXI
+connect_bd_intf_net [get_bd_intf_pins caliptra_package_top_0/M_AXI_CALIPTRA] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S01_AXI]
 
-# Create port connections
-connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] [get_bd_pins caliptra_package_top_0/S_AXI_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
-connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_apb_bridge_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins caliptra_package_top_0/core_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
-# Caliptra SOC adapter connections
-connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins caliptra_package_top_0/S_AXI]
-
-connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
-connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
-connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
-connect_bd_net [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
-connect_bd_net [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
-
-# Create address segments
-assign_bd_address -offset 0x80000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs caliptra_package_top_0/S_AXI/reg0] -force
-assign_bd_address -offset 0x82000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force
-assign_bd_address -offset 0x90000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs caliptra_package_top_0/s_apb/Reg] -force
-
-if {$JTAG} {
-  # Connect JTAG signals to PS GPIO pins
-  connect_bd_net [get_bd_pins caliptra_package_top_0/jtag_out] [get_bd_pins zynq_ultra_ps_e_0/emio_gpio_i]
-  connect_bd_net [get_bd_pins caliptra_package_top_0/jtag_in]  [get_bd_pins zynq_ultra_ps_e_0/emio_gpio_o]
-
-  # Add constraints for JTAG signals
-  add_files -fileset constrs_1 $fpgaDir/src/jtag_constraints.xdc
+connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins caliptra_package_top_0/S_AXI_WRAPPER]
+if {$APB} {
+  connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins axi_apb_bridge_0/AXI4_LITE]
+  connect_bd_intf_net [get_bd_intf_pins axi_apb_bridge_0/APB_M] [get_bd_intf_pins caliptra_package_top_0/s_apb]
 } else {
-  # Tie off JTAG inputs
-  create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0
-  connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins caliptra_package_top_0/jtag_tck]
-  connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins caliptra_package_top_0/jtag_tms]
-  connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins caliptra_package_top_0/jtag_tdi]
-  connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins caliptra_package_top_0/jtag_trst_n]
+  connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins caliptra_package_top_0/S_AXI_CALIPTRA]
 }
+connect_bd_intf_net [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+connect_bd_intf_net [get_bd_intf_pins caliptra_package_top_0/axi_bram] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA]
+
+# Create reset connections
+connect_bd_net [get_bd_pins $ps_pl_resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+connect_bd_net -net proc_sys_reset_0_peripheral_aresetn \
+  [get_bd_pins proc_sys_reset_0/peripheral_aresetn] \
+  [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] \
+  [get_bd_pins axi_interconnect_0/aresetn] \
+  [get_bd_pins caliptra_package_top_0/S_AXI_WRAPPER_ARESETN] \
+  [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
+# Create clock connections
+connect_bd_net \
+  [get_bd_pins $ps_pl_clk] \
+  [get_bd_pins $ps_axi_aclk] \
+  [get_bd_pins proc_sys_reset_0/slowest_sync_clk] \
+  [get_bd_pins axi_apb_bridge_0/s_axi_aclk] \
+  [get_bd_pins axi_interconnect_0/aclk] \
+  [get_bd_pins caliptra_package_top_0/core_clk] \
+  [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] \
+  [get_bd_pins caliptra_ss_package_0/core_clk]
+
+
+# Create address segments for all AXI managers
+set managers {ps_0/M_AXI_FPD caliptra_package_top_0/M_AXI_CALIPTRA}
+foreach manager $managers {
+  # TODO: Commented out segments are placeholders for SS
+  assign_bd_address -offset 0xB0000000 -range 0x00018000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force
+  #assign_bd_address -offset 0xB0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs ss_imem_bram_ctrl_1/S_AXI/Mem0] -force
+  assign_bd_address -offset 0xA4010000 -range 0x00002000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs caliptra_package_top_0/S_AXI_WRAPPER/reg0] -force
+  #assign_bd_address -offset 0xA4020000 -range 0x00002000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs caliptra_ss_package_0/S_AXI_WRAPPER/reg0] -force
+  #assign_bd_address -offset 0xA4030000 -range 0x00002000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs caliptra_ss_package_0/S_AXI_I3C/reg0] -force
+  #assign_bd_address -offset 0xA4040000 -range 0x00002000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs caliptra_ss_package_0/S_AXI_MCU_DMA/reg0] -force
+  if {$APB} {
+    assign_bd_address -offset 0xA4100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs caliptra_package_top_0/s_apb/Reg] -force
+  } else {
+    assign_bd_address -offset 0xA4100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces $manager] [get_bd_addr_segs caliptra_package_top_0/S_AXI_CALIPTRA/reg0] -force
+  }
+}
+
+# Connect JTAG signals to PS GPIO pins
+connect_bd_net [get_bd_pins caliptra_package_top_0/jtag_out] [get_bd_pins $ps_gpio_i]
+connect_bd_net [get_bd_pins caliptra_package_top_0/jtag_in] [get_bd_pins $ps_gpio_o]
+
+# Add constraints for JTAG signals
+add_files -fileset constrs_1 $outputDir/jtag_constraints.xdc
 
 save_bd_design
+puts "Fileset when setting defines the second time: [current_fileset]"
 set_property verilog_define $VERILOG_OPTIONS [current_fileset]
+puts "\n\nVERILOG DEFINES: [get_property verilog_define [current_fileset]]"
 
 # Create the HDL wrapper for the block design and add it. This will be set as top.
 make_wrapper -files [get_files $outputDir/caliptra_fpga_project.srcs/sources_1/bd/caliptra_fpga_project_bd/caliptra_fpga_project_bd.bd] -top
 add_files -norecurse $outputDir/caliptra_fpga_project.gen/sources_1/bd/caliptra_fpga_project_bd/hdl/caliptra_fpga_project_bd_wrapper.v
+set_property top caliptra_fpga_project_bd_wrapper [current_fileset]
 
 update_compile_order -fileset sources_1
 
 # Assign the gated clock conversion setting in the caliptra_package_top out of context run.
-create_ip_run [get_files *.bd]
+create_ip_run [get_files caliptra_fpga_project_bd.bd]
 set_property STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION $GATED_CLOCK_CONVERSION [get_runs caliptra_fpga_project_bd_caliptra_package_top_0_0_synth_1]
 
-# The FPGA loading methods currently in use require the bin file to be generated.
-set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
+# Add DDR pin placement constraints
+add_files -fileset constrs_1 $fpgaDir/src/ddr4_constraints.xdc
 
 # Start build
 if {$BUILD} {
   launch_runs synth_1 -jobs 10
   wait_on_runs synth_1
-  launch_runs impl_1 -jobs 10
+  launch_runs impl_1 -to_step write_device_image -jobs 10
   wait_on_runs impl_1
   open_run impl_1
   report_utilization -file $outputDir/utilization.txt
-  # Embed git hash in USR_ACCESS register for bitstream identification.
-  set_property BITSTREAM.CONFIG.USR_ACCESS 0x$VERSION [current_design]
-  write_bitstream -bin_file $outputDir/caliptra_fpga
+
+  write_hw_platform -fixed -include_bit -force -file $outputDir/caliptra_fpga.xsa
 }
diff --git a/hw/fpga/fpga_wrapper_regs.md b/hw/fpga/fpga_wrapper_regs.md
new file mode 100644
index 0000000000..12508f5a5d
--- /dev/null
+++ b/hw/fpga/fpga_wrapper_regs.md
@@ -0,0 +1,328 @@
+<!---
+Markdown description for SystemRDL register map.
+
+Don't override. Generated from: caliptra_fpga_realtime_regs
+  - caliptra_fpga_realtime_regs.rdl
+-->
+
+## caliptra_fpga_realtime_regs address map
+
+- Absolute Address: 0x0
+- Base Offset: 0x0
+- Size: 0xA4011010
+
+|  Offset  |  Identifier  |Name|
+|----------|--------------|----|
+|0xA4010000|interface_regs|  — |
+|0xA4011000|   fifo_regs  |  — |
+
+## interface_regs register file
+
+- Absolute Address: 0xA4010000
+- Base Offset: 0xA4010000
+- Size: 0x48
+
+|Offset|       Identifier      |Name|
+|------|-----------------------|----|
+| 0x00 | generic_input_wires[0]|  — |
+| 0x04 | generic_input_wires[1]|  — |
+| 0x08 |generic_output_wires[0]|  — |
+| 0x0C |generic_output_wires[1]|  — |
+| 0x10 |    cptra_obf_key[0]   |  — |
+| 0x14 |    cptra_obf_key[1]   |  — |
+| 0x18 |    cptra_obf_key[2]   |  — |
+| 0x1C |    cptra_obf_key[3]   |  — |
+| 0x20 |    cptra_obf_key[4]   |  — |
+| 0x24 |    cptra_obf_key[5]   |  — |
+| 0x28 |    cptra_obf_key[6]   |  — |
+| 0x2C |    cptra_obf_key[7]   |  — |
+| 0x30 |        control        |  — |
+| 0x34 |         status        |  — |
+| 0x38 |         pauser        |  — |
+| 0x3C |     itrng_divisor     |  — |
+| 0x40 |      cycle_count      |  — |
+| 0x44 |      fpga_version     |  — |
+
+### generic_input_wires register
+
+- Absolute Address: 0xA4010000
+- Base Offset: 0x0
+- Size: 0x4
+- Array Dimensions: [2]
+- Array Stride: 0x4
+- Total Size: 0x8
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### generic_input_wires register
+
+- Absolute Address: 0xA4010004
+- Base Offset: 0x0
+- Size: 0x4
+- Array Dimensions: [2]
+- Array Stride: 0x4
+- Total Size: 0x8
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### generic_output_wires register
+
+- Absolute Address: 0xA4010008
+- Base Offset: 0x8
+- Size: 0x4
+- Array Dimensions: [2]
+- Array Stride: 0x4
+- Total Size: 0x8
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |   r  | 0x0 |  — |
+
+### generic_output_wires register
+
+- Absolute Address: 0xA401000C
+- Base Offset: 0x8
+- Size: 0x4
+- Array Dimensions: [2]
+- Array Stride: 0x4
+- Total Size: 0x8
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |   r  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA4010010
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA4010014
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA4010018
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA401001C
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA4010020
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA4010024
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA4010028
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### cptra_obf_key register
+
+- Absolute Address: 0xA401002C
+- Base Offset: 0x10
+- Size: 0x4
+- Array Dimensions: [8]
+- Array Stride: 0x4
+- Total Size: 0x20
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|   value  |  rw  | 0x0 |  — |
+
+### control register
+
+- Absolute Address: 0xA4010030
+- Base Offset: 0x30
+- Size: 0x4
+
+|Bits|     Identifier    |Access|Reset|Name|
+|----|-------------------|------|-----|----|
+|  0 |   cptra_pwrgood   |  rw  | 0x0 |  — |
+|  1 |    cptra_rst_b    |  rw  | 0x0 |  — |
+|  2 |  ss_debug_locked  |  rw  | 0x0 |  — |
+| 4:3|ss_device_lifecycle|  rw  | 0x0 |  — |
+|  5 |     scan_mode     |  rw  | 0x0 |  — |
+|  6 |  bootfsm_brkpoint |  rw  | 0x0 |  — |
+
+### status register
+
+- Absolute Address: 0xA4010034
+- Base Offset: 0x34
+- Size: 0x4
+
+|Bits|       Identifier      |Access|Reset|Name|
+|----|-----------------------|------|-----|----|
+|  0 |   cptra_error_fatal   |   r  | 0x0 |  — |
+|  1 | cptra_error_non_fatal |   r  | 0x0 |  — |
+|  2 |    ready_for_fuses    |   r  | 0x0 |  — |
+|  3 |ready_for_mb_processing|   r  | 0x0 |  — |
+|  4 |   ready_for_runtime   |   r  | 0x0 |  — |
+|  5 |   mailbox_data_avail  |   r  | 0x0 |  — |
+|  6 |   mailbox_flow_done   |   r  | 0x0 |  — |
+
+### pauser register
+
+- Absolute Address: 0xA4010038
+- Base Offset: 0x38
+- Size: 0x4
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|  pauser  |  rw  | 0x0 |  — |
+
+### itrng_divisor register
+
+- Absolute Address: 0xA401003C
+- Base Offset: 0x3C
+- Size: 0x4
+
+|Bits|  Identifier |Access|Reset|Name|
+|----|-------------|------|-----|----|
+|31:0|itrng_divisor|  rw  | 0x0 |  — |
+
+### cycle_count register
+
+- Absolute Address: 0xA4010040
+- Base Offset: 0x40
+- Size: 0x4
+
+|Bits| Identifier|Access|Reset|Name|
+|----|-----------|------|-----|----|
+|31:0|cycle_count|   r  | 0x0 |  — |
+
+### fpga_version register
+
+- Absolute Address: 0xA4010044
+- Base Offset: 0x44
+- Size: 0x4
+
+|Bits| Identifier |Access|Reset|Name|
+|----|------------|------|-----|----|
+|31:0|fpga_version|   r  | 0x0 |  — |
+
+## fifo_regs register file
+
+- Absolute Address: 0xA4011000
+- Base Offset: 0xA4011000
+- Size: 0x10
+
+|Offset|    Identifier   |Name|
+|------|-----------------|----|
+|  0x0 |  log_fifo_data  |  — |
+|  0x4 | log_fifo_status |  — |
+|  0x8 | itrng_fifo_data |  — |
+|  0xC |itrng_fifo_status|  — |
+
+### log_fifo_data register
+
+- Absolute Address: 0xA4011000
+- Base Offset: 0x0
+- Size: 0x4
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+| 7:0| next_char|   r  | 0x0 |  — |
+|  8 |char_valid|   r  | 0x0 |  — |
+
+### log_fifo_status register
+
+- Absolute Address: 0xA4011004
+- Base Offset: 0x4
+- Size: 0x4
+
+|Bits|  Identifier  |Access|Reset|Name|
+|----|--------------|------|-----|----|
+|  0 |log_fifo_empty|   r  | 0x0 |  — |
+|  1 | log_fifo_full|   r  | 0x0 |  — |
+
+### itrng_fifo_data register
+
+- Absolute Address: 0xA4011008
+- Base Offset: 0x8
+- Size: 0x4
+
+|Bits|Identifier|Access|Reset|Name|
+|----|----------|------|-----|----|
+|31:0|itrng_data|  rw  | 0x0 |  — |
+
+### itrng_fifo_status register
+
+- Absolute Address: 0xA401100C
+- Base Offset: 0xC
+- Size: 0x4
+
+|Bits|   Identifier   |Access|Reset|Name|
+|----|----------------|------|-----|----|
+|  0 |itrng_fifo_empty|   r  | 0x0 |  — |
+|  1 | itrng_fifo_full|   r  | 0x0 |  — |
+|  2 |itrng_fifo_reset|  rw  | 0x0 |  — |
diff --git a/hw/fpga/images/versal_boot_switch.jpg b/hw/fpga/images/versal_boot_switch.jpg
new file mode 100644
index 0000000000..c619c9a926
Binary files /dev/null and b/hw/fpga/images/versal_boot_switch.jpg differ
diff --git a/hw/fpga/io_module/io_module.c b/hw/fpga/io_module/io_module.c
index 2a7b3375c9..f35e5be2cf 100644
--- a/hw/fpga/io_module/io_module.c
+++ b/hw/fpga/io_module/io_module.c
@@ -14,6 +14,7 @@ static void uio_release(struct device *dev)
 
 int init_module(void)
 {
+    printk("Setting up uio device\n");
     // Create UIO devices
     dev_set_name(&uio_dev, caliptra_dev_name);
     uio_dev.release = uio_release;
@@ -26,24 +27,46 @@ int init_module(void)
     uio_info.name = caliptra_dev_name;
     uio_info.version = "1.0.0";
 
-    //  SOC connections
+    //  Caliptra FPGA wrapper
     uio_info.mem[0].name = "fpga_wrapper";
-    uio_info.mem[0].addr = 0x80000000;
-    uio_info.mem[0].size = 0x2000;
+    uio_info.mem[0].addr = 0xA4010000;
+    uio_info.mem[0].size = 0x00010000;
     uio_info.mem[0].memtype = UIO_MEM_PHYS;
 
     // Caliptra MMIO interface
     uio_info.mem[1].name = "caliptra";
-    uio_info.mem[1].addr = 0x90020000;
-    uio_info.mem[1].size = 0x20000;
+    uio_info.mem[1].addr = 0xA4100000;
+    uio_info.mem[1].size = 0x00040000;
     uio_info.mem[1].memtype = UIO_MEM_PHYS;
 
+    // Caliptra ROM
+    uio_info.mem[2].name = "rom";
+    uio_info.mem[2].addr = 0xB0000000;
+    uio_info.mem[2].size = 0x00018000;
+    uio_info.mem[2].memtype = UIO_MEM_PHYS;
+/*
+    // SS IMEM
+    uio_info.mem[3].name = "ss_imem";
+    uio_info.mem[3].addr = 0xB0020000;
+    uio_info.mem[3].size = 0x00010000;
+    uio_info.mem[3].memtype = UIO_MEM_PHYS;
+    // SS Wrapper
+    uio_info.mem[4].name = "ss_wrapper";
+    uio_info.mem[4].addr = 0xA4020000;
+    uio_info.mem[4].size = 0x00010000;
+    uio_info.mem[4].memtype = UIO_MEM_PHYS;
+    // I3C
+    uio_info.mem[5].name = "ss_i3c";
+    uio_info.mem[5].addr = 0xA4030000;
+    uio_info.mem[5].size = 0x00010000;
+    uio_info.mem[5].memtype = UIO_MEM_PHYS;
+*/
     // Register device
     if (uio_register_device(&uio_dev, &uio_info) < 0) {
         printk("Failing to register uio device\n");
         return -EIO;
     }
-
+    printk("Initialized uio device\n");
     return 0;
 }
 
diff --git a/hw/fpga/openocd_caliptra.txt b/hw/fpga/openocd_caliptra.txt
index e5d3c5b2c5..a4eda257ef 100644
--- a/hw/fpga/openocd_caliptra.txt
+++ b/hw/fpga/openocd_caliptra.txt
@@ -1,16 +1,20 @@
 adapter driver sysfsgpio
 adapter speed 1000
 
-# Find the gpiochip labeled with "zynqmp_gpio" and get the number
-regexp {.*gpiochip(\d*)/.*} [exec grep zynqmp_gpio {*}[glob /sys/class/gpio/*/label]] trash gpionum
+# Get the number of the versal_gpio gpiochip. This corresponds to the LPD GPIO controller
+regexp {.*gpiochip(\d*)/.*} [exec grep -H versal_gpio {*}[glob /sys/class/gpio/*/label]] trash gpionum
+puts stderr [glob /sys/class/gpio/*/label]
+puts stderr [exec grep pmc_gpio {*}[glob /sys/class/gpio/*/label]]
+
+# PL EMIO starts at pin 26
+set gpionum [expr {$gpionum + 26}]
 
 # Define pin numbers for sysfsgpio
-# EMIO pins start at 78
-sysfsgpio tck_num [expr {$gpionum + 78}]
-sysfsgpio tdi_num [expr {$gpionum + 79}]
-sysfsgpio tms_num [expr {$gpionum + 80}]
-sysfsgpio trst_num [expr {$gpionum + 81}]
-sysfsgpio tdo_num [expr {$gpionum + 82}]
+sysfsgpio tck_num [expr {$gpionum + 0}]
+sysfsgpio tdi_num [expr {$gpionum + 1}]
+sysfsgpio tms_num [expr {$gpionum + 2}]
+sysfsgpio trst_num [expr {$gpionum + 3}]
+sysfsgpio tdo_num [expr {$gpionum + 4}]
 
 transport select jtag
 
diff --git a/hw/fpga/setup_fpga.sh b/hw/fpga/setup_fpga.sh
index c2ab977934..5797bd9998 100755
--- a/hw/fpga/setup_fpga.sh
+++ b/hw/fpga/setup_fpga.sh
@@ -8,47 +8,10 @@ set -e
 CALIPTRA_ROOT=$(realpath "$(dirname "$( readlink -f -- "$0"; )")"/../../)
 
 function usage() {
-    echo "usage: $0 [binfile]"
-}
-
-function disable_cpu_idle() {
-    for i in $(seq 0 3); do
-        cpu_sysfs=/sys/devices/system/cpu/cpu"$i"/cpuidle/state1/disable
-        echo 1 >"$cpu_sysfs"
-        echo "    |- cpu[$i]"
-
-        # verify options were set
-        while IFS= read -r line; do
-            if [[ "$line" -ne "1" ]]; then
-                echo "[-] error setting cpu[$i] into idle state"
-                exit 1
-            fi
-        done <"$cpu_sysfs"
-    done
-}
-
-function reduce_fan_speed() {
-    if [[ ! -d /sys/class/gpio/gpio321 ]]
-    then
-        echo 321 >/sys/class/gpio/export
-        echo out >/sys/class/gpio/gpio321/direction
-    fi
+    echo "usage: $0"
 }
 
 function build_and_install_kernel_modules() {
-    # rom_backdoor.ko
-    if ! lsmod | grep -wq "rom_backdoor"
-    then
-        cd "$CALIPTRA_ROOT/hw/fpga/rom_backdoor" || exit 2
-        make
-
-        if [[ -f "$CALIPTRA_ROOT/hw/fpga/rom_backdoor/rom_backdoor.ko" ]]; then
-            insmod "$CALIPTRA_ROOT/hw/fpga/rom_backdoor/rom_backdoor.ko"
-        else
-            echo "[-] error inserting rom backdoor. module not found"
-            exit 2
-        fi
-    fi
 
     # io_module.ko
     if ! lsmod | grep -wq "io_module"
@@ -58,7 +21,7 @@ function build_and_install_kernel_modules() {
 
         if [[ -f "$CALIPTRA_ROOT/hw/fpga/io_module/io_module.ko" ]]; then
             insmod "$CALIPTRA_ROOT/hw/fpga/io_module/io_module.ko"
-            chmod 666 /dev/uio4
+            chmod 666 /dev/uio0
         else
             echo "[-] error inserting io module. module not found"
             exit 2
@@ -66,25 +29,6 @@ function build_and_install_kernel_modules() {
     fi
 }
 
-function set_fpga_pll_freq() {
-    echo 20000000 >/sys/bus/platform/drivers/xilinx_fclk/fclk0/set_rate
-}
-
-function install_fpga_image() {
-    if [[ $# -ne 1 ]]; then
-        echo "[-] no fpga image provided"
-        exit 3
-    fi
-
-    fpga_image="$1"
-    if [[ -z "$fpga_image" ]]; then
-        echo "[-] image $fpga_image does not exist. exiting."
-        exit 3
-    fi
-
-    fpgautil -b "$fpga_image" -f Full -n Full
-}
-
 # entrypoint
 if [[ $EUID -ne 0 ]]; then
     echo "[-] you must run this script as root"
@@ -92,26 +36,6 @@ if [[ $EUID -ne 0 ]]; then
     exit 1
 fi
 
-# check parameters
-if [[ $# -ne 1 ]]; then
-    usage "$(basename "$0")"
-    exit 1
-fi
-
-param_fpga_image="$1"
-
 # main execution
-echo "[*] Disabling CPU idle for cpu 0-3"
-disable_cpu_idle
-
-echo "[*] Reducing fan speeds"
-reduce_fan_speed
-
-echo "[*] Installing fpga image $param_fpga_image"
-install_fpga_image "$param_fpga_image"
-
 echo "[*] Building and installing kernel modules"
 build_and_install_kernel_modules
-
-echo "[*] Setting fpga frequency"
-set_fpga_pll_freq
diff --git a/hw/fpga/src/caliptra_fpga_realtime_regs.rdl b/hw/fpga/src/caliptra_fpga_realtime_regs.rdl
index 5035249635..c93f8f0b89 100644
--- a/hw/fpga/src/caliptra_fpga_realtime_regs.rdl
+++ b/hw/fpga/src/caliptra_fpga_realtime_regs.rdl
@@ -56,7 +56,7 @@ regfile interface_regs {
         field { sw=r; hw=rw; } cptra_error_non_fatal = 1'b0;
 
         field { sw=r; hw=rw; } ready_for_fuses = 1'b0;
-        field { sw=r; hw=rw; } ready_for_fw_push = 1'b0;
+        field { sw=r; hw=rw; } ready_for_mb_processing = 1'b0;
         field { sw=r; hw=rw; } ready_for_runtime = 1'b0;
 
         field { sw=r; hw=rw; } mailbox_data_avail = 1'b0;
@@ -83,6 +83,13 @@ regfile interface_regs {
 
         field {} cycle_count[32] = 32'b0;
     } cycle_count;
+
+    reg {
+        default sw=r;
+        default hw=rw;
+
+        field {} fpga_version[32] = 32'b0;
+    } fpga_version;
 };
 
 regfile fifo_regs {
@@ -111,6 +118,6 @@ addrmap caliptra_fpga_realtime_regs {
     default regwidth = 32;
     default accesswidth = 32;
 
-    interface_regs interface_regs @ 0x0000;
-    fifo_regs fifo_regs @ 0x1000;
+    interface_regs interface_regs @ 0xA4010000;
+    fifo_regs fifo_regs @ 0xA4011000;
 };
diff --git a/hw/fpga/src/caliptra_fpga_realtime_regs.sv b/hw/fpga/src/caliptra_fpga_realtime_regs.sv
index 1d8276c4e5..642b0b4769 100644
--- a/hw/fpga/src/caliptra_fpga_realtime_regs.sv
+++ b/hw/fpga/src/caliptra_fpga_realtime_regs.sv
@@ -16,7 +16,7 @@ module caliptra_fpga_realtime_regs (
     //--------------------------------------------------------------------------
     logic cpuif_req;
     logic cpuif_req_is_wr;
-    logic [12:0] cpuif_addr;
+    logic [31:0] cpuif_addr;
     logic [31:0] cpuif_wr_data;
     logic [31:0] cpuif_wr_biten;
     logic cpuif_req_stall_wr;
@@ -33,10 +33,10 @@ module caliptra_fpga_realtime_regs (
     logic [1:0] axil_n_in_flight;
     logic axil_prev_was_rd;
     logic axil_arvalid;
-    logic [12:0] axil_araddr;
+    logic [31:0] axil_araddr;
     logic axil_ar_accept;
     logic axil_awvalid;
-    logic [12:0] axil_awaddr;
+    logic [31:0] axil_awaddr;
     logic axil_wvalid;
     logic [31:0] axil_wdata;
     logic [3:0] axil_wstrb;
@@ -114,17 +114,17 @@ module caliptra_fpga_realtime_regs (
             if(axil_arvalid && !axil_prev_was_rd) begin
                 cpuif_req = '1;
                 cpuif_req_is_wr = '0;
-                cpuif_addr = {axil_araddr[12:2], 2'b0};
+                cpuif_addr = {axil_araddr[31:2], 2'b0};
                 if(!cpuif_req_stall_rd) axil_ar_accept = '1;
             end else if(axil_awvalid && axil_wvalid) begin
                 cpuif_req = '1;
                 cpuif_req_is_wr = '1;
-                cpuif_addr = {axil_awaddr[12:2], 2'b0};
+                cpuif_addr = {axil_awaddr[31:2], 2'b0};
                 if(!cpuif_req_stall_wr) axil_aw_accept = '1;
             end else if(axil_arvalid) begin
                 cpuif_req = '1;
                 cpuif_req_is_wr = '0;
-                cpuif_addr = {axil_araddr[12:2], 2'b0};
+                cpuif_addr = {axil_araddr[31:2], 2'b0};
                 if(!cpuif_req_stall_rd) axil_ar_accept = '1;
             end
         end
@@ -218,6 +218,7 @@ module caliptra_fpga_realtime_regs (
             logic pauser;
             logic itrng_divisor;
             logic cycle_count;
+            logic fpga_version;
         } interface_regs;
         struct {
             logic log_fifo_data;
@@ -234,23 +235,24 @@ module caliptra_fpga_realtime_regs (
 
     always_comb begin
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.interface_regs.generic_input_wires[i0] = cpuif_req_masked & (cpuif_addr == 13'h0 + i0*13'h4);
+            decoded_reg_strb.interface_regs.generic_input_wires[i0] = cpuif_req_masked & (cpuif_addr == 32'ha4010000 + (32)'(i0) * 32'h4);
         end
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.interface_regs.generic_output_wires[i0] = cpuif_req_masked & (cpuif_addr == 13'h8 + i0*13'h4);
+            decoded_reg_strb.interface_regs.generic_output_wires[i0] = cpuif_req_masked & (cpuif_addr == 32'ha4010008 + (32)'(i0) * 32'h4);
         end
         for(int i0=0; i0<8; i0++) begin
-            decoded_reg_strb.interface_regs.cptra_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 13'h10 + i0*13'h4);
+            decoded_reg_strb.interface_regs.cptra_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 32'ha4010010 + (32)'(i0) * 32'h4);
         end
-        decoded_reg_strb.interface_regs.control = cpuif_req_masked & (cpuif_addr == 13'h30);
-        decoded_reg_strb.interface_regs.status = cpuif_req_masked & (cpuif_addr == 13'h34);
-        decoded_reg_strb.interface_regs.pauser = cpuif_req_masked & (cpuif_addr == 13'h38);
-        decoded_reg_strb.interface_regs.itrng_divisor = cpuif_req_masked & (cpuif_addr == 13'h3c);
-        decoded_reg_strb.interface_regs.cycle_count = cpuif_req_masked & (cpuif_addr == 13'h40);
-        decoded_reg_strb.fifo_regs.log_fifo_data = cpuif_req_masked & (cpuif_addr == 13'h1000);
-        decoded_reg_strb.fifo_regs.log_fifo_status = cpuif_req_masked & (cpuif_addr == 13'h1004);
-        decoded_reg_strb.fifo_regs.itrng_fifo_data = cpuif_req_masked & (cpuif_addr == 13'h1008);
-        decoded_reg_strb.fifo_regs.itrng_fifo_status = cpuif_req_masked & (cpuif_addr == 13'h100c);
+        decoded_reg_strb.interface_regs.control = cpuif_req_masked & (cpuif_addr == 32'ha4010030);
+        decoded_reg_strb.interface_regs.status = cpuif_req_masked & (cpuif_addr == 32'ha4010034);
+        decoded_reg_strb.interface_regs.pauser = cpuif_req_masked & (cpuif_addr == 32'ha4010038);
+        decoded_reg_strb.interface_regs.itrng_divisor = cpuif_req_masked & (cpuif_addr == 32'ha401003c);
+        decoded_reg_strb.interface_regs.cycle_count = cpuif_req_masked & (cpuif_addr == 32'ha4010040);
+        decoded_reg_strb.interface_regs.fpga_version = cpuif_req_masked & (cpuif_addr == 32'ha4010044);
+        decoded_reg_strb.fifo_regs.log_fifo_data = cpuif_req_masked & (cpuif_addr == 32'ha4011000);
+        decoded_reg_strb.fifo_regs.log_fifo_status = cpuif_req_masked & (cpuif_addr == 32'ha4011004);
+        decoded_reg_strb.fifo_regs.itrng_fifo_data = cpuif_req_masked & (cpuif_addr == 32'ha4011008);
+        decoded_reg_strb.fifo_regs.itrng_fifo_status = cpuif_req_masked & (cpuif_addr == 32'ha401100c);
     end
 
     // Pass down signals to next stage
@@ -324,7 +326,7 @@ module caliptra_fpga_realtime_regs (
                 struct {
                     logic next;
                     logic load_next;
-                } ready_for_fw_push;
+                } ready_for_mb_processing;
                 struct {
                     logic next;
                     logic load_next;
@@ -356,6 +358,12 @@ module caliptra_fpga_realtime_regs (
                     logic load_next;
                 } cycle_count;
             } cycle_count;
+            struct {
+                struct {
+                    logic [31:0] next;
+                    logic load_next;
+                } fpga_version;
+            } fpga_version;
         } interface_regs;
         struct {
             struct {
@@ -451,7 +459,7 @@ module caliptra_fpga_realtime_regs (
                 } ready_for_fuses;
                 struct {
                     logic value;
-                } ready_for_fw_push;
+                } ready_for_mb_processing;
                 struct {
                     logic value;
                 } ready_for_runtime;
@@ -477,6 +485,11 @@ module caliptra_fpga_realtime_regs (
                     logic [31:0] value;
                 } cycle_count;
             } cycle_count;
+            struct {
+                struct {
+                    logic [31:0] value;
+                } fpga_version;
+            } fpga_version;
         } interface_regs;
         struct {
             struct {
@@ -532,8 +545,10 @@ module caliptra_fpga_realtime_regs (
         always_ff @(posedge clk) begin
             if(rst) begin
                 field_storage.interface_regs.generic_input_wires[i0].value.value <= 32'h0;
-            end else if(field_combo.interface_regs.generic_input_wires[i0].value.load_next) begin
-                field_storage.interface_regs.generic_input_wires[i0].value.value <= field_combo.interface_regs.generic_input_wires[i0].value.next;
+            end else begin
+                if(field_combo.interface_regs.generic_input_wires[i0].value.load_next) begin
+                    field_storage.interface_regs.generic_input_wires[i0].value.value <= field_combo.interface_regs.generic_input_wires[i0].value.next;
+                end
             end
         end
         assign hwif_out.interface_regs.generic_input_wires[i0].value.value = field_storage.interface_regs.generic_input_wires[i0].value.value;
@@ -555,8 +570,10 @@ module caliptra_fpga_realtime_regs (
         always_ff @(posedge clk) begin
             if(rst) begin
                 field_storage.interface_regs.generic_output_wires[i0].value.value <= 32'h0;
-            end else if(field_combo.interface_regs.generic_output_wires[i0].value.load_next) begin
-                field_storage.interface_regs.generic_output_wires[i0].value.value <= field_combo.interface_regs.generic_output_wires[i0].value.next;
+            end else begin
+                if(field_combo.interface_regs.generic_output_wires[i0].value.load_next) begin
+                    field_storage.interface_regs.generic_output_wires[i0].value.value <= field_combo.interface_regs.generic_output_wires[i0].value.next;
+                end
             end
         end
         assign hwif_out.interface_regs.generic_output_wires[i0].value.value = field_storage.interface_regs.generic_output_wires[i0].value.value;
@@ -578,8 +595,10 @@ module caliptra_fpga_realtime_regs (
         always_ff @(posedge clk) begin
             if(rst) begin
                 field_storage.interface_regs.cptra_obf_key[i0].value.value <= 32'h0;
-            end else if(field_combo.interface_regs.cptra_obf_key[i0].value.load_next) begin
-                field_storage.interface_regs.cptra_obf_key[i0].value.value <= field_combo.interface_regs.cptra_obf_key[i0].value.next;
+            end else begin
+                if(field_combo.interface_regs.cptra_obf_key[i0].value.load_next) begin
+                    field_storage.interface_regs.cptra_obf_key[i0].value.value <= field_combo.interface_regs.cptra_obf_key[i0].value.next;
+                end
             end
         end
         assign hwif_out.interface_regs.cptra_obf_key[i0].value.value = field_storage.interface_regs.cptra_obf_key[i0].value.value;
@@ -600,8 +619,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.control.cptra_pwrgood.value <= 1'h0;
-        end else if(field_combo.interface_regs.control.cptra_pwrgood.load_next) begin
-            field_storage.interface_regs.control.cptra_pwrgood.value <= field_combo.interface_regs.control.cptra_pwrgood.next;
+        end else begin
+            if(field_combo.interface_regs.control.cptra_pwrgood.load_next) begin
+                field_storage.interface_regs.control.cptra_pwrgood.value <= field_combo.interface_regs.control.cptra_pwrgood.next;
+            end
         end
     end
     assign hwif_out.interface_regs.control.cptra_pwrgood.value = field_storage.interface_regs.control.cptra_pwrgood.value;
@@ -621,8 +642,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.control.cptra_rst_b.value <= 1'h0;
-        end else if(field_combo.interface_regs.control.cptra_rst_b.load_next) begin
-            field_storage.interface_regs.control.cptra_rst_b.value <= field_combo.interface_regs.control.cptra_rst_b.next;
+        end else begin
+            if(field_combo.interface_regs.control.cptra_rst_b.load_next) begin
+                field_storage.interface_regs.control.cptra_rst_b.value <= field_combo.interface_regs.control.cptra_rst_b.next;
+            end
         end
     end
     assign hwif_out.interface_regs.control.cptra_rst_b.value = field_storage.interface_regs.control.cptra_rst_b.value;
@@ -642,8 +665,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.control.ss_debug_locked.value <= 1'h0;
-        end else if(field_combo.interface_regs.control.ss_debug_locked.load_next) begin
-            field_storage.interface_regs.control.ss_debug_locked.value <= field_combo.interface_regs.control.ss_debug_locked.next;
+        end else begin
+            if(field_combo.interface_regs.control.ss_debug_locked.load_next) begin
+                field_storage.interface_regs.control.ss_debug_locked.value <= field_combo.interface_regs.control.ss_debug_locked.next;
+            end
         end
     end
     assign hwif_out.interface_regs.control.ss_debug_locked.value = field_storage.interface_regs.control.ss_debug_locked.value;
@@ -663,8 +688,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.control.ss_device_lifecycle.value <= 2'h0;
-        end else if(field_combo.interface_regs.control.ss_device_lifecycle.load_next) begin
-            field_storage.interface_regs.control.ss_device_lifecycle.value <= field_combo.interface_regs.control.ss_device_lifecycle.next;
+        end else begin
+            if(field_combo.interface_regs.control.ss_device_lifecycle.load_next) begin
+                field_storage.interface_regs.control.ss_device_lifecycle.value <= field_combo.interface_regs.control.ss_device_lifecycle.next;
+            end
         end
     end
     assign hwif_out.interface_regs.control.ss_device_lifecycle.value = field_storage.interface_regs.control.ss_device_lifecycle.value;
@@ -684,8 +711,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.control.scan_mode.value <= 1'h0;
-        end else if(field_combo.interface_regs.control.scan_mode.load_next) begin
-            field_storage.interface_regs.control.scan_mode.value <= field_combo.interface_regs.control.scan_mode.next;
+        end else begin
+            if(field_combo.interface_regs.control.scan_mode.load_next) begin
+                field_storage.interface_regs.control.scan_mode.value <= field_combo.interface_regs.control.scan_mode.next;
+            end
         end
     end
     assign hwif_out.interface_regs.control.scan_mode.value = field_storage.interface_regs.control.scan_mode.value;
@@ -705,8 +734,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.control.bootfsm_brkpoint.value <= 1'h0;
-        end else if(field_combo.interface_regs.control.bootfsm_brkpoint.load_next) begin
-            field_storage.interface_regs.control.bootfsm_brkpoint.value <= field_combo.interface_regs.control.bootfsm_brkpoint.next;
+        end else begin
+            if(field_combo.interface_regs.control.bootfsm_brkpoint.load_next) begin
+                field_storage.interface_regs.control.bootfsm_brkpoint.value <= field_combo.interface_regs.control.bootfsm_brkpoint.next;
+            end
         end
     end
     assign hwif_out.interface_regs.control.bootfsm_brkpoint.value = field_storage.interface_regs.control.bootfsm_brkpoint.value;
@@ -726,8 +757,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.status.cptra_error_fatal.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.cptra_error_fatal.load_next) begin
-            field_storage.interface_regs.status.cptra_error_fatal.value <= field_combo.interface_regs.status.cptra_error_fatal.next;
+        end else begin
+            if(field_combo.interface_regs.status.cptra_error_fatal.load_next) begin
+                field_storage.interface_regs.status.cptra_error_fatal.value <= field_combo.interface_regs.status.cptra_error_fatal.next;
+            end
         end
     end
     assign hwif_out.interface_regs.status.cptra_error_fatal.value = field_storage.interface_regs.status.cptra_error_fatal.value;
@@ -747,8 +780,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.status.cptra_error_non_fatal.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.cptra_error_non_fatal.load_next) begin
-            field_storage.interface_regs.status.cptra_error_non_fatal.value <= field_combo.interface_regs.status.cptra_error_non_fatal.next;
+        end else begin
+            if(field_combo.interface_regs.status.cptra_error_non_fatal.load_next) begin
+                field_storage.interface_regs.status.cptra_error_non_fatal.value <= field_combo.interface_regs.status.cptra_error_non_fatal.next;
+            end
         end
     end
     assign hwif_out.interface_regs.status.cptra_error_non_fatal.value = field_storage.interface_regs.status.cptra_error_non_fatal.value;
@@ -768,32 +803,36 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.status.ready_for_fuses.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.ready_for_fuses.load_next) begin
-            field_storage.interface_regs.status.ready_for_fuses.value <= field_combo.interface_regs.status.ready_for_fuses.next;
+        end else begin
+            if(field_combo.interface_regs.status.ready_for_fuses.load_next) begin
+                field_storage.interface_regs.status.ready_for_fuses.value <= field_combo.interface_regs.status.ready_for_fuses.next;
+            end
         end
     end
     assign hwif_out.interface_regs.status.ready_for_fuses.value = field_storage.interface_regs.status.ready_for_fuses.value;
-    // Field: caliptra_fpga_realtime_regs.interface_regs.status.ready_for_fw_push
+    // Field: caliptra_fpga_realtime_regs.interface_regs.status.ready_for_mb_processing
     always_comb begin
         automatic logic [0:0] next_c;
         automatic logic load_next_c;
-        next_c = field_storage.interface_regs.status.ready_for_fw_push.value;
+        next_c = field_storage.interface_regs.status.ready_for_mb_processing.value;
         load_next_c = '0;
         
         // HW Write
-        next_c = hwif_in.interface_regs.status.ready_for_fw_push.next;
+        next_c = hwif_in.interface_regs.status.ready_for_mb_processing.next;
         load_next_c = '1;
-        field_combo.interface_regs.status.ready_for_fw_push.next = next_c;
-        field_combo.interface_regs.status.ready_for_fw_push.load_next = load_next_c;
+        field_combo.interface_regs.status.ready_for_mb_processing.next = next_c;
+        field_combo.interface_regs.status.ready_for_mb_processing.load_next = load_next_c;
     end
     always_ff @(posedge clk) begin
         if(rst) begin
-            field_storage.interface_regs.status.ready_for_fw_push.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.ready_for_fw_push.load_next) begin
-            field_storage.interface_regs.status.ready_for_fw_push.value <= field_combo.interface_regs.status.ready_for_fw_push.next;
+            field_storage.interface_regs.status.ready_for_mb_processing.value <= 1'h0;
+        end else begin
+            if(field_combo.interface_regs.status.ready_for_mb_processing.load_next) begin
+                field_storage.interface_regs.status.ready_for_mb_processing.value <= field_combo.interface_regs.status.ready_for_mb_processing.next;
+            end
         end
     end
-    assign hwif_out.interface_regs.status.ready_for_fw_push.value = field_storage.interface_regs.status.ready_for_fw_push.value;
+    assign hwif_out.interface_regs.status.ready_for_mb_processing.value = field_storage.interface_regs.status.ready_for_mb_processing.value;
     // Field: caliptra_fpga_realtime_regs.interface_regs.status.ready_for_runtime
     always_comb begin
         automatic logic [0:0] next_c;
@@ -810,8 +849,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.status.ready_for_runtime.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.ready_for_runtime.load_next) begin
-            field_storage.interface_regs.status.ready_for_runtime.value <= field_combo.interface_regs.status.ready_for_runtime.next;
+        end else begin
+            if(field_combo.interface_regs.status.ready_for_runtime.load_next) begin
+                field_storage.interface_regs.status.ready_for_runtime.value <= field_combo.interface_regs.status.ready_for_runtime.next;
+            end
         end
     end
     assign hwif_out.interface_regs.status.ready_for_runtime.value = field_storage.interface_regs.status.ready_for_runtime.value;
@@ -831,8 +872,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.status.mailbox_data_avail.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.mailbox_data_avail.load_next) begin
-            field_storage.interface_regs.status.mailbox_data_avail.value <= field_combo.interface_regs.status.mailbox_data_avail.next;
+        end else begin
+            if(field_combo.interface_regs.status.mailbox_data_avail.load_next) begin
+                field_storage.interface_regs.status.mailbox_data_avail.value <= field_combo.interface_regs.status.mailbox_data_avail.next;
+            end
         end
     end
     assign hwif_out.interface_regs.status.mailbox_data_avail.value = field_storage.interface_regs.status.mailbox_data_avail.value;
@@ -852,8 +895,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.status.mailbox_flow_done.value <= 1'h0;
-        end else if(field_combo.interface_regs.status.mailbox_flow_done.load_next) begin
-            field_storage.interface_regs.status.mailbox_flow_done.value <= field_combo.interface_regs.status.mailbox_flow_done.next;
+        end else begin
+            if(field_combo.interface_regs.status.mailbox_flow_done.load_next) begin
+                field_storage.interface_regs.status.mailbox_flow_done.value <= field_combo.interface_regs.status.mailbox_flow_done.next;
+            end
         end
     end
     assign hwif_out.interface_regs.status.mailbox_flow_done.value = field_storage.interface_regs.status.mailbox_flow_done.value;
@@ -873,8 +918,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.pauser.pauser.value <= 32'h0;
-        end else if(field_combo.interface_regs.pauser.pauser.load_next) begin
-            field_storage.interface_regs.pauser.pauser.value <= field_combo.interface_regs.pauser.pauser.next;
+        end else begin
+            if(field_combo.interface_regs.pauser.pauser.load_next) begin
+                field_storage.interface_regs.pauser.pauser.value <= field_combo.interface_regs.pauser.pauser.next;
+            end
         end
     end
     assign hwif_out.interface_regs.pauser.pauser.value = field_storage.interface_regs.pauser.pauser.value;
@@ -894,8 +941,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.itrng_divisor.itrng_divisor.value <= 32'h0;
-        end else if(field_combo.interface_regs.itrng_divisor.itrng_divisor.load_next) begin
-            field_storage.interface_regs.itrng_divisor.itrng_divisor.value <= field_combo.interface_regs.itrng_divisor.itrng_divisor.next;
+        end else begin
+            if(field_combo.interface_regs.itrng_divisor.itrng_divisor.load_next) begin
+                field_storage.interface_regs.itrng_divisor.itrng_divisor.value <= field_combo.interface_regs.itrng_divisor.itrng_divisor.next;
+            end
         end
     end
     assign hwif_out.interface_regs.itrng_divisor.itrng_divisor.value = field_storage.interface_regs.itrng_divisor.itrng_divisor.value;
@@ -915,11 +964,36 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.interface_regs.cycle_count.cycle_count.value <= 32'h0;
-        end else if(field_combo.interface_regs.cycle_count.cycle_count.load_next) begin
-            field_storage.interface_regs.cycle_count.cycle_count.value <= field_combo.interface_regs.cycle_count.cycle_count.next;
+        end else begin
+            if(field_combo.interface_regs.cycle_count.cycle_count.load_next) begin
+                field_storage.interface_regs.cycle_count.cycle_count.value <= field_combo.interface_regs.cycle_count.cycle_count.next;
+            end
         end
     end
     assign hwif_out.interface_regs.cycle_count.cycle_count.value = field_storage.interface_regs.cycle_count.cycle_count.value;
+    // Field: caliptra_fpga_realtime_regs.interface_regs.fpga_version.fpga_version
+    always_comb begin
+        automatic logic [31:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.interface_regs.fpga_version.fpga_version.value;
+        load_next_c = '0;
+        
+        // HW Write
+        next_c = hwif_in.interface_regs.fpga_version.fpga_version.next;
+        load_next_c = '1;
+        field_combo.interface_regs.fpga_version.fpga_version.next = next_c;
+        field_combo.interface_regs.fpga_version.fpga_version.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.interface_regs.fpga_version.fpga_version.value <= 32'h0;
+        end else begin
+            if(field_combo.interface_regs.fpga_version.fpga_version.load_next) begin
+                field_storage.interface_regs.fpga_version.fpga_version.value <= field_combo.interface_regs.fpga_version.fpga_version.next;
+            end
+        end
+    end
+    assign hwif_out.interface_regs.fpga_version.fpga_version.value = field_storage.interface_regs.fpga_version.fpga_version.value;
     // Field: caliptra_fpga_realtime_regs.fifo_regs.log_fifo_data.next_char
     always_comb begin
         automatic logic [7:0] next_c;
@@ -936,8 +1010,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.log_fifo_data.next_char.value <= 8'h0;
-        end else if(field_combo.fifo_regs.log_fifo_data.next_char.load_next) begin
-            field_storage.fifo_regs.log_fifo_data.next_char.value <= field_combo.fifo_regs.log_fifo_data.next_char.next;
+        end else begin
+            if(field_combo.fifo_regs.log_fifo_data.next_char.load_next) begin
+                field_storage.fifo_regs.log_fifo_data.next_char.value <= field_combo.fifo_regs.log_fifo_data.next_char.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.log_fifo_data.next_char.value = field_storage.fifo_regs.log_fifo_data.next_char.value;
@@ -958,8 +1034,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.log_fifo_data.char_valid.value <= 1'h0;
-        end else if(field_combo.fifo_regs.log_fifo_data.char_valid.load_next) begin
-            field_storage.fifo_regs.log_fifo_data.char_valid.value <= field_combo.fifo_regs.log_fifo_data.char_valid.next;
+        end else begin
+            if(field_combo.fifo_regs.log_fifo_data.char_valid.load_next) begin
+                field_storage.fifo_regs.log_fifo_data.char_valid.value <= field_combo.fifo_regs.log_fifo_data.char_valid.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.log_fifo_data.char_valid.value = field_storage.fifo_regs.log_fifo_data.char_valid.value;
@@ -979,8 +1057,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.log_fifo_status.log_fifo_empty.value <= 1'h0;
-        end else if(field_combo.fifo_regs.log_fifo_status.log_fifo_empty.load_next) begin
-            field_storage.fifo_regs.log_fifo_status.log_fifo_empty.value <= field_combo.fifo_regs.log_fifo_status.log_fifo_empty.next;
+        end else begin
+            if(field_combo.fifo_regs.log_fifo_status.log_fifo_empty.load_next) begin
+                field_storage.fifo_regs.log_fifo_status.log_fifo_empty.value <= field_combo.fifo_regs.log_fifo_status.log_fifo_empty.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.log_fifo_status.log_fifo_empty.value = field_storage.fifo_regs.log_fifo_status.log_fifo_empty.value;
@@ -1000,8 +1080,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.log_fifo_status.log_fifo_full.value <= 1'h0;
-        end else if(field_combo.fifo_regs.log_fifo_status.log_fifo_full.load_next) begin
-            field_storage.fifo_regs.log_fifo_status.log_fifo_full.value <= field_combo.fifo_regs.log_fifo_status.log_fifo_full.next;
+        end else begin
+            if(field_combo.fifo_regs.log_fifo_status.log_fifo_full.load_next) begin
+                field_storage.fifo_regs.log_fifo_status.log_fifo_full.value <= field_combo.fifo_regs.log_fifo_status.log_fifo_full.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.log_fifo_status.log_fifo_full.value = field_storage.fifo_regs.log_fifo_status.log_fifo_full.value;
@@ -1021,8 +1103,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.itrng_fifo_data.itrng_data.value <= 32'h0;
-        end else if(field_combo.fifo_regs.itrng_fifo_data.itrng_data.load_next) begin
-            field_storage.fifo_regs.itrng_fifo_data.itrng_data.value <= field_combo.fifo_regs.itrng_fifo_data.itrng_data.next;
+        end else begin
+            if(field_combo.fifo_regs.itrng_fifo_data.itrng_data.load_next) begin
+                field_storage.fifo_regs.itrng_fifo_data.itrng_data.value <= field_combo.fifo_regs.itrng_fifo_data.itrng_data.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.itrng_fifo_data.itrng_data.value = field_storage.fifo_regs.itrng_fifo_data.itrng_data.value;
@@ -1043,8 +1127,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value <= 1'h0;
-        end else if(field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_empty.load_next) begin
-            field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value <= field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_empty.next;
+        end else begin
+            if(field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_empty.load_next) begin
+                field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value <= field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_empty.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value = field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value;
@@ -1064,8 +1150,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_full.value <= 1'h0;
-        end else if(field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_full.load_next) begin
-            field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_full.value <= field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_full.next;
+        end else begin
+            if(field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_full.load_next) begin
+                field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_full.value <= field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_full.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.itrng_fifo_status.itrng_fifo_full.value = field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_full.value;
@@ -1085,8 +1173,10 @@ module caliptra_fpga_realtime_regs (
     always_ff @(posedge clk) begin
         if(rst) begin
             field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value <= 1'h0;
-        end else if(field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_reset.load_next) begin
-            field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value <= field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_reset.next;
+        end else begin
+            if(field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_reset.load_next) begin
+                field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value <= field_combo.fifo_regs.itrng_fifo_status.itrng_fifo_reset.next;
+            end
         end
     end
     assign hwif_out.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value = field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value;
@@ -1107,15 +1197,15 @@ module caliptra_fpga_realtime_regs (
     logic [31:0] readback_data;
 
     // Assign readback values to a flattened array
-    logic [31:0] readback_array[21];
+    logic [31:0] readback_array[22];
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 0][31:0] = (decoded_reg_strb.interface_regs.generic_input_wires[i0] && !decoded_req_is_wr) ? field_storage.interface_regs.generic_input_wires[i0].value.value : '0;
+        assign readback_array[i0 * 1 + 0][31:0] = (decoded_reg_strb.interface_regs.generic_input_wires[i0] && !decoded_req_is_wr) ? field_storage.interface_regs.generic_input_wires[i0].value.value : '0;
     end
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 2][31:0] = (decoded_reg_strb.interface_regs.generic_output_wires[i0] && !decoded_req_is_wr) ? field_storage.interface_regs.generic_output_wires[i0].value.value : '0;
+        assign readback_array[i0 * 1 + 2][31:0] = (decoded_reg_strb.interface_regs.generic_output_wires[i0] && !decoded_req_is_wr) ? field_storage.interface_regs.generic_output_wires[i0].value.value : '0;
     end
     for(genvar i0=0; i0<8; i0++) begin
-        assign readback_array[i0*1 + 4][31:0] = (decoded_reg_strb.interface_regs.cptra_obf_key[i0] && !decoded_req_is_wr) ? field_storage.interface_regs.cptra_obf_key[i0].value.value : '0;
+        assign readback_array[i0 * 1 + 4][31:0] = (decoded_reg_strb.interface_regs.cptra_obf_key[i0] && !decoded_req_is_wr) ? field_storage.interface_regs.cptra_obf_key[i0].value.value : '0;
     end
     assign readback_array[12][0:0] = (decoded_reg_strb.interface_regs.control && !decoded_req_is_wr) ? field_storage.interface_regs.control.cptra_pwrgood.value : '0;
     assign readback_array[12][1:1] = (decoded_reg_strb.interface_regs.control && !decoded_req_is_wr) ? field_storage.interface_regs.control.cptra_rst_b.value : '0;
@@ -1127,7 +1217,7 @@ module caliptra_fpga_realtime_regs (
     assign readback_array[13][0:0] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.cptra_error_fatal.value : '0;
     assign readback_array[13][1:1] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.cptra_error_non_fatal.value : '0;
     assign readback_array[13][2:2] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.ready_for_fuses.value : '0;
-    assign readback_array[13][3:3] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.ready_for_fw_push.value : '0;
+    assign readback_array[13][3:3] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.ready_for_mb_processing.value : '0;
     assign readback_array[13][4:4] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.ready_for_runtime.value : '0;
     assign readback_array[13][5:5] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.mailbox_data_avail.value : '0;
     assign readback_array[13][6:6] = (decoded_reg_strb.interface_regs.status && !decoded_req_is_wr) ? field_storage.interface_regs.status.mailbox_flow_done.value : '0;
@@ -1135,17 +1225,18 @@ module caliptra_fpga_realtime_regs (
     assign readback_array[14][31:0] = (decoded_reg_strb.interface_regs.pauser && !decoded_req_is_wr) ? field_storage.interface_regs.pauser.pauser.value : '0;
     assign readback_array[15][31:0] = (decoded_reg_strb.interface_regs.itrng_divisor && !decoded_req_is_wr) ? field_storage.interface_regs.itrng_divisor.itrng_divisor.value : '0;
     assign readback_array[16][31:0] = (decoded_reg_strb.interface_regs.cycle_count && !decoded_req_is_wr) ? field_storage.interface_regs.cycle_count.cycle_count.value : '0;
-    assign readback_array[17][7:0] = (decoded_reg_strb.fifo_regs.log_fifo_data && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_data.next_char.value : '0;
-    assign readback_array[17][8:8] = (decoded_reg_strb.fifo_regs.log_fifo_data && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_data.char_valid.value : '0;
-    assign readback_array[17][31:9] = '0;
-    assign readback_array[18][0:0] = (decoded_reg_strb.fifo_regs.log_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_status.log_fifo_empty.value : '0;
-    assign readback_array[18][1:1] = (decoded_reg_strb.fifo_regs.log_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_status.log_fifo_full.value : '0;
-    assign readback_array[18][31:2] = '0;
-    assign readback_array[19][31:0] = (decoded_reg_strb.fifo_regs.itrng_fifo_data && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_data.itrng_data.value : '0;
-    assign readback_array[20][0:0] = (decoded_reg_strb.fifo_regs.itrng_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value : '0;
-    assign readback_array[20][1:1] = (decoded_reg_strb.fifo_regs.itrng_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_full.value : '0;
-    assign readback_array[20][2:2] = (decoded_reg_strb.fifo_regs.itrng_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value : '0;
-    assign readback_array[20][31:3] = '0;
+    assign readback_array[17][31:0] = (decoded_reg_strb.interface_regs.fpga_version && !decoded_req_is_wr) ? field_storage.interface_regs.fpga_version.fpga_version.value : '0;
+    assign readback_array[18][7:0] = (decoded_reg_strb.fifo_regs.log_fifo_data && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_data.next_char.value : '0;
+    assign readback_array[18][8:8] = (decoded_reg_strb.fifo_regs.log_fifo_data && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_data.char_valid.value : '0;
+    assign readback_array[18][31:9] = '0;
+    assign readback_array[19][0:0] = (decoded_reg_strb.fifo_regs.log_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_status.log_fifo_empty.value : '0;
+    assign readback_array[19][1:1] = (decoded_reg_strb.fifo_regs.log_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.log_fifo_status.log_fifo_full.value : '0;
+    assign readback_array[19][31:2] = '0;
+    assign readback_array[20][31:0] = (decoded_reg_strb.fifo_regs.itrng_fifo_data && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_data.itrng_data.value : '0;
+    assign readback_array[21][0:0] = (decoded_reg_strb.fifo_regs.itrng_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_empty.value : '0;
+    assign readback_array[21][1:1] = (decoded_reg_strb.fifo_regs.itrng_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_full.value : '0;
+    assign readback_array[21][2:2] = (decoded_reg_strb.fifo_regs.itrng_fifo_status && !decoded_req_is_wr) ? field_storage.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value : '0;
+    assign readback_array[21][31:3] = '0;
 
     // Reduce the array
     always_comb begin
@@ -1153,7 +1244,7 @@ module caliptra_fpga_realtime_regs (
         readback_done = decoded_req & ~decoded_req_is_wr;
         readback_err = '0;
         readback_data_var = '0;
-        for(int i=0; i<21; i++) readback_data_var |= readback_array[i];
+        for(int i=0; i<22; i++) readback_data_var |= readback_array[i];
         readback_data = readback_data_var;
     end
 
diff --git a/hw/fpga/src/caliptra_fpga_realtime_regs_pkg.sv b/hw/fpga/src/caliptra_fpga_realtime_regs_pkg.sv
index 2c6897de1d..215ed6e3c9 100644
--- a/hw/fpga/src/caliptra_fpga_realtime_regs_pkg.sv
+++ b/hw/fpga/src/caliptra_fpga_realtime_regs_pkg.sv
@@ -4,7 +4,7 @@
 package caliptra_fpga_realtime_regs_pkg;
 
     localparam CALIPTRA_FPGA_REALTIME_REGS_DATA_WIDTH = 32;
-    localparam CALIPTRA_FPGA_REALTIME_REGS_MIN_ADDR_WIDTH = 13;
+    localparam CALIPTRA_FPGA_REALTIME_REGS_MIN_ADDR_WIDTH = 32;
 
     typedef struct {
         logic [31:0] next;
@@ -28,7 +28,7 @@ package caliptra_fpga_realtime_regs_pkg;
 
     typedef struct {
         logic next;
-    } interface_regs__status__ready_for_fw_push__in_t;
+    } interface_regs__status__ready_for_mb_processing__in_t;
 
     typedef struct {
         logic next;
@@ -46,7 +46,7 @@ package caliptra_fpga_realtime_regs_pkg;
         interface_regs__status__cptra_error_fatal__in_t cptra_error_fatal;
         interface_regs__status__cptra_error_non_fatal__in_t cptra_error_non_fatal;
         interface_regs__status__ready_for_fuses__in_t ready_for_fuses;
-        interface_regs__status__ready_for_fw_push__in_t ready_for_fw_push;
+        interface_regs__status__ready_for_mb_processing__in_t ready_for_mb_processing;
         interface_regs__status__ready_for_runtime__in_t ready_for_runtime;
         interface_regs__status__mailbox_data_avail__in_t mailbox_data_avail;
         interface_regs__status__mailbox_flow_done__in_t mailbox_flow_done;
@@ -60,10 +60,19 @@ package caliptra_fpga_realtime_regs_pkg;
         interface_regs__cycle_count__cycle_count__in_t cycle_count;
     } interface_regs__cycle_count__in_t;
 
+    typedef struct {
+        logic [31:0] next;
+    } interface_regs__fpga_version__fpga_version__in_t;
+
+    typedef struct {
+        interface_regs__fpga_version__fpga_version__in_t fpga_version;
+    } interface_regs__fpga_version__in_t;
+
     typedef struct {
         interface_regs__generic_output_wires__in_t generic_output_wires[2];
         interface_regs__status__in_t status;
         interface_regs__cycle_count__in_t cycle_count;
+        interface_regs__fpga_version__in_t fpga_version;
     } interface_regs__in_t;
 
     typedef struct {
@@ -187,7 +196,7 @@ package caliptra_fpga_realtime_regs_pkg;
 
     typedef struct {
         logic value;
-    } interface_regs__status__ready_for_fw_push__out_t;
+    } interface_regs__status__ready_for_mb_processing__out_t;
 
     typedef struct {
         logic value;
@@ -205,7 +214,7 @@ package caliptra_fpga_realtime_regs_pkg;
         interface_regs__status__cptra_error_fatal__out_t cptra_error_fatal;
         interface_regs__status__cptra_error_non_fatal__out_t cptra_error_non_fatal;
         interface_regs__status__ready_for_fuses__out_t ready_for_fuses;
-        interface_regs__status__ready_for_fw_push__out_t ready_for_fw_push;
+        interface_regs__status__ready_for_mb_processing__out_t ready_for_mb_processing;
         interface_regs__status__ready_for_runtime__out_t ready_for_runtime;
         interface_regs__status__mailbox_data_avail__out_t mailbox_data_avail;
         interface_regs__status__mailbox_flow_done__out_t mailbox_flow_done;
@@ -235,6 +244,14 @@ package caliptra_fpga_realtime_regs_pkg;
         interface_regs__cycle_count__cycle_count__out_t cycle_count;
     } interface_regs__cycle_count__out_t;
 
+    typedef struct {
+        logic [31:0] value;
+    } interface_regs__fpga_version__fpga_version__out_t;
+
+    typedef struct {
+        interface_regs__fpga_version__fpga_version__out_t fpga_version;
+    } interface_regs__fpga_version__out_t;
+
     typedef struct {
         interface_regs__generic_input_wires__out_t generic_input_wires[2];
         interface_regs__generic_output_wires__out_t generic_output_wires[2];
@@ -244,6 +261,7 @@ package caliptra_fpga_realtime_regs_pkg;
         interface_regs__pauser__out_t pauser;
         interface_regs__itrng_divisor__out_t itrng_divisor;
         interface_regs__cycle_count__out_t cycle_count;
+        interface_regs__fpga_version__out_t fpga_version;
     } interface_regs__out_t;
 
     typedef struct {
diff --git a/hw/fpga/src/caliptra_package_top.v b/hw/fpga/src/caliptra_package_top.v
index 5816610e35..1dcbe108ad 100644
--- a/hw/fpga/src/caliptra_package_top.v
+++ b/hw/fpga/src/caliptra_package_top.v
@@ -24,7 +24,7 @@
 `define CALIPTRA_APB_ADDR_WIDTH      32 // bit-width APB address
 `define CALIPTRA_APB_DATA_WIDTH      32 // bit-width APB data
 
-module caliptra_package_top (
+module caliptra_package_apb_top (
     input wire core_clk,
 
     // Caliptra APB Interface
@@ -43,7 +43,7 @@ module caliptra_package_top (
     input  wire                       axi_bram_clk,
     input  wire                       axi_bram_en,
     input  wire [3:0]                 axi_bram_we,
-    input  wire [15:0]                axi_bram_addr,
+    input  wire [16:0]                axi_bram_addr,
     input  wire [31:0]                axi_bram_din,
     output wire [31:0]                axi_bram_dout,
     input  wire                       axi_bram_rst,
@@ -53,26 +53,26 @@ module caliptra_package_top (
     output wire [4:0]                 jtag_out,    // JTAG tdo
 
     // FPGA Realtime register AXI Interface
-    input	wire                      S_AXI_ARESETN,
-    input	wire                      S_AXI_AWVALID,
-    output	wire                      S_AXI_AWREADY,
-    input	wire [31:0]               S_AXI_AWADDR,
-    input	wire [2:0]                S_AXI_AWPROT,
-    input	wire                      S_AXI_WVALID,
-    output	wire                      S_AXI_WREADY,
-    input	wire [31:0]               S_AXI_WDATA,
-    input	wire [3:0]                S_AXI_WSTRB,
-    output	wire                      S_AXI_BVALID,
-    input	wire                      S_AXI_BREADY,
-    output	wire [1:0]                S_AXI_BRESP,
-    input	wire                      S_AXI_ARVALID,
-    output	wire                      S_AXI_ARREADY,
-    input	wire [31:0]               S_AXI_ARADDR,
-    input	wire [2:0]                S_AXI_ARPROT,
-    output	wire                      S_AXI_RVALID,
-    input	wire                      S_AXI_RREADY,
-    output	wire [31:0]               S_AXI_RDATA,
-    output	wire [1:0]                S_AXI_RRESP
+    input	wire                      S_AXI_WRAPPER_ARESETN,
+    input	wire                      S_AXI_WRAPPER_AWVALID,
+    output	wire                      S_AXI_WRAPPER_AWREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_AWADDR,
+    input	wire [2:0]                S_AXI_WRAPPER_AWPROT,
+    input	wire                      S_AXI_WRAPPER_WVALID,
+    output	wire                      S_AXI_WRAPPER_WREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_WDATA,
+    input	wire [3:0]                S_AXI_WRAPPER_WSTRB,
+    output	wire                      S_AXI_WRAPPER_BVALID,
+    input	wire                      S_AXI_WRAPPER_BREADY,
+    output	wire [1:0]                S_AXI_WRAPPER_BRESP,
+    input	wire                      S_AXI_WRAPPER_ARVALID,
+    output	wire                      S_AXI_WRAPPER_ARREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_ARADDR,
+    input	wire [2:0]                S_AXI_WRAPPER_ARPROT,
+    output	wire                      S_AXI_WRAPPER_RVALID,
+    input	wire                      S_AXI_WRAPPER_RREADY,
+    output	wire [31:0]               S_AXI_WRAPPER_RDATA,
+    output	wire [1:0]                S_AXI_WRAPPER_RRESP
     );
 
 caliptra_wrapper_top cptra_wrapper (
@@ -92,7 +92,7 @@ caliptra_wrapper_top cptra_wrapper (
     .axi_bram_clk(axi_bram_clk),
     .axi_bram_en(axi_bram_en),
     .axi_bram_we(axi_bram_we),
-    .axi_bram_addr(axi_bram_addr[15:2]),
+    .axi_bram_addr(axi_bram_addr[16:2]),
     .axi_bram_wrdata(axi_bram_din),
     .axi_bram_rddata(axi_bram_dout),
     .axi_bram_rst(axi_bram_rst),
@@ -105,26 +105,260 @@ caliptra_wrapper_top cptra_wrapper (
     .jtag_tdo(jtag_out[4]),
 
     // FPGA Realtime register AXI Interface
-    .S_AXI_ARESETN(S_AXI_ARESETN),
-    .S_AXI_AWVALID(S_AXI_AWVALID),
-    .S_AXI_AWREADY(S_AXI_AWREADY),
-    .S_AXI_AWADDR(S_AXI_AWADDR),
-    .S_AXI_AWPROT(S_AXI_AWPROT),
-    .S_AXI_WVALID(S_AXI_WVALID),
-    .S_AXI_WREADY(S_AXI_WREADY),
-    .S_AXI_WDATA(S_AXI_WDATA),
-    .S_AXI_WSTRB(S_AXI_WSTRB),
-    .S_AXI_BVALID(S_AXI_BVALID),
-    .S_AXI_BREADY(S_AXI_BREADY),
-    .S_AXI_BRESP(S_AXI_BRESP),
-    .S_AXI_ARVALID(S_AXI_ARVALID),
-    .S_AXI_ARREADY(S_AXI_ARREADY),
-    .S_AXI_ARADDR(S_AXI_ARADDR),
-    .S_AXI_ARPROT(S_AXI_ARPROT),
-    .S_AXI_RVALID(S_AXI_RVALID),
-    .S_AXI_RREADY(S_AXI_RREADY),
-    .S_AXI_RDATA(S_AXI_RDATA),
-    .S_AXI_RRESP(S_AXI_RRESP)
+    .S_AXI_WRAPPER_ARESETN(S_AXI_WRAPPER_ARESETN),
+    .S_AXI_WRAPPER_AWVALID(S_AXI_WRAPPER_AWVALID),
+    .S_AXI_WRAPPER_AWREADY(S_AXI_WRAPPER_AWREADY),
+    .S_AXI_WRAPPER_AWADDR(S_AXI_WRAPPER_AWADDR),
+    .S_AXI_WRAPPER_AWPROT(S_AXI_WRAPPER_AWPROT),
+    .S_AXI_WRAPPER_WVALID(S_AXI_WRAPPER_WVALID),
+    .S_AXI_WRAPPER_WREADY(S_AXI_WRAPPER_WREADY),
+    .S_AXI_WRAPPER_WDATA(S_AXI_WRAPPER_WDATA),
+    .S_AXI_WRAPPER_WSTRB(S_AXI_WRAPPER_WSTRB),
+    .S_AXI_WRAPPER_BVALID(S_AXI_WRAPPER_BVALID),
+    .S_AXI_WRAPPER_BREADY(S_AXI_WRAPPER_BREADY),
+    .S_AXI_WRAPPER_BRESP(S_AXI_WRAPPER_BRESP),
+    .S_AXI_WRAPPER_ARVALID(S_AXI_WRAPPER_ARVALID),
+    .S_AXI_WRAPPER_ARREADY(S_AXI_WRAPPER_ARREADY),
+    .S_AXI_WRAPPER_ARADDR(S_AXI_WRAPPER_ARADDR),
+    .S_AXI_WRAPPER_ARPROT(S_AXI_WRAPPER_ARPROT),
+    .S_AXI_WRAPPER_RVALID(S_AXI_WRAPPER_RVALID),
+    .S_AXI_WRAPPER_RREADY(S_AXI_WRAPPER_RREADY),
+    .S_AXI_WRAPPER_RDATA(S_AXI_WRAPPER_RDATA),
+    .S_AXI_WRAPPER_RRESP(S_AXI_WRAPPER_RRESP)
+);
+
+endmodule
+module caliptra_package_axi_top (
+    input wire core_clk,
+
+    // Caliptra AXI Interface
+    input  wire [31:0] S_AXI_CALIPTRA_AWADDR,
+    input  wire [1:0] S_AXI_CALIPTRA_AWBURST,
+    input  wire [2:0] S_AXI_CALIPTRA_AWSIZE,
+    input  wire [7:0] S_AXI_CALIPTRA_AWLEN,
+    input  wire [31:0] S_AXI_CALIPTRA_AWUSER,
+    input  wire [15:0] S_AXI_CALIPTRA_AWID,
+    input  wire S_AXI_CALIPTRA_AWLOCK,
+    input  wire S_AXI_CALIPTRA_AWVALID,
+    output wire S_AXI_CALIPTRA_AWREADY,
+    // W
+    input  wire [31:0] S_AXI_CALIPTRA_WDATA,
+    input  wire [3:0] S_AXI_CALIPTRA_WSTRB,
+    input  wire S_AXI_CALIPTRA_WVALID,
+    output wire S_AXI_CALIPTRA_WREADY,
+    input  wire S_AXI_CALIPTRA_WLAST,
+    // B
+    output wire [1:0] S_AXI_CALIPTRA_BRESP,
+    output wire [15:0] S_AXI_CALIPTRA_BID,
+    output wire S_AXI_CALIPTRA_BVALID,
+    input  wire S_AXI_CALIPTRA_BREADY,
+    // AR
+    input  wire [31:0] S_AXI_CALIPTRA_ARADDR,
+    input  wire [1:0] S_AXI_CALIPTRA_ARBURST,
+    input  wire [2:0] S_AXI_CALIPTRA_ARSIZE,
+    input  wire [7:0] S_AXI_CALIPTRA_ARLEN,
+    input  wire [31:0] S_AXI_CALIPTRA_ARUSER,
+    input  wire [15:0] S_AXI_CALIPTRA_ARID,
+    input  wire S_AXI_CALIPTRA_ARLOCK,
+    input  wire S_AXI_CALIPTRA_ARVALID,
+    output wire S_AXI_CALIPTRA_ARREADY,
+    // R
+    output wire [31:0] S_AXI_CALIPTRA_RDATA,
+    output wire [1:0] S_AXI_CALIPTRA_RRESP,
+    output wire [15:0] S_AXI_CALIPTRA_RID,
+    output wire S_AXI_CALIPTRA_RLAST,
+    output wire S_AXI_CALIPTRA_RVALID,
+    input  wire S_AXI_CALIPTRA_RREADY,
+
+    // Caliptra M_AXI Interface
+    output  wire [31:0] M_AXI_CALIPTRA_AWADDR,
+    output  wire [1:0] M_AXI_CALIPTRA_AWBURST,
+    output  wire [2:0] M_AXI_CALIPTRA_AWSIZE,
+    output  wire [7:0] M_AXI_CALIPTRA_AWLEN,
+    output  wire [31:0] M_AXI_CALIPTRA_AWUSER,
+    output  wire [15:0] M_AXI_CALIPTRA_AWID,
+    output  wire M_AXI_CALIPTRA_AWLOCK,
+    output  wire M_AXI_CALIPTRA_AWVALID,
+    input wire M_AXI_CALIPTRA_AWREADY,
+    // W
+    output  wire [31:0] M_AXI_CALIPTRA_WDATA,
+    output  wire [3:0] M_AXI_CALIPTRA_WSTRB,
+    output  wire M_AXI_CALIPTRA_WVALID,
+    input wire M_AXI_CALIPTRA_WREADY,
+    output  wire M_AXI_CALIPTRA_WLAST,
+    // B
+    input wire [1:0] M_AXI_CALIPTRA_BRESP,
+    input wire  [15:0] M_AXI_CALIPTRA_BID,
+    input wire M_AXI_CALIPTRA_BVALID,
+    output  wire M_AXI_CALIPTRA_BREADY,
+    // AR
+    output  wire [31:0] M_AXI_CALIPTRA_ARADDR,
+    output  wire [1:0] M_AXI_CALIPTRA_ARBURST,
+    output  wire [2:0] M_AXI_CALIPTRA_ARSIZE,
+    output  wire [7:0] M_AXI_CALIPTRA_ARLEN,
+    output  wire [31:0] M_AXI_CALIPTRA_ARUSER,
+    output  wire [15:0] M_AXI_CALIPTRA_ARID,
+    output  wire M_AXI_CALIPTRA_ARLOCK,
+    output  wire M_AXI_CALIPTRA_ARVALID,
+    input wire M_AXI_CALIPTRA_ARREADY,
+    // R
+    input wire [31:0] M_AXI_CALIPTRA_RDATA,
+    input wire [1:0] M_AXI_CALIPTRA_RRESP,
+    input wire [15:0] M_AXI_CALIPTRA_RID,
+    input wire M_AXI_CALIPTRA_RLAST,
+    input wire M_AXI_CALIPTRA_RVALID,
+    output  wire M_AXI_CALIPTRA_RREADY,
+
+    // ROM AXI Interface
+    input  wire                       axi_bram_clk,
+    input  wire                       axi_bram_en,
+    input  wire [3:0]                 axi_bram_we,
+    input  wire [16:0]                axi_bram_addr,
+    input  wire [31:0]                axi_bram_din,
+    output wire [31:0]                axi_bram_dout,
+    input  wire                       axi_bram_rst,
+
+    // JTAG Interface
+    input wire [4:0]                  jtag_in,     // JTAG input signals concatenated
+    output wire [4:0]                 jtag_out,    // JTAG tdo
+
+    // FPGA Realtime register AXI Interface
+    input	wire                      S_AXI_WRAPPER_ARESETN,
+    input	wire                      S_AXI_WRAPPER_AWVALID,
+    output	wire                      S_AXI_WRAPPER_AWREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_AWADDR,
+    input	wire [2:0]                S_AXI_WRAPPER_AWPROT,
+    input	wire                      S_AXI_WRAPPER_WVALID,
+    output	wire                      S_AXI_WRAPPER_WREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_WDATA,
+    input	wire [3:0]                S_AXI_WRAPPER_WSTRB,
+    output	wire                      S_AXI_WRAPPER_BVALID,
+    input	wire                      S_AXI_WRAPPER_BREADY,
+    output	wire [1:0]                S_AXI_WRAPPER_BRESP,
+    input	wire                      S_AXI_WRAPPER_ARVALID,
+    output	wire                      S_AXI_WRAPPER_ARREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_ARADDR,
+    input	wire [2:0]                S_AXI_WRAPPER_ARPROT,
+    output	wire                      S_AXI_WRAPPER_RVALID,
+    input	wire                      S_AXI_WRAPPER_RREADY,
+    output	wire [31:0]               S_AXI_WRAPPER_RDATA,
+    output	wire [1:0]                S_AXI_WRAPPER_RRESP
+    );
+
+caliptra_wrapper_top cptra_wrapper (
+    .core_clk(core_clk),
+
+    // Caliptra AXI Interface
+    .S_AXI_CALIPTRA_AWADDR(S_AXI_CALIPTRA_AWADDR),
+    .S_AXI_CALIPTRA_AWBURST(S_AXI_CALIPTRA_AWBURST),
+    .S_AXI_CALIPTRA_AWSIZE(S_AXI_CALIPTRA_AWSIZE),
+    .S_AXI_CALIPTRA_AWLEN(S_AXI_CALIPTRA_AWLEN),
+    .S_AXI_CALIPTRA_AWUSER(S_AXI_CALIPTRA_AWUSER),
+    .S_AXI_CALIPTRA_AWID(S_AXI_CALIPTRA_AWID),
+    .S_AXI_CALIPTRA_AWLOCK(S_AXI_CALIPTRA_AWLOCK),
+    .S_AXI_CALIPTRA_AWVALID(S_AXI_CALIPTRA_AWVALID),
+    .S_AXI_CALIPTRA_AWREADY(S_AXI_CALIPTRA_AWREADY),
+    .S_AXI_CALIPTRA_WDATA(S_AXI_CALIPTRA_WDATA),
+    .S_AXI_CALIPTRA_WSTRB(S_AXI_CALIPTRA_WSTRB),
+    .S_AXI_CALIPTRA_WVALID(S_AXI_CALIPTRA_WVALID),
+    .S_AXI_CALIPTRA_WREADY(S_AXI_CALIPTRA_WREADY),
+    .S_AXI_CALIPTRA_WLAST(S_AXI_CALIPTRA_WLAST),
+    .S_AXI_CALIPTRA_BRESP(S_AXI_CALIPTRA_BRESP),
+    .S_AXI_CALIPTRA_BID(S_AXI_CALIPTRA_BID),
+    .S_AXI_CALIPTRA_BVALID(S_AXI_CALIPTRA_BVALID),
+    .S_AXI_CALIPTRA_BREADY(S_AXI_CALIPTRA_BREADY),
+    .S_AXI_CALIPTRA_ARADDR(S_AXI_CALIPTRA_ARADDR),
+    .S_AXI_CALIPTRA_ARBURST(S_AXI_CALIPTRA_ARBURST),
+    .S_AXI_CALIPTRA_ARSIZE(S_AXI_CALIPTRA_ARSIZE),
+    .S_AXI_CALIPTRA_ARLEN(S_AXI_CALIPTRA_ARLEN),
+    .S_AXI_CALIPTRA_ARUSER(S_AXI_CALIPTRA_ARUSER),
+    .S_AXI_CALIPTRA_ARID(S_AXI_CALIPTRA_ARID),
+    .S_AXI_CALIPTRA_ARLOCK(S_AXI_CALIPTRA_ARLOCK),
+    .S_AXI_CALIPTRA_ARVALID(S_AXI_CALIPTRA_ARVALID),
+    .S_AXI_CALIPTRA_ARREADY(S_AXI_CALIPTRA_ARREADY),
+    .S_AXI_CALIPTRA_RDATA(S_AXI_CALIPTRA_RDATA),
+    .S_AXI_CALIPTRA_RRESP(S_AXI_CALIPTRA_RRESP),
+    .S_AXI_CALIPTRA_RID(S_AXI_CALIPTRA_RID),
+    .S_AXI_CALIPTRA_RLAST(S_AXI_CALIPTRA_RLAST),
+    .S_AXI_CALIPTRA_RVALID(S_AXI_CALIPTRA_RVALID),
+    .S_AXI_CALIPTRA_RREADY(S_AXI_CALIPTRA_RREADY),
+
+    // Caliptra M_AXI Interface
+    .M_AXI_CALIPTRA_AWADDR(M_AXI_CALIPTRA_AWADDR),
+    .M_AXI_CALIPTRA_AWBURST(M_AXI_CALIPTRA_AWBURST),
+    .M_AXI_CALIPTRA_AWSIZE(M_AXI_CALIPTRA_AWSIZE),
+    .M_AXI_CALIPTRA_AWLEN(M_AXI_CALIPTRA_AWLEN),
+    .M_AXI_CALIPTRA_AWUSER(M_AXI_CALIPTRA_AWUSER),
+    .M_AXI_CALIPTRA_AWID(M_AXI_CALIPTRA_AWID),
+    .M_AXI_CALIPTRA_AWLOCK(M_AXI_CALIPTRA_AWLOCK),
+    .M_AXI_CALIPTRA_AWVALID(M_AXI_CALIPTRA_AWVALID),
+    .M_AXI_CALIPTRA_AWREADY(M_AXI_CALIPTRA_AWREADY),
+    // W
+    .M_AXI_CALIPTRA_WDATA(M_AXI_CALIPTRA_WDATA),
+    .M_AXI_CALIPTRA_WSTRB(M_AXI_CALIPTRA_WSTRB),
+    .M_AXI_CALIPTRA_WVALID(M_AXI_CALIPTRA_WVALID),
+    .M_AXI_CALIPTRA_WREADY(M_AXI_CALIPTRA_WREADY),
+    .M_AXI_CALIPTRA_WLAST(M_AXI_CALIPTRA_WLAST),
+    // B
+    .M_AXI_CALIPTRA_BRESP(M_AXI_CALIPTRA_BRESP),
+    .M_AXI_CALIPTRA_BID(M_AXI_CALIPTRA_BID),
+    .M_AXI_CALIPTRA_BVALID(M_AXI_CALIPTRA_BVALID),
+    .M_AXI_CALIPTRA_BREADY(M_AXI_CALIPTRA_BREADY),
+    // AR
+    .M_AXI_CALIPTRA_ARADDR(M_AXI_CALIPTRA_ARADDR),
+    .M_AXI_CALIPTRA_ARBURST(M_AXI_CALIPTRA_ARBURST),
+    .M_AXI_CALIPTRA_ARSIZE(M_AXI_CALIPTRA_ARSIZE),
+    .M_AXI_CALIPTRA_ARLEN(M_AXI_CALIPTRA_ARLEN),
+    .M_AXI_CALIPTRA_ARUSER(M_AXI_CALIPTRA_ARUSER),
+    .M_AXI_CALIPTRA_ARID(M_AXI_CALIPTRA_ARID),
+    .M_AXI_CALIPTRA_ARLOCK(M_AXI_CALIPTRA_ARLOCK),
+    .M_AXI_CALIPTRA_ARVALID(M_AXI_CALIPTRA_ARVALID),
+    .M_AXI_CALIPTRA_ARREADY(M_AXI_CALIPTRA_ARREADY),
+    // R
+    .M_AXI_CALIPTRA_RDATA(M_AXI_CALIPTRA_RDATA),
+    .M_AXI_CALIPTRA_RRESP(M_AXI_CALIPTRA_RRESP),
+    .M_AXI_CALIPTRA_RID(M_AXI_CALIPTRA_RID),
+    .M_AXI_CALIPTRA_RLAST(M_AXI_CALIPTRA_RLAST),
+    .M_AXI_CALIPTRA_RVALID(M_AXI_CALIPTRA_RVALID),
+    .M_AXI_CALIPTRA_RREADY(M_AXI_CALIPTRA_RREADY),
+
+    // SOC access to program ROM
+    .axi_bram_clk(axi_bram_clk),
+    .axi_bram_en(axi_bram_en),
+    .axi_bram_we(axi_bram_we),
+    .axi_bram_addr(axi_bram_addr[16:2]),
+    .axi_bram_wrdata(axi_bram_din),
+    .axi_bram_rddata(axi_bram_dout),
+    .axi_bram_rst(axi_bram_rst),
+
+    // EL2 JTAG interface
+    .jtag_tck(jtag_in[0]),
+    .jtag_tdi(jtag_in[1]),
+    .jtag_tms(jtag_in[2]),
+    .jtag_trst_n(jtag_in[3]),
+    .jtag_tdo(jtag_out[4]),
+
+    // FPGA Realtime register AXI Interface
+    .S_AXI_WRAPPER_ARESETN(S_AXI_WRAPPER_ARESETN),
+    .S_AXI_WRAPPER_AWVALID(S_AXI_WRAPPER_AWVALID),
+    .S_AXI_WRAPPER_AWREADY(S_AXI_WRAPPER_AWREADY),
+    .S_AXI_WRAPPER_AWADDR(S_AXI_WRAPPER_AWADDR),
+    .S_AXI_WRAPPER_AWPROT(S_AXI_WRAPPER_AWPROT),
+    .S_AXI_WRAPPER_WVALID(S_AXI_WRAPPER_WVALID),
+    .S_AXI_WRAPPER_WREADY(S_AXI_WRAPPER_WREADY),
+    .S_AXI_WRAPPER_WDATA(S_AXI_WRAPPER_WDATA),
+    .S_AXI_WRAPPER_WSTRB(S_AXI_WRAPPER_WSTRB),
+    .S_AXI_WRAPPER_BVALID(S_AXI_WRAPPER_BVALID),
+    .S_AXI_WRAPPER_BREADY(S_AXI_WRAPPER_BREADY),
+    .S_AXI_WRAPPER_BRESP(S_AXI_WRAPPER_BRESP),
+    .S_AXI_WRAPPER_ARVALID(S_AXI_WRAPPER_ARVALID),
+    .S_AXI_WRAPPER_ARREADY(S_AXI_WRAPPER_ARREADY),
+    .S_AXI_WRAPPER_ARADDR(S_AXI_WRAPPER_ARADDR),
+    .S_AXI_WRAPPER_ARPROT(S_AXI_WRAPPER_ARPROT),
+    .S_AXI_WRAPPER_RVALID(S_AXI_WRAPPER_RVALID),
+    .S_AXI_WRAPPER_RREADY(S_AXI_WRAPPER_RREADY),
+    .S_AXI_WRAPPER_RDATA(S_AXI_WRAPPER_RDATA),
+    .S_AXI_WRAPPER_RRESP(S_AXI_WRAPPER_RRESP)
 );
 
 endmodule
diff --git a/hw/fpga/src/caliptra_veer_sram_export.sv b/hw/fpga/src/caliptra_veer_sram_export.sv
index 791511f8bf..185b51d9fe 100644
--- a/hw/fpga/src/caliptra_veer_sram_export.sv
+++ b/hw/fpga/src/caliptra_veer_sram_export.sv
@@ -46,8 +46,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                   .CLK (el2_mem_export.clk                                            ),
                                   .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                   .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                  .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                  .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                   .ROP (                                                              ),
                                   // These are used by SoC
                                   `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -62,8 +62,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                   .CLK (el2_mem_export.clk                                            ),
                                   .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                   .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                  .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                  .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                   .ROP (                                                              ),
                                   // These are used by SoC
                                   `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -77,8 +77,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                   .CLK (el2_mem_export.clk                                            ),
                                   .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                   .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                  .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                  .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                   .ROP (                                                              ),
                                   // These are used by SoC
                                   `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -92,8 +92,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                 .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -107,8 +107,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                 .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -122,8 +122,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                 .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -137,8 +137,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                 .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -152,8 +152,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                 .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                 .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
                                  `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -167,8 +167,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                 .CLK (el2_mem_export.clk                                            ),
                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                 .ROP (                                                              ),
                                 // These are used by SoC
                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -182,8 +182,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                 .CLK (el2_mem_export.clk                                            ),
                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                 .ROP (                                                              ),
                                 // These are used by SoC
                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -197,8 +197,8 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                 .CLK (el2_mem_export.clk                                            ),
                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
-                                .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
+                                .D   ({el2_mem_export.dccm_wr_ecc_bank[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_DATA_WIDTH-1:0]}),
+                                .Q   ({el2_mem_export.dccm_bank_ecc[i][pt.DCCM_ECC_WIDTH-1:0],el2_mem_export.dccm_bank_dout[i][pt.DCCM_DATA_WIDTH-1:0]}     ),
                                 .ROP (                                                              ),
                                 // These are used by SoC
                                 `EL2_LOCAL_DCCM_RAM_TEST_PORTS
@@ -223,8 +223,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .CLK (el2_mem_export.clk                       ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -247,8 +247,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -271,8 +271,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -295,8 +295,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -318,8 +318,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -341,8 +341,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -364,8 +364,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -387,8 +387,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -410,8 +410,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -433,8 +433,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
@@ -456,8 +456,8 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
-                                     .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
+                                     .D   ({el2_mem_export.iccm_bank_wr_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_wr_data[i][31:0]}),
+                                     .Q   ({el2_mem_export.iccm_bank_ecc[i][pt.ICCM_ECC_WIDTH-1:0],el2_mem_export.iccm_bank_dout[i][31:0]}   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
                                      .TEST1   (1'b0   ),
diff --git a/hw/fpga/src/caliptra_wrapper_top.sv b/hw/fpga/src/caliptra_wrapper_top.sv
index c5c9d93c42..1fb35a8b5b 100755
--- a/hw/fpga/src/caliptra_wrapper_top.sv
+++ b/hw/fpga/src/caliptra_wrapper_top.sv
@@ -23,7 +23,8 @@ import caliptra_fpga_realtime_regs_pkg::*;
 
 module caliptra_wrapper_top (
     input bit core_clk,
-    
+
+`ifdef CALIPTRA_APB
     // Caliptra APB Interface
     input  wire [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR,
     input  wire                       PENABLE,
@@ -34,12 +35,91 @@ module caliptra_wrapper_top (
     output wire                       PSLVERR,
     input  wire [`CALIPTRA_APB_DATA_WIDTH-1:0] PWDATA,
     input  wire                       PWRITE,
+`else
+    // Caliptra S_AXI Interface
+    input  wire [31:0] S_AXI_CALIPTRA_AWADDR,
+    input  wire [1:0] S_AXI_CALIPTRA_AWBURST,
+    input  wire [2:0] S_AXI_CALIPTRA_AWSIZE,
+    input  wire [7:0] S_AXI_CALIPTRA_AWLEN,
+    input  wire [31:0] S_AXI_CALIPTRA_AWUSER,
+    input  wire [15:0] S_AXI_CALIPTRA_AWID,
+    input  wire S_AXI_CALIPTRA_AWLOCK,
+    input  wire S_AXI_CALIPTRA_AWVALID,
+    output wire S_AXI_CALIPTRA_AWREADY,
+    // W
+    input  wire [31:0] S_AXI_CALIPTRA_WDATA,
+    input  wire [3:0] S_AXI_CALIPTRA_WSTRB,
+    input  wire S_AXI_CALIPTRA_WVALID,
+    output wire S_AXI_CALIPTRA_WREADY,
+    input  wire S_AXI_CALIPTRA_WLAST,
+    // B
+    output wire [1:0] S_AXI_CALIPTRA_BRESP,
+    output reg  [15:0] S_AXI_CALIPTRA_BID,
+    output wire S_AXI_CALIPTRA_BVALID,
+    input  wire S_AXI_CALIPTRA_BREADY,
+    // AR
+    input  wire [31:0] S_AXI_CALIPTRA_ARADDR,
+    input  wire [1:0] S_AXI_CALIPTRA_ARBURST,
+    input  wire [2:0] S_AXI_CALIPTRA_ARSIZE,
+    input  wire [7:0] S_AXI_CALIPTRA_ARLEN,
+    input  wire [31:0] S_AXI_CALIPTRA_ARUSER,
+    input  wire [15:0] S_AXI_CALIPTRA_ARID,
+    input  wire S_AXI_CALIPTRA_ARLOCK,
+    input  wire S_AXI_CALIPTRA_ARVALID,
+    output wire S_AXI_CALIPTRA_ARREADY,
+    // R
+    output wire [31:0] S_AXI_CALIPTRA_RDATA,
+    output wire [1:0] S_AXI_CALIPTRA_RRESP,
+    output reg  [15:0] S_AXI_CALIPTRA_RID,
+    output wire S_AXI_CALIPTRA_RLAST,
+    output wire S_AXI_CALIPTRA_RVALID,
+    input  wire S_AXI_CALIPTRA_RREADY,
+
+    // Caliptra M_AXI Interface
+    output  wire [31:0] M_AXI_CALIPTRA_AWADDR,
+    output  wire [1:0] M_AXI_CALIPTRA_AWBURST,
+    output  wire [2:0] M_AXI_CALIPTRA_AWSIZE,
+    output  wire [7:0] M_AXI_CALIPTRA_AWLEN,
+    output  wire [31:0] M_AXI_CALIPTRA_AWUSER,
+    output  wire [15:0] M_AXI_CALIPTRA_AWID,
+    output  wire M_AXI_CALIPTRA_AWLOCK,
+    output  wire M_AXI_CALIPTRA_AWVALID,
+    input wire M_AXI_CALIPTRA_AWREADY,
+    // W
+    output  wire [31:0] M_AXI_CALIPTRA_WDATA,
+    output  wire [3:0] M_AXI_CALIPTRA_WSTRB,
+    output  wire M_AXI_CALIPTRA_WVALID,
+    input wire M_AXI_CALIPTRA_WREADY,
+    output  wire M_AXI_CALIPTRA_WLAST,
+    // B
+    input wire [1:0] M_AXI_CALIPTRA_BRESP,
+    input reg  [15:0] M_AXI_CALIPTRA_BID,
+    input wire M_AXI_CALIPTRA_BVALID,
+    output  wire M_AXI_CALIPTRA_BREADY,
+    // AR
+    output  wire [31:0] M_AXI_CALIPTRA_ARADDR,
+    output  wire [1:0] M_AXI_CALIPTRA_ARBURST,
+    output  wire [2:0] M_AXI_CALIPTRA_ARSIZE,
+    output  wire [7:0] M_AXI_CALIPTRA_ARLEN,
+    output  wire [31:0] M_AXI_CALIPTRA_ARUSER,
+    output  wire [15:0] M_AXI_CALIPTRA_ARID,
+    output  wire M_AXI_CALIPTRA_ARLOCK,
+    output  wire M_AXI_CALIPTRA_ARVALID,
+    input wire M_AXI_CALIPTRA_ARREADY,
+    // R
+    input wire [31:0] M_AXI_CALIPTRA_RDATA,
+    input wire [1:0] M_AXI_CALIPTRA_RRESP,
+    input reg  [15:0] M_AXI_CALIPTRA_RID,
+    input wire M_AXI_CALIPTRA_RLAST,
+    input wire M_AXI_CALIPTRA_RVALID,
+    output  wire M_AXI_CALIPTRA_RREADY,
+`endif
 
     // ROM AXI Interface
     input  logic axi_bram_clk,
     input  logic axi_bram_en,
     input  logic [3:0] axi_bram_we,
-    input  logic [13:0] axi_bram_addr,
+    input  logic [14:0] axi_bram_addr,
     input  logic [31:0] axi_bram_wrdata,
     output logic [31:0] axi_bram_rddata,
     input  logic axi_bram_rst,
@@ -52,26 +132,26 @@ module caliptra_wrapper_top (
     output logic                      jtag_tdo,    // JTAG tdo
 
     // FPGA Realtime register AXI Interface
-    input	wire                      S_AXI_ARESETN,
-    input	wire                      S_AXI_AWVALID,
-    output	wire                      S_AXI_AWREADY,
-    input	wire [31:0]               S_AXI_AWADDR,
-    input	wire [2:0]                S_AXI_AWPROT,
-    input	wire                      S_AXI_WVALID,
-    output	wire                      S_AXI_WREADY,
-    input	wire [31:0]               S_AXI_WDATA,
-    input	wire [3:0]                S_AXI_WSTRB,
-    output	wire                      S_AXI_BVALID,
-    input	wire                      S_AXI_BREADY,
-    output	wire [1:0]                S_AXI_BRESP,
-    input	wire                      S_AXI_ARVALID,
-    output	wire                      S_AXI_ARREADY,
-    input	wire [31:0]               S_AXI_ARADDR,
-    input	wire [2:0]                S_AXI_ARPROT,
-    output	wire                      S_AXI_RVALID,
-    input	wire                      S_AXI_RREADY,
-    output	wire [31:0]               S_AXI_RDATA,
-    output	wire [1:0]                S_AXI_RRESP
+    input	wire                      S_AXI_WRAPPER_ARESETN,
+    input	wire                      S_AXI_WRAPPER_AWVALID,
+    output	wire                      S_AXI_WRAPPER_AWREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_AWADDR,
+    input	wire [2:0]                S_AXI_WRAPPER_AWPROT,
+    input	wire                      S_AXI_WRAPPER_WVALID,
+    output	wire                      S_AXI_WRAPPER_WREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_WDATA,
+    input	wire [3:0]                S_AXI_WRAPPER_WSTRB,
+    output	wire                      S_AXI_WRAPPER_BVALID,
+    input	wire                      S_AXI_WRAPPER_BREADY,
+    output	wire [1:0]                S_AXI_WRAPPER_BRESP,
+    input	wire                      S_AXI_WRAPPER_ARVALID,
+    output	wire                      S_AXI_WRAPPER_ARREADY,
+    input	wire [31:0]               S_AXI_WRAPPER_ARADDR,
+    input	wire [2:0]                S_AXI_WRAPPER_ARPROT,
+    output	wire                      S_AXI_WRAPPER_RVALID,
+    input	wire                      S_AXI_WRAPPER_RREADY,
+    output	wire [31:0]               S_AXI_WRAPPER_RDATA,
+    output	wire [1:0]                S_AXI_WRAPPER_RRESP
     );
 
     import soc_ifc_pkg::*;
@@ -80,15 +160,112 @@ module caliptra_wrapper_top (
 
     logic mbox_sram_cs;
     logic mbox_sram_we;
-    logic [14:0] mbox_sram_addr;
-    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata;
-    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata;
+    logic [15:0] mbox_sram_addr;
+    logic [39-1:0] mbox_sram_wdata; // TODO: What file can be brought in for defining CPTRA_MBOX_DATA_AND_ECC_W?
+    logic [39-1:0] mbox_sram_rdata; // TODO: What file can be brought in for defining CPTRA_MBOX_DATA_AND_ECC_W?
 
     logic imem_cs;
     logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr;
     logic [`CALIPTRA_IMEM_DATA_WIDTH-1:0] imem_rdata;
 
-    el2_mem_if el2_mem_export ();
+`ifndef CALIPTRA_APB
+    axi_if #(
+        .AW(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
+        .DW(`CALIPTRA_AXI_DATA_WIDTH),
+        .IW(`CALIPTRA_AXI_ID_WIDTH),
+        .UW(`CALIPTRA_AXI_USER_WIDTH)
+    ) s_axi (.clk(core_clk), .rst_n(hwif_out.interface_regs.control.cptra_rst_b.value));
+
+    // AW
+    assign s_axi.awaddr   = S_AXI_CALIPTRA_AWADDR;
+    assign s_axi.awburst  = S_AXI_CALIPTRA_AWBURST;
+    assign s_axi.awsize   = S_AXI_CALIPTRA_AWSIZE;
+    assign s_axi.awlen    = S_AXI_CALIPTRA_AWLEN;
+    assign s_axi.awuser   = hwif_out.interface_regs.pauser.pauser.value; //S_AXI_CALIPTRA_AWUSER;
+    assign s_axi.awid     = S_AXI_CALIPTRA_AWID;
+    assign s_axi.awlock   = S_AXI_CALIPTRA_AWLOCK;
+    assign s_axi.awvalid  = S_AXI_CALIPTRA_AWVALID;
+    assign S_AXI_CALIPTRA_AWREADY = s_axi.awready;
+    // W
+    assign s_axi.wdata    = S_AXI_CALIPTRA_WDATA;
+    assign s_axi.wstrb    = S_AXI_CALIPTRA_WSTRB;
+    assign s_axi.wvalid   = S_AXI_CALIPTRA_WVALID;
+    assign S_AXI_CALIPTRA_WREADY = s_axi.wready;
+    assign s_axi.wlast    = S_AXI_CALIPTRA_WLAST;
+    // B
+    assign S_AXI_CALIPTRA_BRESP  = s_axi.bresp;
+    assign S_AXI_CALIPTRA_BID    = s_axi.bid;
+    assign S_AXI_CALIPTRA_BVALID = s_axi.bvalid;
+    assign s_axi.bready  = S_AXI_CALIPTRA_BREADY;
+    // AR
+    assign s_axi.araddr  = S_AXI_CALIPTRA_ARADDR;
+    assign s_axi.arburst = S_AXI_CALIPTRA_ARBURST;
+    assign s_axi.arsize  = S_AXI_CALIPTRA_ARSIZE;
+    assign s_axi.arlen   = S_AXI_CALIPTRA_ARLEN;
+    assign s_axi.aruser  = hwif_out.interface_regs.pauser.pauser.value; // S_AXI_CALIPTRA_ARUSER;
+    assign s_axi.arid    = S_AXI_CALIPTRA_ARID;
+    assign s_axi.arlock  = S_AXI_CALIPTRA_ARLOCK;
+    assign s_axi.arvalid = S_AXI_CALIPTRA_ARVALID;
+    assign S_AXI_CALIPTRA_ARREADY = s_axi.arready;
+    // R
+    assign S_AXI_CALIPTRA_RDATA  = s_axi.rdata;
+    assign S_AXI_CALIPTRA_RRESP  = s_axi.rresp;
+    assign S_AXI_CALIPTRA_RID    = s_axi.rid;
+    assign S_AXI_CALIPTRA_RLAST  = s_axi.rlast;
+    assign S_AXI_CALIPTRA_RVALID = s_axi.rvalid;
+    assign s_axi.rready = S_AXI_CALIPTRA_RREADY;
+
+    // Unused master interface
+    axi_if #(
+        .AW(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
+        .DW(`CALIPTRA_AXI_DATA_WIDTH),
+        .IW(`CALIPTRA_AXI_ID_WIDTH),
+        .UW(`CALIPTRA_AXI_USER_WIDTH)
+    ) m_axi (.clk(core_clk), .rst_n(hwif_out.interface_regs.control.cptra_rst_b.value));
+
+    // AW
+    assign M_AXI_CALIPTRA_AWADDR =  m_axi.awaddr;
+    assign M_AXI_CALIPTRA_AWBURST = m_axi.awburst;
+    assign M_AXI_CALIPTRA_AWSIZE =  m_axi.awsize;
+    assign M_AXI_CALIPTRA_AWLEN =   m_axi.awlen;
+    assign M_AXI_CALIPTRA_AWUSER =  m_axi.awuser;
+    assign M_AXI_CALIPTRA_AWID = m_axi.awid;
+    assign M_AXI_CALIPTRA_AWLOCK = m_axi.awlock;
+    assign M_AXI_CALIPTRA_AWVALID = m_axi.awvalid;
+    assign m_axi.awready = M_AXI_CALIPTRA_AWREADY;
+    // W
+    assign M_AXI_CALIPTRA_WDATA =   m_axi.wdata;
+    assign M_AXI_CALIPTRA_WSTRB =   m_axi.wstrb;
+    assign M_AXI_CALIPTRA_WVALID =  m_axi.wvalid;
+    assign m_axi.wready = M_AXI_CALIPTRA_WREADY;
+    assign M_AXI_CALIPTRA_WLAST =   m_axi.wlast;
+    // B
+    assign m_axi.bresp =    M_AXI_CALIPTRA_BRESP;
+    assign m_axi.bid =      M_AXI_CALIPTRA_BID;
+    assign m_axi.bvalid =   M_AXI_CALIPTRA_BVALID;
+    assign M_AXI_CALIPTRA_BREADY = m_axi.bready;
+    // AR
+    assign M_AXI_CALIPTRA_ARADDR = m_axi.araddr;
+    assign M_AXI_CALIPTRA_ARBURST = m_axi.arburst;
+    assign M_AXI_CALIPTRA_ARSIZE = m_axi.arsize;
+    assign M_AXI_CALIPTRA_ARLEN = m_axi.arlen;
+    assign M_AXI_CALIPTRA_ARUSER = m_axi.aruser;
+    assign M_AXI_CALIPTRA_ARID = m_axi.arid;
+    assign M_AXI_CALIPTRA_ARLOCK = m_axi.arlock;
+    assign M_AXI_CALIPTRA_ARVALID = m_axi.arvalid;
+    assign m_axi.arready = M_AXI_CALIPTRA_ARREADY;
+    // R
+    assign m_axi.rdata =    M_AXI_CALIPTRA_RDATA;
+    assign m_axi.rresp =    M_AXI_CALIPTRA_RRESP;
+    assign m_axi.rid =      M_AXI_CALIPTRA_RID;
+    assign m_axi.rlast =    M_AXI_CALIPTRA_RLAST;
+    assign m_axi.rvalid =   M_AXI_CALIPTRA_RVALID;
+    assign M_AXI_CALIPTRA_RREADY = m_axi.rready;
+
+
+`endif
+    el2_mem_if el2_mem_export();
+    mldsa_mem_if mldsa_memory_export();
 
     initial begin
         BootFSM_BrkPoint = 1'b1; //Set to 1 even before anything starts
@@ -99,6 +276,11 @@ module caliptra_wrapper_top (
     logic [3:0] itrng_data;
     logic itrng_valid;
 
+    mldsa_mem_top mldsa_mem_top_inst (
+        .clk_i(core_clk),
+        .mldsa_memory_export(mldsa_memory_export.resp)
+);
+
 //=========================================================================-
 // DUT instance
 //=========================================================================-
@@ -121,9 +303,12 @@ caliptra_top caliptra_top_dut (
     .jtag_tms(jtag_tms),
     .jtag_trst_n(jtag_trst_n),
     .jtag_tdo(jtag_tdo),
+    // jtag_tdoEn
 
+`ifdef CALIPTRA_APB
+    // SoC APB Interface
     .PADDR(PADDR),
-    .PPROT(PPROT), // TODO: PPROT not provided?
+    .PPROT(PPROT),
     .PAUSER(hwif_out.interface_regs.pauser.pauser.value),
     .PENABLE(PENABLE),
     .PRDATA(PRDATA),
@@ -132,17 +317,24 @@ caliptra_top caliptra_top_dut (
     .PSLVERR(PSLVERR),
     .PWDATA(PWDATA),
     .PWRITE(PWRITE),
+`else
+    // Subordinate AXI Interface
+    .s_axi_w_if(s_axi.w_sub),
+    .s_axi_r_if(s_axi.r_sub),
 
-    .qspi_clk_o (),
-    .qspi_cs_no (),
-    .qspi_d_i   (),
-    .qspi_d_o   (),
-    .qspi_d_en_o(),
+    // Manager AXI Interface
+    .m_axi_w_if(m_axi.w_mgr),
+    .m_axi_r_if(m_axi.r_mgr),
+
+    // TODO: New addition
+    .recovery_data_avail(0),
+`endif
 
     .el2_mem_export(el2_mem_export.veer_sram_src),
+    .mldsa_memory_export(mldsa_memory_export.req),
 
     .ready_for_fuses(hwif_in.interface_regs.status.ready_for_fuses.next),
-    .ready_for_fw_push(hwif_in.interface_regs.status.ready_for_fw_push.next),
+    .ready_for_mb_processing(hwif_in.interface_regs.status.ready_for_mb_processing.next),
     .ready_for_runtime(hwif_in.interface_regs.status.ready_for_runtime.next),
 
     .mbox_sram_cs(mbox_sram_cs),
@@ -157,6 +349,7 @@ caliptra_top caliptra_top_dut (
 
     .mailbox_data_avail(hwif_in.interface_regs.status.mailbox_data_avail.next),
     .mailbox_flow_done(hwif_in.interface_regs.status.mailbox_flow_done.next),
+
     .BootFSM_BrkPoint(BootFSM_BrkPoint),
 
     //SoC Interrupts
@@ -181,73 +374,146 @@ caliptra_veer_sram_export veer_sram_export_inst (
 );
 
 // Mailbox RAM
-fpga_mbox_ram mbox_ram1
-(
-    .clka(core_clk),
-
-    .ena(mbox_sram_cs),
-    .wea(mbox_sram_we),
-    .addra(mbox_sram_addr),
-    .dina(mbox_sram_wdata),
-
-    .douta(mbox_sram_rdata)
-);
+   xpm_memory_spram #(
+      .ADDR_WIDTH_A(16),             // DECIMAL
+      .AUTO_SLEEP_TIME(0),           // DECIMAL
+      .BYTE_WRITE_WIDTH_A(39),       // DECIMAL
+      .CASCADE_HEIGHT(0),            // DECIMAL
+      .ECC_MODE("no_ecc"),           // String
+      .MEMORY_INIT_FILE("none"),     // String
+      .MEMORY_INIT_PARAM("0"),       // String
+      .MEMORY_OPTIMIZATION("true"),  // String
+      .MEMORY_PRIMITIVE("auto"),     // String
+      .MEMORY_SIZE(256*1024*8*39/32), // DECIMAL
+      .MESSAGE_CONTROL(0),           // DECIMAL
+      .READ_DATA_WIDTH_A(39),        // DECIMAL
+      .READ_LATENCY_A(1),            // DECIMAL
+      .READ_RESET_VALUE_A("0"),      // String
+      .RST_MODE_A("SYNC"),           // String
+      .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .USE_MEM_INIT(1),              // DECIMAL
+      .USE_MEM_INIT_MMI(0),          // DECIMAL
+      .WAKEUP_TIME("disable_sleep"), // String
+      .WRITE_DATA_WIDTH_A(39),       // DECIMAL
+      .WRITE_MODE_A("read_first"),   // String
+      .WRITE_PROTECT(1)              // DECIMAL
+   )
+   mbox_ram1 (
+      .dbiterra(),
+      .douta(mbox_sram_rdata),
+      .sbiterra(),
+      .addra(mbox_sram_addr),
+      .clka(core_clk),
+      .dina(mbox_sram_wdata),
+      .ena(mbox_sram_cs),
+      .injectdbiterra(0),
+      .injectsbiterra(0),
+      .regcea(1'b1),
+      .rsta(axi_bram_rst),
+      .sleep(0),
+      .wea(mbox_sram_we)
+
+   );
 
 // SRAM for imem/ROM
-fpga_imem imem_inst1(
-    // Port A for Caliptra
-    .clka(core_clk),
-    .ena(imem_cs),
-    .wea(8'h0),
-    .addra(imem_addr),
-    .dina(0),
-    .douta(imem_rdata),
-    // Port B to the AXI bus for loading ROM
-    .clkb(axi_bram_clk),
-    .enb(axi_bram_en),
-    .web(axi_bram_we),
-    .addrb(axi_bram_addr),
-    .dinb(axi_bram_wrdata),
-    .doutb(axi_bram_rddata),
-    .rstb(axi_bram_rst)
-);
+   xpm_memory_tdpram #(
+      .ADDR_WIDTH_A(`CALIPTRA_IMEM_ADDR_WIDTH), // DECIMAL
+      .ADDR_WIDTH_B(15),              // DECIMAL
+      .AUTO_SLEEP_TIME(0),            // DECIMAL
+      .BYTE_WRITE_WIDTH_A(64),        // DECIMAL
+      .BYTE_WRITE_WIDTH_B(8),         // DECIMAL
+      .CASCADE_HEIGHT(0),             // DECIMAL
+      .CLOCKING_MODE("common_clock"), // String
+      .ECC_MODE("no_ecc"),            // String
+      .MEMORY_INIT_FILE("none"),      // String
+      .MEMORY_INIT_PARAM("0"),        // String
+      .MEMORY_OPTIMIZATION("false"),  // String
+      .MEMORY_PRIMITIVE("auto"),      // String
+      .MEMORY_SIZE(96*1024*8),        // DECIMAL
+      .MESSAGE_CONTROL(0),            // DECIMAL
+      .READ_DATA_WIDTH_A(64),         // DECIMAL
+      .READ_DATA_WIDTH_B(32),         // DECIMAL
+      .READ_LATENCY_A(1),             // DECIMAL
+      .READ_LATENCY_B(1),             // DECIMAL
+      .READ_RESET_VALUE_A("0"),       // String
+      .READ_RESET_VALUE_B("0"),       // String
+      .RST_MODE_A("SYNC"),            // String
+      .RST_MODE_B("SYNC"),            // String
+      .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
+      .USE_MEM_INIT(1),               // DECIMAL
+      .USE_MEM_INIT_MMI(0),           // DECIMAL
+      .WAKEUP_TIME("disable_sleep"),  // String
+      .WRITE_DATA_WIDTH_A(64),        // DECIMAL
+      .WRITE_DATA_WIDTH_B(32),        // DECIMAL
+      .WRITE_MODE_A("no_change"),     // String
+      .WRITE_MODE_B("no_change"),     // String
+      .WRITE_PROTECT(1)               // DECIMAL
+   )
+   imem_inst1 (
+      .dbiterra(),
+      .dbiterrb(),
+      .douta(imem_rdata),
+      .doutb(axi_bram_rddata),
+      .sbiterra(),
+      .sbiterrb(),
+      .addra(imem_addr),
+      .addrb(axi_bram_addr),
+      .clka(core_clk),
+      .clkb(core_clk),
+      .dina(0),
+      .dinb(axi_bram_wrdata),
+      .ena(imem_cs),
+      .enb(axi_bram_en),
+      .injectdbiterra(0),
+      .injectdbiterrb(0),
+      .injectsbiterra(0),
+      .injectsbiterrb(0),
+      .regcea(1),
+      .regceb(1),
+      .rsta(axi_bram_rst),
+      .rstb(axi_bram_rst),
+      .sleep(0),
+      .wea(8'h0),
+      .web(axi_bram_we)
+   );
 
     axi4lite_intf s_axil ();
 
     caliptra_fpga_realtime_regs__in_t hwif_in;
     caliptra_fpga_realtime_regs__out_t hwif_out;
 
-    assign S_AXI_AWREADY = s_axil.AWREADY;
-    assign S_AXI_WREADY = s_axil.WREADY;
-    assign S_AXI_BVALID = s_axil.BVALID;
-    assign S_AXI_BRESP = s_axil.BRESP;
-    assign S_AXI_ARREADY = s_axil.ARREADY;
-    assign S_AXI_RVALID = s_axil.RVALID;
-    assign S_AXI_RDATA = s_axil.RDATA;
-    assign S_AXI_RRESP = s_axil.RRESP;
+    assign S_AXI_WRAPPER_AWREADY = s_axil.AWREADY;
+    assign S_AXI_WRAPPER_WREADY = s_axil.WREADY;
+    assign S_AXI_WRAPPER_BVALID = s_axil.BVALID;
+    assign S_AXI_WRAPPER_BRESP = s_axil.BRESP;
+    assign S_AXI_WRAPPER_ARREADY = s_axil.ARREADY;
+    assign S_AXI_WRAPPER_RVALID = s_axil.RVALID;
+    assign S_AXI_WRAPPER_RDATA = s_axil.RDATA;
+    assign S_AXI_WRAPPER_RRESP = s_axil.RRESP;
 
     always_comb begin
-        s_axil.AWVALID = S_AXI_AWVALID;
-        s_axil.AWADDR = S_AXI_AWADDR;
-        s_axil.AWPROT = S_AXI_AWPROT;
+        s_axil.AWVALID = S_AXI_WRAPPER_AWVALID;
+        s_axil.AWADDR =  S_AXI_WRAPPER_AWADDR;
+        s_axil.AWPROT =  S_AXI_WRAPPER_AWPROT;
 
-        s_axil.WVALID = S_AXI_WVALID;
-        s_axil.WDATA = S_AXI_WDATA;
-        s_axil.WSTRB = S_AXI_WSTRB;
+        s_axil.WVALID =  S_AXI_WRAPPER_WVALID;
+        s_axil.WDATA =   S_AXI_WRAPPER_WDATA;
+        s_axil.WSTRB =   S_AXI_WRAPPER_WSTRB;
 
-        s_axil.BREADY = S_AXI_BREADY;
+        s_axil.BREADY =  S_AXI_WRAPPER_BREADY;
 
-        s_axil.ARVALID = S_AXI_ARVALID;
-        s_axil.ARADDR = S_AXI_ARADDR;
-        s_axil.ARPROT = S_AXI_ARPROT;
+        s_axil.ARVALID = S_AXI_WRAPPER_ARVALID;
+        s_axil.ARADDR =  S_AXI_WRAPPER_ARADDR;
+        s_axil.ARPROT =  S_AXI_WRAPPER_ARPROT;
 
-        s_axil.RREADY = S_AXI_RREADY;
+        s_axil.RREADY =  S_AXI_WRAPPER_RREADY;
     end
 
     // Register Block
     caliptra_fpga_realtime_regs regs (
         .clk(core_clk),
-        .rst(~S_AXI_ARESETN),
+        .rst(~S_AXI_WRAPPER_ARESETN),
 
         .s_axil(s_axil),
 
@@ -272,17 +538,52 @@ fpga_imem imem_inst1(
     assign fifo_write_en = caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_combo.CPTRA_GENERIC_OUTPUT_WIRES[0].generic_wires.load_next;
     assign fifo_char[7:0] = caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_combo.CPTRA_GENERIC_OUTPUT_WIRES[0].generic_wires.next[7:0];
 
-    log_fifo log_fifo_inst(
-        .clk (core_clk),
-        .srst (~S_AXI_ARESETN),
-        .dout (hwif_in.fifo_regs.log_fifo_data.next_char.next),
-        .empty (log_fifo_empty),
-        .full (hwif_in.fifo_regs.log_fifo_status.log_fifo_full.next),
-        .din (fifo_char),
-        .wr_en (fifo_write_en),
-        .rd_en (log_fifo_valid_f & hwif_out.fifo_regs.log_fifo_data.next_char.rd_swacc),
-        .prog_full () // [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0]
-    );
+   xpm_fifo_sync #(
+      .CASCADE_HEIGHT(0),         // DECIMAL
+      .DOUT_RESET_VALUE("0"),     // String
+      .ECC_MODE("no_ecc"),        // String
+      .FIFO_MEMORY_TYPE("block"), // String
+      .FIFO_READ_LATENCY(0),      // DECIMAL
+      .FIFO_WRITE_DEPTH(64*1024), // DECIMAL
+      .FULL_RESET_VALUE(0),       // DECIMAL
+      .PROG_EMPTY_THRESH(10),     // DECIMAL
+      .PROG_FULL_THRESH(7168),    // DECIMAL Currently unused
+      .RD_DATA_COUNT_WIDTH(16),   // DECIMAL
+      .READ_DATA_WIDTH(8),        // DECIMAL
+      .READ_MODE("fwft"),         // String
+      .SIM_ASSERT_CHK(0),         // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .USE_ADV_FEATURES("0000"),  // String
+      .WAKEUP_TIME(0),            // DECIMAL
+      .WRITE_DATA_WIDTH(8),       // DECIMAL
+      .WR_DATA_COUNT_WIDTH(16)    // DECIMAL
+   )
+   log_fifo_inst (
+      .almost_empty(),
+      .almost_full(),
+      .data_valid(),
+      .dbiterr(),
+      .dout(hwif_in.fifo_regs.log_fifo_data.next_char.next),
+      .empty(log_fifo_empty),
+      .full(hwif_in.fifo_regs.log_fifo_status.log_fifo_full.next),
+      .overflow(),
+      .prog_empty(),
+      .prog_full(),
+      .rd_data_count(),
+      .rd_rst_busy(),
+      .sbiterr(),
+      .underflow(),
+      .wr_ack(),
+      .wr_data_count(),
+      .wr_rst_busy(),
+      .din(fifo_char),
+      .injectdbiterr(0),
+      .injectsbiterr(0),
+      .rd_en(log_fifo_valid_f & hwif_out.fifo_regs.log_fifo_data.next_char.rd_swacc),
+      .rst(~S_AXI_WRAPPER_ARESETN),
+      .sleep(0),
+      .wr_clk(core_clk),
+      .wr_en(fifo_write_en)
+   );
 
 
 `ifdef CALIPTRA_INTERNAL_TRNG
@@ -294,17 +595,52 @@ fpga_imem imem_inst1(
         trng_fifo_wr_en <= hwif_out.fifo_regs.itrng_fifo_data.itrng_data.wr_swacc;
     end
 
-    itrng_fifo trng_fifo_inst(
-        .clk (core_clk),
-        .srst (hwif_out.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value),
-        .dout (itrng_data),
-        .empty (hwif_in.fifo_regs.itrng_fifo_status.itrng_fifo_empty.next),
-        .full (hwif_in.fifo_regs.itrng_fifo_status.itrng_fifo_full.next),
-        .din (hwif_out.fifo_regs.itrng_fifo_data.itrng_data.value),
-        .wr_en (trng_fifo_wr_en),
-        .rd_en (throttled_etrng_req),
-        .valid (itrng_valid)
-    );
+   xpm_fifo_sync #(
+      .CASCADE_HEIGHT(0),         // DECIMAL
+      .DOUT_RESET_VALUE("0"),     // String
+      .ECC_MODE("no_ecc"),        // String
+      .FIFO_MEMORY_TYPE("block"), // String
+      .FIFO_READ_LATENCY(1),      // DECIMAL
+      .FIFO_WRITE_DEPTH(1024),    // DECIMAL
+      .FULL_RESET_VALUE(0),       // DECIMAL
+      .PROG_EMPTY_THRESH(10),     // DECIMAL
+      .PROG_FULL_THRESH(10),      // DECIMAL
+      .RD_DATA_COUNT_WIDTH(13),   // DECIMAL
+      .READ_DATA_WIDTH(4),        // DECIMAL
+      .READ_MODE("std"),          // String
+      .SIM_ASSERT_CHK(0),         // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .USE_ADV_FEATURES("1000"),  // String
+      .WAKEUP_TIME(0),            // DECIMAL
+      .WRITE_DATA_WIDTH(32),      // DECIMAL
+      .WR_DATA_COUNT_WIDTH(11)    // DECIMAL
+   )
+   trng_fifo_inst (
+      .almost_empty(),
+      .almost_full(),
+      .data_valid(itrng_valid),
+      .dbiterr(),
+      .dout(itrng_data),
+      .empty(hwif_in.fifo_regs.itrng_fifo_status.itrng_fifo_empty.next),
+      .full(hwif_in.fifo_regs.itrng_fifo_status.itrng_fifo_full.next),
+      .overflow(),
+      .prog_empty(),
+      .prog_full(),
+      .rd_data_count(),
+      .rd_rst_busy(),
+      .sbiterr(),
+      .underflow(),
+      .wr_ack(),
+      .wr_data_count(),
+      .wr_rst_busy(),
+      .din(hwif_out.fifo_regs.itrng_fifo_data.itrng_data.value),
+      .injectdbiterr(0),
+      .injectsbiterr(0),
+      .rd_en(throttled_etrng_req),
+      .rst(hwif_out.fifo_regs.itrng_fifo_status.itrng_fifo_reset.value),
+      .sleep(0),
+      .wr_clk(core_clk),
+      .wr_en(trng_fifo_wr_en)
+   );
 
     // Throttle etrng_req.
     reg [31:0] counter;
@@ -333,4 +669,6 @@ fpga_imem imem_inst1(
     end
     assign hwif_in.interface_regs.cycle_count.cycle_count.next = cycle_count;
 
+
+    assign hwif_in.interface_regs.fpga_version.fpga_version.next = `FPGA_VERSION;
 endmodule
diff --git a/hw/fpga/src/ddr4_constraints.xdc b/hw/fpga/src/ddr4_constraints.xdc
new file mode 100644
index 0000000000..07c5a9168e
--- /dev/null
+++ b/hw/fpga/src/ddr4_constraints.xdc
@@ -0,0 +1,118 @@
+set_property PACKAGE_PIN AR47 [get_ports {ddr4_dimm1_act_n[0]}]
+set_property PACKAGE_PIN AL46 [get_ports {ddr4_dimm1_adr[0]}]
+set_property PACKAGE_PIN AL42 [get_ports {ddr4_dimm1_adr[10]}]
+set_property PACKAGE_PIN AK38 [get_ports {ddr4_dimm1_adr[11]}]
+set_property PACKAGE_PIN AN42 [get_ports {ddr4_dimm1_adr[12]}]
+set_property PACKAGE_PIN AU45 [get_ports {ddr4_dimm1_adr[13]}]
+set_property PACKAGE_PIN AK39 [get_ports {ddr4_dimm1_adr[14]}]
+set_property PACKAGE_PIN AK40 [get_ports {ddr4_dimm1_adr[15]}]
+set_property PACKAGE_PIN AL44 [get_ports {ddr4_dimm1_adr[16]}]
+set_property PACKAGE_PIN AU44 [get_ports {ddr4_dimm1_adr[1]}]
+set_property PACKAGE_PIN AR44 [get_ports {ddr4_dimm1_adr[2]}]
+set_property PACKAGE_PIN AM41 [get_ports {ddr4_dimm1_adr[3]}]
+set_property PACKAGE_PIN AL41 [get_ports {ddr4_dimm1_adr[4]}]
+set_property PACKAGE_PIN AL37 [get_ports {ddr4_dimm1_adr[5]}]
+set_property PACKAGE_PIN AM38 [get_ports {ddr4_dimm1_adr[6]}]
+set_property PACKAGE_PIN AP43 [get_ports {ddr4_dimm1_adr[7]}]
+set_property PACKAGE_PIN AN47 [get_ports {ddr4_dimm1_adr[8]}]
+set_property PACKAGE_PIN AT44 [get_ports {ddr4_dimm1_adr[9]}]
+set_property PACKAGE_PIN AN43 [get_ports {ddr4_dimm1_ba[0]}]
+set_property PACKAGE_PIN AL47 [get_ports {ddr4_dimm1_ba[1]}]
+set_property PACKAGE_PIN AP42 [get_ports {ddr4_dimm1_bg[0]}]
+set_property PACKAGE_PIN AT47 [get_ports {ddr4_dimm1_bg[1]}]
+set_property PACKAGE_PIN AR46 [get_ports {ddr4_dimm1_ck_t[0]}]
+set_property PACKAGE_PIN AT46 [get_ports {ddr4_dimm1_ck_c[0]}]
+set_property PACKAGE_PIN AR45 [get_ports {ddr4_dimm1_cke[0]}]
+set_property PACKAGE_PIN AL43 [get_ports {ddr4_dimm1_cs_n[0]}]
+set_property PACKAGE_PIN BC41 [get_ports {ddr4_dimm1_dm_n[0]}]
+set_property PACKAGE_PIN BB43 [get_ports {ddr4_dimm1_dm_n[1]}]
+set_property PACKAGE_PIN BB44 [get_ports {ddr4_dimm1_dm_n[2]}]
+set_property PACKAGE_PIN AR42 [get_ports {ddr4_dimm1_dm_n[3]}]
+set_property PACKAGE_PIN AH46 [get_ports {ddr4_dimm1_dm_n[4]}]
+set_property PACKAGE_PIN AH45 [get_ports {ddr4_dimm1_dm_n[5]}]
+set_property PACKAGE_PIN AG41 [get_ports {ddr4_dimm1_dm_n[6]}]
+set_property PACKAGE_PIN AG39 [get_ports {ddr4_dimm1_dm_n[7]}]
+set_property PACKAGE_PIN BE41 [get_ports {ddr4_dimm1_dq[0]}]
+set_property PACKAGE_PIN AV42 [get_ports {ddr4_dimm1_dq[10]}]
+set_property PACKAGE_PIN AV43 [get_ports {ddr4_dimm1_dq[11]}]
+set_property PACKAGE_PIN BE42 [get_ports {ddr4_dimm1_dq[12]}]
+set_property PACKAGE_PIN BD42 [get_ports {ddr4_dimm1_dq[13]}]
+set_property PACKAGE_PIN AW43 [get_ports {ddr4_dimm1_dq[14]}]
+set_property PACKAGE_PIN AW42 [get_ports {ddr4_dimm1_dq[15]}]
+set_property PACKAGE_PIN BD45 [get_ports {ddr4_dimm1_dq[16]}]
+set_property PACKAGE_PIN BC45 [get_ports {ddr4_dimm1_dq[17]}]
+set_property PACKAGE_PIN AV45 [get_ports {ddr4_dimm1_dq[18]}]
+set_property PACKAGE_PIN AW44 [get_ports {ddr4_dimm1_dq[19]}]
+set_property PACKAGE_PIN BF41 [get_ports {ddr4_dimm1_dq[1]}]
+set_property PACKAGE_PIN BD44 [get_ports {ddr4_dimm1_dq[20]}]
+set_property PACKAGE_PIN BE45 [get_ports {ddr4_dimm1_dq[21]}]
+set_property PACKAGE_PIN AW45 [get_ports {ddr4_dimm1_dq[22]}]
+set_property PACKAGE_PIN AY44 [get_ports {ddr4_dimm1_dq[23]}]
+set_property PACKAGE_PIN AM37 [get_ports {ddr4_dimm1_dq[24]}]
+set_property PACKAGE_PIN AN38 [get_ports {ddr4_dimm1_dq[25]}]
+set_property PACKAGE_PIN AR39 [get_ports {ddr4_dimm1_dq[26]}]
+set_property PACKAGE_PIN AT39 [get_ports {ddr4_dimm1_dq[27]}]
+set_property PACKAGE_PIN AT40 [get_ports {ddr4_dimm1_dq[28]}]
+set_property PACKAGE_PIN AT41 [get_ports {ddr4_dimm1_dq[29]}]
+set_property PACKAGE_PIN AV41 [get_ports {ddr4_dimm1_dq[2]}]
+set_property PACKAGE_PIN AP39 [get_ports {ddr4_dimm1_dq[30]}]
+set_property PACKAGE_PIN AN40 [get_ports {ddr4_dimm1_dq[31]}]
+set_property PACKAGE_PIN AJ47 [get_ports {ddr4_dimm1_dq[32]}]
+set_property PACKAGE_PIN AH47 [get_ports {ddr4_dimm1_dq[33]}]
+set_property PACKAGE_PIN AE46 [get_ports {ddr4_dimm1_dq[34]}]
+set_property PACKAGE_PIN AD45 [get_ports {ddr4_dimm1_dq[35]}]
+set_property PACKAGE_PIN AK47 [get_ports {ddr4_dimm1_dq[36]}]
+set_property PACKAGE_PIN AK46 [get_ports {ddr4_dimm1_dq[37]}]
+set_property PACKAGE_PIN AE47 [get_ports {ddr4_dimm1_dq[38]}]
+set_property PACKAGE_PIN AD47 [get_ports {ddr4_dimm1_dq[39]}]
+set_property PACKAGE_PIN AU41 [get_ports {ddr4_dimm1_dq[3]}]
+set_property PACKAGE_PIN AJ45 [get_ports {ddr4_dimm1_dq[40]}]
+set_property PACKAGE_PIN AJ44 [get_ports {ddr4_dimm1_dq[41]}]
+set_property PACKAGE_PIN AE44 [get_ports {ddr4_dimm1_dq[42]}]
+set_property PACKAGE_PIN AD44 [get_ports {ddr4_dimm1_dq[43]}]
+set_property PACKAGE_PIN AK45 [get_ports {ddr4_dimm1_dq[44]}]
+set_property PACKAGE_PIN AK44 [get_ports {ddr4_dimm1_dq[45]}]
+set_property PACKAGE_PIN AE45 [get_ports {ddr4_dimm1_dq[46]}]
+set_property PACKAGE_PIN AF44 [get_ports {ddr4_dimm1_dq[47]}]
+set_property PACKAGE_PIN AH41 [get_ports {ddr4_dimm1_dq[48]}]
+set_property PACKAGE_PIN AH40 [get_ports {ddr4_dimm1_dq[49]}]
+set_property PACKAGE_PIN BG41 [get_ports {ddr4_dimm1_dq[4]}]
+set_property PACKAGE_PIN AD40 [get_ports {ddr4_dimm1_dq[50]}]
+set_property PACKAGE_PIN AC39 [get_ports {ddr4_dimm1_dq[51]}]
+set_property PACKAGE_PIN AH39 [get_ports {ddr4_dimm1_dq[52]}]
+set_property PACKAGE_PIN AJ40 [get_ports {ddr4_dimm1_dq[53]}]
+set_property PACKAGE_PIN AD41 [get_ports {ddr4_dimm1_dq[54]}]
+set_property PACKAGE_PIN AE40 [get_ports {ddr4_dimm1_dq[55]}]
+set_property PACKAGE_PIN AG37 [get_ports {ddr4_dimm1_dq[56]}]
+set_property PACKAGE_PIN AH38 [get_ports {ddr4_dimm1_dq[57]}]
+set_property PACKAGE_PIN AD37 [get_ports {ddr4_dimm1_dq[58]}]
+set_property PACKAGE_PIN AC37 [get_ports {ddr4_dimm1_dq[59]}]
+set_property PACKAGE_PIN BF42 [get_ports {ddr4_dimm1_dq[5]}]
+set_property PACKAGE_PIN AH37 [get_ports {ddr4_dimm1_dq[60]}]
+set_property PACKAGE_PIN AJ38 [get_ports {ddr4_dimm1_dq[61]}]
+set_property PACKAGE_PIN AD39 [get_ports {ddr4_dimm1_dq[62]}]
+set_property PACKAGE_PIN AD38 [get_ports {ddr4_dimm1_dq[63]}]
+set_property PACKAGE_PIN AW41 [get_ports {ddr4_dimm1_dq[6]}]
+set_property PACKAGE_PIN AW40 [get_ports {ddr4_dimm1_dq[7]}]
+set_property PACKAGE_PIN BC42 [get_ports {ddr4_dimm1_dq[8]}]
+set_property PACKAGE_PIN BC43 [get_ports {ddr4_dimm1_dq[9]}]
+set_property PACKAGE_PIN AY41 [get_ports {ddr4_dimm1_dqs_t[0]}]
+set_property PACKAGE_PIN BA41 [get_ports {ddr4_dimm1_dqs_c[0]}]
+set_property PACKAGE_PIN AY42 [get_ports {ddr4_dimm1_dqs_t[1]}]
+set_property PACKAGE_PIN BA43 [get_ports {ddr4_dimm1_dqs_c[1]}]
+set_property PACKAGE_PIN AY45 [get_ports {ddr4_dimm1_dqs_t[2]}]
+set_property PACKAGE_PIN BA44 [get_ports {ddr4_dimm1_dqs_c[2]}]
+set_property PACKAGE_PIN AP40 [get_ports {ddr4_dimm1_dqs_t[3]}]
+set_property PACKAGE_PIN AP41 [get_ports {ddr4_dimm1_dqs_c[3]}]
+set_property PACKAGE_PIN AF47 [get_ports {ddr4_dimm1_dqs_t[4]}]
+set_property PACKAGE_PIN AF46 [get_ports {ddr4_dimm1_dqs_c[4]}]
+set_property PACKAGE_PIN AH43 [get_ports {ddr4_dimm1_dqs_t[5]}]
+set_property PACKAGE_PIN AG44 [get_ports {ddr4_dimm1_dqs_c[5]}]
+set_property PACKAGE_PIN AF39 [get_ports {ddr4_dimm1_dqs_t[6]}]
+set_property PACKAGE_PIN AF40 [get_ports {ddr4_dimm1_dqs_c[6]}]
+set_property PACKAGE_PIN AE38 [get_ports {ddr4_dimm1_dqs_t[7]}]
+set_property PACKAGE_PIN AF37 [get_ports {ddr4_dimm1_dqs_c[7]}]
+set_property PACKAGE_PIN AM39 [get_ports {ddr4_dimm1_odt[0]}]
+set_property PACKAGE_PIN AD42 [get_ports {ddr4_dimm1_reset_n[0]}]
+set_property PACKAGE_PIN AE42 [get_ports {ddr4_dimm1_sma_clk_clk_p[0]}]
+set_property PACKAGE_PIN AF43 [get_ports {ddr4_dimm1_sma_clk_clk_n[0]}]
diff --git a/hw/fpga/src/gen.sh b/hw/fpga/src/gen.sh
index 16c04e0034..d83a1feb83 100755
--- a/hw/fpga/src/gen.sh
+++ b/hw/fpga/src/gen.sh
@@ -1,3 +1,4 @@
 # Licensed under the Apache-2.0 license
 
 python3 -m peakrdl regblock caliptra_fpga_realtime_regs.rdl -o ./ --cpuif axi4-lite
+python3 -m peakrdl markdown caliptra_fpga_realtime_regs.rdl -o ../fpga_wrapper_regs.md
diff --git a/hw/fpga/src/jtag_constraints.xdc b/hw/fpga/src/jtag_constraints.xdc
deleted file mode 100644
index 9d66b5d60f..0000000000
--- a/hw/fpga/src/jtag_constraints.xdc
+++ /dev/null
@@ -1,2 +0,0 @@
-create_clock -period 5000.000 -name {caliptra_fpga_project_bd_i/zynq_ultra_ps_e_0/inst/emio_gpio_o[0]} -waveform {0.000 2500.000} [get_pins {caliptra_fpga_project_bd_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[0]}]
-set_clock_groups -asynchronous -group [get_clocks {caliptra_fpga_project_bd_i/zynq_ultra_ps_e_0/inst/emio_gpio_o[0]}]
diff --git a/hw/fpga/src/kv_reg.sv b/hw/fpga/src/kv_reg.sv
deleted file mode 100644
index 1e2d6cf9fe..0000000000
--- a/hw/fpga/src/kv_reg.sv
+++ /dev/null
@@ -1,447 +0,0 @@
-// FPGA replacement for KV with a configurable depth to use less resources
-
-`define KV_DEPTH 16
-
-module kv_reg (
-        input wire clk,
-        input wire rst,
-
-        input wire s_cpuif_req,
-        input wire s_cpuif_req_is_wr,
-        input wire [11:0] s_cpuif_addr,
-        input wire [31:0] s_cpuif_wr_data,
-        input wire [31:0] s_cpuif_wr_biten,
-        output wire s_cpuif_req_stall_wr,
-        output wire s_cpuif_req_stall_rd,
-        output wire s_cpuif_rd_ack,
-        output wire s_cpuif_rd_err,
-        output wire [31:0] s_cpuif_rd_data,
-        output wire s_cpuif_wr_ack,
-        output wire s_cpuif_wr_err,
-
-        input kv_reg_pkg::kv_reg__in_t hwif_in,
-        output kv_reg_pkg::kv_reg__out_t hwif_out
-    );
-
-    //--------------------------------------------------------------------------
-    // CPU Bus interface logic
-    //--------------------------------------------------------------------------
-    logic cpuif_req;
-    logic cpuif_req_is_wr;
-    logic [11:0] cpuif_addr;
-    logic [31:0] cpuif_wr_data;
-    logic [31:0] cpuif_wr_biten;
-    logic cpuif_req_stall_wr;
-    logic cpuif_req_stall_rd;
-
-    logic cpuif_rd_ack;
-    logic cpuif_rd_err;
-    logic [31:0] cpuif_rd_data;
-
-    logic cpuif_wr_ack;
-    logic cpuif_wr_err;
-
-    assign cpuif_req = s_cpuif_req;
-    assign cpuif_req_is_wr = s_cpuif_req_is_wr;
-    assign cpuif_addr = s_cpuif_addr;
-    assign cpuif_wr_data = s_cpuif_wr_data;
-    assign cpuif_wr_biten = s_cpuif_wr_biten;
-    assign s_cpuif_req_stall_wr = cpuif_req_stall_wr;
-    assign s_cpuif_req_stall_rd = cpuif_req_stall_rd;
-    assign s_cpuif_rd_ack = cpuif_rd_ack;
-    assign s_cpuif_rd_err = cpuif_rd_err;
-    assign s_cpuif_rd_data = cpuif_rd_data;
-    assign s_cpuif_wr_ack = cpuif_wr_ack;
-    assign s_cpuif_wr_err = cpuif_wr_err;
-
-    logic cpuif_req_masked;
-
-    // Read & write latencies are balanced. Stalls not required
-    assign cpuif_req_stall_rd = '0;
-    assign cpuif_req_stall_wr = '0;
-    assign cpuif_req_masked = cpuif_req;
-
-    //--------------------------------------------------------------------------
-    // Address Decode
-    //--------------------------------------------------------------------------
-    typedef struct packed{
-        logic [`KV_DEPTH-1:0]KEY_CTRL;
-        logic [`KV_DEPTH-1:0][12-1:0]KEY_ENTRY;
-        logic CLEAR_SECRETS;
-    } decoded_reg_strb_t;
-    decoded_reg_strb_t decoded_reg_strb;
-    logic decoded_req;
-    logic decoded_req_is_wr;
-    logic [31:0] decoded_wr_data;
-    logic [31:0] decoded_wr_biten;
-
-    always_comb begin
-        for(int i0=0; i0<`KV_DEPTH; i0++) begin
-            decoded_reg_strb.KEY_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4);
-        end
-        for(int i0=0; i0<`KV_DEPTH; i0++) begin
-            for(int i1=0; i1<12; i1++) begin
-                decoded_reg_strb.KEY_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h30 + i1*'h4);
-            end
-        end
-        decoded_reg_strb.CLEAR_SECRETS = cpuif_req_masked & (cpuif_addr == 'hc00);
-    end
-
-    // Pass down signals to next stage
-    assign decoded_req = cpuif_req_masked;
-    assign decoded_req_is_wr = cpuif_req_is_wr;
-    assign decoded_wr_data = cpuif_wr_data;
-    assign decoded_wr_biten = cpuif_wr_biten;
-
-
-    // Writes are always granted with no error response
-    assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
-    assign cpuif_wr_err = '0;
-    //--------------------------------------------------------------------------
-    // Field logic
-    //--------------------------------------------------------------------------
-    typedef struct packed{
-        struct packed{
-            struct packed{
-                logic next;
-                logic load_next;
-            } lock_wr;
-            struct packed{
-                logic next;
-                logic load_next;
-            } lock_use;
-            struct packed{
-                logic next;
-                logic load_next;
-            } clear;
-            struct packed{
-                logic next;
-                logic load_next;
-            } rsvd0;
-            struct packed{
-                logic [4:0] next;
-                logic load_next;
-            } rsvd1;
-            struct packed{
-                logic [7:0] next;
-                logic load_next;
-            } dest_valid;
-            struct packed{
-                logic [3:0] next;
-                logic load_next;
-            } last_dword;
-        } [`KV_DEPTH-1:0]KEY_CTRL;
-        struct packed{
-            struct packed{
-                logic [31:0] next;
-                logic load_next;
-            } data;
-        } [`KV_DEPTH-1:0][12-1:0]KEY_ENTRY;
-        struct packed{
-            struct packed{
-                logic next;
-                logic load_next;
-            } wr_debug_values;
-            struct packed{
-                logic next;
-                logic load_next;
-            } sel_debug_value;
-        } CLEAR_SECRETS;
-    } field_combo_t;
-    field_combo_t field_combo;
-
-    typedef struct packed{
-        struct packed{
-            struct packed{
-                logic value;
-            } lock_wr;
-            struct packed{
-                logic value;
-            } lock_use;
-            struct packed{
-                logic value;
-            } clear;
-            struct packed{
-                logic value;
-            } rsvd0;
-            struct packed{
-                logic [4:0] value;
-            } rsvd1;
-            struct packed{
-                logic [7:0] value;
-            } dest_valid;
-            struct packed{
-                logic [3:0] value;
-            } last_dword;
-        } [`KV_DEPTH-1:0]KEY_CTRL;
-        struct packed{
-            struct packed{
-                logic [31:0] value;
-            } data;
-        } [`KV_DEPTH-1:0][12-1:0]KEY_ENTRY;
-        struct packed{
-            struct packed{
-                logic value;
-            } wr_debug_values;
-            struct packed{
-                logic value;
-            } sel_debug_value;
-        } CLEAR_SECRETS;
-    } field_storage_t;
-    field_storage_t field_storage;
-
-    for(genvar i0=0; i0<`KV_DEPTH; i0++) begin
-        // Field: kv_reg.KEY_CTRL[].lock_wr
-        always_comb begin
-            automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].lock_wr.value;
-            automatic logic load_next_c = '0;
-            if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr && !(hwif_in.KEY_CTRL[i0].lock_wr.swwel)) begin // SW write
-                next_c = (field_storage.KEY_CTRL[i0].lock_wr.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].lock_wr.next = next_c;
-            field_combo.KEY_CTRL[i0].lock_wr.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin
-            if(~hwif_in.core_only_rst_b) begin
-                field_storage.KEY_CTRL[i0].lock_wr.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].lock_wr.load_next) begin
-                field_storage.KEY_CTRL[i0].lock_wr.value <= field_combo.KEY_CTRL[i0].lock_wr.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].lock_wr.value = field_storage.KEY_CTRL[i0].lock_wr.value;
-        // Field: kv_reg.KEY_CTRL[].lock_use
-        always_comb begin
-            automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].lock_use.value;
-            automatic logic load_next_c = '0;
-            if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr && !(hwif_in.KEY_CTRL[i0].lock_use.swwel)) begin // SW write
-                next_c = (field_storage.KEY_CTRL[i0].lock_use.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].lock_use.next = next_c;
-            field_combo.KEY_CTRL[i0].lock_use.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin
-            if(~hwif_in.core_only_rst_b) begin
-                field_storage.KEY_CTRL[i0].lock_use.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].lock_use.load_next) begin
-                field_storage.KEY_CTRL[i0].lock_use.value <= field_combo.KEY_CTRL[i0].lock_use.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].lock_use.value = field_storage.KEY_CTRL[i0].lock_use.value;
-        // Field: kv_reg.KEY_CTRL[].clear
-        always_comb begin
-            automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].clear.value;
-            automatic logic load_next_c = '0;
-            if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write
-                next_c = (field_storage.KEY_CTRL[i0].clear.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
-                load_next_c = '1;
-            end else if(1) begin // singlepulse clears back to 0
-                next_c = '0;
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].clear.next = next_c;
-            field_combo.KEY_CTRL[i0].clear.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-            if(~hwif_in.reset_b) begin
-                field_storage.KEY_CTRL[i0].clear.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].clear.load_next) begin
-                field_storage.KEY_CTRL[i0].clear.value <= field_combo.KEY_CTRL[i0].clear.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].clear.value = field_storage.KEY_CTRL[i0].clear.value;
-        // Field: kv_reg.KEY_CTRL[].rsvd0
-        always_comb begin
-            automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].rsvd0.value;
-            automatic logic load_next_c = '0;
-            if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write
-                next_c = (field_storage.KEY_CTRL[i0].rsvd0.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
-                load_next_c = '1;
-            end else if(hwif_in.KEY_CTRL[i0].rsvd0.hwclr) begin // HW Clear
-                next_c = '0;
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].rsvd0.next = next_c;
-            field_combo.KEY_CTRL[i0].rsvd0.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-            if(~hwif_in.reset_b) begin
-                field_storage.KEY_CTRL[i0].rsvd0.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].rsvd0.load_next) begin
-                field_storage.KEY_CTRL[i0].rsvd0.value <= field_combo.KEY_CTRL[i0].rsvd0.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].rsvd0.value = field_storage.KEY_CTRL[i0].rsvd0.value;
-        // Field: kv_reg.KEY_CTRL[].rsvd1
-        always_comb begin
-            automatic logic [4:0] next_c = field_storage.KEY_CTRL[i0].rsvd1.value;
-            automatic logic load_next_c = '0;
-            if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write
-                next_c = (field_storage.KEY_CTRL[i0].rsvd1.value & ~decoded_wr_biten[8:4]) | (decoded_wr_data[8:4] & decoded_wr_biten[8:4]);
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].rsvd1.next = next_c;
-            field_combo.KEY_CTRL[i0].rsvd1.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-            if(~hwif_in.reset_b) begin
-                field_storage.KEY_CTRL[i0].rsvd1.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].rsvd1.load_next) begin
-                field_storage.KEY_CTRL[i0].rsvd1.value <= field_combo.KEY_CTRL[i0].rsvd1.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].rsvd1.value = field_storage.KEY_CTRL[i0].rsvd1.value;
-        // Field: kv_reg.KEY_CTRL[].dest_valid
-        always_comb begin
-            automatic logic [7:0] next_c = field_storage.KEY_CTRL[i0].dest_valid.value;
-            automatic logic load_next_c = '0;
-            if(hwif_in.KEY_CTRL[i0].dest_valid.we) begin // HW Write - we
-                next_c = hwif_in.KEY_CTRL[i0].dest_valid.next;
-                load_next_c = '1;
-            end else if(hwif_in.KEY_CTRL[i0].dest_valid.hwclr) begin // HW Clear
-                next_c = '0;
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].dest_valid.next = next_c;
-            field_combo.KEY_CTRL[i0].dest_valid.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin
-            if(~hwif_in.hard_reset_b) begin
-                field_storage.KEY_CTRL[i0].dest_valid.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].dest_valid.load_next) begin
-                field_storage.KEY_CTRL[i0].dest_valid.value <= field_combo.KEY_CTRL[i0].dest_valid.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].dest_valid.value = field_storage.KEY_CTRL[i0].dest_valid.value;
-        // Field: kv_reg.KEY_CTRL[].last_dword
-        always_comb begin
-            automatic logic [3:0] next_c = field_storage.KEY_CTRL[i0].last_dword.value;
-            automatic logic load_next_c = '0;
-            if(hwif_in.KEY_CTRL[i0].last_dword.we) begin // HW Write - we
-                next_c = hwif_in.KEY_CTRL[i0].last_dword.next;
-                load_next_c = '1;
-            end else if(hwif_in.KEY_CTRL[i0].last_dword.hwclr) begin // HW Clear
-                next_c = '0;
-                load_next_c = '1;
-            end
-            field_combo.KEY_CTRL[i0].last_dword.next = next_c;
-            field_combo.KEY_CTRL[i0].last_dword.load_next = load_next_c;
-        end
-        always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin
-            if(~hwif_in.hard_reset_b) begin
-                field_storage.KEY_CTRL[i0].last_dword.value <= 'h0;
-            end else if(field_combo.KEY_CTRL[i0].last_dword.load_next) begin
-                field_storage.KEY_CTRL[i0].last_dword.value <= field_combo.KEY_CTRL[i0].last_dword.next;
-            end
-        end
-        assign hwif_out.KEY_CTRL[i0].last_dword.value = field_storage.KEY_CTRL[i0].last_dword.value;
-    end
-    for(genvar i0=0; i0<`KV_DEPTH; i0++) begin
-        for(genvar i1=0; i1<12; i1++) begin
-            // Field: kv_reg.KEY_ENTRY[][].data
-            always_comb begin
-                automatic logic [31:0] next_c = field_storage.KEY_ENTRY[i0][i1].data.value;
-                automatic logic load_next_c = '0;
-                if(decoded_reg_strb.KEY_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.KEY_ENTRY[i0][i1].data.swwel)) begin // SW write
-                    next_c = (field_storage.KEY_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
-                    load_next_c = '1;
-                end else if(hwif_in.KEY_ENTRY[i0][i1].data.we) begin // HW Write - we
-                    next_c = hwif_in.KEY_ENTRY[i0][i1].data.next;
-                    load_next_c = '1;
-                end else if(hwif_in.KEY_ENTRY[i0][i1].data.hwclr) begin // HW Clear
-                    next_c = '0;
-                    load_next_c = '1;
-                end
-                field_combo.KEY_ENTRY[i0][i1].data.next = next_c;
-                field_combo.KEY_ENTRY[i0][i1].data.load_next = load_next_c;
-            end
-            always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin
-                if(~hwif_in.hard_reset_b) begin
-                    field_storage.KEY_ENTRY[i0][i1].data.value <= 'h0;
-                end else if(field_combo.KEY_ENTRY[i0][i1].data.load_next) begin
-                    field_storage.KEY_ENTRY[i0][i1].data.value <= field_combo.KEY_ENTRY[i0][i1].data.next;
-                end
-            end
-            assign hwif_out.KEY_ENTRY[i0][i1].data.value = field_storage.KEY_ENTRY[i0][i1].data.value;
-        end
-    end
-    // Field: kv_reg.CLEAR_SECRETS.wr_debug_values
-    always_comb begin
-        automatic logic [0:0] next_c = field_storage.CLEAR_SECRETS.wr_debug_values.value;
-        automatic logic load_next_c = '0;
-        if(decoded_reg_strb.CLEAR_SECRETS && decoded_req_is_wr) begin // SW write
-            next_c = (field_storage.CLEAR_SECRETS.wr_debug_values.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
-            load_next_c = '1;
-        end else if(1) begin // singlepulse clears back to 0
-            next_c = '0;
-            load_next_c = '1;
-        end
-        field_combo.CLEAR_SECRETS.wr_debug_values.next = next_c;
-        field_combo.CLEAR_SECRETS.wr_debug_values.load_next = load_next_c;
-    end
-    always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-        if(~hwif_in.reset_b) begin
-            field_storage.CLEAR_SECRETS.wr_debug_values.value <= 'h0;
-        end else if(field_combo.CLEAR_SECRETS.wr_debug_values.load_next) begin
-            field_storage.CLEAR_SECRETS.wr_debug_values.value <= field_combo.CLEAR_SECRETS.wr_debug_values.next;
-        end
-    end
-    assign hwif_out.CLEAR_SECRETS.wr_debug_values.value = field_storage.CLEAR_SECRETS.wr_debug_values.value;
-    // Field: kv_reg.CLEAR_SECRETS.sel_debug_value
-    always_comb begin
-        automatic logic [0:0] next_c = field_storage.CLEAR_SECRETS.sel_debug_value.value;
-        automatic logic load_next_c = '0;
-        if(decoded_reg_strb.CLEAR_SECRETS && decoded_req_is_wr) begin // SW write
-            next_c = (field_storage.CLEAR_SECRETS.sel_debug_value.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
-            load_next_c = '1;
-        end
-        field_combo.CLEAR_SECRETS.sel_debug_value.next = next_c;
-        field_combo.CLEAR_SECRETS.sel_debug_value.load_next = load_next_c;
-    end
-    always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-        if(~hwif_in.reset_b) begin
-            field_storage.CLEAR_SECRETS.sel_debug_value.value <= 'h0;
-        end else if(field_combo.CLEAR_SECRETS.sel_debug_value.load_next) begin
-            field_storage.CLEAR_SECRETS.sel_debug_value.value <= field_combo.CLEAR_SECRETS.sel_debug_value.next;
-        end
-    end
-    assign hwif_out.CLEAR_SECRETS.sel_debug_value.value = field_storage.CLEAR_SECRETS.sel_debug_value.value;
-    //--------------------------------------------------------------------------
-    // Readback
-    //--------------------------------------------------------------------------
-    logic readback_err;
-    logic readback_done;
-    logic [31:0] readback_data;
-    
-    // Assign readback values to a flattened array
-    logic [`KV_DEPTH:0][31:0] readback_array;
-    for(genvar i0=0; i0<`KV_DEPTH; i0++) begin
-        assign readback_array[i0*1 + 0][0:0] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].lock_wr.value : '0;
-        assign readback_array[i0*1 + 0][1:1] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].lock_use.value : '0;
-        assign readback_array[i0*1 + 0][2:2] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].clear.value : '0;
-        assign readback_array[i0*1 + 0][3:3] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].rsvd0.value : '0;
-        assign readback_array[i0*1 + 0][8:4] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].rsvd1.value : '0;
-        assign readback_array[i0*1 + 0][16:9] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].dest_valid.value : '0;
-        assign readback_array[i0*1 + 0][20:17] = (decoded_reg_strb.KEY_CTRL[i0] && !decoded_req_is_wr) ? field_storage.KEY_CTRL[i0].last_dword.value : '0;
-        assign readback_array[i0*1 + 0][31:21] = '0;
-    end
-    assign readback_array[`KV_DEPTH][0:0] = (decoded_reg_strb.CLEAR_SECRETS && !decoded_req_is_wr) ? field_storage.CLEAR_SECRETS.wr_debug_values.value : '0;
-    assign readback_array[`KV_DEPTH][1:1] = (decoded_reg_strb.CLEAR_SECRETS && !decoded_req_is_wr) ? field_storage.CLEAR_SECRETS.sel_debug_value.value : '0;
-    assign readback_array[`KV_DEPTH][31:2] = '0;
-
-
-    // Reduce the array
-    always_comb begin
-        automatic logic [31:0] readback_data_var;
-        readback_done = decoded_req & ~decoded_req_is_wr;
-        readback_err = '0;
-        readback_data_var = '0;
-        for(int i=0; i<(`KV_DEPTH+1); i++) readback_data_var |= readback_array[i];
-        readback_data = readback_data_var;
-    end
-
-    assign cpuif_rd_ack = readback_done;
-    assign cpuif_rd_data = readback_data;
-    assign cpuif_rd_err = readback_err;
-endmodule
\ No newline at end of file
diff --git a/hw/latest/registers/src/aes.rs b/hw/latest/registers/src/aes.rs
index 4100333390..c33f9c8c9a 100644
--- a/hw/latest/registers/src/aes.rs
+++ b/hw/latest/registers/src/aes.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/aes_clp.rs b/hw/latest/registers/src/aes_clp.rs
index 62a5a03abd..a520238abe 100644
--- a/hw/latest/registers/src/aes_clp.rs
+++ b/hw/latest/registers/src/aes_clp.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -13,7 +13,7 @@ pub struct AesClpReg {
     _priv: (),
 }
 impl AesClpReg {
-    pub const PTR: *mut u32 = 0x10011100 as *mut u32;
+    pub const PTR: *mut u32 = 0x10011800 as *mut u32;
     /// # Safety
     ///
     /// Caller must ensure that all concurrent use of this
@@ -81,7 +81,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     pub fn aes_name(&self) -> ureg::Array<2, ureg::RegRef<crate::aes_clp::meta::AesName, &TMmio>> {
         unsafe {
             ureg::Array::new_with_mmio(
-                self.ptr.wrapping_add(0x100 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -96,7 +96,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ) -> ureg::Array<2, ureg::RegRef<crate::aes_clp::meta::AesVersion, &TMmio>> {
         unsafe {
             ureg::Array::new_with_mmio(
-                self.ptr.wrapping_add(0x108 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(8 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -108,7 +108,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     pub fn aes_kv_rd_key_ctrl(&self) -> ureg::RegRef<crate::aes_clp::meta::AesKvRdKeyCtrl, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x600 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x200 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -122,7 +122,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ) -> ureg::RegRef<crate::aes_clp::meta::AesKvRdKeyStatus, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
-                self.ptr.wrapping_add(0x604 / core::mem::size_of::<u32>()),
+                self.ptr.wrapping_add(0x204 / core::mem::size_of::<u32>()),
                 core::borrow::Borrow::borrow(&self.mmio),
             )
         }
@@ -130,7 +130,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     #[inline(always)]
     pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> {
         IntrBlockRfBlock {
-            ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::<u32>()) },
+            ptr: unsafe { self.ptr.add(0x400 / core::mem::size_of::<u32>()) },
             mmio: core::borrow::Borrow::borrow(&self.mmio),
         }
     }
@@ -488,7 +488,7 @@ pub struct IntrBlockRf {
     _priv: (),
 }
 impl IntrBlockRf {
-    pub const PTR: *mut u32 = 0x800 as *mut u32;
+    pub const PTR: *mut u32 = 0x400 as *mut u32;
     /// # Safety
     ///
     /// Caller must ensure that all concurrent use of this
@@ -1273,7 +1273,7 @@ pub mod enums {
         #[inline(always)]
         fn try_from(val: u32) -> Result<KvErrorE, ()> {
             if val < 0x100 {
-                Ok(unsafe { core::mem::transmute(val) })
+                Ok(unsafe { core::mem::transmute::<u32, KvErrorE>(val) })
             } else {
                 Err(())
             }
diff --git a/hw/latest/registers/src/axi_dma.rs b/hw/latest/registers/src/axi_dma.rs
index 57d1f7eeaa..b059e9add8 100644
--- a/hw/latest/registers/src/axi_dma.rs
+++ b/hw/latest/registers/src/axi_dma.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/csrng.rs b/hw/latest/registers/src/csrng.rs
index 3de0edf033..d8c5369285 100644
--- a/hw/latest/registers/src/csrng.rs
+++ b/hw/latest/registers/src/csrng.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/doe.rs b/hw/latest/registers/src/doe.rs
index 16b978ba30..a4d5d6fe0c 100644
--- a/hw/latest/registers/src/doe.rs
+++ b/hw/latest/registers/src/doe.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/dv.rs b/hw/latest/registers/src/dv.rs
index 5593c2d571..0f22b5ccfc 100644
--- a/hw/latest/registers/src/dv.rs
+++ b/hw/latest/registers/src/dv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/ecc.rs b/hw/latest/registers/src/ecc.rs
index 5f9d92f28b..47db331009 100644
--- a/hw/latest/registers/src/ecc.rs
+++ b/hw/latest/registers/src/ecc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/el2_pic_ctrl.rs b/hw/latest/registers/src/el2_pic_ctrl.rs
index dedecf1c63..3ffb6aacb6 100644
--- a/hw/latest/registers/src/el2_pic_ctrl.rs
+++ b/hw/latest/registers/src/el2_pic_ctrl.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/entropy_src.rs b/hw/latest/registers/src/entropy_src.rs
index bcccd5c7ad..7d23d6fbe4 100644
--- a/hw/latest/registers/src/entropy_src.rs
+++ b/hw/latest/registers/src/entropy_src.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/hmac.rs b/hw/latest/registers/src/hmac.rs
index 1c877becf1..a9020f18d2 100644
--- a/hw/latest/registers/src/hmac.rs
+++ b/hw/latest/registers/src/hmac.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/i3ccsr.rs b/hw/latest/registers/src/i3ccsr.rs
index 9ffb3471c7..f897ac0bfe 100644
--- a/hw/latest/registers/src/i3ccsr.rs
+++ b/hw/latest/registers/src/i3ccsr.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/kv.rs b/hw/latest/registers/src/kv.rs
index 4896ff95d6..965a7e8aa6 100644
--- a/hw/latest/registers/src/kv.rs
+++ b/hw/latest/registers/src/kv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/lib.rs b/hw/latest/registers/src/lib.rs
index a095dfa911..4a06875332 100644
--- a/hw/latest/registers/src/lib.rs
+++ b/hw/latest/registers/src/lib.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![no_std]
 #![allow(clippy::erasing_op)]
diff --git a/hw/latest/registers/src/mbox.rs b/hw/latest/registers/src/mbox.rs
index 557ac89d90..4d8b36a276 100644
--- a/hw/latest/registers/src/mbox.rs
+++ b/hw/latest/registers/src/mbox.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/mbox_sram.rs b/hw/latest/registers/src/mbox_sram.rs
index 2ace81b408..1bcdacbdd9 100644
--- a/hw/latest/registers/src/mbox_sram.rs
+++ b/hw/latest/registers/src/mbox_sram.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/mldsa.rs b/hw/latest/registers/src/mldsa.rs
index ea2efa3e8d..7dbb8b3745 100644
--- a/hw/latest/registers/src/mldsa.rs
+++ b/hw/latest/registers/src/mldsa.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -100,14 +100,6 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
         }
     }
     /// Control register to set the type of MLDSA operations.
-    /// [br] bit #[1:0]: This can be:
-    /// [br]            000 for NONE
-    /// [br]            001 for KEYGEN
-    /// [br]            010 for SIGNING
-    /// [br]            011 for VERIFYING
-    /// [br]            100 for KEYGEN+SIGN
-    ///
-    /// [br] bit #3: Zeroize all internal registers after MLDSA process, to avoid SCA leakage.
     ///
     /// Read value: [`mldsa::regs::CtrlReadVal`]; Write value: [`mldsa::regs::CtrlWriteVal`]
     #[inline(always)]
@@ -205,6 +197,21 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    /// 16 32-bit registers storing the external_mu in big-endian representation.
+    /// The external_mu can be any 512-bit value in [0 : 2^512-1].
+    ///
+    /// Read value: [`u32`]; Write value: [`u32`]
+    #[inline(always)]
+    pub fn external_mu(
+        &self,
+    ) -> ureg::Array<16, ureg::RegRef<crate::mldsa::meta::ExternalMu, &TMmio>> {
+        unsafe {
+            ureg::Array::new_with_mmio(
+                self.ptr.wrapping_add(0x118 / core::mem::size_of::<u32>()),
+                core::borrow::Borrow::borrow(&self.mmio),
+            )
+        }
+    }
     /// 648 32-bit registers storing the public key in big-endian representation.
     /// These registers are read by MLDSA user after keygen operation,
     /// or set before verifying operation.
@@ -574,7 +581,14 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct CtrlWriteVal(u32);
     impl CtrlWriteVal {
-        /// Control command field
+        /// Control command field. This can be:
+        /// [br]            000 for NONE
+        /// [br]            001 for KEYGEN
+        /// [br]            010 for SIGNING
+        /// [br]            011 for VERIFYING
+        /// [br]            100 for KEYGEN+SIGN
+        ///                
+        /// [br] After each software write, hardware will erase the register
         #[inline(always)]
         pub fn ctrl(
             self,
@@ -582,7 +596,9 @@ pub mod regs {
         ) -> Self {
             Self((self.0 & !(7 << 0)) | (u32::from(f(super::enums::selector::CtrlSelector())) << 0))
         }
-        /// Zeroize all internal registers
+        /// Zeroize all internal registers: Zeroize all internal registers and memories to avoid SCA leakage.
+        /// [br] Software write generates only a single-cycle pulse on the
+        /// hardware interface and then will be erased
         #[inline(always)]
         pub fn zeroize(self, val: bool) -> Self {
             Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
@@ -592,6 +608,11 @@ pub mod regs {
         pub fn pcr_sign(self, val: bool) -> Self {
             Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
         }
+        /// ExternalMu Mode
+        #[inline(always)]
+        pub fn external_mu(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
+        }
     }
     impl From<u32> for CtrlWriteVal {
         #[inline(always)]
@@ -1308,6 +1329,7 @@ pub mod meta {
     pub type SignRnd = ureg::WriteOnlyReg32<0, u32>;
     pub type Msg = ureg::WriteOnlyReg32<0, u32>;
     pub type VerifyRes = ureg::ReadOnlyReg32<u32>;
+    pub type ExternalMu = ureg::WriteOnlyReg32<0, u32>;
     pub type Pubkey = ureg::ReadWriteReg32<0, u32, u32>;
     pub type Signature = ureg::ReadWriteReg32<0, u32, u32>;
     pub type PrivkeyOut = ureg::ReadOnlyReg32<u32>;
diff --git a/hw/latest/registers/src/pv.rs b/hw/latest/registers/src/pv.rs
index 2fbe1aef71..f410a9f4b6 100644
--- a/hw/latest/registers/src/pv.rs
+++ b/hw/latest/registers/src/pv.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/sha256.rs b/hw/latest/registers/src/sha256.rs
index 45ee50a4d7..7ae84d8340 100644
--- a/hw/latest/registers/src/sha256.rs
+++ b/hw/latest/registers/src/sha256.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/sha512.rs b/hw/latest/registers/src/sha512.rs
index 26d9f44678..32c1b97581 100644
--- a/hw/latest/registers/src/sha512.rs
+++ b/hw/latest/registers/src/sha512.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/sha512_acc.rs b/hw/latest/registers/src/sha512_acc.rs
index 94dca8abe2..b0b3042699 100644
--- a/hw/latest/registers/src/sha512_acc.rs
+++ b/hw/latest/registers/src/sha512_acc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/registers/src/soc_ifc.rs b/hw/latest/registers/src/soc_ifc.rs
index 49a597e5ea..59b5d7c957 100644
--- a/hw/latest/registers/src/soc_ifc.rs
+++ b/hw/latest/registers/src/soc_ifc.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -2686,7 +2686,7 @@ pub mod regs {
             ((self.0 >> 4) & 1) != 0
         }
         #[inline(always)]
-        pub fn active_mode_en(&self) -> bool {
+        pub fn subsystem_mode_en(&self) -> bool {
             ((self.0 >> 5) & 1) != 0
         }
     }
@@ -4046,7 +4046,6 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct FuseEccRevocationReadVal(u32);
     impl FuseEccRevocationReadVal {
-        ///
         #[inline(always)]
         pub fn ecc_revocation(&self) -> u32 {
             (self.0 >> 0) & 0xf
@@ -4072,7 +4071,6 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct FuseEccRevocationWriteVal(u32);
     impl FuseEccRevocationWriteVal {
-        ///
         #[inline(always)]
         pub fn ecc_revocation(self, val: u32) -> Self {
             Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0))
@@ -4138,7 +4136,6 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct FusePqcKeyTypeReadVal(u32);
     impl FusePqcKeyTypeReadVal {
-        ///
         #[inline(always)]
         pub fn key_type(&self) -> u32 {
             (self.0 >> 0) & 3
@@ -4164,7 +4161,6 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct FusePqcKeyTypeWriteVal(u32);
     impl FusePqcKeyTypeWriteVal {
-        ///
         #[inline(always)]
         pub fn key_type(self, val: u32) -> Self {
             Self((self.0 & !(3 << 0)) | ((val & 3) << 0))
@@ -4185,7 +4181,6 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct FuseSocManifestMaxSvnReadVal(u32);
     impl FuseSocManifestMaxSvnReadVal {
-        ///
         #[inline(always)]
         pub fn svn(&self) -> u32 {
             (self.0 >> 0) & 0xff
@@ -4211,7 +4206,6 @@ pub mod regs {
     #[derive(Clone, Copy)]
     pub struct FuseSocManifestMaxSvnWriteVal(u32);
     impl FuseSocManifestMaxSvnWriteVal {
-        ///
         #[inline(always)]
         pub fn svn(self, val: u32) -> Self {
             Self((self.0 & !(0xff << 0)) | ((val & 0xff) << 0))
diff --git a/hw/latest/registers/src/soc_ifc_trng.rs b/hw/latest/registers/src/soc_ifc_trng.rs
index 4326da588e..9f6cc4b130 100644
--- a/hw/latest/registers/src/soc_ifc_trng.rs
+++ b/hw/latest/registers/src/soc_ifc_trng.rs
@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+// generated by caliptra_registers_generator with caliptra-rtl repo at fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
diff --git a/hw/latest/rtl b/hw/latest/rtl
index e11dacf5fb..fc2ec4574c 160000
--- a/hw/latest/rtl
+++ b/hw/latest/rtl
@@ -1 +1 @@
-Subproject commit e11dacf5fb10f347f3581ca5de9fdcd0947251e8
+Subproject commit fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7