You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Hi,
I don't know whether this is an expected behavior of Atomics but when I run perf on my code I see that there are cache misses on try_recv call. I have a bounded queue, which has 8 senders and 1 receiver. In the sender sides, I couldn't find any notable miss, because of that I raise that issue for the receiver side.
My call:
There are other small misses but they are negligible compared to these 3 lines. If you can help to figure this out, I'll appreciate that. Thanks in advance.
The text was updated successfully, but these errors were encountered:
Hmm, since mfence does the serialization, the previous cache should not be available for the load from r15+0x80 (i.e., self.tail), but I thought the load from r15+0x190 was the access to self.mark_bit, so I thought that could be omitted. However, normal offset of self.mark_bit is actually 0x108...
Hi,
I don't know whether this is an expected behavior of Atomics but when I run perf on my code I see that there are cache misses on
try_recv
call. I have a bounded queue, which has 8 senders and 1 receiver. In the sender sides, I couldn't find any notable miss, because of that I raise that issue for the receiver side.My call:
There are other small misses but they are negligible compared to these 3 lines. If you can help to figure this out, I'll appreciate that. Thanks in advance.
The text was updated successfully, but these errors were encountered: