Running Extract.Single.1 test... ExtractSingle1 .cctor .cctor .ctor .ctor ExtractSingle1 1 2 3 4 5 6 7 ****** START compiling JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this (MethodHash=37eaf1fb) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = true OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: Stack probing is DISABLED IL to import: IL_0000 00 nop IL_0001 72 e2 29 00 70 ldstr 0x700029E2 IL_0006 28 0c 00 00 0a call 0xA00000C IL_000b 00 nop IL_000c 7e 10 04 00 04 ldsfld 0x4000410 IL_0011 17 ldc.i4.1 IL_0012 28 52 01 00 0a call 0xA000152 IL_0017 0a stloc.0 IL_0018 72 e2 29 00 70 ldstr 0x700029E2 IL_001d 28 0c 00 00 0a call 0xA00000C IL_0022 00 nop IL_0023 02 ldarg.0 IL_0024 7c 12 04 00 04 ldflda 0x4000412 IL_0029 28 5e 00 00 0a call 0xA00005E IL_002e 06 ldloc.0 IL_002f 28 4e 00 00 2b call 0x2B00004E IL_0034 00 nop IL_0035 72 e2 29 00 70 ldstr 0x700029E2 IL_003a 28 0c 00 00 0a call 0xA00000C IL_003f 00 nop IL_0040 02 ldarg.0 IL_0041 7e 10 04 00 04 ldsfld 0x4000410 IL_0046 02 ldarg.0 IL_0047 7c 12 04 00 04 ldflda 0x4000412 IL_004c 28 5e 00 00 0a call 0xA00005E IL_0051 72 ee 15 00 70 ldstr 0x700015EE IL_0056 28 99 08 00 06 call 0x6000899 IL_005b 00 nop IL_005c 2a ret lvaSetClass: setting class for V00 to (00007FF8295010F0) JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1 Set preferred register for V00 to [rcx] 'this' passed in register rcx ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 loc0 float *************** In compInitDebuggingInfo() for JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 2 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 05Dh 1: 01h 01h V01 loc0 000h 05Dh New Basic Block BB01 [0000] created. New scratch BB01 Debuggable code - Add new BB01 [0000] to perform initialization of variables info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this Jump targets: none New Basic Block BB02 [0001] created. BB02 [000..05D) CLFLG_MINOPT set for method JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this IL Code Size,Instr 93, 29, Basic Block count 2, Local Variable Num,Ref count 2, 5 for method JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this IL Code Size,Instr 93, 29, Basic Block count 2, Local Variable Num,Ref count 2, 5 for method JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this OPTIONS: opts.MinOpts() == true Basic block list for 'JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal BB02 [0001] 1 1 [000..05D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED impImportBlockPending for BB02 Importing BB02 (PC=000) of 'JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this' [ 0] 0 (0x000) nop [000004] ------------ * STMT void (IL 0x000... ???) [000003] ------------ \--* NO_OP void [ 0] 1 (0x001) ldstr 700029E2 [ 1] 6 (0x006) call 0A00000C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000008] ------------ * STMT void (IL 0x001... ???) [000006] --C-G------- \--* CALL void System.Console.WriteLine [000005] ------------ arg0 \--* CNS_STR ref [ 0] 11 (0x00b) nop [000010] ------------ * STMT void (IL 0x00B... ???) [000009] ------------ \--* NO_OP void [ 0] 12 (0x00c) ldsfld 04000410HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) call 0A000152 In Compiler::impImportCall: opcode is call, kind=0, callRetType is float, structSize is 0 HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 lvaGrabTemp returning 2 (V02 tmp0) called for impSpillStackEnsure. [000019] ------------ * STMT void (IL 0x00C... ???) [000015] ------------ | /--* CNS_INT int 1 [000016] ----G------- | /--* HWIntrinsic float float Extract [000014] ----G------- | | \--* OBJ(16) simd16 [000012] ------------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000013] ----G------- | | \--* ADD byref [000011] ----G------- | | \--* FIELD ref _clsVar [000018] -A--G------- \--* ASG float [000017] D------N---- \--* LCL_VAR float V02 tmp0 [ 1] 23 (0x017) stloc.0 [000023] ------------ * STMT void (IL 0x017... ???) [000020] ------------ | /--* LCL_VAR float V02 tmp0 [000022] -A---------- \--* ASG float [000021] D------N---- \--* LCL_VAR float V01 loc0 [ 0] 24 (0x018) ldstr 700029E2 [ 1] 29 (0x01d) call 0A00000C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000027] ------------ * STMT void (IL 0x018... ???) [000025] --C-G------- \--* CALL void System.Console.WriteLine [000024] ------------ arg0 \--* CNS_STR ref [ 0] 34 (0x022) nop [000029] ------------ * STMT void (IL 0x022... ???) [000028] ------------ \--* NO_OP void [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldflda 04000412 [ 1] 41 (0x029) call 0A00005E In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 lvaGrabTemp returning 3 (V03 tmp1) called for impSpillStackEnsure. [000036] ------------ * STMT void (IL 0x023... ???) [000033] --CXG------- | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000032] ---XG------- this in rcx | | \--* ADDR byref [000031] ---XG------- | | \--* FIELD struct _dataTable [000030] ------------ | | \--* LCL_VAR ref V00 this [000035] -ACXG------- \--* ASG long [000034] D------N---- \--* LCL_VAR long V03 tmp1 [ 1] 46 (0x02e) ldloc.0 [ 2] 47 (0x02f) call 2B00004E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000042] ------------ * STMT void (IL 0x02E... ???) [000039] --C-G------- \--* CALL void System.Runtime.CompilerServices.Unsafe.Write [000037] ------------ arg0 +--* LCL_VAR long V03 tmp1 [000038] ------------ arg1 \--* LCL_VAR float V01 loc0 [ 0] 52 (0x034) nop [000044] ------------ * STMT void (IL 0x034... ???) [000043] ------------ \--* NO_OP void [ 0] 53 (0x035) ldstr 700029E2 [ 1] 58 (0x03a) call 0A00000C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000048] ------------ * STMT void (IL 0x035... ???) [000046] --C-G------- \--* CALL void System.Console.WriteLine [000045] ------------ arg0 \--* CNS_STR ref [ 0] 63 (0x03f) nop [000050] ------------ * STMT void (IL 0x03F... ???) [000049] ------------ \--* NO_OP void [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldsfld 04000410HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 [ 2] 70 (0x046) ldarg.0 [ 3] 71 (0x047) ldflda 04000412 [ 3] 76 (0x04c) call 0A00005E In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 lvaGrabTemp returning 4 (V04 tmp2) called for non-inline candidate call. HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 [000063] ------------ * STMT void (IL 0x040... ???) [000055] ----G------- | /--* OBJ(16) simd16 [000053] ------------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G------- | | \--* ADD byref [000052] ----G------- | | \--* FIELD ref _clsVar [000062] -A--G---R--- \--* ASG simd16 (copy) [000060] D----------- \--* LCL_VAR simd16 V04 tmp2 lvaGrabTemp returning 5 (V05 tmp3) called for impSpillStackEnsure. [000067] ------------ * STMT void (IL ???... ???) [000051] ------------ | /--* LCL_VAR ref V00 this [000066] -A---------- \--* ASG ref [000065] D------N---- \--* LCL_VAR ref V05 tmp3 lvaSetClass: setting class for V05 to (00007FF8295010F0) JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1 lvaGrabTemp returning 6 (V06 tmp4) called for impSpillStackEnsure. [000071] ------------ * STMT void (IL ???... ???) [000059] --CXG------- | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000058] ---XG------- this in rcx | | \--* ADDR byref [000057] ---XG------- | | \--* FIELD struct _dataTable [000056] ------------ | | \--* LCL_VAR ref V00 this [000070] -ACXG------- \--* ASG long [000069] D------N---- \--* LCL_VAR long V06 tmp4 [ 3] 81 (0x051) ldstr 700015EE [ 4] 86 (0x056) call 06000899 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 Calling impNormStructVal on: [000064] ------------ * LCL_VAR simd16 V04 tmp2 HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 resulting tree: [000078] x----------- * OBJ(16) simd16 [000077] L----------- \--* ADDR byref [000064] ------------ \--* LCL_VAR simd16 V04 tmp2 [000080] ------------ * STMT void (IL 0x051... ???) [000074] --C-G------- \--* CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult [000068] ------------ this in rcx +--* LCL_VAR ref V05 tmp3 [000078] x----------- arg1 +--* OBJ(16) simd16 [000077] L----------- | \--* ADDR byref [000064] ------------ | \--* LCL_VAR simd16 V04 tmp2 [000072] ------------ arg2 +--* LCL_VAR long V06 tmp4 [000073] ------------ arg3 \--* CNS_STR ref [ 0] 91 (0x05b) nop [000082] ------------ * STMT void (IL 0x05B... ???) [000081] ------------ \--* NO_OP void [ 0] 92 (0x05c) ret [000084] ------------ * STMT void (IL 0x05C... ???) [000083] ------------ \--* RETURN void New BlockSet epoch 1, # of blocks (including unused BB00): 3, bitset array size: 1 (short) *************** In fgMorph() *************** In fgDebugCheckBBlist *************** After fgAddInternal() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal BB02 [0001] 1 1 [000..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** In fgRemoveEmptyFinally() No EH in this method, nothing to remove. *************** In fgMergeFinallyChains() No EH in this method, nothing to merge. *************** In fgCloneFinally() No EH in this method, no cloning. *************** In fgMarkImplicitByRefs() *************** In fgPromoteStructs() promotion opt flag not enabled *************** In fgMarkAddressExposedLocals() *************** In fgRetypeImplicitByRefArgs() *************** In fgMorphBlocks() Morphing BB01 of 'JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this' fgMorphTree BB01, stmt 1 (before) [000000] ------------ * NOP void fgMorphTree BB01, stmt 2 (before) [000090] ------------ then /--* NOP void [000091] --C-G------- /--* COLON void [000089] --C-G------- else | \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE [000092] --C-G------- * QMARK void [000087] ------------ | /--* CNS_INT int 0 [000088] Q----------- if \--* EQ int [000086] ------------ \--* IND int [000085] ------------ \--* CNS_INT(h) long 0x7ff826874428 token argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Morphing BB02 of 'JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this' fgMorphTree BB02, stmt 3 (before) [000003] ------------ * NO_OP void fgMorphTree BB02, stmt 4 (before) [000006] --C-G------- * CALL void System.Console.WriteLine [000005] ------------ arg0 \--* CNS_STR ref argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000095] x---G+------ * IND ref [000094] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" Replaced with placeholder node: [000096] ----------L- * ARGPLACE ref Shuffled argument table: rcx fgArgTabEntry[arg 0 95.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB02, stmt 4 (after) [000006] --CXG+------ * CALL void System.Console.WriteLine [000095] x---G+------ arg0 in rcx \--* IND ref [000094] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" fgMorphTree BB02, stmt 5 (before) [000009] ------------ * NO_OP void fgMorphTree BB02, stmt 6 (before) [000015] ------------ /--* CNS_INT int 1 [000016] ----G------- /--* HWIntrinsic float float Extract [000014] ----G------- | \--* OBJ(16) simd16 [000012] ------------ | | /--* CNS_INT long 8 Fseq[#FirstElem] [000013] ----G------- | \--* ADD byref [000011] ----G------- | \--* FIELD ref _clsVar [000018] -A--G------- * ASG float [000017] D------N---- \--* LCL_VAR float V02 tmp0 fgMorphTree BB02, stmt 6 (after) [000015] -----+------ /--* CNS_INT int 1 [000016] ---XG+------ /--* HWIntrinsic float float Extract [000014] ---XG+------ | \--* OBJ(16) simd16 [000012] -----+------ | | /--* CNS_INT long 8 Fseq[#FirstElem] [000013] ----G+------ | \--* ADD byref [000011] x---G+------ | \--* IND ref [000098] -----+------ | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000018] -A-XG+------ * ASG float [000017] D----+-N---- \--* LCL_VAR float V02 tmp0 fgMorphTree BB02, stmt 7 (before) [000020] ------------ /--* LCL_VAR float V02 tmp0 [000022] -A---------- * ASG float [000021] D------N---- \--* LCL_VAR float V01 loc0 fgMorphTree BB02, stmt 8 (before) [000025] --C-G------- * CALL void System.Console.WriteLine [000024] ------------ arg0 \--* CNS_STR ref argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000100] x---G+------ * IND ref [000099] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" Replaced with placeholder node: [000101] ----------L- * ARGPLACE ref Shuffled argument table: rcx fgArgTabEntry[arg 0 100.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB02, stmt 8 (after) [000025] --CXG+------ * CALL void System.Console.WriteLine [000100] x---G+------ arg0 in rcx \--* IND ref [000099] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" fgMorphTree BB02, stmt 9 (before) [000028] ------------ * NO_OP void fgMorphTree BB02, stmt 10 (before) [000033] --CXG------- /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000032] ---XG------- this in rcx | \--* ADDR byref [000031] ---XG------- | \--* FIELD struct _dataTable [000030] ------------ | \--* LCL_VAR ref V00 this [000035] -ACXG------- * ASG long [000034] D------N---- \--* LCL_VAR long V03 tmp1 Before explicit null check morphing: [000031] ---XG--N---- * FIELD struct _dataTable [000030] ------------ \--* LCL_VAR ref V00 this After adding explicit null check: [000031] ---XG--N---- * IND struct [000106] ------------ | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000107] ------------ | /--* ADD byref [000105] ------------ | | \--* LCL_VAR ref V00 this [000108] ---X-------- \--* COMMA byref [000104] ---X---N---- \--* NULLCHECK byte [000103] ------------ \--* LCL_VAR ref V00 this argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000106] -----+------ /--* CNS_INT long 32 field offset Fseq[_dataTable] [000107] -----+------ /--* ADD byref [000105] -----+------ | \--* LCL_VAR ref V00 this [000108] ---XG+-N---- * COMMA byref [000104] ---X-+-N---- \--* NULLCHECK byte [000103] -----+------ \--* LCL_VAR ref V00 this Replaced with placeholder node: [000110] ----------L- * ARGPLACE byref Shuffled argument table: rcx fgArgTabEntry[arg 0 108.COMMA, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB02, stmt 10 (after) [000033] --CXG+------ /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000106] -----+------ | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000107] -----+------ | | /--* ADD byref [000105] -----+------ | | | \--* LCL_VAR ref V00 this [000108] ---XG+-N---- this in rcx | \--* COMMA byref [000104] ---X-+-N---- | \--* NULLCHECK byte [000103] -----+------ | \--* LCL_VAR ref V00 this [000035] -ACXG+------ * ASG long [000034] D----+-N---- \--* LCL_VAR long V03 tmp1 fgMorphTree BB02, stmt 11 (before) [000039] --C-G------- * CALL void System.Runtime.CompilerServices.Unsafe.Write [000037] ------------ arg0 +--* LCL_VAR long V03 tmp1 [000038] ------------ arg1 \--* LCL_VAR float V01 loc0 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000037] -----+------ * LCL_VAR long V03 tmp1 Replaced with placeholder node: [000112] ----------L- * ARGPLACE long Deferred argument ('mm1'): [000038] -----+------ * LCL_VAR float V01 loc0 Replaced with placeholder node: [000114] ----------L- * ARGPLACE float Shuffled argument table: rcx mm1 fgArgTabEntry[arg 0 37.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 38.LCL_VAR, mm1, regs=1, align=1, lateArgInx=1, processed] fgMorphTree BB02, stmt 11 (after) [000039] --CXG+------ * CALL void System.Runtime.CompilerServices.Unsafe.Write [000037] -----+------ arg0 in rcx +--* LCL_VAR long V03 tmp1 [000038] -----+------ arg1 in mm1 \--* LCL_VAR float V01 loc0 fgMorphTree BB02, stmt 12 (before) [000043] ------------ * NO_OP void fgMorphTree BB02, stmt 13 (before) [000046] --C-G------- * CALL void System.Console.WriteLine [000045] ------------ arg0 \--* CNS_STR ref argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000117] x---G+------ * IND ref [000116] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" Replaced with placeholder node: [000118] ----------L- * ARGPLACE ref Shuffled argument table: rcx fgArgTabEntry[arg 0 117.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB02, stmt 13 (after) [000046] --CXG+------ * CALL void System.Console.WriteLine [000117] x---G+------ arg0 in rcx \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" fgMorphTree BB02, stmt 14 (before) [000049] ------------ * NO_OP void fgMorphTree BB02, stmt 15 (before) [000055] ----G------- /--* OBJ(16) simd16 [000053] ------------ | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G------- | \--* ADD byref [000052] ----G------- | \--* FIELD ref _clsVar [000062] -A--G---R--- * ASG simd16 (copy) [000060] D----------- \--* LCL_VAR simd16 V04 tmp2 fgMorphCopyBlock:block assignment to morph: [000055] ---XG+------ /--* OBJ(16) simd16 [000053] -----+------ | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G+------ | \--* ADD byref [000052] x---G+------ | \--* IND ref [000120] -----+------ | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000062] -A-XG---R--- * ASG simd16 (copy) [000060] D----+-N---- \--* LCL_VAR simd16 V04 tmp2 with no promoted structs this requires a CopyBlock. Local V04 should not be enregistered because: written in a block op fgMorphTree BB02, stmt 15 (after) [000055] ---XG+------ /--* IND simd16 [000053] -----+------ | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G+------ | \--* ADD byref [000052] x---G+------ | \--* IND ref [000120] -----+------ | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000062] -A-XG+--R--- * ASG simd16 (copy) [000060] D----+-N---- \--* LCL_VAR simd16 V04 tmp2 fgMorphTree BB02, stmt 16 (before) [000051] ------------ /--* LCL_VAR ref V00 this [000066] -A---------- * ASG ref [000065] D------N---- \--* LCL_VAR ref V05 tmp3 fgMorphTree BB02, stmt 17 (before) [000059] --CXG------- /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000058] ---XG------- this in rcx | \--* ADDR byref [000057] ---XG------- | \--* FIELD struct _dataTable [000056] ------------ | \--* LCL_VAR ref V00 this [000070] -ACXG------- * ASG long [000069] D------N---- \--* LCL_VAR long V06 tmp4 Before explicit null check morphing: [000057] ---XG--N---- * FIELD struct _dataTable [000056] ------------ \--* LCL_VAR ref V00 this After adding explicit null check: [000057] ---XG--N---- * IND struct [000124] ------------ | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000125] ------------ | /--* ADD byref [000123] ------------ | | \--* LCL_VAR ref V00 this [000126] ---X-------- \--* COMMA byref [000122] ---X---N---- \--* NULLCHECK byte [000121] ------------ \--* LCL_VAR ref V00 this argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000124] -----+------ /--* CNS_INT long 32 field offset Fseq[_dataTable] [000125] -----+------ /--* ADD byref [000123] -----+------ | \--* LCL_VAR ref V00 this [000126] ---XG+-N---- * COMMA byref [000122] ---X-+-N---- \--* NULLCHECK byte [000121] -----+------ \--* LCL_VAR ref V00 this Replaced with placeholder node: [000128] ----------L- * ARGPLACE byref Shuffled argument table: rcx fgArgTabEntry[arg 0 126.COMMA, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB02, stmt 17 (after) [000059] --CXG+------ /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000124] -----+------ | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000125] -----+------ | | /--* ADD byref [000123] -----+------ | | | \--* LCL_VAR ref V00 this [000126] ---XG+-N---- this in rcx | \--* COMMA byref [000122] ---X-+-N---- | \--* NULLCHECK byte [000121] -----+------ | \--* LCL_VAR ref V00 this [000070] -ACXG+------ * ASG long [000069] D----+-N---- \--* LCL_VAR long V06 tmp4 fgMorphTree BB02, stmt 18 (before) [000074] --C-G------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult [000068] ------------ this in rcx +--* LCL_VAR ref V05 tmp3 [000078] x----------- arg1 +--* OBJ(16) simd16 [000077] L----------- | \--* ADDR byref [000064] ------------ | \--* LCL_VAR simd16 V04 tmp2 [000072] ------------ arg2 +--* LCL_VAR long V06 tmp4 [000073] ------------ arg3 \--* CNS_STR ref lvaGrabTemp returning 7 (V07 tmp5) called for by-value struct argument. HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Single Found type Hardware Intrinsic SIMD Vector128 Local V07 should not be enregistered because: it is a struct New refCnts for V07: refCnt = 1, refCntWtd = 2 fgMorphCopyBlock:block assignment to morph: [000064] -----+-N---- /--* LCL_VAR simd16 V04 tmp2 [000131] -A------R--- * ASG simd16 (copy) [000130] D------N---- \--* LCL_VAR simd16 V07 tmp5 with no promoted structs this requires a CopyBlock. Local V07 should not be enregistered because: written in a block op Local V04 should not be enregistered because: written in a block op argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000068] -----+------ * LCL_VAR ref V05 tmp3 lvaGrabTemp returning 8 (V08 tmp6) called for argument with side effect. Evaluate to a temp: [000068] -----+------ /--* LCL_VAR ref V05 tmp3 [000135] -A--------L- * ASG ref [000134] D------N---- \--* LCL_VAR ref V08 tmp6 Local V07 should not be enregistered because: it is address exposed Deferred argument ('r9'): [000133] x---G+------ * IND ref [000132] -----+------ \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" Replaced with placeholder node: [000141] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000072] -----+------ * LCL_VAR long V06 tmp4 Replaced with placeholder node: [000143] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx r9 r8 fgArgTabEntry[arg 0 136.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V08, isTmp, processed] fgArgTabEntry[arg 1 139.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V07, isTmp, processed] fgArgTabEntry[arg 3 133.IND, r9, regs=1, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 2 72.LCL_VAR, r8, regs=1, align=1, lateArgInx=3, processed] fgMorphTree BB02, stmt 18 (after) [000074] -ACXG+------ * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult [000068] -----+------ | /--* LCL_VAR ref V05 tmp3 [000135] -A--------L- this SETUP +--* ASG ref [000134] D------N---- | \--* LCL_VAR ref V08 tmp6 [000064] -----+-N---- | /--* LCL_VAR simd16 V04 tmp2 [000131] -A------R-L- arg1 SETUP +--* ASG simd16 (copy) [000130] D------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000136] ------------ this in rcx +--* LCL_VAR ref V08 tmp6 [000139] L----------- arg1 in rdx +--* ADDR byref [000138] -------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000133] x---G+------ arg3 in r9 +--* IND ref [000132] -----+------ | \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" [000072] -----+------ arg2 in r8 \--* LCL_VAR long V06 tmp4 fgMorphTree BB02, stmt 19 (before) [000081] ------------ * NO_OP void fgMorphTree BB02, stmt 20 (before) [000083] ------------ * RETURN void Expanding top-level qmark in BB01 (before) -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000001] ------------ * STMT void (IL ???... ???) [000000] -----+------ \--* NOP void ***** BB01, stmt 2 [000093] ------------ * STMT void (IL ???... ???) [000090] -----+?----- then | /--* NOP void [000091] --C-G+?----- | /--* COLON void [000089] --C-G+?----- else | | \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE [000092] --C-G+------ \--* QMARK void [000087] -----+------ | /--* CNS_INT int 0 [000088] J----+-N---- if \--* EQ int [000086] x----+------ \--* IND int [000085] -----+------ \--* CNS_INT(h) long 0x7ff826874428 token ------------------------------------------------------------------------------------------------------------------- New Basic Block BB03 [0002] created. BB02 previous predecessor was BB01, now is BB03 New Basic Block BB04 [0003] created. New Basic Block BB05 [0004] created. Removing statement [000093] in BB01 as useless: [000093] ------------ * STMT void (IL ???... ???) [000090] -----+?----- then | /--* NOP void [000091] --C-G+?----- | /--* COLON void [000089] --C-G+?----- else | | \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE [000092] --C-G+------ \--* QMARK void [000087] -----+------ | /--* CNS_INT int 0 [000088] J----+-N---- if \--* EQ int [000086] x----+------ \--* IND int [000085] -----+------ \--* CNS_INT(h) long 0x7ff826874428 token Expanding top-level qmark in BB01 (after) -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal BB04 [0003] 1 1 [???..???)-> BB03 ( cond ) internal BB05 [0004] 1 0.50 [???..???) internal BB03 [0002] 2 1 [???..???) i internal label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB04} ***** BB01, stmt 1 [000001] ------------ * STMT void (IL ???... ???) [000000] -----+------ \--* NOP void ------------ BB04 [???..???) -> BB03 (cond), preds={} succs={BB05,BB03} ***** BB04, stmt 2 [000146] ------------ * STMT void (IL ???... ???) [000145] ------------ \--* JTRUE void [000087] -----+------ | /--* CNS_INT int 0 [000088] J----+-N---- \--* EQ int [000086] x----+------ \--* IND int [000085] -----+------ \--* CNS_INT(h) long 0x7ff826874428 token ------------ BB05 [???..???), preds={} succs={BB03} ***** BB05, stmt 3 [000147] ------------ * STMT void (IL ???... ???) [000089] --C-G+?----- \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB03 [???..???), preds={} succs={BB02} ------------------------------------------------------------------------------------------------------------------- Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal BB04 [0003] 1 1 [???..???)-> BB03 ( cond ) internal BB05 [0004] 1 0.50 [???..???) internal BB03 [0002] 2 1 [???..???) i internal label target BB02 [0001] 1 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB04 to BB02 Renumber BB05 to BB03 Renumber BB03 to BB04 Renumber BB02 to BB05 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal BB02 [0003] 1 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 0.50 [???..???) internal BB04 [0002] 2 1 [???..???) i internal label target BB05 [0001] 1 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short) *************** In fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal BB02 [0003] 1 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 0.50 [???..???) internal BB04 [0002] 2 1 [???..???) i internal label target BB05 [0001] 1 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgComputeEdgeWeights() fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- fgComputeEdgeWeights() was able to compute exact edge weights for all of the 5 edges, using 1 passes. Edge weights into BB02 :BB01 (100) Edge weights into BB03 :BB02 (50) Edge weights into BB04 :BB02 (50), BB03 (50) Edge weights into BB05 :BB04 (100) *************** In fgCreateFunclets() After fgCreateFunclets() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In Allocate Objects Trees before Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000001] ------------ * STMT void (IL ???... ???) [000000] -----+------ \--* NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02, stmt 2 [000146] ------------ * STMT void (IL ???... ???) [000145] ------------ \--* JTRUE void [000087] -----+------ | /--* CNS_INT int 0 [000088] J----+-N---- \--* EQ int [000086] x----+------ \--* IND int [000085] -----+------ \--* CNS_INT(h) long 0x7ff826874428 token ------------ BB03 [???..???), preds={BB02} succs={BB04} ***** BB03, stmt 3 [000147] ------------ * STMT void (IL ???... ???) [000089] --C-G+?----- \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ***** BB05, stmt 4 [000004] ------------ * STMT void (IL 0x000...0x000) [000003] -----+------ \--* NO_OP void ***** BB05, stmt 5 [000008] ------------ * STMT void (IL 0x001...0x00B) [000006] --CXG+------ \--* CALL void System.Console.WriteLine [000095] x---G+------ arg0 in rcx \--* IND ref [000094] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 6 [000010] ------------ * STMT void (IL 0x00B... ???) [000009] -----+------ \--* NO_OP void ***** BB05, stmt 7 [000019] ------------ * STMT void (IL 0x00C...0x017) [000015] -----+------ | /--* CNS_INT int 1 [000016] ---XG+------ | /--* HWIntrinsic float float Extract [000014] ---XG+------ | | \--* OBJ(16) simd16 [000012] -----+------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000013] ----G+------ | | \--* ADD byref [000011] x---G+------ | | \--* IND ref [000098] -----+------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000018] -A-XG+------ \--* ASG float [000017] D----+-N---- \--* LCL_VAR float V02 tmp0 ***** BB05, stmt 8 [000023] ------------ * STMT void (IL 0x017... ???) [000020] -----+------ | /--* LCL_VAR float V02 tmp0 [000022] -A---+------ \--* ASG float [000021] D----+-N---- \--* LCL_VAR float V01 loc0 ***** BB05, stmt 9 [000027] ------------ * STMT void (IL 0x018...0x022) [000025] --CXG+------ \--* CALL void System.Console.WriteLine [000100] x---G+------ arg0 in rcx \--* IND ref [000099] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 10 [000029] ------------ * STMT void (IL 0x022... ???) [000028] -----+------ \--* NO_OP void ***** BB05, stmt 11 [000036] ------------ * STMT void (IL 0x023...0x034) [000033] --CXG+------ | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000106] -----+------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000107] -----+------ | | | /--* ADD byref [000105] -----+------ | | | | \--* LCL_VAR ref V00 this [000108] ---XG+-N---- this in rcx | | \--* COMMA byref [000104] ---X-+-N---- | | \--* NULLCHECK byte [000103] -----+------ | | \--* LCL_VAR ref V00 this [000035] -ACXG+------ \--* ASG long [000034] D----+-N---- \--* LCL_VAR long V03 tmp1 ***** BB05, stmt 12 [000042] ------------ * STMT void (IL 0x02E... ???) [000039] --CXG+------ \--* CALL void System.Runtime.CompilerServices.Unsafe.Write [000037] -----+------ arg0 in rcx +--* LCL_VAR long V03 tmp1 [000038] -----+------ arg1 in mm1 \--* LCL_VAR float V01 loc0 ***** BB05, stmt 13 [000044] ------------ * STMT void (IL 0x034... ???) [000043] -----+------ \--* NO_OP void ***** BB05, stmt 14 [000048] ------------ * STMT void (IL 0x035...0x03F) [000046] --CXG+------ \--* CALL void System.Console.WriteLine [000117] x---G+------ arg0 in rcx \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 15 [000050] ------------ * STMT void (IL 0x03F... ???) [000049] -----+------ \--* NO_OP void ***** BB05, stmt 16 [000063] ------------ * STMT void (IL 0x040...0x05B) [000055] ---XG+------ | /--* IND simd16 [000053] -----+------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G+------ | | \--* ADD byref [000052] x---G+------ | | \--* IND ref [000120] -----+------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000062] -A-XG+--R--- \--* ASG simd16 (copy) [000060] D----+-N---- \--* LCL_VAR simd16 V04 tmp2 ***** BB05, stmt 17 [000067] ------------ * STMT void (IL ???... ???) [000051] -----+------ | /--* LCL_VAR ref V00 this [000066] -A---+------ \--* ASG ref [000065] D----+-N---- \--* LCL_VAR ref V05 tmp3 ***** BB05, stmt 18 [000071] ------------ * STMT void (IL ???... ???) [000059] --CXG+------ | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000124] -----+------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000125] -----+------ | | | /--* ADD byref [000123] -----+------ | | | | \--* LCL_VAR ref V00 this [000126] ---XG+-N---- this in rcx | | \--* COMMA byref [000122] ---X-+-N---- | | \--* NULLCHECK byte [000121] -----+------ | | \--* LCL_VAR ref V00 this [000070] -ACXG+------ \--* ASG long [000069] D----+-N---- \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 19 [000080] ------------ * STMT void (IL 0x051... ???) [000074] -ACXG+------ \--* CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult [000068] -----+------ | /--* LCL_VAR ref V05 tmp3 [000135] -A--------L- this SETUP +--* ASG ref [000134] D------N---- | \--* LCL_VAR ref V08 tmp6 [000064] -----+-N---- | /--* LCL_VAR simd16 V04 tmp2 [000131] -A------R-L- arg1 SETUP +--* ASG simd16 (copy) [000130] D------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000136] ------------ this in rcx +--* LCL_VAR ref V08 tmp6 [000139] L----------- arg1 in rdx +--* ADDR byref [000138] -------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000133] x---G+------ arg3 in r9 +--* IND ref [000132] -----+------ | \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" [000072] -----+------ arg2 in r8 \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 20 [000082] ------------ * STMT void (IL 0x05B... ???) [000081] -----+------ \--* NO_OP void ***** BB05, stmt 21 [000084] ------------ * STMT void (IL 0x05C...0x05C) [000083] -----+------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Exiting Allocate Objects Trees after Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000001] ------------ * STMT void (IL ???... ???) [000000] -----+------ \--* NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02, stmt 2 [000146] ------------ * STMT void (IL ???... ???) [000145] ------------ \--* JTRUE void [000087] -----+------ | /--* CNS_INT int 0 [000088] J----+-N---- \--* EQ int [000086] x----+------ \--* IND int [000085] -----+------ \--* CNS_INT(h) long 0x7ff826874428 token ------------ BB03 [???..???), preds={BB02} succs={BB04} ***** BB03, stmt 3 [000147] ------------ * STMT void (IL ???... ???) [000089] --C-G+?----- \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ***** BB05, stmt 4 [000004] ------------ * STMT void (IL 0x000...0x000) [000003] -----+------ \--* NO_OP void ***** BB05, stmt 5 [000008] ------------ * STMT void (IL 0x001...0x00B) [000006] --CXG+------ \--* CALL void System.Console.WriteLine [000095] x---G+------ arg0 in rcx \--* IND ref [000094] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 6 [000010] ------------ * STMT void (IL 0x00B... ???) [000009] -----+------ \--* NO_OP void ***** BB05, stmt 7 [000019] ------------ * STMT void (IL 0x00C...0x017) [000015] -----+------ | /--* CNS_INT int 1 [000016] ---XG+------ | /--* HWIntrinsic float float Extract [000014] ---XG+------ | | \--* OBJ(16) simd16 [000012] -----+------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000013] ----G+------ | | \--* ADD byref [000011] x---G+------ | | \--* IND ref [000098] -----+------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000018] -A-XG+------ \--* ASG float [000017] D----+-N---- \--* LCL_VAR float V02 tmp0 ***** BB05, stmt 8 [000023] ------------ * STMT void (IL 0x017... ???) [000020] -----+------ | /--* LCL_VAR float V02 tmp0 [000022] -A---+------ \--* ASG float [000021] D----+-N---- \--* LCL_VAR float V01 loc0 ***** BB05, stmt 9 [000027] ------------ * STMT void (IL 0x018...0x022) [000025] --CXG+------ \--* CALL void System.Console.WriteLine [000100] x---G+------ arg0 in rcx \--* IND ref [000099] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 10 [000029] ------------ * STMT void (IL 0x022... ???) [000028] -----+------ \--* NO_OP void ***** BB05, stmt 11 [000036] ------------ * STMT void (IL 0x023...0x034) [000033] --CXG+------ | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000106] -----+------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000107] -----+------ | | | /--* ADD byref [000105] -----+------ | | | | \--* LCL_VAR ref V00 this [000108] ---XG+-N---- this in rcx | | \--* COMMA byref [000104] ---X-+-N---- | | \--* NULLCHECK byte [000103] -----+------ | | \--* LCL_VAR ref V00 this [000035] -ACXG+------ \--* ASG long [000034] D----+-N---- \--* LCL_VAR long V03 tmp1 ***** BB05, stmt 12 [000042] ------------ * STMT void (IL 0x02E... ???) [000039] --CXG+------ \--* CALL void System.Runtime.CompilerServices.Unsafe.Write [000037] -----+------ arg0 in rcx +--* LCL_VAR long V03 tmp1 [000038] -----+------ arg1 in mm1 \--* LCL_VAR float V01 loc0 ***** BB05, stmt 13 [000044] ------------ * STMT void (IL 0x034... ???) [000043] -----+------ \--* NO_OP void ***** BB05, stmt 14 [000048] ------------ * STMT void (IL 0x035...0x03F) [000046] --CXG+------ \--* CALL void System.Console.WriteLine [000117] x---G+------ arg0 in rcx \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 15 [000050] ------------ * STMT void (IL 0x03F... ???) [000049] -----+------ \--* NO_OP void ***** BB05, stmt 16 [000063] ------------ * STMT void (IL 0x040...0x05B) [000055] ---XG+------ | /--* IND simd16 [000053] -----+------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G+------ | | \--* ADD byref [000052] x---G+------ | | \--* IND ref [000120] -----+------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000062] -A-XG+--R--- \--* ASG simd16 (copy) [000060] D----+-N---- \--* LCL_VAR simd16 V04 tmp2 ***** BB05, stmt 17 [000067] ------------ * STMT void (IL ???... ???) [000051] -----+------ | /--* LCL_VAR ref V00 this [000066] -A---+------ \--* ASG ref [000065] D----+-N---- \--* LCL_VAR ref V05 tmp3 ***** BB05, stmt 18 [000071] ------------ * STMT void (IL ???... ???) [000059] --CXG+------ | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000124] -----+------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000125] -----+------ | | | /--* ADD byref [000123] -----+------ | | | | \--* LCL_VAR ref V00 this [000126] ---XG+-N---- this in rcx | | \--* COMMA byref [000122] ---X-+-N---- | | \--* NULLCHECK byte [000121] -----+------ | | \--* LCL_VAR ref V00 this [000070] -ACXG+------ \--* ASG long [000069] D----+-N---- \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 19 [000080] ------------ * STMT void (IL 0x051... ???) [000074] -ACXG+------ \--* CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult [000068] -----+------ | /--* LCL_VAR ref V05 tmp3 [000135] -A--------L- this SETUP +--* ASG ref [000134] D------N---- | \--* LCL_VAR ref V08 tmp6 [000064] -----+-N---- | /--* LCL_VAR simd16 V04 tmp2 [000131] -A------R-L- arg1 SETUP +--* ASG simd16 (copy) [000130] D------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000136] ------------ this in rcx +--* LCL_VAR ref V08 tmp6 [000139] L----------- arg1 in rdx +--* ADDR byref [000138] -------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000133] x---G+------ arg3 in r9 +--* IND ref [000132] -----+------ | \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" [000072] -----+------ arg2 in r8 \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 20 [000082] ------------ * STMT void (IL 0x05B... ???) [000081] -----+------ \--* NO_OP void ***** BB05, stmt 21 [000084] ------------ * STMT void (IL 0x05C...0x05C) [000083] -----+------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In lvaMarkLocalVars() lvaGrabTemp returning 9 (V09 tmp7) (a long lifetime temp) called for OutgoingArgSpace. *** marking local variables in block BB01 (weight=1 ) [000001] ------------ * STMT void (IL ???... ???) [000000] -----+------ \--* NOP void *** marking local variables in block BB02 (weight=1 ) [000146] ------------ * STMT void (IL ???... ???) [000145] ------------ \--* JTRUE void [000087] -----+------ | /--* CNS_INT int 0 [000088] J----+-N---- \--* EQ int [000086] x----+------ \--* IND int [000085] -----+------ \--* CNS_INT(h) long 0x7ff826874428 token *** marking local variables in block BB03 (weight=0.50) [000147] ------------ * STMT void (IL ???... ???) [000089] --C-G+?----- \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE *** marking local variables in block BB04 (weight=1 ) *** marking local variables in block BB05 (weight=1 ) [000004] ------------ * STMT void (IL 0x000...0x000) [000003] -----+------ \--* NO_OP void [000008] ------------ * STMT void (IL 0x001...0x00B) [000006] --CXG+------ \--* CALL void System.Console.WriteLine [000095] x---G+------ arg0 in rcx \--* IND ref [000094] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" [000010] ------------ * STMT void (IL 0x00B... ???) [000009] -----+------ \--* NO_OP void [000019] ------------ * STMT void (IL 0x00C...0x017) [000015] -----+------ | /--* CNS_INT int 1 [000016] ---XG+------ | /--* HWIntrinsic float float Extract [000014] ---XG+------ | | \--* OBJ(16) simd16 [000012] -----+------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000013] ----G+------ | | \--* ADD byref [000011] x---G+------ | | \--* IND ref [000098] -----+------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000018] -A-XG+------ \--* ASG float [000017] D----+-N---- \--* LCL_VAR float V02 tmp0 New refCnts for V02: refCnt = 1, refCntWtd = 2 [000023] ------------ * STMT void (IL 0x017... ???) [000020] -----+------ | /--* LCL_VAR float V02 tmp0 [000022] -A---+------ \--* ASG float [000021] D----+-N---- \--* LCL_VAR float V01 loc0 New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 4 [000027] ------------ * STMT void (IL 0x018...0x022) [000025] --CXG+------ \--* CALL void System.Console.WriteLine [000100] x---G+------ arg0 in rcx \--* IND ref [000099] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" [000029] ------------ * STMT void (IL 0x022... ???) [000028] -----+------ \--* NO_OP void [000036] ------------ * STMT void (IL 0x023...0x034) [000033] --CXG+------ | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000106] -----+------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000107] -----+------ | | | /--* ADD byref [000105] -----+------ | | | | \--* LCL_VAR ref V00 this [000108] ---XG+-N---- this in rcx | | \--* COMMA byref [000104] ---X-+-N---- | | \--* NULLCHECK byte [000103] -----+------ | | \--* LCL_VAR ref V00 this [000035] -ACXG+------ \--* ASG long [000034] D----+-N---- \--* LCL_VAR long V03 tmp1 New refCnts for V03: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 2 [000042] ------------ * STMT void (IL 0x02E... ???) [000039] --CXG+------ \--* CALL void System.Runtime.CompilerServices.Unsafe.Write [000037] -----+------ arg0 in rcx +--* LCL_VAR long V03 tmp1 [000038] -----+------ arg1 in mm1 \--* LCL_VAR float V01 loc0 New refCnts for V03: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 2, refCntWtd = 2 [000044] ------------ * STMT void (IL 0x034... ???) [000043] -----+------ \--* NO_OP void [000048] ------------ * STMT void (IL 0x035...0x03F) [000046] --CXG+------ \--* CALL void System.Console.WriteLine [000117] x---G+------ arg0 in rcx \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" [000050] ------------ * STMT void (IL 0x03F... ???) [000049] -----+------ \--* NO_OP void [000063] ------------ * STMT void (IL 0x040...0x05B) [000055] ---XG+------ | /--* IND simd16 [000053] -----+------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] [000054] ----G+------ | | \--* ADD byref [000052] x---G+------ | | \--* IND ref [000120] -----+------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] [000062] -A-XG+--R--- \--* ASG simd16 (copy) [000060] D----+-N---- \--* LCL_VAR simd16 V04 tmp2 New refCnts for V04: refCnt = 1, refCntWtd = 2 [000067] ------------ * STMT void (IL ???... ???) [000051] -----+------ | /--* LCL_VAR ref V00 this [000066] -A---+------ \--* ASG ref [000065] D----+-N---- \--* LCL_VAR ref V05 tmp3 New refCnts for V05: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 3, refCntWtd = 3 [000071] ------------ * STMT void (IL ???... ???) [000059] --CXG+------ | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr [000124] -----+------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] [000125] -----+------ | | | /--* ADD byref [000123] -----+------ | | | | \--* LCL_VAR ref V00 this [000126] ---XG+-N---- this in rcx | | \--* COMMA byref [000122] ---X-+-N---- | | \--* NULLCHECK byte [000121] -----+------ | | \--* LCL_VAR ref V00 this [000070] -ACXG+------ \--* ASG long [000069] D----+-N---- \--* LCL_VAR long V06 tmp4 New refCnts for V06: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 5, refCntWtd = 5 [000080] ------------ * STMT void (IL 0x051... ???) [000074] -ACXG+------ \--* CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult [000068] -----+------ | /--* LCL_VAR ref V05 tmp3 [000135] -A--------L- this SETUP +--* ASG ref [000134] D------N---- | \--* LCL_VAR ref V08 tmp6 [000064] -----+-N---- | /--* LCL_VAR simd16 V04 tmp2 [000131] -A------R-L- arg1 SETUP +--* ASG simd16 (copy) [000130] D------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000136] ------------ this in rcx +--* LCL_VAR ref V08 tmp6 [000139] L----------- arg1 in rdx +--* ADDR byref [000138] -------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 [000133] x---G+------ arg3 in r9 +--* IND ref [000132] -----+------ | \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" [000072] -----+------ arg2 in r8 \--* LCL_VAR long V06 tmp4 New refCnts for V08: refCnt = 1, refCntWtd = 2 New refCnts for V05: refCnt = 2, refCntWtd = 4 New refCnts for V07: refCnt = 2, refCntWtd = 4 New refCnts for V04: refCnt = 2, refCntWtd = 4 New refCnts for V08: refCnt = 2, refCntWtd = 4 New refCnts for V07: refCnt = 3, refCntWtd = 6 New refCnts for V06: refCnt = 2, refCntWtd = 4 [000082] ------------ * STMT void (IL 0x05B... ???) [000081] -----+------ \--* NO_OP void [000084] ------------ * STMT void (IL 0x05C...0x05C) [000083] -----+------ \--* RETURN void New refCnts for V00: refCnt = 6, refCntWtd = 6 New refCnts for V00: refCnt = 7, refCntWtd = 7 Local V00 should not be enregistered because: It is a GC Ref and we are compiling MinOpts Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V03 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V05 should not be enregistered because: It is a GC Ref and we are compiling MinOpts Local V06 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set Local V08 should not be enregistered because: It is a GC Ref and we are compiling MinOpts Local V09 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set refCnt table for 'RunClsVarScenario': V03 tmp1 [ long]: refCnt = 2, refCntWtd = 4 V04 tmp2 [simd16]: refCnt = 2, refCntWtd = 4 V06 tmp4 [ long]: refCnt = 2, refCntWtd = 4 V02 tmp0 [ float]: refCnt = 2, refCntWtd = 4 V01 loc0 [ float]: refCnt = 2, refCntWtd = 2 V00 this [ ref]: refCnt = 7, refCntWtd = 7 pref [rcx] V07 tmp5 [simd16]: refCnt = 3, refCntWtd = 6 V05 tmp3 [ ref]: refCnt = 2, refCntWtd = 4 V08 tmp6 [ ref]: refCnt = 2, refCntWtd = 4 V09 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 *************** In fgFindOperOrder() *************** In fgSetBlockOrder() The biggest BB has 22 tree nodes -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 0, 0) [000001] ------------ * STMT void (IL ???... ???) N001 ( 0, 0) [000000] ------------ \--* NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02, stmt 2 ( 9, 16) [000146] ------------ * STMT void (IL ???... ???) N005 ( 9, 16) [000145] ------------ \--* JTRUE void N003 ( 1, 1) [000087] ------------ | /--* CNS_INT int 0 N004 ( 7, 14) [000088] J------N---- \--* EQ int N002 ( 5, 12) [000086] x----------- \--* IND int N001 ( 3, 10) [000085] ------------ \--* CNS_INT(h) long 0x7ff826874428 token ------------ BB03 [???..???), preds={BB02} succs={BB04} ***** BB03, stmt 3 ( 14, 5) [000147] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000089] --C-G-?----- \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ***** BB05, stmt 4 ( 1, 1) [000004] ------------ * STMT void (IL 0x000...0x000) N001 ( 1, 1) [000003] ------------ \--* NO_OP void ***** BB05, stmt 5 ( 19, 18) [000008] ------------ * STMT void (IL 0x001...0x00B) N006 ( 19, 18) [000006] --CXG------- \--* CALL void System.Console.WriteLine N004 ( 5, 12) [000095] x---G------- arg0 in rcx \--* IND ref N003 ( 3, 10) [000094] ------------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 6 ( 1, 1) [000010] ------------ * STMT void (IL 0x00B... ???) N001 ( 1, 1) [000009] ------------ \--* NO_OP void ***** BB05, stmt 7 ( 19, 25) [000019] ------------ * STMT void (IL 0x00C...0x017) N006 ( 1, 1) [000015] ------------ | /--* CNS_INT int 1 N007 ( 15, 20) [000016] ---XG------- | /--* HWIntrinsic float float Extract N005 ( 13, 18) [000014] ---XG------- | | \--* OBJ(16) simd16 N003 ( 1, 1) [000012] ------------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] N004 ( 7, 14) [000013] ----G------- | | \--* ADD byref N002 ( 5, 12) [000011] x---G------- | | \--* IND ref N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] N009 ( 19, 25) [000018] -A-XG---R--- \--* ASG float N008 ( 3, 4) [000017] D------N---- \--* LCL_VAR float V02 tmp0 ***** BB05, stmt 8 ( 7, 9) [000023] ------------ * STMT void (IL 0x017... ???) N001 ( 3, 4) [000020] ------------ | /--* LCL_VAR float V02 tmp0 N003 ( 7, 9) [000022] -A------R--- \--* ASG float N002 ( 3, 4) [000021] D------N---- \--* LCL_VAR float V01 loc0 ***** BB05, stmt 9 ( 19, 18) [000027] ------------ * STMT void (IL 0x018...0x022) N006 ( 19, 18) [000025] --CXG------- \--* CALL void System.Console.WriteLine N004 ( 5, 12) [000100] x---G------- arg0 in rcx \--* IND ref N003 ( 3, 10) [000099] ------------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 10 ( 1, 1) [000029] ------------ * STMT void (IL 0x022... ???) N001 ( 1, 1) [000028] ------------ \--* NO_OP void ***** BB05, stmt 11 ( 27, 17) [000036] ------------ * STMT void (IL 0x023...0x034) N009 ( 23, 14) [000033] --CXG------- | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr N005 ( 1, 1) [000106] ------------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] N006 ( 5, 4) [000107] ------------ | | | /--* ADD byref N004 ( 3, 2) [000105] ------------ | | | | \--* LCL_VAR ref V00 this N007 ( 9, 7) [000108] ---XG--N---- this in rcx | | \--* COMMA byref N003 ( 4, 3) [000104] ---X---N---- | | \--* NULLCHECK byte N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V00 this N011 ( 27, 17) [000035] -ACXG---R--- \--* ASG long N010 ( 3, 2) [000034] D------N---- \--* LCL_VAR long V03 tmp1 ***** BB05, stmt 12 ( 20, 13) [000042] ------------ * STMT void (IL 0x02E... ???) N009 ( 20, 13) [000039] --CXG------- \--* CALL void System.Runtime.CompilerServices.Unsafe.Write N005 ( 3, 2) [000037] ------------ arg0 in rcx +--* LCL_VAR long V03 tmp1 N006 ( 3, 4) [000038] ------------ arg1 in mm1 \--* LCL_VAR float V01 loc0 ***** BB05, stmt 13 ( 1, 1) [000044] ------------ * STMT void (IL 0x034... ???) N001 ( 1, 1) [000043] ------------ \--* NO_OP void ***** BB05, stmt 14 ( 19, 18) [000048] ------------ * STMT void (IL 0x035...0x03F) N006 ( 19, 18) [000046] --CXG------- \--* CALL void System.Console.WriteLine N004 ( 5, 12) [000117] x---G------- arg0 in rcx \--* IND ref N003 ( 3, 10) [000116] ------------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 15 ( 1, 1) [000050] ------------ * STMT void (IL 0x03F... ???) N001 ( 1, 1) [000049] ------------ \--* NO_OP void ***** BB05, stmt 16 ( 14, 19) [000063] ------------ * STMT void (IL 0x040...0x05B) N005 ( 10, 16) [000055] ---XG------- | /--* IND simd16 N003 ( 1, 1) [000053] ------------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] N004 ( 7, 14) [000054] ----G------- | | \--* ADD byref N002 ( 5, 12) [000052] x---G------- | | \--* IND ref N001 ( 3, 10) [000120] ------------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] N007 ( 14, 19) [000062] -A-XG---R--- \--* ASG simd16 (copy) N006 ( 3, 2) [000060] D------N---- \--* LCL_VAR simd16 V04 tmp2 ***** BB05, stmt 17 ( 7, 5) [000067] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000051] ------------ | /--* LCL_VAR ref V00 this N003 ( 7, 5) [000066] -A------R--- \--* ASG ref N002 ( 3, 2) [000065] D------N---- \--* LCL_VAR ref V05 tmp3 ***** BB05, stmt 18 ( 27, 17) [000071] ------------ * STMT void (IL ???... ???) N009 ( 23, 14) [000059] --CXG------- | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr N005 ( 1, 1) [000124] ------------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] N006 ( 5, 4) [000125] ------------ | | | /--* ADD byref N004 ( 3, 2) [000123] ------------ | | | | \--* LCL_VAR ref V00 this N007 ( 9, 7) [000126] ---XG--N---- this in rcx | | \--* COMMA byref N003 ( 4, 3) [000122] ---X---N---- | | \--* NULLCHECK byte N002 ( 3, 2) [000121] ------------ | | \--* LCL_VAR ref V00 this N011 ( 27, 17) [000070] -ACXG---R--- \--* ASG long N010 ( 3, 2) [000069] D------N---- \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 19 ( 45, 39) [000080] ------------ * STMT void (IL 0x051... ???) N022 ( 45, 39) [000074] -ACXG------- \--* CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult N001 ( 3, 2) [000068] ------------ | /--* LCL_VAR ref V05 tmp3 N003 ( 7, 5) [000135] -A------R-L- this SETUP +--* ASG ref N002 ( 3, 2) [000134] D------N---- | \--* LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- | /--* LCL_VAR simd16 V04 tmp2 N006 ( 7, 5) [000131] -A------R-L- arg1 SETUP +--* ASG simd16 (copy) N005 ( 3, 2) [000130] D------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ this in rcx +--* LCL_VAR ref V08 tmp6 N014 ( 3, 3) [000139] L----------- arg1 in rdx +--* ADDR byref N013 ( 3, 2) [000138] -------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 N016 ( 5, 12) [000133] x---G------- arg3 in r9 +--* IND ref N015 ( 3, 10) [000132] ------------ | \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" N017 ( 3, 2) [000072] ------------ arg2 in r8 \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 20 ( 1, 1) [000082] ------------ * STMT void (IL 0x05B... ???) N001 ( 1, 1) [000081] ------------ \--* NO_OP void ***** BB05, stmt 21 ( 0, 0) [000084] ------------ * STMT void (IL 0x05C...0x05C) N001 ( 0, 0) [000083] ------------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** In IR Rationalize Trees before IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal BB03 [0004] 1 BB02 0.50 [???..???) internal BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 0, 0) [000001] ------------ * STMT void (IL ???... ???) N001 ( 0, 0) [000000] ------------ \--* NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02, stmt 2 ( 9, 16) [000146] ------------ * STMT void (IL ???... ???) N005 ( 9, 16) [000145] ------------ \--* JTRUE void N003 ( 1, 1) [000087] ------------ | /--* CNS_INT int 0 N004 ( 7, 14) [000088] J------N---- \--* EQ int N002 ( 5, 12) [000086] x----------- \--* IND int N001 ( 3, 10) [000085] ------------ \--* CNS_INT(h) long 0x7ff826874428 token ------------ BB03 [???..???), preds={BB02} succs={BB04} ***** BB03, stmt 3 ( 14, 5) [000147] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000089] --C-G-?----- \--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ***** BB05, stmt 4 ( 1, 1) [000004] ------------ * STMT void (IL 0x000...0x000) N001 ( 1, 1) [000003] ------------ \--* NO_OP void ***** BB05, stmt 5 ( 19, 18) [000008] ------------ * STMT void (IL 0x001...0x00B) N006 ( 19, 18) [000006] --CXG------- \--* CALL void System.Console.WriteLine N004 ( 5, 12) [000095] x---G------- arg0 in rcx \--* IND ref N003 ( 3, 10) [000094] ------------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 6 ( 1, 1) [000010] ------------ * STMT void (IL 0x00B... ???) N001 ( 1, 1) [000009] ------------ \--* NO_OP void ***** BB05, stmt 7 ( 19, 25) [000019] ------------ * STMT void (IL 0x00C...0x017) N006 ( 1, 1) [000015] ------------ | /--* CNS_INT int 1 N007 ( 15, 20) [000016] ---XG------- | /--* HWIntrinsic float float Extract N005 ( 13, 18) [000014] ---XG------- | | \--* OBJ(16) simd16 N003 ( 1, 1) [000012] ------------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] N004 ( 7, 14) [000013] ----G------- | | \--* ADD byref N002 ( 5, 12) [000011] x---G------- | | \--* IND ref N001 ( 3, 10) [000098] ------------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] N009 ( 19, 25) [000018] -A-XG---R--- \--* ASG float N008 ( 3, 4) [000017] D------N---- \--* LCL_VAR float V02 tmp0 ***** BB05, stmt 8 ( 7, 9) [000023] ------------ * STMT void (IL 0x017... ???) N001 ( 3, 4) [000020] ------------ | /--* LCL_VAR float V02 tmp0 N003 ( 7, 9) [000022] -A------R--- \--* ASG float N002 ( 3, 4) [000021] D------N---- \--* LCL_VAR float V01 loc0 ***** BB05, stmt 9 ( 19, 18) [000027] ------------ * STMT void (IL 0x018...0x022) N006 ( 19, 18) [000025] --CXG------- \--* CALL void System.Console.WriteLine N004 ( 5, 12) [000100] x---G------- arg0 in rcx \--* IND ref N003 ( 3, 10) [000099] ------------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 10 ( 1, 1) [000029] ------------ * STMT void (IL 0x022... ???) N001 ( 1, 1) [000028] ------------ \--* NO_OP void ***** BB05, stmt 11 ( 27, 17) [000036] ------------ * STMT void (IL 0x023...0x034) N009 ( 23, 14) [000033] --CXG------- | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr N005 ( 1, 1) [000106] ------------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] N006 ( 5, 4) [000107] ------------ | | | /--* ADD byref N004 ( 3, 2) [000105] ------------ | | | | \--* LCL_VAR ref V00 this N007 ( 9, 7) [000108] ---XG--N---- this in rcx | | \--* COMMA byref N003 ( 4, 3) [000104] ---X---N---- | | \--* NULLCHECK byte N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V00 this N011 ( 27, 17) [000035] -ACXG---R--- \--* ASG long N010 ( 3, 2) [000034] D------N---- \--* LCL_VAR long V03 tmp1 ***** BB05, stmt 12 ( 20, 13) [000042] ------------ * STMT void (IL 0x02E... ???) N009 ( 20, 13) [000039] --CXG------- \--* CALL void System.Runtime.CompilerServices.Unsafe.Write N005 ( 3, 2) [000037] ------------ arg0 in rcx +--* LCL_VAR long V03 tmp1 N006 ( 3, 4) [000038] ------------ arg1 in mm1 \--* LCL_VAR float V01 loc0 ***** BB05, stmt 13 ( 1, 1) [000044] ------------ * STMT void (IL 0x034... ???) N001 ( 1, 1) [000043] ------------ \--* NO_OP void ***** BB05, stmt 14 ( 19, 18) [000048] ------------ * STMT void (IL 0x035...0x03F) N006 ( 19, 18) [000046] --CXG------- \--* CALL void System.Console.WriteLine N004 ( 5, 12) [000117] x---G------- arg0 in rcx \--* IND ref N003 ( 3, 10) [000116] ------------ \--* CNS_INT(h) long 0x99BB9538 "ClsVarScenario" ***** BB05, stmt 15 ( 1, 1) [000050] ------------ * STMT void (IL 0x03F... ???) N001 ( 1, 1) [000049] ------------ \--* NO_OP void ***** BB05, stmt 16 ( 14, 19) [000063] ------------ * STMT void (IL 0x040...0x05B) N005 ( 10, 16) [000055] ---XG------- | /--* IND simd16 N003 ( 1, 1) [000053] ------------ | | | /--* CNS_INT long 8 Fseq[#FirstElem] N004 ( 7, 14) [000054] ----G------- | | \--* ADD byref N002 ( 5, 12) [000052] x---G------- | | \--* IND ref N001 ( 3, 10) [000120] ------------ | | \--* CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] N007 ( 14, 19) [000062] -A-XG---R--- \--* ASG simd16 (copy) N006 ( 3, 2) [000060] D------N---- \--* LCL_VAR simd16 V04 tmp2 ***** BB05, stmt 17 ( 7, 5) [000067] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000051] ------------ | /--* LCL_VAR ref V00 this N003 ( 7, 5) [000066] -A------R--- \--* ASG ref N002 ( 3, 2) [000065] D------N---- \--* LCL_VAR ref V05 tmp3 ***** BB05, stmt 18 ( 27, 17) [000071] ------------ * STMT void (IL ???... ???) N009 ( 23, 14) [000059] --CXG------- | /--* CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr N005 ( 1, 1) [000124] ------------ | | | /--* CNS_INT long 32 field offset Fseq[_dataTable] N006 ( 5, 4) [000125] ------------ | | | /--* ADD byref N004 ( 3, 2) [000123] ------------ | | | | \--* LCL_VAR ref V00 this N007 ( 9, 7) [000126] ---XG--N---- this in rcx | | \--* COMMA byref N003 ( 4, 3) [000122] ---X---N---- | | \--* NULLCHECK byte N002 ( 3, 2) [000121] ------------ | | \--* LCL_VAR ref V00 this N011 ( 27, 17) [000070] -ACXG---R--- \--* ASG long N010 ( 3, 2) [000069] D------N---- \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 19 ( 45, 39) [000080] ------------ * STMT void (IL 0x051... ???) N022 ( 45, 39) [000074] -ACXG------- \--* CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult N001 ( 3, 2) [000068] ------------ | /--* LCL_VAR ref V05 tmp3 N003 ( 7, 5) [000135] -A------R-L- this SETUP +--* ASG ref N002 ( 3, 2) [000134] D------N---- | \--* LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- | /--* LCL_VAR simd16 V04 tmp2 N006 ( 7, 5) [000131] -A------R-L- arg1 SETUP +--* ASG simd16 (copy) N005 ( 3, 2) [000130] D------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ this in rcx +--* LCL_VAR ref V08 tmp6 N014 ( 3, 3) [000139] L----------- arg1 in rdx +--* ADDR byref N013 ( 3, 2) [000138] -------N---- | \--* LCL_VAR simd16(AX) V07 tmp5 N016 ( 5, 12) [000133] x---G------- arg3 in r9 +--* IND ref N015 ( 3, 10) [000132] ------------ | \--* CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" N017 ( 3, 2) [000072] ------------ arg2 in r8 \--* LCL_VAR long V06 tmp4 ***** BB05, stmt 20 ( 1, 1) [000082] ------------ * STMT void (IL 0x05B... ???) N001 ( 1, 1) [000081] ------------ \--* NO_OP void ***** BB05, stmt 21 ( 0, 0) [000084] ------------ * STMT void (IL 0x05C...0x05C) N001 ( 0, 0) [000083] ------------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N011 ( 27, 17) [000035] DACXG------- * STORE_LCL_VAR long V03 tmp1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N011 ( 27, 17) [000070] DACXG------- * STORE_LCL_VAR long V06 tmp4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 *************** Exiting IR Rationalize Trees after IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] x----------- t86 = * IND int N003 ( 1, 1) [000087] ------------ t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- t88 = * EQ int /--* t88 int N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref N003 ( 1, 1) [000012] ------------ t12 = CNS_INT long 8 Fseq[#FirstElem] /--* t11 ref +--* t12 long N004 ( 7, 14) [000013] ----G------- t13 = * ADD byref /--* t13 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] ------------ t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] ------------ t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t37 long arg0 in rcx +--* t38 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref N003 ( 1, 1) [000053] ------------ t53 = CNS_INT long 8 Fseq[#FirstElem] /--* t52 ref +--* t53 long N004 ( 7, 14) [000054] ----G------- t54 = * ADD byref /--* t54 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] ------------ t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t136 ref this in rcx +--* t138 byref arg1 in rdx +--* t133 ref arg3 in r9 +--* t72 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Bumping outgoingArgSpaceSize to 32 for call [000089] outgoingArgSpaceSize 32 sufficient for call [000006], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000025], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000033], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000039], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000046], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000059], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000074], which needs 32 *************** In fgDebugCheckBBlist *************** In Lowering Trees before Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] x----------- t86 = * IND int N003 ( 1, 1) [000087] ------------ t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- t88 = * EQ int /--* t88 int N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref N003 ( 1, 1) [000012] ------------ t12 = CNS_INT long 8 Fseq[#FirstElem] /--* t11 ref +--* t12 long N004 ( 7, 14) [000013] ----G------- t13 = * ADD byref /--* t13 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] ------------ t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] ------------ t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t37 long arg0 in rcx +--* t38 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref N003 ( 1, 1) [000053] ------------ t53 = CNS_INT long 8 Fseq[#FirstElem] /--* t52 ref +--* t53 long N004 ( 7, 14) [000054] ----G------- t54 = * ADD byref /--* t54 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] ------------ t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t136 ref this in rcx +--* t138 byref arg1 in rdx +--* t133 ref arg3 in r9 +--* t72 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- No addressing mode: N001 ( 3, 10) [000085] ------------ * CNS_INT(h) long 0x7ff826874428 token lowering call (before): N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE No addressing mode: N003 ( 3, 10) [000094] ------------ * CNS_INT(h) long 0x99BB9538 "ClsVarScenario" lowering call (before): N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000096] ----------L- * ARGPLACE ref late: ====== lowering arg : N004 ( 5, 12) [000095] x---G------- * IND ref new node is : [000148] ----G------- * PUTARG_REG ref REG rcx lowering call (after): N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine No addressing mode: N001 ( 3, 10) [000098] ------------ * CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] Addressing mode: Base N002 ( 5, 12) [000011] x---G------- * IND ref + 8 New addressing mode node: [000149] ------------ * LEA(b+8) byref No addressing mode: N003 ( 3, 10) [000099] ------------ * CNS_INT(h) long 0x99BB9538 "ClsVarScenario" lowering call (before): N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000101] ----------L- * ARGPLACE ref late: ====== lowering arg : N004 ( 5, 12) [000100] x---G------- * IND ref new node is : [000150] ----G------- * PUTARG_REG ref REG rcx lowering call (after): N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine lowering call (before): N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr objp: ====== lowering arg : N001 ( 0, 0) [000110] ----------L- * ARGPLACE byref args: ====== late: ====== lowering arg : N006 ( 5, 4) [000107] ------------ * ADD byref new node is : [000151] ------------ * PUTARG_REG byref REG rcx lowering call (after): N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr lowering call (before): N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t37 long arg0 in rcx +--* t38 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000112] ----------L- * ARGPLACE long lowering arg : N002 ( 0, 0) [000114] ----------L- * ARGPLACE float late: ====== lowering arg : N005 ( 3, 2) [000037] ------------ * LCL_VAR long V03 tmp1 new node is : [000152] ------------ * PUTARG_REG long REG rcx lowering arg : N006 ( 3, 4) [000038] ------------ * LCL_VAR float V01 loc0 new node is : [000153] ------------ * PUTARG_REG float REG mm1 lowering call (after): N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 /--* t37 long [000152] ------------ t152 = * PUTARG_REG long REG rcx N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t38 float [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write No addressing mode: N003 ( 3, 10) [000116] ------------ * CNS_INT(h) long 0x99BB9538 "ClsVarScenario" lowering call (before): N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000118] ----------L- * ARGPLACE ref late: ====== lowering arg : N004 ( 5, 12) [000117] x---G------- * IND ref new node is : [000154] ----G------- * PUTARG_REG ref REG rcx lowering call (after): N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine No addressing mode: N001 ( 3, 10) [000120] ------------ * CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] Addressing mode: Base N002 ( 5, 12) [000052] x---G------- * IND ref + 8 New addressing mode node: [000155] ------------ * LEA(b+8) byref lowering call (before): N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr objp: ====== lowering arg : N001 ( 0, 0) [000128] ----------L- * ARGPLACE byref args: ====== late: ====== lowering arg : N006 ( 5, 4) [000125] ------------ * ADD byref new node is : [000156] ------------ * PUTARG_REG byref REG rcx lowering call (after): N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr No addressing mode: N015 ( 3, 10) [000132] ------------ * CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" lowering call (before): N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t136 ref this in rcx +--* t138 byref arg1 in rdx +--* t133 ref arg3 in r9 +--* t72 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult objp: ====== lowering arg : N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 args: ====== lowering arg : N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 lowering arg : N007 ( 0, 0) [000143] ----------L- * ARGPLACE long lowering arg : N008 ( 0, 0) [000141] ----------L- * ARGPLACE ref late: ====== lowering arg : N012 ( 3, 2) [000136] ------------ * LCL_VAR ref V08 tmp6 new node is : [000157] ------------ * PUTARG_REG ref REG rcx lowering arg : N013 ( 3, 2) [000138] -------N---- * LCL_VAR_ADDR byref V07 tmp5 new node is : [000158] ------------ * PUTARG_REG byref REG rdx lowering arg : N016 ( 5, 12) [000133] x---G------- * IND ref new node is : [000159] ----G------- * PUTARG_REG ref REG r9 lowering arg : N017 ( 3, 2) [000072] ------------ * LCL_VAR long V06 tmp4 new node is : [000160] ------------ * PUTARG_REG long REG r8 lowering call (after): N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 /--* t136 ref [000157] ------------ t157 = * PUTARG_REG ref REG rcx N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 /--* t138 byref [000158] ------------ t158 = * PUTARG_REG byref REG rdx N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref /--* t133 ref [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t72 long [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult lowering GT_RETURN N001 ( 0, 0) [000083] ------------ * RETURN void ============Lower has completed modifying nodes. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] xc---------- t86 = * IND int N003 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- * EQ void N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref /--* t11 ref [000149] -c---------- t149 = * LEA(b+8) byref /--* t149 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 /--* t37 long [000152] ------------ t152 = * PUTARG_REG long REG rcx N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t38 float [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref /--* t52 ref [000155] -c---------- t155 = * LEA(b+8) byref /--* t155 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 /--* t136 ref [000157] ------------ t157 = * PUTARG_REG ref REG rcx N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 /--* t138 byref [000158] ------------ t158 = * PUTARG_REG byref REG rdx N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref /--* t133 ref [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t72 long [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this ref do-not-enreg[] this class-hnd ; V01 loc0 float do-not-enreg[] ; V02 tmp0 float do-not-enreg[] ; V03 tmp1 long do-not-enreg[] ; V04 tmp2 simd16 do-not-enreg[SB] ; V05 tmp3 ref do-not-enreg[] class-hnd ; V06 tmp4 long do-not-enreg[] ; V07 tmp5 simd16 do-not-enreg[XSB] addr-exposed ; V08 tmp6 ref do-not-enreg[] ; V09 OutArgs lclBlk (32) do-not-enreg[] *************** In fgPerBlockLocalVarLiveness() *************** In fgInterBlockLocalVarLiveness() *************** In fgExtendDbgLifetimes() Marking vars alive over their entire scope : Local variable scopes = 2 VarNum LVNum Name Beg End Sorted by enter scope: 0: 01h 01h V01 loc0 000h 05Dh <-- next enter scope 1: 00h 00h V00 this 000h 05Dh Sorted by exit scope: 0: 01h 01h V01 loc0 000h 05Dh <-- next exit scope 1: 00h 00h V00 this 000h 05Dh Scope info: block BB01 marking in scope: {} Scope info: block BB02 marking in scope: {} Scope info: block BB03 marking in scope: {} Scope info: block BB04 marking in scope: {} Scope info: block BB05 marking in scope: {V01} Debug scopes: BB01: {} BB02: {} BB03: {} BB04: {} BB05: {V01} Scope info: block BB01 UNmarking in scope: {} BB liveness after fgExtendDbgLifetimes(): BB01 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap BB02 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap BB03 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap BB04 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap BB05 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(1)={ V01} + ByrefExposed + GcHeap Liveness pass finished after lowering, IR: lvasortagain = 0 -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] xc---------- t86 = * IND int N003 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- * EQ void N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref /--* t11 ref [000149] -c---------- t149 = * LEA(b+8) byref /--* t149 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 /--* t37 long [000152] ------------ t152 = * PUTARG_REG long REG rcx N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t38 float [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref /--* t52 ref [000155] -c---------- t155 = * LEA(b+8) byref /--* t155 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 /--* t136 ref [000157] ------------ t157 = * PUTARG_REG ref REG rcx N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 /--* t138 byref [000158] ------------ t158 = * PUTARG_REG byref REG rdx N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref /--* t133 ref [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t72 long [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Exiting Lowering Trees after Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] xc---------- t86 = * IND int N003 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- * EQ void N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref /--* t11 ref [000149] -c---------- t149 = * LEA(b+8) byref /--* t149 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 /--* t37 long [000152] ------------ t152 = * PUTARG_REG long REG rcx N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t38 float [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref /--* t52 ref [000155] -c---------- t155 = * LEA(b+8) byref /--* t155 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 /--* t136 ref [000157] ------------ t157 = * PUTARG_REG ref REG rcx N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 /--* t138 byref [000158] ------------ t158 = * PUTARG_REG byref REG rdx N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref /--* t133 ref [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t72 long [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In StackLevelSetter Trees before StackLevelSetter -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] xc---------- t86 = * IND int N003 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- * EQ void N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref /--* t11 ref [000149] -c---------- t149 = * LEA(b+8) byref /--* t149 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 /--* t37 long [000152] ------------ t152 = * PUTARG_REG long REG rcx N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t38 float [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref /--* t52 ref [000155] -c---------- t155 = * LEA(b+8) byref /--* t155 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 /--* t136 ref [000157] ------------ t157 = * PUTARG_REG ref REG rcx N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 /--* t138 byref [000158] ------------ t158 = * PUTARG_REG byref REG rdx N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref /--* t133 ref [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t72 long [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Exiting StackLevelSetter Trees after StackLevelSetter -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 0, 0) [000000] ------------ NOP void ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token /--* t85 long N002 ( 5, 12) [000086] xc---------- t86 = * IND int N003 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 /--* t86 int +--* t87 int N004 ( 7, 14) [000088] J------N---- * EQ void N005 ( 9, 16) [000145] ------------ * JTRUE void ------------ BB03 [???..???), preds={BB02} succs={BB04} N001 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000003] ------------ NO_OP void ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t94 long N004 ( 5, 12) [000095] x---G------- t95 = * IND ref /--* t95 ref [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N006 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb N001 ( 1, 1) [000009] ------------ NO_OP void ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t98 long N002 ( 5, 12) [000011] x---G------- t11 = * IND ref /--* t11 ref [000149] -c---------- t149 = * LEA(b+8) byref /--* t149 byref N005 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 N006 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 /--* t14 simd16 +--* t15 int N007 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract /--* t16 float N009 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 N001 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 /--* t20 float N003 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 N003 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t99 long N004 ( 5, 12) [000100] x---G------- t100 = * IND ref /--* t100 ref [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N006 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 N001 ( 1, 1) [000028] ------------ NO_OP void ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this /--* t103 ref N003 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this N005 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t105 ref +--* t106 long N006 ( 5, 4) [000107] ------------ t107 = * ADD byref /--* t107 byref [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N009 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N011 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e N005 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 /--* t37 long [000152] ------------ t152 = * PUTARG_REG long REG rcx N006 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 /--* t38 float [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N009 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 N001 ( 1, 1) [000043] ------------ NO_OP void ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 N003 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" /--* t116 long N004 ( 5, 12) [000117] x---G------- t117 = * IND ref /--* t117 ref [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N006 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000049] ------------ NO_OP void ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 N001 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] /--* t120 long N002 ( 5, 12) [000052] x---G------- t52 = * IND ref /--* t52 ref [000155] -c---------- t155 = * LEA(b+8) byref /--* t155 byref N005 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 /--* t55 simd16 N007 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 N001 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this /--* t51 ref N003 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 N002 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this /--* t121 ref N003 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte N004 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this N005 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] /--* t123 ref +--* t124 long N006 ( 5, 4) [000125] ------------ t125 = * ADD byref /--* t125 byref [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N009 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N011 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 N001 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 /--* t68 ref N003 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 N004 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 /--* t64 simd16 N006 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 N012 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 /--* t136 ref [000157] ------------ t157 = * PUTARG_REG ref REG rcx N013 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 /--* t138 byref [000158] ------------ t158 = * PUTARG_REG byref REG rdx N015 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" /--* t132 long N016 ( 5, 12) [000133] x---G------- t133 = * IND ref /--* t133 ref [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N017 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 /--* t72 long [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N022 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 1, 1) [000081] ------------ NO_OP void ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 0, 0) [000083] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} BB02 use def in out {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} BB03 use def in out {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} BB04 use def in out {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} BB05 use def in out {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01 V02 V03 V04 V06} {V01} FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 Removing register rbp from LSRA register masks After removing register: LSRA register masks. Total allocated: 64, total used: 35 0: [rax rcx rdx rbx rsi rdi r8-r15] 1: [mm0-mm15] 2: [rax] 3: [rcx] 4: [rdx] 5: [rbx] 6: [rsp] 7: [] 8: [rsi] 9: [rdi] 10: [r8] 11: [r9] 12: [r10] 13: [r11] 14: [r12] 15: [r13] 16: [r14] 17: [r15] 18: [mm0] 19: [mm1] 20: [mm2] 21: [mm3] 22: [mm4] 23: [mm5] 24: [mm6] 25: [mm7] 26: [mm8] 27: [mm9] 28: [mm10] 29: [mm11] 30: [mm12] 31: [mm13] 32: [mm14] 33: [mm15] 34: [] TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 0.50) BB04( 1 ) BB05( 1 ) BB01 [???..???), preds={} succs={BB02} ===== N001. NOP BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N001. CNS_INT(h) 0x7ff826874428 token N002. IND N003. CNS_INT 0 N004. EQ N005. JTRUE BB03 [???..???), preds={BB02} succs={BB04} ===== N001. CALL help BB04 [???..???), preds={BB02,BB03} succs={BB05} ===== BB05 [000..05D) (return), preds={BB04} succs={} ===== N000. IL_OFFSET IL offset: 0x0 N001. NO_OP N000. IL_OFFSET IL offset: 0x1 N003. t94 = CNS_INT(h) 0x99BB9538 "ClsVarScenario" N004. t95 = IND ; t94 N000. t148 = PUTARG_REG; t95 N006. CALL ; t148 N000. IL_OFFSET IL offset: 0xb N001. NO_OP N000. IL_OFFSET IL offset: 0xc N001. t98* = CNS_INT(h) 0x1c599bb5f78 static Fseq[_clsVar] N002. t11 = IND ; t98* N000. t149 = LEA(b+8) ; t11 N005. t14 = IND ; t149 N006. CNS_INT 1 N007. t16 = HWIntrinsic; t14 N009. V02 MEM; t16 N000. IL_OFFSET IL offset: 0x17 N001. t20 = V02 MEM N003. V01 MEM; t20 N000. IL_OFFSET IL offset: 0x18 N003. t99 = CNS_INT(h) 0x99BB9538 "ClsVarScenario" N004. t100 = IND ; t99 N000. t150 = PUTARG_REG; t100 N006. CALL ; t150 N000. IL_OFFSET IL offset: 0x22 N001. NO_OP N000. IL_OFFSET IL offset: 0x23 N002. t103 = V00 MEM N003. NULLCHECK; t103 N004. t105 = V00 MEM N005. CNS_INT 32 field offset Fseq[_dataTable] N006. t107 = ADD ; t105 N000. t151 = PUTARG_REG; t107 N009. t33 = CALL ; t151 N011. V03 MEM; t33 N000. IL_OFFSET IL offset: 0x2e N005. t37 = V03 MEM N000. t152 = PUTARG_REG; t37 N006. t38 = V01 MEM N000. t153 = PUTARG_REG; t38 N009. CALL ; t152,t153 N000. IL_OFFSET IL offset: 0x34 N001. NO_OP N000. IL_OFFSET IL offset: 0x35 N003. t116 = CNS_INT(h) 0x99BB9538 "ClsVarScenario" N004. t117 = IND ; t116 N000. t154 = PUTARG_REG; t117 N006. CALL ; t154 N000. IL_OFFSET IL offset: 0x3f N001. NO_OP N000. IL_OFFSET IL offset: 0x40 N001. t120* = CNS_INT(h) 0x1c599bb5f78 static Fseq[_clsVar] N002. t52 = IND ; t120* N000. t155 = LEA(b+8) ; t52 N005. t55 = IND ; t155 N007. V04 MEM; t55 N001. t51 = V00 MEM N003. V05 MEM; t51 N002. t121 = V00 MEM N003. NULLCHECK; t121 N004. t123 = V00 MEM N005. CNS_INT 32 field offset Fseq[_dataTable] N006. t125 = ADD ; t123 N000. t156 = PUTARG_REG; t125 N009. t59 = CALL ; t156 N011. V06 MEM; t59 N000. IL_OFFSET IL offset: 0x51 N001. t68 = V05 MEM N003. V08 MEM; t68 N004. t64 = V04 MEM N006. V07 MEM; t64 N012. t136 = V08 MEM N000. t157 = PUTARG_REG; t136 N013. t138 = LCL_VAR_ADDR V07 tmp5 N000. t158 = PUTARG_REG; t138 N015. t132 = CNS_INT(h) 0x99BB9540 "RunClsVarScenario" N016. t133 = IND ; t132 N000. t159 = PUTARG_REG; t133 N017. t72 = V06 MEM N000. t160 = PUTARG_REG; t72 N022. CALL ; t157,t158,t159,t160 N000. IL_OFFSET IL offset: 0x5b N001. NO_OP N000. IL_OFFSET IL offset: 0x5c N001. RETURN buildIntervals second part ======== Int arg V00 in reg rcx NEW BLOCK BB01 DefList: { } N002 ( 0, 0) [000000] ------------ * NOP void REG NA +[--] consume=0 produce=0 NEW BLOCK BB02 Setting BB02 as the predecessor for determining incoming variable registers of BB01 DefList: { } N006 ( 3, 10) [000085] -c---------- * CNS_INT(h) long 0x7ff826874428 token REG NA Contained DefList: { } N008 ( 5, 12) [000086] xc---------- * IND int REG NA Contained DefList: { } N010 ( 1, 1) [000087] -c---------- * CNS_INT int 0 REG NA Contained DefList: { } N012 ( 7, 14) [000088] J------N---- * EQ void REG NA +[--] consume=0 produce=0 DefList: { } N014 ( 9, 16) [000145] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 NEW BLOCK BB03 Setting BB03 as the predecessor for determining incoming variable registers of BB02 DefList: { } N018 ( 14, 5) [000089] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE +[--] consume=0 produce=0 BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> BB03 regmask=[mm0] minReg=1> BB03 regmask=[mm1] minReg=1> BB03 regmask=[mm2] minReg=1> BB03 regmask=[mm3] minReg=1> BB03 regmask=[mm4] minReg=1> BB03 regmask=[mm5] minReg=1> NEW BLOCK BB04 Setting BB04 as the predecessor for determining incoming variable registers of BB02 NEW BLOCK BB05 Setting BB05 as the predecessor for determining incoming variable registers of BB04 DefList: { } N024 ( 1, 1) [000004] ------------ * IL_OFFSET void IL offset: 0x0 REG NA +[--] consume=0 produce=0 DefList: { } N026 ( 1, 1) [000003] ------------ * NO_OP void REG NA +[--] consume=0 produce=0 DefList: { } N028 ( 19, 18) [000008] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N030 ( 3, 10) [000094] ------------ * CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 0: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB05 regmask=[allIntButFP] minReg=1> DefList: { N030.t94. CNS_INT } N032 ( 5, 12) [000095] x---G------- * IND ref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 1: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N032.t95. IND } N034 (???,???) [000148] ----G------- * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 2: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N034.t148. PUTARG_REG } N036 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine +[--] consume=1 produce=0 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> DefList: { } N038 ( 1, 1) [000010] ------------ * IL_OFFSET void IL offset: 0xb REG NA +[--] consume=0 produce=0 DefList: { } N040 ( 1, 1) [000009] ------------ * NO_OP void REG NA +[--] consume=0 produce=0 DefList: { } N042 ( 19, 25) [000019] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N044 ( 3, 10) [000098] ------------ * CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 3: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB05 regmask=[allIntButFP] minReg=1> DefList: { N044.t98. CNS_INT } N046 ( 5, 12) [000011] x---G------- * IND ref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 4: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N046.t11. IND } N048 (???,???) [000149] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N046.t11. IND } N050 ( 13, 18) [000014] ---XG------- * IND simd16 REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 5: RefPositions {} physReg:NA Preferences=[allFloat] IND BB05 regmask=[allFloat] minReg=1> DefList: { N050.t14. IND } N052 ( 1, 1) [000015] -c---------- * CNS_INT int 1 REG NA Contained DefList: { N050.t14. IND } N054 ( 15, 20) [000016] ---XG------- * HWIntrinsic float float Extract REG NA +[--] consume=1 produce=1 Interval 6: RefPositions {} physReg:NA Preferences=[allIntButFP] HWIntrinsic BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allFloat] minReg=1 last> HWIntrinsic BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 7: RefPositions {} physReg:NA Preferences=[allFloat] HWIntrinsic BB05 regmask=[allFloat] minReg=1> DefList: { N054.t16. HWIntrinsic } N056 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allFloat] minReg=1 last> DefList: { } N058 ( 7, 9) [000023] ------------ * IL_OFFSET void IL offset: 0x17 REG NA +[--] consume=0 produce=0 DefList: { } N060 ( 3, 4) [000020] ------------ * LCL_VAR float V02 tmp0 NA REG NA +[--] consume=0 produce=1 Def candidates [allFloat], Use candidates [allFloat] Interval 8: RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB05 regmask=[allFloat] minReg=1> DefList: { N060.t20. LCL_VAR } N062 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allFloat] minReg=1 last> DefList: { } N064 ( 19, 18) [000027] ------------ * IL_OFFSET void IL offset: 0x18 REG NA +[--] consume=0 produce=0 DefList: { } N066 ( 3, 10) [000099] ------------ * CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 9: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB05 regmask=[allIntButFP] minReg=1> DefList: { N066.t99. CNS_INT } N068 ( 5, 12) [000100] x---G------- * IND ref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 10: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N068.t100. IND } N070 (???,???) [000150] ----G------- * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 11: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N070.t150. PUTARG_REG } N072 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine +[--] consume=1 produce=0 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> DefList: { } N074 ( 1, 1) [000029] ------------ * IL_OFFSET void IL offset: 0x22 REG NA +[--] consume=0 produce=0 DefList: { } N076 ( 1, 1) [000028] ------------ * NO_OP void REG NA +[--] consume=0 produce=0 DefList: { } N078 ( 27, 17) [000036] ------------ * IL_OFFSET void IL offset: 0x23 REG NA +[--] consume=0 produce=0 DefList: { } N080 ( 3, 2) [000103] ------------ * LCL_VAR ref V00 this NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 12: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N080.t103. LCL_VAR } N082 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte REG NA +[--] consume=1 produce=0 BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N084 ( 3, 2) [000105] ------------ * LCL_VAR ref V00 this NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 13: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N084.t105. LCL_VAR } N086 ( 1, 1) [000106] -c---------- * CNS_INT long 32 field offset Fseq[_dataTable] REG NA Contained DefList: { N084.t105. LCL_VAR } N088 ( 5, 4) [000107] ------------ * ADD byref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 14: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to ADD BB05 regmask=[allIntButFP] minReg=1> DefList: { N088.t107. ADD } N090 (???,???) [000151] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 15: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N090.t151. PUTARG_REG } N092 ( 23, 14) [000033] --CXG------- * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> Interval 16: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rax] minReg=1> CALL BB05 regmask=[rax] minReg=1 fixed> DefList: { N092.t33. CALL } N094 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N096 ( 20, 13) [000042] ------------ * IL_OFFSET void IL offset: 0x2e REG NA +[--] consume=0 produce=0 DefList: { } N098 ( 3, 2) [000037] ------------ * LCL_VAR long V03 tmp1 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 17: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N098.t37. LCL_VAR } N100 (???,???) [000152] ------------ * PUTARG_REG long REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 18: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N100.t152. PUTARG_REG } N102 ( 3, 4) [000038] ------------ * LCL_VAR float V01 loc0 NA REG NA +[--] consume=0 produce=1 Def candidates [allFloat], Use candidates [allFloat] Interval 19: RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB05 regmask=[allFloat] minReg=1> DefList: { N100.t152. PUTARG_REG; N102.t38. LCL_VAR } N104 (???,???) [000153] ------------ * PUTARG_REG float REG mm1 +[--] consume=1 produce=1 BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> Def candidates [mm1], Use candidates [mm1] Interval 20: RefPositions {} physReg:NA Preferences=[allFloat] BB05 regmask=[mm1] minReg=1> PUTARG_REG BB05 regmask=[mm1] minReg=1 fixed> DefList: { N100.t152. PUTARG_REG; N104.t153. PUTARG_REG } N106 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write +[--] consume=2 produce=0 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> DefList: { } N108 ( 1, 1) [000044] ------------ * IL_OFFSET void IL offset: 0x34 REG NA +[--] consume=0 produce=0 DefList: { } N110 ( 1, 1) [000043] ------------ * NO_OP void REG NA +[--] consume=0 produce=0 DefList: { } N112 ( 19, 18) [000048] ------------ * IL_OFFSET void IL offset: 0x35 REG NA +[--] consume=0 produce=0 DefList: { } N114 ( 3, 10) [000116] ------------ * CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 21: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB05 regmask=[allIntButFP] minReg=1> DefList: { N114.t116. CNS_INT } N116 ( 5, 12) [000117] x---G------- * IND ref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 22: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N116.t117. IND } N118 (???,???) [000154] ----G------- * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 23: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N118.t154. PUTARG_REG } N120 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine +[--] consume=1 produce=0 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> DefList: { } N122 ( 1, 1) [000050] ------------ * IL_OFFSET void IL offset: 0x3f REG NA +[--] consume=0 produce=0 DefList: { } N124 ( 1, 1) [000049] ------------ * NO_OP void REG NA +[--] consume=0 produce=0 DefList: { } N126 ( 14, 19) [000063] ------------ * IL_OFFSET void IL offset: 0x40 REG NA +[--] consume=0 produce=0 DefList: { } N128 ( 3, 10) [000120] ------------ * CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 24: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB05 regmask=[allIntButFP] minReg=1> DefList: { N128.t120. CNS_INT } N130 ( 5, 12) [000052] x---G------- * IND ref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 25: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N130.t52. IND } N132 (???,???) [000155] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N130.t52. IND } N134 ( 10, 16) [000055] ---XG------- * IND simd16 REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 26: RefPositions {} physReg:NA Preferences=[allFloat] IND BB05 regmask=[allFloat] minReg=1> DefList: { N134.t55. IND } N136 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allFloat] minReg=1 last> DefList: { } N138 ( 3, 2) [000051] ------------ * LCL_VAR ref V00 this NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 27: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N138.t51. LCL_VAR } N140 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N142 ( 3, 2) [000121] ------------ * LCL_VAR ref V00 this NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 28: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N142.t121. LCL_VAR } N144 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte REG NA +[--] consume=1 produce=0 BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N146 ( 3, 2) [000123] ------------ * LCL_VAR ref V00 this NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 29: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N146.t123. LCL_VAR } N148 ( 1, 1) [000124] -c---------- * CNS_INT long 32 field offset Fseq[_dataTable] REG NA Contained DefList: { N146.t123. LCL_VAR } N150 ( 5, 4) [000125] ------------ * ADD byref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 30: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to ADD BB05 regmask=[allIntButFP] minReg=1> DefList: { N150.t125. ADD } N152 (???,???) [000156] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 31: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N152.t156. PUTARG_REG } N154 ( 23, 14) [000059] --CXG------- * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> Interval 32: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rax] minReg=1> CALL BB05 regmask=[rax] minReg=1 fixed> DefList: { N154.t59. CALL } N156 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N158 ( 45, 39) [000080] ------------ * IL_OFFSET void IL offset: 0x51 REG NA +[--] consume=0 produce=0 DefList: { } N160 ( 3, 2) [000068] ------------ * LCL_VAR ref V05 tmp3 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 33: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N160.t68. LCL_VAR } N162 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N164 ( 3, 2) [000064] -------N---- * LCL_VAR simd16 V04 tmp2 NA REG NA +[--] consume=0 produce=1 Def candidates [allFloat], Use candidates [allFloat] Interval 34: RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB05 regmask=[allFloat] minReg=1> DefList: { N164.t64. LCL_VAR } N166 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 NA REG NA +[--] consume=1 produce=0 BB05 regmask=[allFloat] minReg=1 last> DefList: { } N168 ( 3, 2) [000136] ------------ * LCL_VAR ref V08 tmp6 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 35: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N168.t136. LCL_VAR } N170 (???,???) [000157] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 36: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> DefList: { N170.t157. PUTARG_REG } N172 ( 3, 2) [000138] -------N---- * LCL_VAR_ADDR byref V07 tmp5 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 37: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR_ADDR BB05 regmask=[allIntButFP] minReg=1> DefList: { N170.t157. PUTARG_REG; N172.t138. LCL_VAR_ADDR } N174 (???,???) [000158] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 38: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[rdx] minReg=1> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> DefList: { N170.t157. PUTARG_REG; N174.t158. PUTARG_REG } N176 ( 3, 10) [000132] ------------ * CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 39: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB05 regmask=[allIntButFP] minReg=1> DefList: { N170.t157. PUTARG_REG; N174.t158. PUTARG_REG; N176.t132. CNS_INT } N178 ( 5, 12) [000133] x---G------- * IND ref REG NA +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 40: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N170.t157. PUTARG_REG; N174.t158. PUTARG_REG; N178.t133. IND } N180 (???,???) [000159] ----G------- * PUTARG_REG ref REG r9 +[--] consume=1 produce=1 BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> Def candidates [r9], Use candidates [r9] Interval 41: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[r9] minReg=1> PUTARG_REG BB05 regmask=[r9] minReg=1 fixed> DefList: { N170.t157. PUTARG_REG; N174.t158. PUTARG_REG; N180.t159. PUTARG_REG } N182 ( 3, 2) [000072] ------------ * LCL_VAR long V06 tmp4 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 42: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N170.t157. PUTARG_REG; N174.t158. PUTARG_REG; N180.t159. PUTARG_REG; N182.t72. LCL_VAR } N184 (???,???) [000160] ------------ * PUTARG_REG long REG r8 +[--] consume=1 produce=1 BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> Def candidates [r8], Use candidates [r8] Interval 43: RefPositions {} physReg:NA Preferences=[allIntButFP] BB05 regmask=[r8] minReg=1> PUTARG_REG BB05 regmask=[r8] minReg=1 fixed> DefList: { N170.t157. PUTARG_REG; N174.t158. PUTARG_REG; N180.t159. PUTARG_REG; N184.t160. PUTARG_REG } N186 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult +[--] consume=4 produce=0 BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm2] minReg=1> BB05 regmask=[mm3] minReg=1> BB05 regmask=[mm4] minReg=1> BB05 regmask=[mm5] minReg=1> DefList: { } N188 ( 1, 1) [000082] ------------ * IL_OFFSET void IL offset: 0x5b REG NA +[--] consume=0 produce=0 DefList: { } N190 ( 1, 1) [000081] ------------ * NO_OP void REG NA +[--] consume=0 produce=0 DefList: { } N192 ( 0, 0) [000084] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N194 ( 0, 0) [000083] ------------ * RETURN void REG NA +[--] consume=0 produce=0 Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (constant) RefPositions {#18@31 #19@32} physReg:NA Preferences=[allIntButFP] Interval 1: RefPositions {#20@33 #22@34} physReg:NA Preferences=[rcx] Interval 2: RefPositions {#24@35 #26@36} physReg:NA Preferences=[rcx] Interval 3: (constant) RefPositions {#40@45 #41@46} physReg:NA Preferences=[allIntButFP] Interval 4: RefPositions {#42@47 #43@50} physReg:NA Preferences=[allIntButFP] Interval 5: RefPositions {#44@51 #46@54} physReg:NA Preferences=[allFloat] Interval 6: (INTERNAL) RefPositions {#45@54 #47@54} physReg:NA Preferences=[allIntButFP] Interval 7: RefPositions {#48@55 #49@56} physReg:NA Preferences=[allFloat] Interval 8: RefPositions {#50@61 #51@62} physReg:NA Preferences=[allFloat] Interval 9: (constant) RefPositions {#52@67 #53@68} physReg:NA Preferences=[allIntButFP] Interval 10: RefPositions {#54@69 #56@70} physReg:NA Preferences=[rcx] Interval 11: RefPositions {#58@71 #60@72} physReg:NA Preferences=[rcx] Interval 12: RefPositions {#74@81 #75@82} physReg:NA Preferences=[allIntButFP] Interval 13: RefPositions {#76@85 #77@88} physReg:NA Preferences=[allIntButFP] Interval 14: RefPositions {#78@89 #80@90} physReg:NA Preferences=[rcx] RelatedInterval [000001C5A1EB9720] Interval 15: RefPositions {#82@91 #84@92} physReg:NA Preferences=[rcx] Interval 16: RefPositions {#99@93 #100@94} physReg:NA Preferences=[rax] Interval 17: RefPositions {#101@99 #103@100} physReg:NA Preferences=[rcx] Interval 18: RefPositions {#105@101 #112@106} physReg:NA Preferences=[rcx] Interval 19: RefPositions {#106@103 #108@104} physReg:NA Preferences=[mm1] Interval 20: RefPositions {#110@105 #114@106} physReg:NA Preferences=[mm1] Interval 21: (constant) RefPositions {#128@115 #129@116} physReg:NA Preferences=[allIntButFP] Interval 22: RefPositions {#130@117 #132@118} physReg:NA Preferences=[rcx] Interval 23: RefPositions {#134@119 #136@120} physReg:NA Preferences=[rcx] Interval 24: (constant) RefPositions {#150@129 #151@130} physReg:NA Preferences=[allIntButFP] Interval 25: RefPositions {#152@131 #153@134} physReg:NA Preferences=[allIntButFP] Interval 26: RefPositions {#154@135 #155@136} physReg:NA Preferences=[allFloat] Interval 27: RefPositions {#156@139 #157@140} physReg:NA Preferences=[allIntButFP] Interval 28: RefPositions {#158@143 #159@144} physReg:NA Preferences=[allIntButFP] Interval 29: RefPositions {#160@147 #161@150} physReg:NA Preferences=[allIntButFP] Interval 30: RefPositions {#162@151 #164@152} physReg:NA Preferences=[rcx] RelatedInterval [000001C5A1EBB960] Interval 31: RefPositions {#166@153 #168@154} physReg:NA Preferences=[rcx] Interval 32: RefPositions {#183@155 #184@156} physReg:NA Preferences=[rax] Interval 33: RefPositions {#185@161 #186@162} physReg:NA Preferences=[allIntButFP] Interval 34: RefPositions {#187@165 #188@166} physReg:NA Preferences=[allFloat] Interval 35: RefPositions {#189@169 #191@170} physReg:NA Preferences=[rcx] Interval 36: RefPositions {#193@171 #212@186} physReg:NA Preferences=[rcx] Interval 37: RefPositions {#194@173 #196@174} physReg:NA Preferences=[rdx] Interval 38: RefPositions {#198@175 #214@186} physReg:NA Preferences=[rdx] Interval 39: (constant) RefPositions {#199@177 #200@178} physReg:NA Preferences=[allIntButFP] Interval 40: RefPositions {#201@179 #203@180} physReg:NA Preferences=[r9] Interval 41: RefPositions {#205@181 #216@186} physReg:NA Preferences=[r9] Interval 42: RefPositions {#206@183 #208@184} physReg:NA Preferences=[r8] Interval 43: RefPositions {#210@185 #218@186} physReg:NA Preferences=[r8] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ #27 RefTypeKill BB03 regmask=[rax] minReg=1 last> #21 RefTypeKill BB03 regmask=[rcx] minReg=1 last> #29 RefTypeKill BB03 regmask=[rdx] minReg=1 last> #30 RefTypeKill BB03 regmask=[r8] minReg=1 last> #31 RefTypeKill BB03 regmask=[r9] minReg=1 last> #32 RefTypeKill BB03 regmask=[r10] minReg=1 last> #33 RefTypeKill BB03 regmask=[r11] minReg=1 last> #34 RefTypeKill BB03 regmask=[mm0] minReg=1 last> #35 RefTypeKill BB03 regmask=[mm1] minReg=1 last> #36 RefTypeKill BB03 regmask=[mm2] minReg=1 last> #37 RefTypeKill BB03 regmask=[mm3] minReg=1 last> #38 RefTypeKill BB03 regmask=[mm4] minReg=1 last> #39 RefTypeKill BB03 regmask=[mm5] minReg=1 last> #19 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #22 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #23 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #25 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #26 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #28 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #61 RefTypeKill BB05 regmask=[rax] minReg=1 last> #55 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #63 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #64 RefTypeKill BB05 regmask=[r8] minReg=1 last> #65 RefTypeKill BB05 regmask=[r9] minReg=1 last> #66 RefTypeKill BB05 regmask=[r10] minReg=1 last> #67 RefTypeKill BB05 regmask=[r11] minReg=1 last> #68 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #69 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #70 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #71 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #72 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #73 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #41 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #43 RefTypeDef IND BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #46 RefTypeDef IND BB05 regmask=[allFloat] minReg=1> #47 RefTypeDef HWIntrinsic BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allFloat] minReg=1 last> HWIntrinsic BB05 regmask=[allIntButFP] minReg=1 last> #49 RefTypeDef HWIntrinsic BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #51 RefTypeDef LCL_VAR BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #53 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #56 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #57 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #59 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #60 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #62 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #85 RefTypeKill BB05 regmask=[rax] minReg=1 last> #79 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #87 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #88 RefTypeKill BB05 regmask=[r8] minReg=1 last> #89 RefTypeKill BB05 regmask=[r9] minReg=1 last> #90 RefTypeKill BB05 regmask=[r10] minReg=1 last> #91 RefTypeKill BB05 regmask=[r11] minReg=1 last> #92 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #93 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #94 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #95 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #96 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #97 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #75 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #77 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #80 RefTypeDef ADD BB05 regmask=[rcx] minReg=1> #81 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #83 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #84 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #86 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #98 RefTypeKill BB05 regmask=[rax] minReg=1 last> #102 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #117 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #118 RefTypeKill BB05 regmask=[r8] minReg=1 last> #119 RefTypeKill BB05 regmask=[r9] minReg=1 last> #120 RefTypeKill BB05 regmask=[r10] minReg=1 last> #121 RefTypeKill BB05 regmask=[r11] minReg=1 last> #122 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #107 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #124 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #125 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #126 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #127 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #115 RefTypeFixedReg BB05 regmask=[rax] minReg=1> #100 RefTypeDef CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[allIntButFP] minReg=1 last> #103 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> #104 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #111 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #112 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #108 RefTypeDef LCL_VAR BB05 regmask=[mm1] minReg=1> #109 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> #113 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> #114 RefTypeDef PUTARG_REG BB05 regmask=[mm1] minReg=1 fixed> #116 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #123 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> #137 RefTypeKill BB05 regmask=[rax] minReg=1 last> #131 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #139 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #140 RefTypeKill BB05 regmask=[r8] minReg=1 last> #141 RefTypeKill BB05 regmask=[r9] minReg=1 last> #142 RefTypeKill BB05 regmask=[r10] minReg=1 last> #143 RefTypeKill BB05 regmask=[r11] minReg=1 last> #144 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #145 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #146 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #147 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #148 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #149 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #129 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #132 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #133 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #135 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #136 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #138 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #169 RefTypeKill BB05 regmask=[rax] minReg=1 last> #163 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #171 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #172 RefTypeKill BB05 regmask=[r8] minReg=1 last> #173 RefTypeKill BB05 regmask=[r9] minReg=1 last> #174 RefTypeKill BB05 regmask=[r10] minReg=1 last> #175 RefTypeKill BB05 regmask=[r11] minReg=1 last> #176 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #177 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #178 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #179 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #180 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #181 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #151 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #153 RefTypeDef IND BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #155 RefTypeDef IND BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #157 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #159 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #161 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #164 RefTypeDef ADD BB05 regmask=[rcx] minReg=1> #165 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #167 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #168 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #170 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #182 RefTypeKill BB05 regmask=[rax] minReg=1 last> #190 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #195 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #207 RefTypeKill BB05 regmask=[r8] minReg=1 last> #202 RefTypeKill BB05 regmask=[r9] minReg=1 last> #224 RefTypeKill BB05 regmask=[r10] minReg=1 last> #225 RefTypeKill BB05 regmask=[r11] minReg=1 last> #226 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #227 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #228 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #229 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #230 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #231 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #219 RefTypeFixedReg BB05 regmask=[rax] minReg=1> #184 RefTypeDef CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[allIntButFP] minReg=1 last> #186 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #188 RefTypeDef LCL_VAR BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #191 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> #192 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #211 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #212 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #196 RefTypeDef LCL_VAR_ADDR BB05 regmask=[rdx] minReg=1> #197 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> #213 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> #214 RefTypeDef PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> #200 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #203 RefTypeDef IND BB05 regmask=[r9] minReg=1> #204 RefTypeFixedReg BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> #215 RefTypeFixedReg BB05 regmask=[r9] minReg=1> #216 RefTypeDef PUTARG_REG BB05 regmask=[r9] minReg=1 fixed> #208 RefTypeDef LCL_VAR BB05 regmask=[r8] minReg=1> #209 RefTypeFixedReg BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> #217 RefTypeFixedReg BB05 regmask=[r8] minReg=1> #218 RefTypeDef PUTARG_REG BB05 regmask=[r8] minReg=1 fixed> #220 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #221 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> #223 RefTypeFixedReg BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> #222 RefTypeFixedReg BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> BB05 regmask=[mm0] minReg=1 last> BB05 regmask=[mm1] minReg=1 last> BB05 regmask=[mm2] minReg=1 last> BB05 regmask=[mm3] minReg=1 last> BB05 regmask=[mm4] minReg=1 last> BB05 regmask=[mm5] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: BB01 [???..???), preds={} succs={BB02} ===== N002. NOP BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N006. CNS_INT(h) 0x7ff826874428 token REG NA N008. IND N010. CNS_INT 0 REG NA N012. EQ N014. JTRUE BB03 [???..???), preds={BB02} succs={BB04} ===== N018. CALL help Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 BB04 [???..???), preds={BB02,BB03} succs={BB05} ===== BB05 [000..05D) (return), preds={BB04} succs={} ===== N024. IL_OFFSET IL offset: 0x0 REG NA N026. NO_OP REG NA N028. IL_OFFSET IL offset: 0x1 REG NA N030. CNS_INT(h) 0x99BB9538 "ClsVarScenario" REG NA Def:(#18) N032. IND Use:(#19) * Def:(#20) N034. PUTARG_REG Use:(#22) Fixed:rcx(#21) * Def:(#24) rcx N036. CALL Use:(#26) Fixed:rcx(#25) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N038. IL_OFFSET IL offset: 0xb REG NA N040. NO_OP REG NA N042. IL_OFFSET IL offset: 0xc REG NA N044. CNS_INT(h) 0x1c599bb5f78 static Fseq[_clsVar] REG NA Def:(#40) N046. IND Use:(#41) * Def:(#42) N048. LEA(b+8) N050. IND Use:(#43) * Def:(#44) N052. CNS_INT 1 REG NA N054. HWIntrinsic Def:(#45) Use:(#46) * Use:(#47) * Def:(#48) N056. V02 MEM Use:(#49) * N058. IL_OFFSET IL offset: 0x17 REG NA N060. V02 MEM Def:(#50) N062. V01 MEM Use:(#51) * N064. IL_OFFSET IL offset: 0x18 REG NA N066. CNS_INT(h) 0x99BB9538 "ClsVarScenario" REG NA Def:(#52) N068. IND Use:(#53) * Def:(#54) N070. PUTARG_REG Use:(#56) Fixed:rcx(#55) * Def:(#58) rcx N072. CALL Use:(#60) Fixed:rcx(#59) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N074. IL_OFFSET IL offset: 0x22 REG NA N076. NO_OP REG NA N078. IL_OFFSET IL offset: 0x23 REG NA N080. V00 MEM Def:(#74) N082. NULLCHECK Use:(#75) * N084. V00 MEM Def:(#76) N086. CNS_INT 32 field offset Fseq[_dataTable] REG NA N088. ADD Use:(#77) * Def:(#78) Pref: N090. PUTARG_REG Use:(#80) Fixed:rcx(#79) * Def:(#82) rcx N092. CALL Use:(#84) Fixed:rcx(#83) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 Def:(#99) rax N094. V03 MEM Use:(#100) * N096. IL_OFFSET IL offset: 0x2e REG NA N098. V03 MEM Def:(#101) N100. PUTARG_REG Use:(#103) Fixed:rcx(#102) * Def:(#105) rcx N102. V01 MEM Def:(#106) N104. PUTARG_REG Use:(#108) Fixed:mm1(#107) * Def:(#110) mm1 N106. CALL Use:(#112) Fixed:rcx(#111) * Use:(#114) Fixed:mm1(#113) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N108. IL_OFFSET IL offset: 0x34 REG NA N110. NO_OP REG NA N112. IL_OFFSET IL offset: 0x35 REG NA N114. CNS_INT(h) 0x99BB9538 "ClsVarScenario" REG NA Def:(#128) N116. IND Use:(#129) * Def:(#130) N118. PUTARG_REG Use:(#132) Fixed:rcx(#131) * Def:(#134) rcx N120. CALL Use:(#136) Fixed:rcx(#135) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N122. IL_OFFSET IL offset: 0x3f REG NA N124. NO_OP REG NA N126. IL_OFFSET IL offset: 0x40 REG NA N128. CNS_INT(h) 0x1c599bb5f78 static Fseq[_clsVar] REG NA Def:(#150) N130. IND Use:(#151) * Def:(#152) N132. LEA(b+8) N134. IND Use:(#153) * Def:(#154) N136. V04 MEM Use:(#155) * N138. V00 MEM Def:(#156) N140. V05 MEM Use:(#157) * N142. V00 MEM Def:(#158) N144. NULLCHECK Use:(#159) * N146. V00 MEM Def:(#160) N148. CNS_INT 32 field offset Fseq[_dataTable] REG NA N150. ADD Use:(#161) * Def:(#162) Pref: N152. PUTARG_REG Use:(#164) Fixed:rcx(#163) * Def:(#166) rcx N154. CALL Use:(#168) Fixed:rcx(#167) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 Def:(#183) rax N156. V06 MEM Use:(#184) * N158. IL_OFFSET IL offset: 0x51 REG NA N160. V05 MEM Def:(#185) N162. V08 MEM Use:(#186) * N164. V04 MEM Def:(#187) N166. V07 MEM Use:(#188) * N168. V08 MEM Def:(#189) N170. PUTARG_REG Use:(#191) Fixed:rcx(#190) * Def:(#193) rcx N172. LCL_VAR_ADDR V07 tmp5 NA REG NA Def:(#194) N174. PUTARG_REG Use:(#196) Fixed:rdx(#195) * Def:(#198) rdx N176. CNS_INT(h) 0x99BB9540 "RunClsVarScenario" REG NA Def:(#199) N178. IND Use:(#200) * Def:(#201) N180. PUTARG_REG Use:(#203) Fixed:r9(#202) * Def:(#205) r9 N182. V06 MEM Def:(#206) N184. PUTARG_REG Use:(#208) Fixed:r8(#207) * Def:(#210) r8 N186. CALL Use:(#212) Fixed:rcx(#211) * Use:(#214) Fixed:rdx(#213) * Use:(#216) Fixed:r9(#215) * Use:(#218) Fixed:r8(#217) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N188. IL_OFFSET IL offset: 0x5b REG NA N190. NO_OP REG NA N192. IL_OFFSET IL offset: 0x5c REG NA N194. RETURN Linear scan intervals after buildIntervals: Interval 0: (constant) RefPositions {#18@31 #19@32} physReg:NA Preferences=[allIntButFP] Interval 1: RefPositions {#20@33 #22@34} physReg:NA Preferences=[rcx] Interval 2: RefPositions {#24@35 #26@36} physReg:NA Preferences=[rcx] Interval 3: (constant) RefPositions {#40@45 #41@46} physReg:NA Preferences=[allIntButFP] Interval 4: RefPositions {#42@47 #43@50} physReg:NA Preferences=[allIntButFP] Interval 5: RefPositions {#44@51 #46@54} physReg:NA Preferences=[allFloat] Interval 6: (INTERNAL) RefPositions {#45@54 #47@54} physReg:NA Preferences=[allIntButFP] Interval 7: RefPositions {#48@55 #49@56} physReg:NA Preferences=[allFloat] Interval 8: RefPositions {#50@61 #51@62} physReg:NA Preferences=[allFloat] Interval 9: (constant) RefPositions {#52@67 #53@68} physReg:NA Preferences=[allIntButFP] Interval 10: RefPositions {#54@69 #56@70} physReg:NA Preferences=[rcx] Interval 11: RefPositions {#58@71 #60@72} physReg:NA Preferences=[rcx] Interval 12: RefPositions {#74@81 #75@82} physReg:NA Preferences=[allIntButFP] Interval 13: RefPositions {#76@85 #77@88} physReg:NA Preferences=[allIntButFP] Interval 14: RefPositions {#78@89 #80@90} physReg:NA Preferences=[rcx] RelatedInterval [000001C5A1EB9720] Interval 15: RefPositions {#82@91 #84@92} physReg:NA Preferences=[rcx] Interval 16: RefPositions {#99@93 #100@94} physReg:NA Preferences=[rax] Interval 17: RefPositions {#101@99 #103@100} physReg:NA Preferences=[rcx] Interval 18: RefPositions {#105@101 #112@106} physReg:NA Preferences=[rcx] Interval 19: RefPositions {#106@103 #108@104} physReg:NA Preferences=[mm1] Interval 20: RefPositions {#110@105 #114@106} physReg:NA Preferences=[mm1] Interval 21: (constant) RefPositions {#128@115 #129@116} physReg:NA Preferences=[allIntButFP] Interval 22: RefPositions {#130@117 #132@118} physReg:NA Preferences=[rcx] Interval 23: RefPositions {#134@119 #136@120} physReg:NA Preferences=[rcx] Interval 24: (constant) RefPositions {#150@129 #151@130} physReg:NA Preferences=[allIntButFP] Interval 25: RefPositions {#152@131 #153@134} physReg:NA Preferences=[allIntButFP] Interval 26: RefPositions {#154@135 #155@136} physReg:NA Preferences=[allFloat] Interval 27: RefPositions {#156@139 #157@140} physReg:NA Preferences=[allIntButFP] Interval 28: RefPositions {#158@143 #159@144} physReg:NA Preferences=[allIntButFP] Interval 29: RefPositions {#160@147 #161@150} physReg:NA Preferences=[allIntButFP] Interval 30: RefPositions {#162@151 #164@152} physReg:NA Preferences=[rcx] RelatedInterval [000001C5A1EBB960] Interval 31: RefPositions {#166@153 #168@154} physReg:NA Preferences=[rcx] Interval 32: RefPositions {#183@155 #184@156} physReg:NA Preferences=[rax] Interval 33: RefPositions {#185@161 #186@162} physReg:NA Preferences=[allIntButFP] Interval 34: RefPositions {#187@165 #188@166} physReg:NA Preferences=[allFloat] Interval 35: RefPositions {#189@169 #191@170} physReg:NA Preferences=[rcx] Interval 36: RefPositions {#193@171 #212@186} physReg:NA Preferences=[rcx] Interval 37: RefPositions {#194@173 #196@174} physReg:NA Preferences=[rdx] Interval 38: RefPositions {#198@175 #214@186} physReg:NA Preferences=[rdx] Interval 39: (constant) RefPositions {#199@177 #200@178} physReg:NA Preferences=[allIntButFP] Interval 40: RefPositions {#201@179 #203@180} physReg:NA Preferences=[r9] Interval 41: RefPositions {#205@181 #216@186} physReg:NA Preferences=[r9] Interval 42: RefPositions {#206@183 #208@184} physReg:NA Preferences=[r8] Interval 43: RefPositions {#210@185 #218@186} physReg:NA Preferences=[r8] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (constant) RefPositions {#18@31 #19@32} physReg:NA Preferences=[allIntButFP] Interval 1: RefPositions {#20@33 #22@34} physReg:NA Preferences=[rcx] Interval 2: RefPositions {#24@35 #26@36} physReg:NA Preferences=[rcx] Interval 3: (constant) RefPositions {#40@45 #41@46} physReg:NA Preferences=[allIntButFP] Interval 4: RefPositions {#42@47 #43@50} physReg:NA Preferences=[allIntButFP] Interval 5: RefPositions {#44@51 #46@54} physReg:NA Preferences=[allFloat] Interval 6: (INTERNAL) RefPositions {#45@54 #47@54} physReg:NA Preferences=[allIntButFP] Interval 7: RefPositions {#48@55 #49@56} physReg:NA Preferences=[allFloat] Interval 8: RefPositions {#50@61 #51@62} physReg:NA Preferences=[allFloat] Interval 9: (constant) RefPositions {#52@67 #53@68} physReg:NA Preferences=[allIntButFP] Interval 10: RefPositions {#54@69 #56@70} physReg:NA Preferences=[rcx] Interval 11: RefPositions {#58@71 #60@72} physReg:NA Preferences=[rcx] Interval 12: RefPositions {#74@81 #75@82} physReg:NA Preferences=[allIntButFP] Interval 13: RefPositions {#76@85 #77@88} physReg:NA Preferences=[allIntButFP] Interval 14: RefPositions {#78@89 #80@90} physReg:NA Preferences=[rcx] RelatedInterval [000001C5A1EB9720] Interval 15: RefPositions {#82@91 #84@92} physReg:NA Preferences=[rcx] Interval 16: RefPositions {#99@93 #100@94} physReg:NA Preferences=[rax] Interval 17: RefPositions {#101@99 #103@100} physReg:NA Preferences=[rcx] Interval 18: RefPositions {#105@101 #112@106} physReg:NA Preferences=[rcx] Interval 19: RefPositions {#106@103 #108@104} physReg:NA Preferences=[mm1] Interval 20: RefPositions {#110@105 #114@106} physReg:NA Preferences=[mm1] Interval 21: (constant) RefPositions {#128@115 #129@116} physReg:NA Preferences=[allIntButFP] Interval 22: RefPositions {#130@117 #132@118} physReg:NA Preferences=[rcx] Interval 23: RefPositions {#134@119 #136@120} physReg:NA Preferences=[rcx] Interval 24: (constant) RefPositions {#150@129 #151@130} physReg:NA Preferences=[allIntButFP] Interval 25: RefPositions {#152@131 #153@134} physReg:NA Preferences=[allIntButFP] Interval 26: RefPositions {#154@135 #155@136} physReg:NA Preferences=[allFloat] Interval 27: RefPositions {#156@139 #157@140} physReg:NA Preferences=[allIntButFP] Interval 28: RefPositions {#158@143 #159@144} physReg:NA Preferences=[allIntButFP] Interval 29: RefPositions {#160@147 #161@150} physReg:NA Preferences=[allIntButFP] Interval 30: RefPositions {#162@151 #164@152} physReg:NA Preferences=[rcx] RelatedInterval [000001C5A1EBB960] Interval 31: RefPositions {#166@153 #168@154} physReg:NA Preferences=[rcx] Interval 32: RefPositions {#183@155 #184@156} physReg:NA Preferences=[rax] Interval 33: RefPositions {#185@161 #186@162} physReg:NA Preferences=[allIntButFP] Interval 34: RefPositions {#187@165 #188@166} physReg:NA Preferences=[allFloat] Interval 35: RefPositions {#189@169 #191@170} physReg:NA Preferences=[rcx] Interval 36: RefPositions {#193@171 #212@186} physReg:NA Preferences=[rcx] Interval 37: RefPositions {#194@173 #196@174} physReg:NA Preferences=[rdx] Interval 38: RefPositions {#198@175 #214@186} physReg:NA Preferences=[rdx] Interval 39: (constant) RefPositions {#199@177 #200@178} physReg:NA Preferences=[allIntButFP] Interval 40: RefPositions {#201@179 #203@180} physReg:NA Preferences=[r9] Interval 41: RefPositions {#205@181 #216@186} physReg:NA Preferences=[r9] Interval 42: RefPositions {#206@183 #208@184} physReg:NA Preferences=[r8] Interval 43: RefPositions {#210@185 #218@186} physReg:NA Preferences=[r8] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ #27 RefTypeKill BB03 regmask=[rax] minReg=1 last> #21 RefTypeKill BB03 regmask=[rcx] minReg=1 last> #29 RefTypeKill BB03 regmask=[rdx] minReg=1 last> #30 RefTypeKill BB03 regmask=[r8] minReg=1 last> #31 RefTypeKill BB03 regmask=[r9] minReg=1 last> #32 RefTypeKill BB03 regmask=[r10] minReg=1 last> #33 RefTypeKill BB03 regmask=[r11] minReg=1 last> #34 RefTypeKill BB03 regmask=[mm0] minReg=1 last> #35 RefTypeKill BB03 regmask=[mm1] minReg=1 last> #36 RefTypeKill BB03 regmask=[mm2] minReg=1 last> #37 RefTypeKill BB03 regmask=[mm3] minReg=1 last> #38 RefTypeKill BB03 regmask=[mm4] minReg=1 last> #39 RefTypeKill BB03 regmask=[mm5] minReg=1 last> #19 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #22 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #23 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #25 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #26 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #28 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #61 RefTypeKill BB05 regmask=[rax] minReg=1 last> #55 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #63 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #64 RefTypeKill BB05 regmask=[r8] minReg=1 last> #65 RefTypeKill BB05 regmask=[r9] minReg=1 last> #66 RefTypeKill BB05 regmask=[r10] minReg=1 last> #67 RefTypeKill BB05 regmask=[r11] minReg=1 last> #68 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #69 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #70 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #71 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #72 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #73 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #41 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #43 RefTypeDef IND BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #46 RefTypeDef IND BB05 regmask=[allFloat] minReg=1> #47 RefTypeDef HWIntrinsic BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allFloat] minReg=1 last> HWIntrinsic BB05 regmask=[allIntButFP] minReg=1 last> #49 RefTypeDef HWIntrinsic BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #51 RefTypeDef LCL_VAR BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #53 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #56 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #57 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #59 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #60 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #62 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #85 RefTypeKill BB05 regmask=[rax] minReg=1 last> #79 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #87 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #88 RefTypeKill BB05 regmask=[r8] minReg=1 last> #89 RefTypeKill BB05 regmask=[r9] minReg=1 last> #90 RefTypeKill BB05 regmask=[r10] minReg=1 last> #91 RefTypeKill BB05 regmask=[r11] minReg=1 last> #92 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #93 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #94 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #95 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #96 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #97 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #75 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #77 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #80 RefTypeDef ADD BB05 regmask=[rcx] minReg=1> #81 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #83 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #84 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #86 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #98 RefTypeKill BB05 regmask=[rax] minReg=1 last> #102 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #117 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #118 RefTypeKill BB05 regmask=[r8] minReg=1 last> #119 RefTypeKill BB05 regmask=[r9] minReg=1 last> #120 RefTypeKill BB05 regmask=[r10] minReg=1 last> #121 RefTypeKill BB05 regmask=[r11] minReg=1 last> #122 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #107 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #124 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #125 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #126 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #127 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #115 RefTypeFixedReg BB05 regmask=[rax] minReg=1> #100 RefTypeDef CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[allIntButFP] minReg=1 last> #103 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> #104 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #111 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #112 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #108 RefTypeDef LCL_VAR BB05 regmask=[mm1] minReg=1> #109 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> #113 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> #114 RefTypeDef PUTARG_REG BB05 regmask=[mm1] minReg=1 fixed> #116 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #123 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> #137 RefTypeKill BB05 regmask=[rax] minReg=1 last> #131 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #139 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #140 RefTypeKill BB05 regmask=[r8] minReg=1 last> #141 RefTypeKill BB05 regmask=[r9] minReg=1 last> #142 RefTypeKill BB05 regmask=[r10] minReg=1 last> #143 RefTypeKill BB05 regmask=[r11] minReg=1 last> #144 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #145 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #146 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #147 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #148 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #149 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #129 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #132 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #133 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #135 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #136 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #138 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #169 RefTypeKill BB05 regmask=[rax] minReg=1 last> #163 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #171 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #172 RefTypeKill BB05 regmask=[r8] minReg=1 last> #173 RefTypeKill BB05 regmask=[r9] minReg=1 last> #174 RefTypeKill BB05 regmask=[r10] minReg=1 last> #175 RefTypeKill BB05 regmask=[r11] minReg=1 last> #176 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #177 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #178 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #179 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #180 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #181 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #151 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #153 RefTypeDef IND BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #155 RefTypeDef IND BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #157 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #159 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #161 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #164 RefTypeDef ADD BB05 regmask=[rcx] minReg=1> #165 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #167 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #168 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #170 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #182 RefTypeKill BB05 regmask=[rax] minReg=1 last> #190 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #195 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #207 RefTypeKill BB05 regmask=[r8] minReg=1 last> #202 RefTypeKill BB05 regmask=[r9] minReg=1 last> #224 RefTypeKill BB05 regmask=[r10] minReg=1 last> #225 RefTypeKill BB05 regmask=[r11] minReg=1 last> #226 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #227 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #228 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #229 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #230 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #231 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #219 RefTypeFixedReg BB05 regmask=[rax] minReg=1> #184 RefTypeDef CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[allIntButFP] minReg=1 last> #186 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #188 RefTypeDef LCL_VAR BB05 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 last> #191 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> #192 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #211 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #212 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #196 RefTypeDef LCL_VAR_ADDR BB05 regmask=[rdx] minReg=1> #197 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> #213 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> #214 RefTypeDef PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> #200 RefTypeDef CNS_INT BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #203 RefTypeDef IND BB05 regmask=[r9] minReg=1> #204 RefTypeFixedReg BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> #215 RefTypeFixedReg BB05 regmask=[r9] minReg=1> #216 RefTypeDef PUTARG_REG BB05 regmask=[r9] minReg=1 fixed> #208 RefTypeDef LCL_VAR BB05 regmask=[r8] minReg=1> #209 RefTypeFixedReg BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> #217 RefTypeFixedReg BB05 regmask=[r8] minReg=1> #218 RefTypeDef PUTARG_REG BB05 regmask=[r8] minReg=1 fixed> #220 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #221 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> #223 RefTypeFixedReg BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> #222 RefTypeFixedReg BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> BB05 regmask=[mm0] minReg=1 last> BB05 regmask=[mm1] minReg=1 last> BB05 regmask=[mm2] minReg=1 last> BB05 regmask=[mm3] minReg=1 last> BB05 regmask=[mm4] minReg=1 last> BB05 regmask=[mm5] minReg=1 last> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ | | | | | | | | | | | | 0.#0 BB1 PredBB0 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 4.#1 BB2 PredBB1 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 16.#2 BB3 PredBB2 | | | | | | | | | | | | 19.#3 rax Kill Keep rax | | | | | | | | | | | | 19.#4 rcx Kill Keep rcx | | | | | | | | | | | | 19.#5 rdx Kill Keep rdx | | | | | | | | | | | | 19.#6 r8 Kill Keep r8 | | | | | | | | | | | | 19.#7 r9 Kill Keep r9 | | | | | | | | | | | | 19.#8 r10 Kill Keep r10 | | | | | | | | | | | | 19.#9 r11 Kill Keep r11 | | | | | | | | | | | | 19.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | 19.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | 19.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | 19.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | 19.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | 19.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 20.#16 BB4 PredBB2 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 22.#17 BB5 PredBB4 | | | | | | | | | | | | 31.#18 C0 Def Alloc rcx | |C0 a| | | | | | | | | | 32.#19 C0 Use * Keep rcx | |C0 a| | | | | | | | | | 33.#20 I1 Def Alloc rcx | |I1 a| | | | | | | | | | 34.#21 rcx Fixd Keep rcx | |I1 a| | | | | | | | | | 34.#22 I1 Use * Keep rcx | |I1 a| | | | | | | | | | 35.#23 rcx Fixd Keep rcx | | | | | | | | | | | | 35.#24 I2 Def Alloc rcx | |I2 a| | | | | | | | | | 36.#25 rcx Fixd Keep rcx | |I2 a| | | | | | | | | | 36.#26 I2 Use * Keep rcx | |I2 a| | | | | | | | | | 37.#27 rax Kill Keep rax | | | | | | | | | | | | 37.#28 rcx Kill Keep rcx | | | | | | | | | | | | 37.#29 rdx Kill Keep rdx | | | | | | | | | | | | 37.#30 r8 Kill Keep r8 | | | | | | | | | | | | 37.#31 r9 Kill Keep r9 | | | | | | | | | | | | 37.#32 r10 Kill Keep r10 | | | | | | | | | | | | 37.#33 r11 Kill Keep r11 | | | | | | | | | | | | 37.#34 mm0 Kill Keep mm0 | | | | | | | | | | | | 37.#35 mm1 Kill Keep mm1 | | | | | | | | | | | | 37.#36 mm2 Kill Keep mm2 | | | | | | | | | | | | 37.#37 mm3 Kill Keep mm3 | | | | | | | | | | | | 37.#38 mm4 Kill Keep mm4 | | | | | | | | | | | | 37.#39 mm5 Kill Keep mm5 | | | | | | | | | | | | 45.#40 C3 Def Alloc rcx | |C3 a| | | | | | | | | | 46.#41 C3 Use * Keep rcx | |C3 a| | | | | | | | | | 47.#42 I4 Def Alloc rcx | |I4 a| | | | | | | | | | 50.#43 I4 Use * Keep rcx | |I4 a| | | | | | | | | | 51.#44 I5 Def Alloc mm0 | | | | | | |I5 a| | | | | 54.#45 I6 Def Alloc rcx | |I6 a| | | | |I5 a| | | | | 54.#46 I5 Use * Keep mm0 | |I6 a| | | | |I5 a| | | | | 54.#47 I6 Use * Keep rcx | |I6 a| | | | |I5 a| | | | | 55.#48 I7 Def Alloc mm0 | | | | | | |I7 a| | | | | 56.#49 I7 Use * Keep mm0 | | | | | | |I7 a| | | | | 61.#50 I8 Def Alloc mm0 | | | | | | |I8 a| | | | | 62.#51 I8 Use * Keep mm0 | | | | | | |I8 a| | | | | 67.#52 C9 Def Alloc rcx | |C9 a| | | | | | | | | | 68.#53 C9 Use * Keep rcx | |C9 a| | | | | | | | | | 69.#54 I10 Def Alloc rcx | |I10a| | | | | | | | | | 70.#55 rcx Fixd Keep rcx | |I10a| | | | | | | | | | 70.#56 I10 Use * Keep rcx | |I10a| | | | | | | | | | 71.#57 rcx Fixd Keep rcx | | | | | | | | | | | | 71.#58 I11 Def Alloc rcx | |I11a| | | | | | | | | | 72.#59 rcx Fixd Keep rcx | |I11a| | | | | | | | | | 72.#60 I11 Use * Keep rcx | |I11a| | | | | | | | | | 73.#61 rax Kill Keep rax | | | | | | | | | | | | 73.#62 rcx Kill Keep rcx | | | | | | | | | | | | 73.#63 rdx Kill Keep rdx | | | | | | | | | | | | 73.#64 r8 Kill Keep r8 | | | | | | | | | | | | 73.#65 r9 Kill Keep r9 | | | | | | | | | | | | 73.#66 r10 Kill Keep r10 | | | | | | | | | | | | 73.#67 r11 Kill Keep r11 | | | | | | | | | | | | 73.#68 mm0 Kill Keep mm0 | | | | | | | | | | | | 73.#69 mm1 Kill Keep mm1 | | | | | | | | | | | | 73.#70 mm2 Kill Keep mm2 | | | | | | | | | | | | 73.#71 mm3 Kill Keep mm3 | | | | | | | | | | | | 73.#72 mm4 Kill Keep mm4 | | | | | | | | | | | | 73.#73 mm5 Kill Keep mm5 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 81.#74 I12 Def Alloc rcx | |I12a| | | | | | | | | | 82.#75 I12 Use * Keep rcx | |I12a| | | | | | | | | | 85.#76 I13 Def Alloc rcx | |I13a| | | | | | | | | | 88.#77 I13 Use * Keep rcx | |I13a| | | | | | | | | | 89.#78 I14 Def Alloc rcx | |I14a| | | | | | | | | | 90.#79 rcx Fixd Keep rcx | |I14a| | | | | | | | | | 90.#80 I14 Use * Keep rcx | |I14a| | | | | | | | | | 91.#81 rcx Fixd Keep rcx | | | | | | | | | | | | 91.#82 I15 Def Alloc rcx | |I15a| | | | | | | | | | 92.#83 rcx Fixd Keep rcx | |I15a| | | | | | | | | | 92.#84 I15 Use * Keep rcx | |I15a| | | | | | | | | | 93.#85 rax Kill Keep rax | | | | | | | | | | | | 93.#86 rcx Kill Keep rcx | | | | | | | | | | | | 93.#87 rdx Kill Keep rdx | | | | | | | | | | | | 93.#88 r8 Kill Keep r8 | | | | | | | | | | | | 93.#89 r9 Kill Keep r9 | | | | | | | | | | | | 93.#90 r10 Kill Keep r10 | | | | | | | | | | | | 93.#91 r11 Kill Keep r11 | | | | | | | | | | | | 93.#92 mm0 Kill Keep mm0 | | | | | | | | | | | | 93.#93 mm1 Kill Keep mm1 | | | | | | | | | | | | 93.#94 mm2 Kill Keep mm2 | | | | | | | | | | | | 93.#95 mm3 Kill Keep mm3 | | | | | | | | | | | | 93.#96 mm4 Kill Keep mm4 | | | | | | | | | | | | 93.#97 mm5 Kill Keep mm5 | | | | | | | | | | | | 93.#98 rax Fixd Keep rax | | | | | | | | | | | | 93.#99 I16 Def Alloc rax |I16a| | | | | | | | | | | 94.#100 I16 Use * Keep rax |I16a| | | | | | | | | | | 99.#101 I17 Def Alloc rcx | |I17a| | | | | | | | | | 100.#102 rcx Fixd Keep rcx | |I17a| | | | | | | | | | 100.#103 I17 Use * Keep rcx | |I17a| | | | | | | | | | 101.#104 rcx Fixd Keep rcx | | | | | | | | | | | | 101.#105 I18 Def Alloc rcx | |I18a| | | | | | | | | | 103.#106 I19 Def Alloc mm1 | |I18a| | | | | |I19a| | | | 104.#107 mm1 Fixd Keep mm1 | |I18a| | | | | |I19a| | | | 104.#108 I19 Use * Keep mm1 | |I18a| | | | | |I19a| | | | 105.#109 mm1 Fixd Keep mm1 | |I18a| | | | | | | | | | 105.#110 I20 Def Alloc mm1 | |I18a| | | | | |I20a| | | | 106.#111 rcx Fixd Keep rcx | |I18a| | | | | |I20a| | | | 106.#112 I18 Use * Keep rcx | |I18a| | | | | |I20a| | | | 106.#113 mm1 Fixd Keep mm1 | |I18a| | | | | |I20a| | | | 106.#114 I20 Use * Keep mm1 | |I18a| | | | | |I20a| | | | 107.#115 rax Kill Keep rax | | | | | | | | | | | | 107.#116 rcx Kill Keep rcx | | | | | | | | | | | | 107.#117 rdx Kill Keep rdx | | | | | | | | | | | | 107.#118 r8 Kill Keep r8 | | | | | | | | | | | | 107.#119 r9 Kill Keep r9 | | | | | | | | | | | | 107.#120 r10 Kill Keep r10 | | | | | | | | | | | | 107.#121 r11 Kill Keep r11 | | | | | | | | | | | | 107.#122 mm0 Kill Keep mm0 | | | | | | | | | | | | 107.#123 mm1 Kill Keep mm1 | | | | | | | | | | | | 107.#124 mm2 Kill Keep mm2 | | | | | | | | | | | | 107.#125 mm3 Kill Keep mm3 | | | | | | | | | | | | 107.#126 mm4 Kill Keep mm4 | | | | | | | | | | | | 107.#127 mm5 Kill Keep mm5 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 115.#128 C21 Def Alloc rcx | |C21a| | | | | | | | | | 116.#129 C21 Use * Keep rcx | |C21a| | | | | | | | | | 117.#130 I22 Def Alloc rcx | |I22a| | | | | | | | | | 118.#131 rcx Fixd Keep rcx | |I22a| | | | | | | | | | 118.#132 I22 Use * Keep rcx | |I22a| | | | | | | | | | 119.#133 rcx Fixd Keep rcx | | | | | | | | | | | | 119.#134 I23 Def Alloc rcx | |I23a| | | | | | | | | | 120.#135 rcx Fixd Keep rcx | |I23a| | | | | | | | | | 120.#136 I23 Use * Keep rcx | |I23a| | | | | | | | | | 121.#137 rax Kill Keep rax | | | | | | | | | | | | 121.#138 rcx Kill Keep rcx | | | | | | | | | | | | 121.#139 rdx Kill Keep rdx | | | | | | | | | | | | 121.#140 r8 Kill Keep r8 | | | | | | | | | | | | 121.#141 r9 Kill Keep r9 | | | | | | | | | | | | 121.#142 r10 Kill Keep r10 | | | | | | | | | | | | 121.#143 r11 Kill Keep r11 | | | | | | | | | | | | 121.#144 mm0 Kill Keep mm0 | | | | | | | | | | | | 121.#145 mm1 Kill Keep mm1 | | | | | | | | | | | | 121.#146 mm2 Kill Keep mm2 | | | | | | | | | | | | 121.#147 mm3 Kill Keep mm3 | | | | | | | | | | | | 121.#148 mm4 Kill Keep mm4 | | | | | | | | | | | | 121.#149 mm5 Kill Keep mm5 | | | | | | | | | | | | 129.#150 C24 Def Alloc rcx | |C24a| | | | | | | | | | 130.#151 C24 Use * Keep rcx | |C24a| | | | | | | | | | 131.#152 I25 Def Alloc rcx | |I25a| | | | | | | | | | 134.#153 I25 Use * Keep rcx | |I25a| | | | | | | | | | 135.#154 I26 Def Alloc mm0 | | | | | | |I26a| | | | | 136.#155 I26 Use * Keep mm0 | | | | | | |I26a| | | | | 139.#156 I27 Def Alloc rcx | |I27a| | | | | | | | | | 140.#157 I27 Use * Keep rcx | |I27a| | | | | | | | | | 143.#158 I28 Def Alloc rcx | |I28a| | | | | | | | | | 144.#159 I28 Use * Keep rcx | |I28a| | | | | | | | | | 147.#160 I29 Def Alloc rcx | |I29a| | | | | | | | | | 150.#161 I29 Use * Keep rcx | |I29a| | | | | | | | | | 151.#162 I30 Def Alloc rcx | |I30a| | | | | | | | | | 152.#163 rcx Fixd Keep rcx | |I30a| | | | | | | | | | 152.#164 I30 Use * Keep rcx | |I30a| | | | | | | | | | 153.#165 rcx Fixd Keep rcx | | | | | | | | | | | | 153.#166 I31 Def Alloc rcx | |I31a| | | | | | | | | | 154.#167 rcx Fixd Keep rcx | |I31a| | | | | | | | | | 154.#168 I31 Use * Keep rcx | |I31a| | | | | | | | | | 155.#169 rax Kill Keep rax | | | | | | | | | | | | 155.#170 rcx Kill Keep rcx | | | | | | | | | | | | 155.#171 rdx Kill Keep rdx | | | | | | | | | | | | 155.#172 r8 Kill Keep r8 | | | | | | | | | | | | 155.#173 r9 Kill Keep r9 | | | | | | | | | | | | 155.#174 r10 Kill Keep r10 | | | | | | | | | | | | 155.#175 r11 Kill Keep r11 | | | | | | | | | | | | 155.#176 mm0 Kill Keep mm0 | | | | | | | | | | | | 155.#177 mm1 Kill Keep mm1 | | | | | | | | | | | | 155.#178 mm2 Kill Keep mm2 | | | | | | | | | | | | 155.#179 mm3 Kill Keep mm3 | | | | | | | | | | | | 155.#180 mm4 Kill Keep mm4 | | | | | | | | | | | | 155.#181 mm5 Kill Keep mm5 | | | | | | | | | | | | 155.#182 rax Fixd Keep rax | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 155.#183 I32 Def Alloc rax |I32a| | | | | | | | | | | 156.#184 I32 Use * Keep rax |I32a| | | | | | | | | | | 161.#185 I33 Def Alloc rcx | |I33a| | | | | | | | | | 162.#186 I33 Use * Keep rcx | |I33a| | | | | | | | | | 165.#187 I34 Def Alloc mm0 | | | | | | |I34a| | | | | 166.#188 I34 Use * Keep mm0 | | | | | | |I34a| | | | | 169.#189 I35 Def Alloc rcx | |I35a| | | | | | | | | | 170.#190 rcx Fixd Keep rcx | |I35a| | | | | | | | | | 170.#191 I35 Use * Keep rcx | |I35a| | | | | | | | | | 171.#192 rcx Fixd Keep rcx | | | | | | | | | | | | 171.#193 I36 Def Alloc rcx | |I36a| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 173.#194 I37 Def Alloc rdx | |I36a|I37a| | | | | | | | | | 174.#195 rdx Fixd Keep rdx | |I36a|I37a| | | | | | | | | | 174.#196 I37 Use * Keep rdx | |I36a|I37a| | | | | | | | | | 175.#197 rdx Fixd Keep rdx | |I36a| | | | | | | | | | | 175.#198 I38 Def Alloc rdx | |I36a|I38a| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+ 177.#199 C39 Def Alloc r9 | |I36a|I38a| | | | |C39a| | | | | | 178.#200 C39 Use * Keep r9 | |I36a|I38a| | | | |C39a| | | | | | 179.#201 I40 Def Alloc r9 | |I36a|I38a| | | | |I40a| | | | | | 180.#202 r9 Fixd Keep r9 | |I36a|I38a| | | | |I40a| | | | | | 180.#203 I40 Use * Keep r9 | |I36a|I38a| | | | |I40a| | | | | | 181.#204 r9 Fixd Keep r9 | |I36a|I38a| | | | | | | | | | | 181.#205 I41 Def Alloc r9 | |I36a|I38a| | | | |I41a| | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 183.#206 I42 Def Alloc r8 | |I36a|I38a| | | | |I42a|I41a| | | | | | 184.#207 r8 Fixd Keep r8 | |I36a|I38a| | | | |I42a|I41a| | | | | | 184.#208 I42 Use * Keep r8 | |I36a|I38a| | | | |I42a|I41a| | | | | | 185.#209 r8 Fixd Keep r8 | |I36a|I38a| | | | | |I41a| | | | | | 185.#210 I43 Def Alloc r8 | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#211 rcx Fixd Keep rcx | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#212 I36 Use * Keep rcx | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#213 rdx Fixd Keep rdx | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#214 I38 Use * Keep rdx | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#215 r9 Fixd Keep r9 | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#216 I41 Use * Keep r9 | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#217 r8 Fixd Keep r8 | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#218 I43 Use * Keep r8 | |I36a|I38a| | | | |I43a|I41a| | | | | | 187.#219 rax Kill Keep rax | | | | | | | | | | | | | | | 187.#220 rcx Kill Keep rcx | | | | | | | | | | | | | | | 187.#221 rdx Kill Keep rdx | | | | | | | | | | | | | | | 187.#222 r8 Kill Keep r8 | | | | | | | | | | | | | | | 187.#223 r9 Kill Keep r9 | | | | | | | | | | | | | | | 187.#224 r10 Kill Keep r10 | | | | | | | | | | | | | | | 187.#225 r11 Kill Keep r11 | | | | | | | | | | | | | | | 187.#226 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 187.#227 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 187.#228 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 187.#229 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 187.#230 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 187.#231 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ #27 RefTypeKill BB03 regmask=[rax] minReg=1 last> #21 RefTypeKill BB03 regmask=[rcx] minReg=1 last> #29 RefTypeKill BB03 regmask=[rdx] minReg=1 last> #30 RefTypeKill BB03 regmask=[r8] minReg=1 last> #31 RefTypeKill BB03 regmask=[r9] minReg=1 last> #32 RefTypeKill BB03 regmask=[r10] minReg=1 last> #33 RefTypeKill BB03 regmask=[r11] minReg=1 last> #34 RefTypeKill BB03 regmask=[mm0] minReg=1 last> #35 RefTypeKill BB03 regmask=[mm1] minReg=1 last> #36 RefTypeKill BB03 regmask=[mm2] minReg=1 last> #37 RefTypeKill BB03 regmask=[mm3] minReg=1 last> #38 RefTypeKill BB03 regmask=[mm4] minReg=1 last> #39 RefTypeKill BB03 regmask=[mm5] minReg=1 last> #19 RefTypeDef CNS_INT BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #22 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #23 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #25 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #26 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #28 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #61 RefTypeKill BB05 regmask=[rax] minReg=1 last> #55 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #63 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #64 RefTypeKill BB05 regmask=[r8] minReg=1 last> #65 RefTypeKill BB05 regmask=[r9] minReg=1 last> #66 RefTypeKill BB05 regmask=[r10] minReg=1 last> #67 RefTypeKill BB05 regmask=[r11] minReg=1 last> #68 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #69 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #70 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #71 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #72 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #73 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #41 RefTypeDef CNS_INT BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #43 RefTypeDef IND BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #46 RefTypeDef IND BB05 regmask=[mm0] minReg=1> #47 RefTypeDef HWIntrinsic BB05 regmask=[rcx] minReg=1> BB05 regmask=[mm0] minReg=1 last> HWIntrinsic BB05 regmask=[rcx] minReg=1 last> #49 RefTypeDef HWIntrinsic BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm0] minReg=1 last> #51 RefTypeDef LCL_VAR BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm0] minReg=1 last> #53 RefTypeDef CNS_INT BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #56 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #57 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #59 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #60 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #62 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #85 RefTypeKill BB05 regmask=[rax] minReg=1 last> #79 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #87 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #88 RefTypeKill BB05 regmask=[r8] minReg=1 last> #89 RefTypeKill BB05 regmask=[r9] minReg=1 last> #90 RefTypeKill BB05 regmask=[r10] minReg=1 last> #91 RefTypeKill BB05 regmask=[r11] minReg=1 last> #92 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #93 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #94 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #95 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #96 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #97 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #75 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #77 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #80 RefTypeDef ADD BB05 regmask=[rcx] minReg=1> #81 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #83 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #84 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #86 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #98 RefTypeKill BB05 regmask=[rax] minReg=1 last> #102 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #117 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #118 RefTypeKill BB05 regmask=[r8] minReg=1 last> #119 RefTypeKill BB05 regmask=[r9] minReg=1 last> #120 RefTypeKill BB05 regmask=[r10] minReg=1 last> #121 RefTypeKill BB05 regmask=[r11] minReg=1 last> #122 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #107 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #124 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #125 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #126 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #127 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #115 RefTypeFixedReg BB05 regmask=[rax] minReg=1> #100 RefTypeDef CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[rax] minReg=1 last> #103 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> #104 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #111 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #112 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #108 RefTypeDef LCL_VAR BB05 regmask=[mm1] minReg=1> #109 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> #113 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> #114 RefTypeDef PUTARG_REG BB05 regmask=[mm1] minReg=1 fixed> #116 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #123 RefTypeFixedReg BB05 regmask=[mm1] minReg=1> BB05 regmask=[mm1] minReg=1 last fixed> #137 RefTypeKill BB05 regmask=[rax] minReg=1 last> #131 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #139 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #140 RefTypeKill BB05 regmask=[r8] minReg=1 last> #141 RefTypeKill BB05 regmask=[r9] minReg=1 last> #142 RefTypeKill BB05 regmask=[r10] minReg=1 last> #143 RefTypeKill BB05 regmask=[r11] minReg=1 last> #144 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #145 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #146 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #147 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #148 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #149 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #129 RefTypeDef CNS_INT BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #132 RefTypeDef IND BB05 regmask=[rcx] minReg=1> #133 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #135 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #136 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #138 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #169 RefTypeKill BB05 regmask=[rax] minReg=1 last> #163 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #171 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #172 RefTypeKill BB05 regmask=[r8] minReg=1 last> #173 RefTypeKill BB05 regmask=[r9] minReg=1 last> #174 RefTypeKill BB05 regmask=[r10] minReg=1 last> #175 RefTypeKill BB05 regmask=[r11] minReg=1 last> #176 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #177 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #178 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #179 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #180 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #181 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #151 RefTypeDef CNS_INT BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #153 RefTypeDef IND BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #155 RefTypeDef IND BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm0] minReg=1 last> #157 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #159 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #161 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #164 RefTypeDef ADD BB05 regmask=[rcx] minReg=1> #165 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #167 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #168 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #170 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #182 RefTypeKill BB05 regmask=[rax] minReg=1 last> #190 RefTypeKill BB05 regmask=[rcx] minReg=1 last> #195 RefTypeKill BB05 regmask=[rdx] minReg=1 last> #207 RefTypeKill BB05 regmask=[r8] minReg=1 last> #202 RefTypeKill BB05 regmask=[r9] minReg=1 last> #224 RefTypeKill BB05 regmask=[r10] minReg=1 last> #225 RefTypeKill BB05 regmask=[r11] minReg=1 last> #226 RefTypeKill BB05 regmask=[mm0] minReg=1 last> #227 RefTypeKill BB05 regmask=[mm1] minReg=1 last> #228 RefTypeKill BB05 regmask=[mm2] minReg=1 last> #229 RefTypeKill BB05 regmask=[mm3] minReg=1 last> #230 RefTypeKill BB05 regmask=[mm4] minReg=1 last> #231 RefTypeKill BB05 regmask=[mm5] minReg=1 last> #219 RefTypeFixedReg BB05 regmask=[rax] minReg=1> #184 RefTypeDef CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[rax] minReg=1 last> #186 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #188 RefTypeDef LCL_VAR BB05 regmask=[mm0] minReg=1> BB05 regmask=[mm0] minReg=1 last> #191 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> #192 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #211 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> #212 RefTypeDef PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> #196 RefTypeDef LCL_VAR_ADDR BB05 regmask=[rdx] minReg=1> #197 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> #213 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> #214 RefTypeDef PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> #200 RefTypeDef CNS_INT BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last> #203 RefTypeDef IND BB05 regmask=[r9] minReg=1> #204 RefTypeFixedReg BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> #215 RefTypeFixedReg BB05 regmask=[r9] minReg=1> #216 RefTypeDef PUTARG_REG BB05 regmask=[r9] minReg=1 fixed> #208 RefTypeDef LCL_VAR BB05 regmask=[r8] minReg=1> #209 RefTypeFixedReg BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> #217 RefTypeFixedReg BB05 regmask=[r8] minReg=1> #218 RefTypeDef PUTARG_REG BB05 regmask=[r8] minReg=1 fixed> #220 RefTypeFixedReg BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> #221 RefTypeFixedReg BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> #223 RefTypeFixedReg BB05 regmask=[r9] minReg=1> BB05 regmask=[r9] minReg=1 last fixed> #222 RefTypeFixedReg BB05 regmask=[r8] minReg=1> BB05 regmask=[r8] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> BB05 regmask=[mm0] minReg=1 last> BB05 regmask=[mm1] minReg=1 last> BB05 regmask=[mm2] minReg=1 last> BB05 regmask=[mm3] minReg=1 last> BB05 regmask=[mm4] minReg=1 last> BB05 regmask=[mm5] minReg=1 last> Active intervals at end of allocation: Trees after linear scan register allocator (LSRA) -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N002 ( 0, 0) [000000] ------------ NOP void REG NA ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N006 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token REG NA /--* t85 long N008 ( 5, 12) [000086] xc---------- t86 = * IND int REG NA N010 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 REG NA /--* t86 int +--* t87 int N012 ( 7, 14) [000088] J------N---- * EQ void REG NA N014 ( 9, 16) [000145] ------------ * JTRUE void REG NA ------------ BB03 [???..???), preds={BB02} succs={BB04} N018 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} ------------ BB05 [000..05D) (return), preds={BB04} succs={} N024 ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 REG NA N026 ( 1, 1) [000003] ------------ NO_OP void REG NA N028 ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 REG NA N030 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG rcx /--* t94 long N032 ( 5, 12) [000095] x---G------- t95 = * IND ref REG rcx /--* t95 ref N034 (???,???) [000148] ----G------- t148 = * PUTARG_REG ref REG rcx /--* t148 ref arg0 in rcx N036 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine N038 ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb REG NA N040 ( 1, 1) [000009] ------------ NO_OP void REG NA N042 ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc REG NA N044 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] REG rcx /--* t98 long N046 ( 5, 12) [000011] x---G------- t11 = * IND ref REG rcx /--* t11 ref N048 (???,???) [000149] -c---------- t149 = * LEA(b+8) byref REG NA /--* t149 byref N050 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 REG mm0 N052 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 REG NA /--* t14 simd16 +--* t15 int N054 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract REG mm0 /--* t16 float N056 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 NA REG NA N058 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 REG NA N060 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 mm0 REG mm0 /--* t20 float N062 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 NA REG NA N064 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 REG NA N066 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG rcx /--* t99 long N068 ( 5, 12) [000100] x---G------- t100 = * IND ref REG rcx /--* t100 ref N070 (???,???) [000150] ----G------- t150 = * PUTARG_REG ref REG rcx /--* t150 ref arg0 in rcx N072 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine N074 ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 REG NA N076 ( 1, 1) [000028] ------------ NO_OP void REG NA N078 ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 REG NA N080 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this rcx REG rcx /--* t103 ref N082 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte REG NA N084 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this rcx REG rcx N086 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] REG NA /--* t105 ref +--* t106 long N088 ( 5, 4) [000107] ------------ t107 = * ADD byref REG rcx /--* t107 byref N090 (???,???) [000151] ------------ t151 = * PUTARG_REG byref REG rcx /--* t151 byref this in rcx N092 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t33 long N094 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 NA REG NA N096 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e REG NA N098 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 rcx REG rcx /--* t37 long N100 (???,???) [000152] ------------ t152 = * PUTARG_REG long REG rcx N102 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 mm1 REG mm1 /--* t38 float N104 (???,???) [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 N106 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write N108 ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 REG NA N110 ( 1, 1) [000043] ------------ NO_OP void REG NA N112 ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 REG NA N114 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG rcx /--* t116 long N116 ( 5, 12) [000117] x---G------- t117 = * IND ref REG rcx /--* t117 ref N118 (???,???) [000154] ----G------- t154 = * PUTARG_REG ref REG rcx /--* t154 ref arg0 in rcx N120 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine N122 ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f REG NA N124 ( 1, 1) [000049] ------------ NO_OP void REG NA N126 ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 REG NA N128 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] REG rcx /--* t120 long N130 ( 5, 12) [000052] x---G------- t52 = * IND ref REG rcx /--* t52 ref N132 (???,???) [000155] -c---------- t155 = * LEA(b+8) byref REG NA /--* t155 byref N134 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 REG mm0 /--* t55 simd16 N136 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 NA REG NA N138 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this rcx REG rcx /--* t51 ref N140 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 NA REG NA N142 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this rcx REG rcx /--* t121 ref N144 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte REG NA N146 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this rcx REG rcx N148 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] REG NA /--* t123 ref +--* t124 long N150 ( 5, 4) [000125] ------------ t125 = * ADD byref REG rcx /--* t125 byref N152 (???,???) [000156] ------------ t156 = * PUTARG_REG byref REG rcx /--* t156 byref this in rcx N154 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr /--* t59 long N156 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 NA REG NA N158 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 REG NA N160 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 rcx REG rcx /--* t68 ref N162 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 NA REG NA N164 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 mm0 REG mm0 /--* t64 simd16 N166 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 NA REG NA N168 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 rcx REG rcx /--* t136 ref N170 (???,???) [000157] ------------ t157 = * PUTARG_REG ref REG rcx N172 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 rdx REG rdx /--* t138 byref N174 (???,???) [000158] ------------ t158 = * PUTARG_REG byref REG rdx N176 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" REG r9 /--* t132 long N178 ( 5, 12) [000133] x---G------- t133 = * IND ref REG r9 /--* t133 ref N180 (???,???) [000159] ----G------- t159 = * PUTARG_REG ref REG r9 N182 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 r8 REG r8 /--* t72 long N184 (???,???) [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 N186 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult N188 ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b REG NA N190 ( 1, 1) [000081] ------------ NO_OP void REG NA N192 ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c REG NA N194 ( 0, 0) [000083] ------------ RETURN void REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 4.#1 BB2 PredBB1 | | | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 16.#2 BB3 PredBB2 | | | | | | | | | | | | | | | 19.#3 rax Kill Keep rax | | | | | | | | | | | | | | | 19.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | | 19.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | | 19.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | | 19.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | | 19.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | | 19.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | | 19.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 19.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 19.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 19.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 19.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 19.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 20.#16 BB4 PredBB2 | | | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 22.#17 BB5 PredBB4 | | | | | | | | | | | | | | | 31.#18 C0 Def Alloc rcx | |C0 a| | | | | | | | | | | | | 32.#19 C0 Use * Keep rcx | |C0 i| | | | | | | | | | | | | 33.#20 I1 Def Alloc rcx | |I1 a| | | | | | | | | | | | | 34.#21 rcx Fixd Keep rcx | |I1 a| | | | | | | | | | | | | 34.#22 I1 Use * Keep rcx | |I1 i| | | | | | | | | | | | | 35.#23 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 35.#24 I2 Def Alloc rcx | |I2 a| | | | | | | | | | | | | 36.#25 rcx Fixd Keep rcx | |I2 a| | | | | | | | | | | | | 36.#26 I2 Use * Keep rcx | |I2 i| | | | | | | | | | | | | 37.#27 rax Kill Keep rax | | | | | | | | | | | | | | | 37.#28 rcx Kill Keep rcx | | | | | | | | | | | | | | | 37.#29 rdx Kill Keep rdx | | | | | | | | | | | | | | | 37.#30 r8 Kill Keep r8 | | | | | | | | | | | | | | | 37.#31 r9 Kill Keep r9 | | | | | | | | | | | | | | | 37.#32 r10 Kill Keep r10 | | | | | | | | | | | | | | | 37.#33 r11 Kill Keep r11 | | | | | | | | | | | | | | | 37.#34 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 37.#35 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 37.#36 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 37.#37 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 37.#38 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 37.#39 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | 45.#40 C3 Def Alloc rcx | |C3 a| | | | | | | | | | | | | 46.#41 C3 Use * Keep rcx | |C3 i| | | | | | | | | | | | | 47.#42 I4 Def Alloc rcx | |I4 a| | | | | | | | | | | | | 50.#43 I4 Use * Keep rcx | |I4 i| | | | | | | | | | | | | 51.#44 I5 Def Alloc mm0 | | | | | | | | | |I5 a| | | | | 54.#45 I6 Def Alloc rcx | |I6 a| | | | | | | |I5 a| | | | | 54.#46 I5 Use * Keep mm0 | |I6 a| | | | | | | |I5 i| | | | | 54.#47 I6 Use * Keep rcx | |I6 i| | | | | | | | | | | | | 55.#48 I7 Def Alloc mm0 | | | | | | | | | |I7 a| | | | | 56.#49 I7 Use * Keep mm0 | | | | | | | | | |I7 i| | | | | 61.#50 I8 Def Alloc mm0 | | | | | | | | | |I8 a| | | | | 62.#51 I8 Use * Keep mm0 | | | | | | | | | |I8 i| | | | | 67.#52 C9 Def Alloc rcx | |C9 a| | | | | | | | | | | | | 68.#53 C9 Use * Keep rcx | |C9 i| | | | | | | | | | | | | 69.#54 I10 Def Alloc rcx | |I10a| | | | | | | | | | | | | 70.#55 rcx Fixd Keep rcx | |I10a| | | | | | | | | | | | | 70.#56 I10 Use * Keep rcx | |I10i| | | | | | | | | | | | | 71.#57 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 71.#58 I11 Def Alloc rcx | |I11a| | | | | | | | | | | | | 72.#59 rcx Fixd Keep rcx | |I11a| | | | | | | | | | | | | 72.#60 I11 Use * Keep rcx | |I11i| | | | | | | | | | | | | 73.#61 rax Kill Keep rax | | | | | | | | | | | | | | | 73.#62 rcx Kill Keep rcx | | | | | | | | | | | | | | | 73.#63 rdx Kill Keep rdx | | | | | | | | | | | | | | | 73.#64 r8 Kill Keep r8 | | | | | | | | | | | | | | | 73.#65 r9 Kill Keep r9 | | | | | | | | | | | | | | | 73.#66 r10 Kill Keep r10 | | | | | | | | | | | | | | | 73.#67 r11 Kill Keep r11 | | | | | | | | | | | | | | | 73.#68 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 73.#69 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 73.#70 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 73.#71 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 73.#72 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 73.#73 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | 81.#74 I12 Def Alloc rcx | |I12a| | | | | | | | | | | | | 82.#75 I12 Use * Keep rcx | |I12i| | | | | | | | | | | | | 85.#76 I13 Def Alloc rcx | |I13a| | | | | | | | | | | | | 88.#77 I13 Use * Keep rcx | |I13i| | | | | | | | | | | | | 89.#78 I14 Def Alloc rcx | |I14a| | | | | | | | | | | | | 90.#79 rcx Fixd Keep rcx | |I14a| | | | | | | | | | | | | 90.#80 I14 Use * Keep rcx | |I14i| | | | | | | | | | | | | 91.#81 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 91.#82 I15 Def Alloc rcx | |I15a| | | | | | | | | | | | | 92.#83 rcx Fixd Keep rcx | |I15a| | | | | | | | | | | | | 92.#84 I15 Use * Keep rcx | |I15i| | | | | | | | | | | | | 93.#85 rax Kill Keep rax | | | | | | | | | | | | | | | 93.#86 rcx Kill Keep rcx | | | | | | | | | | | | | | | 93.#87 rdx Kill Keep rdx | | | | | | | | | | | | | | | 93.#88 r8 Kill Keep r8 | | | | | | | | | | | | | | | 93.#89 r9 Kill Keep r9 | | | | | | | | | | | | | | | 93.#90 r10 Kill Keep r10 | | | | | | | | | | | | | | | 93.#91 r11 Kill Keep r11 | | | | | | | | | | | | | | | 93.#92 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 93.#93 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 93.#94 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 93.#95 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 93.#96 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 93.#97 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | 93.#98 rax Fixd Keep rax | | | | | | | | | | | | | | | 93.#99 I16 Def Alloc rax |I16a| | | | | | | | | | | | | | 94.#100 I16 Use * Keep rax |I16i| | | | | | | | | | | | | | 99.#101 I17 Def Alloc rcx | |I17a| | | | | | | | | | | | | 100.#102 rcx Fixd Keep rcx | |I17a| | | | | | | | | | | | | 100.#103 I17 Use * Keep rcx | |I17i| | | | | | | | | | | | | 101.#104 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 101.#105 I18 Def Alloc rcx | |I18a| | | | | | | | | | | | | 103.#106 I19 Def Alloc mm1 | |I18a| | | | | | | | |I19a| | | | 104.#107 mm1 Fixd Keep mm1 | |I18a| | | | | | | | |I19a| | | | 104.#108 I19 Use * Keep mm1 | |I18a| | | | | | | | |I19i| | | | 105.#109 mm1 Fixd Keep mm1 | |I18a| | | | | | | | | | | | | 105.#110 I20 Def Alloc mm1 | |I18a| | | | | | | | |I20a| | | | 106.#111 rcx Fixd Keep rcx | |I18a| | | | | | | | |I20a| | | | 106.#112 I18 Use * Keep rcx | |I18i| | | | | | | | |I20a| | | | 106.#113 mm1 Fixd Keep mm1 | | | | | | | | | | |I20a| | | | 106.#114 I20 Use * Keep mm1 | | | | | | | | | | |I20i| | | | 107.#115 rax Kill Keep rax | | | | | | | | | | | | | | | 107.#116 rcx Kill Keep rcx | | | | | | | | | | | | | | | 107.#117 rdx Kill Keep rdx | | | | | | | | | | | | | | | 107.#118 r8 Kill Keep r8 | | | | | | | | | | | | | | | 107.#119 r9 Kill Keep r9 | | | | | | | | | | | | | | | 107.#120 r10 Kill Keep r10 | | | | | | | | | | | | | | | 107.#121 r11 Kill Keep r11 | | | | | | | | | | | | | | | 107.#122 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 107.#123 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 107.#124 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 107.#125 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 107.#126 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 107.#127 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | 115.#128 C21 Def Alloc rcx | |C21a| | | | | | | | | | | | | 116.#129 C21 Use * Keep rcx | |C21i| | | | | | | | | | | | | 117.#130 I22 Def Alloc rcx | |I22a| | | | | | | | | | | | | 118.#131 rcx Fixd Keep rcx | |I22a| | | | | | | | | | | | | 118.#132 I22 Use * Keep rcx | |I22i| | | | | | | | | | | | | 119.#133 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 119.#134 I23 Def Alloc rcx | |I23a| | | | | | | | | | | | | 120.#135 rcx Fixd Keep rcx | |I23a| | | | | | | | | | | | | 120.#136 I23 Use * Keep rcx | |I23i| | | | | | | | | | | | | 121.#137 rax Kill Keep rax | | | | | | | | | | | | | | | 121.#138 rcx Kill Keep rcx | | | | | | | | | | | | | | | 121.#139 rdx Kill Keep rdx | | | | | | | | | | | | | | | 121.#140 r8 Kill Keep r8 | | | | | | | | | | | | | | | 121.#141 r9 Kill Keep r9 | | | | | | | | | | | | | | | 121.#142 r10 Kill Keep r10 | | | | | | | | | | | | | | | 121.#143 r11 Kill Keep r11 | | | | | | | | | | | | | | | 121.#144 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 121.#145 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 121.#146 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 121.#147 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 121.#148 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 121.#149 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | 129.#150 C24 Def Alloc rcx | |C24a| | | | | | | | | | | | | 130.#151 C24 Use * Keep rcx | |C24i| | | | | | | | | | | | | 131.#152 I25 Def Alloc rcx | |I25a| | | | | | | | | | | | | 134.#153 I25 Use * Keep rcx | |I25i| | | | | | | | | | | | | 135.#154 I26 Def Alloc mm0 | | | | | | | | | |I26a| | | | | 136.#155 I26 Use * Keep mm0 | | | | | | | | | |I26i| | | | | 139.#156 I27 Def Alloc rcx | |I27a| | | | | | | | | | | | | 140.#157 I27 Use * Keep rcx | |I27i| | | | | | | | | | | | | 143.#158 I28 Def Alloc rcx | |I28a| | | | | | | | | | | | | 144.#159 I28 Use * Keep rcx | |I28i| | | | | | | | | | | | | 147.#160 I29 Def Alloc rcx | |I29a| | | | | | | | | | | | | 150.#161 I29 Use * Keep rcx | |I29i| | | | | | | | | | | | | 151.#162 I30 Def Alloc rcx | |I30a| | | | | | | | | | | | | 152.#163 rcx Fixd Keep rcx | |I30a| | | | | | | | | | | | | 152.#164 I30 Use * Keep rcx | |I30i| | | | | | | | | | | | | 153.#165 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 153.#166 I31 Def Alloc rcx | |I31a| | | | | | | | | | | | | 154.#167 rcx Fixd Keep rcx | |I31a| | | | | | | | | | | | | 154.#168 I31 Use * Keep rcx | |I31i| | | | | | | | | | | | | 155.#169 rax Kill Keep rax | | | | | | | | | | | | | | | 155.#170 rcx Kill Keep rcx | | | | | | | | | | | | | | | 155.#171 rdx Kill Keep rdx | | | | | | | | | | | | | | | 155.#172 r8 Kill Keep r8 | | | | | | | | | | | | | | | 155.#173 r9 Kill Keep r9 | | | | | | | | | | | | | | | 155.#174 r10 Kill Keep r10 | | | | | | | | | | | | | | | 155.#175 r11 Kill Keep r11 | | | | | | | | | | | | | | | 155.#176 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 155.#177 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 155.#178 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 155.#179 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 155.#180 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 155.#181 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | 155.#182 rax Fixd Keep rax | | | | | | | | | | | | | | | 155.#183 I32 Def Alloc rax |I32a| | | | | | | | | | | | | | 156.#184 I32 Use * Keep rax |I32i| | | | | | | | | | | | | | 161.#185 I33 Def Alloc rcx | |I33a| | | | | | | | | | | | | 162.#186 I33 Use * Keep rcx | |I33i| | | | | | | | | | | | | 165.#187 I34 Def Alloc mm0 | | | | | | | | | |I34a| | | | | 166.#188 I34 Use * Keep mm0 | | | | | | | | | |I34i| | | | | 169.#189 I35 Def Alloc rcx | |I35a| | | | | | | | | | | | | 170.#190 rcx Fixd Keep rcx | |I35a| | | | | | | | | | | | | 170.#191 I35 Use * Keep rcx | |I35i| | | | | | | | | | | | | 171.#192 rcx Fixd Keep rcx | | | | | | | | | | | | | | | 171.#193 I36 Def Alloc rcx | |I36a| | | | | | | | | | | | | 173.#194 I37 Def Alloc rdx | |I36a|I37a| | | | | | | | | | | | 174.#195 rdx Fixd Keep rdx | |I36a|I37a| | | | | | | | | | | | 174.#196 I37 Use * Keep rdx | |I36a|I37i| | | | | | | | | | | | 175.#197 rdx Fixd Keep rdx | |I36a| | | | | | | | | | | | | 175.#198 I38 Def Alloc rdx | |I36a|I38a| | | | | | | | | | | | 177.#199 C39 Def Alloc r9 | |I36a|I38a| | | | | |C39a| | | | | | 178.#200 C39 Use * Keep r9 | |I36a|I38a| | | | | |C39i| | | | | | 179.#201 I40 Def Alloc r9 | |I36a|I38a| | | | | |I40a| | | | | | 180.#202 r9 Fixd Keep r9 | |I36a|I38a| | | | | |I40a| | | | | | 180.#203 I40 Use * Keep r9 | |I36a|I38a| | | | | |I40i| | | | | | 181.#204 r9 Fixd Keep r9 | |I36a|I38a| | | | | | | | | | | | 181.#205 I41 Def Alloc r9 | |I36a|I38a| | | | | |I41a| | | | | | 183.#206 I42 Def Alloc r8 | |I36a|I38a| | | | |I42a|I41a| | | | | | 184.#207 r8 Fixd Keep r8 | |I36a|I38a| | | | |I42a|I41a| | | | | | 184.#208 I42 Use * Keep r8 | |I36a|I38a| | | | |I42i|I41a| | | | | | 185.#209 r8 Fixd Keep r8 | |I36a|I38a| | | | | |I41a| | | | | | 185.#210 I43 Def Alloc r8 | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#211 rcx Fixd Keep rcx | |I36a|I38a| | | | |I43a|I41a| | | | | | 186.#212 I36 Use * Keep rcx | |I36i|I38a| | | | |I43a|I41a| | | | | | 186.#213 rdx Fixd Keep rdx | | |I38a| | | | |I43a|I41a| | | | | | 186.#214 I38 Use * Keep rdx | | |I38i| | | | |I43a|I41a| | | | | | 186.#215 r9 Fixd Keep r9 | | | | | | | |I43a|I41a| | | | | | 186.#216 I41 Use * Keep r9 | | | | | | | |I43a|I41i| | | | | | 186.#217 r8 Fixd Keep r8 | | | | | | | |I43a| | | | | | | 186.#218 I43 Use * Keep r8 | | | | | | | |I43i| | | | | | | 187.#219 rax Kill Keep rax | | | | | | | | | | | | | | | 187.#220 rcx Kill Keep rcx | | | | | | | | | | | | | | | 187.#221 rdx Kill Keep rdx | | | | | | | | | | | | | | | 187.#222 r8 Kill Keep r8 | | | | | | | | | | | | | | | 187.#223 r9 Kill Keep r9 | | | | | | | | | | | | | | | 187.#224 r10 Kill Keep r10 | | | | | | | | | | | | | | | 187.#225 r11 Kill Keep r11 | | | | | | | | | | | | | | | 187.#226 mm0 Kill Keep mm0 | | | | | | | | | | | | | | | 187.#227 mm1 Kill Keep mm1 | | | | | | | | | | | | | | | 187.#228 mm2 Kill Keep mm2 | | | | | | | | | | | | | | | 187.#229 mm3 Kill Keep mm3 | | | | | | | | | | | | | | | 187.#230 mm4 Kill Keep mm4 | | | | | | | | | | | | | | | 187.#231 mm5 Kill Keep mm5 | | | | | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 5 Total Reg Cand Vars: 0 Total number of Intervals: 43 Total number of RefPositions: 231 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: BB01 [???..???), preds={} succs={BB02} ===== N002. NOP BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N006. CNS_INT(h) 0x7ff826874428 token REG NA N008. IND N010. CNS_INT 0 REG NA N012. EQ N014. JTRUE BB03 [???..???), preds={BB02} succs={BB04} ===== N018. CALL help BB04 [???..???), preds={BB02,BB03} succs={BB05} ===== BB05 [000..05D) (return), preds={BB04} succs={} ===== N024. IL_OFFSET IL offset: 0x0 REG NA N026. NO_OP REG NA N028. IL_OFFSET IL offset: 0x1 REG NA N030. rcx = CNS_INT(h) 0x99BB9538 "ClsVarScenario" REG rcx N032. rcx = IND ; rcx N034. rcx = PUTARG_REG; rcx N036. CALL ; rcx N038. IL_OFFSET IL offset: 0xb REG NA N040. NO_OP REG NA N042. IL_OFFSET IL offset: 0xc REG NA N044. rcx* = CNS_INT(h) 0x1c599bb5f78 static Fseq[_clsVar] REG rcx N046. rcx = IND ; rcx* N048. STK = LEA(b+8) ; rcx N050. mm0 = IND ; STK N052. CNS_INT 1 REG NA N054. mm0 = HWIntrinsic; mm0 N056. V02 MEM; mm0 N058. IL_OFFSET IL offset: 0x17 REG NA N060. mm0 = V02 MEM N062. V01 MEM; mm0 N064. IL_OFFSET IL offset: 0x18 REG NA N066. rcx = CNS_INT(h) 0x99BB9538 "ClsVarScenario" REG rcx N068. rcx = IND ; rcx N070. rcx = PUTARG_REG; rcx N072. CALL ; rcx N074. IL_OFFSET IL offset: 0x22 REG NA N076. NO_OP REG NA N078. IL_OFFSET IL offset: 0x23 REG NA N080. rcx = V00 MEM N082. NULLCHECK; rcx N084. rcx = V00 MEM N086. CNS_INT 32 field offset Fseq[_dataTable] REG NA N088. rcx = ADD ; rcx N090. rcx = PUTARG_REG; rcx N092. rax = CALL ; rcx N094. V03 MEM; rax N096. IL_OFFSET IL offset: 0x2e REG NA N098. rcx = V03 MEM N100. rcx = PUTARG_REG; rcx N102. mm1 = V01 MEM N104. mm1 = PUTARG_REG; mm1 N106. CALL ; rcx,mm1 N108. IL_OFFSET IL offset: 0x34 REG NA N110. NO_OP REG NA N112. IL_OFFSET IL offset: 0x35 REG NA N114. rcx = CNS_INT(h) 0x99BB9538 "ClsVarScenario" REG rcx N116. rcx = IND ; rcx N118. rcx = PUTARG_REG; rcx N120. CALL ; rcx N122. IL_OFFSET IL offset: 0x3f REG NA N124. NO_OP REG NA N126. IL_OFFSET IL offset: 0x40 REG NA N128. rcx* = CNS_INT(h) 0x1c599bb5f78 static Fseq[_clsVar] REG rcx N130. rcx = IND ; rcx* N132. STK = LEA(b+8) ; rcx N134. mm0 = IND ; STK N136. V04 MEM; mm0 N138. rcx = V00 MEM N140. V05 MEM; rcx N142. rcx = V00 MEM N144. NULLCHECK; rcx N146. rcx = V00 MEM N148. CNS_INT 32 field offset Fseq[_dataTable] REG NA N150. rcx = ADD ; rcx N152. rcx = PUTARG_REG; rcx N154. rax = CALL ; rcx N156. V06 MEM; rax N158. IL_OFFSET IL offset: 0x51 REG NA N160. rcx = V05 MEM N162. V08 MEM; rcx N164. mm0 = V04 MEM N166. V07 MEM; mm0 N168. rcx = V08 MEM N170. rcx = PUTARG_REG; rcx N172. rdx = LCL_VAR_ADDR V07 tmp5 rdx REG rdx N174. rdx = PUTARG_REG; rdx N176. r9 = CNS_INT(h) 0x99BB9540 "RunClsVarScenario" REG r9 N178. r9 = IND ; r9 N180. r9 = PUTARG_REG; r9 N182. r8 = V06 MEM N184. r8 = PUTARG_REG; r8 N186. CALL ; rcx,rdx,r9,r8 N188. IL_OFFSET IL offset: 0x5b REG NA N190. NO_OP REG NA N192. IL_OFFSET IL offset: 0x5c REG NA N194. RETURN *************** In genGenerateCode() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [???..???) i internal label target LIR BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR BB03 [0004] 1 BB02 0.50 [???..???) internal LIR BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR BB05 [0001] 1 BB04 1 [000..05D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Finalizing stack frame Marking regs modified: [rdi] ([rax rcx rdx r8-r11 mm0-mm5] => [rax rcx rdx rdi r8-r11 mm0-mm5]) Marking regs modified: [rsi] ([rax rcx rdx rdi r8-r11 mm0-mm5] => [rax rcx rdx rsi rdi r8-r11 mm0-mm5]) Modified regs: [rax rcx rdx rsi rdi r8-r11 mm0-mm5] Callee-saved registers pushed: 2 [rsi rdi] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V01 loc0, size=4, stkOffs=-0x24 Assign V02 tmp0, size=4, stkOffs=-0x28 Assign V03 tmp1, size=8, stkOffs=-0x30 Pad V04 tmp2, size=16, stkOffs=-0x30, pad=0 Assign V04 tmp2, size=16, stkOffs=-0x40 Assign V05 tmp3, size=8, stkOffs=-0x48 Assign V06 tmp4, size=8, stkOffs=-0x50 Pad V07 tmp5, size=16, stkOffs=-0x50, pad=0 Assign V07 tmp5, size=16, stkOffs=-0x60 Assign V08 tmp6, size=8, stkOffs=-0x68 Assign V09 OutArgs, size=32, stkOffs=-0x88 ; Final local variable assignments ; ; V00 this [V00 ] ( 7, 7 ) ref -> [rbp+0x10] do-not-enreg[] this class-hnd ; V01 loc0 [V01,T04] ( 2, 2 ) float -> [rbp-0x14] do-not-enreg[] must-init ; V02 tmp0 [V02,T03] ( 2, 4 ) float -> [rbp-0x18] do-not-enreg[] must-init ; V03 tmp1 [V03,T00] ( 2, 4 ) long -> [rbp-0x20] do-not-enreg[] must-init ; V04 tmp2 [V04,T01] ( 2, 4 ) simd16 -> [rbp-0x30] do-not-enreg[SB] must-init ; V05 tmp3 [V05 ] ( 2, 4 ) ref -> [rbp-0x38] do-not-enreg[] must-init class-hnd ; V06 tmp4 [V06,T02] ( 2, 4 ) long -> [rbp-0x40] do-not-enreg[] must-init ; V07 tmp5 [V07 ] ( 3, 6 ) simd16 -> [rbp-0x50] do-not-enreg[XSB] addr-exposed ; V08 tmp6 [V08 ] ( 2, 4 ) ref -> [rbp-0x58] do-not-enreg[] must-init ; V09 OutArgs [V09 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] do-not-enreg[] ; ; Lcl frame size = 112 =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.40030060: i internal label target LIR BB01 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap Change life 0000000000000000 {} -> 000000000000001F {V01 V02 V03 V04 V06} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M3588_BB01: Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Setting stack level from -572662307 to 0 Scope info: begin block BB01, IL range [???..???) Scope info: ignoring block beginning Generating: N002 ( 0, 0) [000000] ------------ NOP void REG NA Scope info: end block BB01, IL range [???..???) Scope info: ignoring block end =============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40000040: internal LIR BB02 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap Liveness not changing: 000000000000001F {V01 V02 V03 V04 V06} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M3588_BB02: Scope info: begin block BB02, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M3588_IG02,ins#0,ofs#0) label Generating: N006 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x7ff826874428 token REG NA /--* t85 long Generating: N008 ( 5, 12) [000086] xc---------- t86 = * IND int REG NA Generating: N010 ( 1, 1) [000087] -c---------- t87 = CNS_INT int 0 REG NA /--* t86 int +--* t87 int Generating: N012 ( 7, 14) [000088] J------N---- * EQ void REG NA IN0001: cmp dword ptr [(reloc 0x7ff826874428)], 0 Generating: N014 ( 9, 16) [000145] ------------ * JTRUE void REG NA IN0002: je L_M3588_BB04 Scope info: end block BB02, IL range [???..???) Scope info: ignoring block end =============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x00000000.40000040: internal LIR BB03 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap Liveness not changing: 000000000000001F {V01 V02 V03 V04 V06} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M3588_BB03: Scope info: begin block BB03, IL range [???..???) Scope info: ignoring block beginning genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Generating: N018 ( 14, 5) [000089] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0003: call CORINFO_HELP_DBG_IS_JUST_MY_CODE Scope info: end block BB03, IL range [???..???) Scope info: ignoring block end =============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x00000000.40030060: i internal label target LIR BB04 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap Liveness not changing: 000000000000001F {V01 V02 V03 V04 V06} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M3588_BB04: G_M3588_IG02: ; offs=000000H, funclet=00 Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB04, IL range [???..???) Scope info: ignoring block beginning genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Scope info: end block BB04, IL range [???..???) Scope info: ignoring block end =============== Generating BB05 [000..05D) (return), preds={BB04} succs={} flags=0x00000000.40080420: i gcsafe LIR BB05 IN (5)={V03 V04 V06 V02 V01} + ByrefExposed + GcHeap OUT(1)={ V01} + ByrefExposed + GcHeap Liveness not changing: 000000000000001F {V01 V02 V03 V04 V06} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M3588_BB05: Scope info: begin block BB05, IL range [000..05D) Scope info: opening scope, LVnum=1 [000..05D) Scope info: >> new scope, VarNum=1, tracked? yes, VarIndex=4, bbLiveIn=000000000000001F {V01 V02 V03 V04 V06} Scope info: opening scope, LVnum=0 [000..05D) Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=000000000000001F {V01 V02 V03 V04 V06} Scope info: open scopes = 1 (V01 loc0) [000..05D) 0 (V00 this) [000..05D) Added IP mapping: 0x0000 STACK_EMPTY (G_M3588_IG03,ins#0,ofs#0) label Generating: N024 ( 1, 1) [000004] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N026 ( 1, 1) [000003] ------------ NO_OP void REG NA IN0004: nop Added IP mapping: 0x0001 STACK_EMPTY (G_M3588_IG03,ins#1,ofs#1) Generating: N028 ( 19, 18) [000008] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N030 ( 3, 10) [000094] ------------ t94 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG rcx IN0005: mov rcx, 0x1C599BB9538 /--* t94 long Generating: N032 ( 5, 12) [000095] x---G------- t95 = * IND ref REG rcx IN0006: mov rcx, gword ptr [rcx] GC regs: 00000000 {} => 00000002 {rcx} /--* t95 ref Generating: N034 (???,???) [000148] ----G------- t148 = * PUTARG_REG ref REG rcx GC regs: 00000002 {rcx} => 00000000 {} GC regs: 00000000 {} => 00000002 {rcx} /--* t148 ref arg0 in rcx Generating: N036 ( 19, 18) [000006] --CXG------- * CALL void System.Console.WriteLine GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x0006 CALL_INSTRUCTION (G_M3588_IG03,ins#3,ofs#14) IN0007: call System.Console:WriteLine(ref) Added IP mapping: 0x000B STACK_EMPTY (G_M3588_IG03,ins#4,ofs#19) Generating: N038 ( 1, 1) [000010] ------------ IL_OFFSET void IL offset: 0xb REG NA Generating: N040 ( 1, 1) [000009] ------------ NO_OP void REG NA IN0008: nop Added IP mapping: 0x000C STACK_EMPTY (G_M3588_IG03,ins#5,ofs#20) Generating: N042 ( 19, 25) [000019] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N044 ( 3, 10) [000098] ------------ t98 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] REG rcx IN0009: mov rcx, 0x1C599BB5F78 /--* t98 long Generating: N046 ( 5, 12) [000011] x---G------- t11 = * IND ref REG rcx IN000a: mov rcx, gword ptr [rcx] GC regs: 00000000 {} => 00000002 {rcx} /--* t11 ref Generating: N048 (???,???) [000149] -c---------- t149 = * LEA(b+8) byref REG NA /--* t149 byref Generating: N050 ( 13, 18) [000014] ---XG------- t14 = * IND simd16 REG mm0 GC regs: 00000002 {rcx} => 00000000 {} IN000b: vmovupd xmm0, xmmword ptr [rcx+8] Generating: N052 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 1 REG NA /--* t14 simd16 +--* t15 int Generating: N054 ( 15, 20) [000016] ---XG------- t16 = * HWIntrinsic float float Extract REG mm0 IN000c: vextractps xmm0, ecx, 1 IN000d: vmovd xmm0, ecx /--* t16 float Generating: N056 ( 19, 25) [000018] DA-XG------- * STORE_LCL_VAR float V02 tmp0 NA REG NA IN000e: vmovss dword ptr [V02 rbp-18H], xmm0 Added IP mapping: 0x0017 (G_M3588_IG03,ins#11,ofs#56) Generating: N058 ( 7, 9) [000023] ------------ IL_OFFSET void IL offset: 0x17 REG NA Generating: N060 ( 3, 4) [000020] ------------ t20 = LCL_VAR float V02 tmp0 mm0 REG mm0 IN000f: vmovss xmm0, dword ptr [V02 rbp-18H] /--* t20 float Generating: N062 ( 7, 9) [000022] DA---------- * STORE_LCL_VAR float V01 loc0 NA REG NA IN0010: vmovss dword ptr [V01 rbp-14H], xmm0 Added IP mapping: 0x0018 STACK_EMPTY (G_M3588_IG03,ins#13,ofs#68) Generating: N064 ( 19, 18) [000027] ------------ IL_OFFSET void IL offset: 0x18 REG NA Generating: N066 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG rcx IN0011: mov rcx, 0x1C599BB9538 /--* t99 long Generating: N068 ( 5, 12) [000100] x---G------- t100 = * IND ref REG rcx IN0012: mov rcx, gword ptr [rcx] GC regs: 00000000 {} => 00000002 {rcx} /--* t100 ref Generating: N070 (???,???) [000150] ----G------- t150 = * PUTARG_REG ref REG rcx GC regs: 00000002 {rcx} => 00000000 {} GC regs: 00000000 {} => 00000002 {rcx} /--* t150 ref arg0 in rcx Generating: N072 ( 19, 18) [000025] --CXG------- * CALL void System.Console.WriteLine GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x001D CALL_INSTRUCTION (G_M3588_IG03,ins#15,ofs#81) IN0013: call System.Console:WriteLine(ref) Added IP mapping: 0x0022 STACK_EMPTY (G_M3588_IG03,ins#16,ofs#86) Generating: N074 ( 1, 1) [000029] ------------ IL_OFFSET void IL offset: 0x22 REG NA Generating: N076 ( 1, 1) [000028] ------------ NO_OP void REG NA IN0014: nop Added IP mapping: 0x0023 STACK_EMPTY (G_M3588_IG03,ins#17,ofs#87) Generating: N078 ( 27, 17) [000036] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N080 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V00 this rcx REG rcx IN0015: mov rcx, gword ptr [V00 rbp+10H] GC regs: 00000000 {} => 00000002 {rcx} /--* t103 ref Generating: N082 ( 4, 3) [000104] ---X---N---- * NULLCHECK byte REG NA GC regs: 00000002 {rcx} => 00000000 {} IN0016: cmp dword ptr [rcx], ecx Generating: N084 ( 3, 2) [000105] ------------ t105 = LCL_VAR ref V00 this rcx REG rcx IN0017: mov rcx, gword ptr [V00 rbp+10H] GC regs: 00000000 {} => 00000002 {rcx} Generating: N086 ( 1, 1) [000106] -c---------- t106 = CNS_INT long 32 field offset Fseq[_dataTable] REG NA /--* t105 ref +--* t106 long Generating: N088 ( 5, 4) [000107] ------------ t107 = * ADD byref REG rcx GC regs: 00000002 {rcx} => 00000000 {} IN0018: add rcx, 32 Byref regs: 00000000 {} => 00000002 {rcx} /--* t107 byref Generating: N090 (???,???) [000151] ------------ t151 = * PUTARG_REG byref REG rcx Byref regs: 00000002 {rcx} => 00000000 {} Byref regs: 00000000 {} => 00000002 {rcx} /--* t151 byref this in rcx Generating: N092 ( 23, 14) [000033] --CXG------- t33 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr Byref regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x0029 CALL_INSTRUCTION (G_M3588_IG03,ins#21,ofs#101) IN0019: call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single]:get_outArrayPtr():long:this /--* t33 long Generating: N094 ( 27, 17) [000035] DA-XG------- * STORE_LCL_VAR long V03 tmp1 NA REG NA IN001a: mov qword ptr [V03 rbp-20H], rax Added IP mapping: 0x002E (G_M3588_IG03,ins#23,ofs#110) Generating: N096 ( 20, 13) [000042] ------------ IL_OFFSET void IL offset: 0x2e REG NA Generating: N098 ( 3, 2) [000037] ------------ t37 = LCL_VAR long V03 tmp1 rcx REG rcx IN001b: mov rcx, qword ptr [V03 rbp-20H] /--* t37 long Generating: N100 (???,???) [000152] ------------ t152 = * PUTARG_REG long REG rcx Generating: N102 ( 3, 4) [000038] ------------ t38 = LCL_VAR float V01 loc0 mm1 REG mm1 IN001c: vmovss xmm1, dword ptr [V01 rbp-14H] /--* t38 float Generating: N104 (???,???) [000153] ------------ t153 = * PUTARG_REG float REG mm1 /--* t152 long arg0 in rcx +--* t153 float arg1 in mm1 Generating: N106 ( 20, 13) [000039] --CXG------- * CALL void System.Runtime.CompilerServices.Unsafe.Write Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x002F CALL_INSTRUCTION (G_M3588_IG03,ins#25,ofs#120) IN001d: call System.Runtime.CompilerServices.Unsafe:Write(long,float) Added IP mapping: 0x0034 STACK_EMPTY (G_M3588_IG03,ins#26,ofs#125) Generating: N108 ( 1, 1) [000044] ------------ IL_OFFSET void IL offset: 0x34 REG NA Generating: N110 ( 1, 1) [000043] ------------ NO_OP void REG NA IN001e: nop Added IP mapping: 0x0035 STACK_EMPTY (G_M3588_IG03,ins#27,ofs#126) Generating: N112 ( 19, 18) [000048] ------------ IL_OFFSET void IL offset: 0x35 REG NA Generating: N114 ( 3, 10) [000116] ------------ t116 = CNS_INT(h) long 0x99BB9538 "ClsVarScenario" REG rcx IN001f: mov rcx, 0x1C599BB9538 /--* t116 long Generating: N116 ( 5, 12) [000117] x---G------- t117 = * IND ref REG rcx IN0020: mov rcx, gword ptr [rcx] GC regs: 00000000 {} => 00000002 {rcx} /--* t117 ref Generating: N118 (???,???) [000154] ----G------- t154 = * PUTARG_REG ref REG rcx GC regs: 00000002 {rcx} => 00000000 {} GC regs: 00000000 {} => 00000002 {rcx} /--* t154 ref arg0 in rcx Generating: N120 ( 19, 18) [000046] --CXG------- * CALL void System.Console.WriteLine GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x003A CALL_INSTRUCTION (G_M3588_IG03,ins#29,ofs#139) IN0021: call System.Console:WriteLine(ref) Added IP mapping: 0x003F STACK_EMPTY (G_M3588_IG03,ins#30,ofs#144) Generating: N122 ( 1, 1) [000050] ------------ IL_OFFSET void IL offset: 0x3f REG NA Generating: N124 ( 1, 1) [000049] ------------ NO_OP void REG NA IN0022: nop Added IP mapping: 0x0040 STACK_EMPTY (G_M3588_IG03,ins#31,ofs#145) Generating: N126 ( 14, 19) [000063] ------------ IL_OFFSET void IL offset: 0x40 REG NA Generating: N128 ( 3, 10) [000120] ------------ t120 = CNS_INT(h) long 0x1c599bb5f78 static Fseq[_clsVar] REG rcx IN0023: mov rcx, 0x1C599BB5F78 /--* t120 long Generating: N130 ( 5, 12) [000052] x---G------- t52 = * IND ref REG rcx IN0024: mov rcx, gword ptr [rcx] GC regs: 00000000 {} => 00000002 {rcx} /--* t52 ref Generating: N132 (???,???) [000155] -c---------- t155 = * LEA(b+8) byref REG NA /--* t155 byref Generating: N134 ( 10, 16) [000055] ---XG------- t55 = * IND simd16 REG mm0 GC regs: 00000002 {rcx} => 00000000 {} IN0025: vmovupd xmm0, xmmword ptr [rcx+8] /--* t55 simd16 Generating: N136 ( 14, 19) [000062] DA-XG------- * STORE_LCL_VAR simd16 V04 tmp2 NA REG NA IN0026: vmovapd xmmword ptr [V04 rbp-30H], xmm0 Generating: N138 ( 3, 2) [000051] ------------ t51 = LCL_VAR ref V00 this rcx REG rcx IN0027: mov rcx, gword ptr [V00 rbp+10H] GC regs: 00000000 {} => 00000002 {rcx} /--* t51 ref Generating: N140 ( 7, 5) [000066] DA---------- * STORE_LCL_VAR ref V05 tmp3 NA REG NA GC regs: 00000002 {rcx} => 00000000 {} IN0028: mov gword ptr [V05 rbp-38H], rcx Generating: N142 ( 3, 2) [000121] ------------ t121 = LCL_VAR ref V00 this rcx REG rcx IN0029: mov rcx, gword ptr [V00 rbp+10H] GC regs: 00000000 {} => 00000002 {rcx} /--* t121 ref Generating: N144 ( 4, 3) [000122] ---X---N---- * NULLCHECK byte REG NA GC regs: 00000002 {rcx} => 00000000 {} IN002a: cmp dword ptr [rcx], ecx Generating: N146 ( 3, 2) [000123] ------------ t123 = LCL_VAR ref V00 this rcx REG rcx IN002b: mov rcx, gword ptr [V00 rbp+10H] GC regs: 00000000 {} => 00000002 {rcx} Generating: N148 ( 1, 1) [000124] -c---------- t124 = CNS_INT long 32 field offset Fseq[_dataTable] REG NA /--* t123 ref +--* t124 long Generating: N150 ( 5, 4) [000125] ------------ t125 = * ADD byref REG rcx GC regs: 00000002 {rcx} => 00000000 {} IN002c: add rcx, 32 Byref regs: 00000000 {} => 00000002 {rcx} /--* t125 byref Generating: N152 (???,???) [000156] ------------ t156 = * PUTARG_REG byref REG rcx Byref regs: 00000002 {rcx} => 00000000 {} Byref regs: 00000000 {} => 00000002 {rcx} /--* t156 byref this in rcx Generating: N154 ( 23, 14) [000059] --CXG------- t59 = * CALL long JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single].get_outArrayPtr Byref regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x004C CALL_INSTRUCTION (G_M3588_IG03,ins#41,ofs#192) IN002d: call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single]:get_outArrayPtr():long:this /--* t59 long Generating: N156 ( 27, 17) [000070] DA-XG------- * STORE_LCL_VAR long V06 tmp4 NA REG NA IN002e: mov qword ptr [V06 rbp-40H], rax Added IP mapping: 0x0051 (G_M3588_IG03,ins#43,ofs#201) Generating: N158 ( 45, 39) [000080] ------------ IL_OFFSET void IL offset: 0x51 REG NA Generating: N160 ( 3, 2) [000068] ------------ t68 = LCL_VAR ref V05 tmp3 rcx REG rcx IN002f: mov rcx, gword ptr [V05 rbp-38H] GC regs: 00000000 {} => 00000002 {rcx} /--* t68 ref Generating: N162 ( 7, 5) [000135] DA--------L- * STORE_LCL_VAR ref V08 tmp6 NA REG NA GC regs: 00000002 {rcx} => 00000000 {} IN0030: mov gword ptr [V08 rbp-58H], rcx Generating: N164 ( 3, 2) [000064] -------N---- t64 = LCL_VAR simd16 V04 tmp2 mm0 REG mm0 IN0031: vmovapd xmm0, xmmword ptr [V04 rbp-30H] /--* t64 simd16 Generating: N166 ( 7, 5) [000131] DA--------L- * STORE_LCL_VAR simd16(AX) V07 tmp5 NA REG NA IN0032: vmovapd xmmword ptr [V07 rbp-50H], xmm0 Generating: N168 ( 3, 2) [000136] ------------ t136 = LCL_VAR ref V08 tmp6 rcx REG rcx IN0033: mov rcx, gword ptr [V08 rbp-58H] GC regs: 00000000 {} => 00000002 {rcx} /--* t136 ref Generating: N170 (???,???) [000157] ------------ t157 = * PUTARG_REG ref REG rcx GC regs: 00000002 {rcx} => 00000000 {} GC regs: 00000000 {} => 00000002 {rcx} Generating: N172 ( 3, 2) [000138] -------N---- t138 = LCL_VAR_ADDR byref V07 tmp5 rdx REG rdx IN0034: lea rdx, bword ptr [V07 rbp-50H] Byref regs: 00000000 {} => 00000004 {rdx} /--* t138 byref Generating: N174 (???,???) [000158] ------------ t158 = * PUTARG_REG byref REG rdx Byref regs: 00000004 {rdx} => 00000000 {} Byref regs: 00000000 {} => 00000004 {rdx} Generating: N176 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x99BB9540 "RunClsVarScenario" REG r9 IN0035: mov r9, 0x1C599BB9540 /--* t132 long Generating: N178 ( 5, 12) [000133] x---G------- t133 = * IND ref REG r9 IN0036: mov r9, gword ptr [r9] GC regs: 00000002 {rcx} => 00000202 {rcx r9} /--* t133 ref Generating: N180 (???,???) [000159] ----G------- t159 = * PUTARG_REG ref REG r9 GC regs: 00000202 {rcx r9} => 00000002 {rcx} GC regs: 00000002 {rcx} => 00000202 {rcx r9} Generating: N182 ( 3, 2) [000072] ------------ t72 = LCL_VAR long V06 tmp4 r8 REG r8 IN0037: mov r8, qword ptr [V06 rbp-40H] /--* t72 long Generating: N184 (???,???) [000160] ------------ t160 = * PUTARG_REG long REG r8 /--* t157 ref this in rcx +--* t158 byref arg1 in rdx +--* t159 ref arg3 in r9 +--* t160 long arg2 in r8 Generating: N186 ( 45, 39) [000074] --CXG------- * CALL void JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1.ValidateResult GC regs: 00000202 {rcx r9} => 00000200 {r9} Byref regs: 00000004 {rdx} => 00000000 {} GC regs: 00000200 {r9} => 00000000 {} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Added IP mapping: 0x0056 CALL_INSTRUCTION (G_M3588_IG03,ins#52,ofs#246) IN0038: call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:ValidateResult(struct,long,ref):this Added IP mapping: 0x005B STACK_EMPTY (G_M3588_IG03,ins#53,ofs#251) Generating: N188 ( 1, 1) [000082] ------------ IL_OFFSET void IL offset: 0x5b REG NA Generating: N190 ( 1, 1) [000081] ------------ NO_OP void REG NA IN0039: nop Added IP mapping: 0x005C STACK_EMPTY (G_M3588_IG03,ins#54,ofs#252) Generating: N192 ( 0, 0) [000084] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N194 ( 0, 0) [000083] ------------ RETURN void REG NA IN003a: nop Scope info: end block BB05, IL range [000..05D) Scope info: ending scope, LVnum=1 [000..05D) Scope info: ending scope, LVnum=0 [000..05D) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M3588_IG03,ins#55,ofs#253) label Reserving epilog IG for block BB05 G_M3588_IG03: ; offs=000012H, funclet=00 *************** After placeholder IG creation G_M3588_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M3588_IG02: ; offs=000000H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M3588_IG03: ; offs=000012H, size=00FDH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M3588_IG04: ; epilog placeholder, next placeholder=, BB05 [0001], epilog, emitadd <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Change life 000000000000001F {V01 V02 V03 V04 V06} -> 0000000000000000 {} # compCycleEstimate = 252, compSizeEstimate = 225 JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this ; Final local variable assignments ; ; V00 this [V00 ] ( 7, 7 ) ref -> [rbp+0x10] do-not-enreg[] this class-hnd ; V01 loc0 [V01,T04] ( 2, 2 ) float -> [rbp-0x14] do-not-enreg[] must-init ; V02 tmp0 [V02,T03] ( 2, 4 ) float -> [rbp-0x18] do-not-enreg[] must-init ; V03 tmp1 [V03,T00] ( 2, 4 ) long -> [rbp-0x20] do-not-enreg[] must-init ; V04 tmp2 [V04,T01] ( 2, 4 ) simd16 -> [rbp-0x30] do-not-enreg[SB] must-init ; V05 tmp3 [V05 ] ( 2, 4 ) ref -> [rbp-0x38] do-not-enreg[] must-init class-hnd ; V06 tmp4 [V06,T02] ( 2, 4 ) long -> [rbp-0x40] do-not-enreg[] must-init ; V07 tmp5 [V07 ] ( 3, 6 ) simd16 -> [rbp-0x50] do-not-enreg[XSB] addr-exposed ; V08 tmp6 [V08 ] ( 2, 4 ) ref -> [rbp-0x58] do-not-enreg[] must-init ; V09 OutArgs [V09 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] do-not-enreg[] ; ; Lcl frame size = 112 *************** Before prolog / epilog generation G_M3588_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M3588_IG02: ; offs=000000H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M3588_IG03: ; offs=000012H, size=00FDH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M3588_IG04: ; epilog placeholder, next placeholder=, BB05 [0001], epilog, emitadd <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M3588_IG01,ins#0,ofs#0) label __prolog: Found 16 lvMustInit stk vars, frame offsets 88 through 16 IN003b: push rbp IN003c: push rdi IN003d: push rsi IN003e: sub rsp, 112 IN003f: vzeroupper IN0040: lea rbp, [rsp+80H] IN0041: mov rsi, rcx IN0042: lea rdi, [rbp-58H] IN0043: mov ecx, 18 IN0044: xor rax, rax IN0045: rep stosd IN0046: mov rcx, rsi *************** In genFnPrologCalleeRegArgs() for int regs IN0047: mov gword ptr [V00 rbp+10H], rcx *************** In genEnregisterIncomingStackArgs() G_M3588_IG01: ; offs=000000H, funclet=00 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN0048: lea rsp, [rbp-10H] IN0049: pop rsi IN004a: pop rdi IN004b: pop rbp IN004c: ret G_M3588_IG04: ; offs=00010FH, funclet=00 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M3588_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M3588_IG02: ; offs=000029H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M3588_IG03: ; offs=00003BH, size=00FDH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M3588_IG04: ; offs=000138H, size=0008H, epilog, nogc, emitadd *************** In emitJumpDistBind() Binding: IN0002: 000000 je L_M3588_BB04 Binding L_M3588_BB04 to G_M3588_IG03 Estimate of fwd jump [A1EBDE24/002]: 0030 -> 003B = 0009 Shrinking jump [A1EBDE24/002] Total shrinkage = 4, min extra jump size = 4294967295 Hot code size = 0x13C bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xc) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M3588_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN003b: 000000 55 push rbp IN003c: 000001 57 push rdi IN003d: 000002 56 push rsi IN003e: 000003 4883EC70 sub rsp, 112 IN003f: 000007 C5F877 vzeroupper IN0040: 00000A 488DAC2480000000 lea rbp, [rsp+80H] IN0041: 000012 488BF1 mov rsi, rcx IN0042: 000015 488D7DA8 lea rdi, [rbp-58H] IN0043: 000019 B912000000 mov ecx, 18 IN0044: 00001E 33C0 xor rax, rax IN0045: 000020 F3AB rep stosd IN0046: 000022 488BCE mov rcx, rsi IN0047: 000025 48894D10 mov gword ptr [rbp+10H], rcx G_M3588_IG02: ; func=00, offs=000029H, size=000EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz IN0001: 000029 833DB870EDFF00 cmp dword ptr [(reloc 0x7ff826874428)], 0 IN0002: 000030 7405 je SHORT G_M3588_IG03 [A1EBFBE8] ptr arg pop 0 IN0003: 000032 E899C8335F call CORINFO_HELP_DBG_IS_JUST_MY_CODE G_M3588_IG03: ; func=00, offs=000037H, size=00FDH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0004: 000037 90 nop IN0005: 000038 48B93895BB99C5010000 mov rcx, 0x1C599BB9538 gcrReg +[rcx] IN0006: 000042 488B09 mov rcx, gword ptr [rcx] New gcrReg live regs=00000000 {} gcrReg -[rcx] [A1EBFC48] ptr arg pop 0 IN0007: 000045 E84698FFFF call System.Console:WriteLine(ref) IN0008: 00004A 90 nop IN0009: 00004B 48B9785FBB99C5010000 mov rcx, 0x1C599BB5F78 gcrReg +[rcx] IN000a: 000055 488B09 mov rcx, gword ptr [rcx] IN000b: 000058 C4E179104108 vmovupd xmm0, xmmword ptr [rcx+8] IN000c: 00005E C4E37917C101 vextractps xmm0, ecx, 1 IN000d: 000064 C4E1796EC1 vmovd xmm0, ecx IN000e: 000069 C4E17A1145E8 vmovss dword ptr [rbp-18H], xmm0 IN000f: 00006F C4E17A1045E8 vmovss xmm0, dword ptr [rbp-18H] IN0010: 000075 C4E17A1145EC vmovss dword ptr [rbp-14H], xmm0 gcrReg -[rcx] IN0011: 00007B 48B93895BB99C5010000 mov rcx, 0x1C599BB9538 gcrReg +[rcx] IN0012: 000085 488B09 mov rcx, gword ptr [rcx] New gcrReg live regs=00000000 {} gcrReg -[rcx] [A1EBFD08] ptr arg pop 0 IN0013: 000088 E80398FFFF call System.Console:WriteLine(ref) IN0014: 00008D 90 nop gcrReg +[rcx] IN0015: 00008E 488B4D10 mov rcx, gword ptr [rbp+10H] IN0016: 000092 3909 cmp dword ptr [rcx], ecx IN0017: 000094 488B4D10 mov rcx, gword ptr [rbp+10H] gcrReg -[rcx] byrReg +[rcx] IN0018: 000098 4883C120 add rcx, 32 New byrReg live regs=00000000 {} byrReg -[rcx] [A1EBFDC8] ptr arg pop 0 IN0019: 00009C E86FD8FFFF call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single]:get_outArrayPtr():long:this IN001a: 0000A1 488945E0 mov qword ptr [rbp-20H], rax IN001b: 0000A5 488B4DE0 mov rcx, qword ptr [rbp-20H] IN001c: 0000A9 C4E17A104DEC vmovss xmm1, dword ptr [rbp-14H] [A1EBFE70] ptr arg pop 0 IN001d: 0000AF E8FCD8FFFF call System.Runtime.CompilerServices.Unsafe:Write(long,float) IN001e: 0000B4 90 nop IN001f: 0000B5 48B93895BB99C5010000 mov rcx, 0x1C599BB9538 gcrReg +[rcx] IN0020: 0000BF 488B09 mov rcx, gword ptr [rcx] New gcrReg live regs=00000000 {} gcrReg -[rcx] [A1EBFF10] ptr arg pop 0 IN0021: 0000C2 E8C997FFFF call System.Console:WriteLine(ref) IN0022: 0000C7 90 nop IN0023: 0000C8 48B9785FBB99C5010000 mov rcx, 0x1C599BB5F78 gcrReg +[rcx] IN0024: 0000D2 488B09 mov rcx, gword ptr [rcx] IN0025: 0000D5 C4E179104108 vmovupd xmm0, xmmword ptr [rcx+8] IN0026: 0000DB C4E1792945D0 vmovapd xmmword ptr [rbp-30H], xmm0 IN0027: 0000E1 488B4D10 mov rcx, gword ptr [rbp+10H] IN0028: 0000E5 48894DC8 mov gword ptr [rbp-38H], rcx IN0029: 0000E9 488B4D10 mov rcx, gword ptr [rbp+10H] IN002a: 0000ED 3909 cmp dword ptr [rcx], ecx IN002b: 0000EF 488B4D10 mov rcx, gword ptr [rbp+10H] gcrReg -[rcx] byrReg +[rcx] IN002c: 0000F3 4883C120 add rcx, 32 New byrReg live regs=00000000 {} byrReg -[rcx] [A1EBFFD0] ptr arg pop 0 IN002d: 0000F7 E814D8FFFF call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single]:get_outArrayPtr():long:this IN002e: 0000FC 488945C0 mov qword ptr [rbp-40H], rax gcrReg +[rcx] IN002f: 000100 488B4DC8 mov rcx, gword ptr [rbp-38H] IN0030: 000104 48894DA8 mov gword ptr [rbp-58H], rcx IN0031: 000108 C4E1792845D0 vmovapd xmm0, xmmword ptr [rbp-30H] IN0032: 00010E C4E1792945B0 vmovapd xmmword ptr [rbp-50H], xmm0 IN0033: 000114 488B4DA8 mov rcx, gword ptr [rbp-58H] byrReg +[rdx] IN0034: 000118 488D55B0 lea rdx, bword ptr [rbp-50H] IN0035: 00011C 49B94095BB99C5010000 mov r9, 0x1C599BB9540 gcrReg +[r9] IN0036: 000126 4D8B09 mov r9, gword ptr [r9] IN0037: 000129 4C8B45C0 mov r8, qword ptr [rbp-40H] New gcrReg live regs=00000000 {} gcrReg -[rcx] gcrReg -[r9] New byrReg live regs=00000000 {} byrReg -[rdx] [A1EC0138] ptr arg pop 0 IN0038: 00012D E8E6BCFFFF call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:ValidateResult(struct,long,ref):this IN0039: 000132 90 nop IN003a: 000133 90 nop G_M3588_IG04: ; func=00, offs=000134H, size=0008H, epilog, nogc, emitadd IN0048: 000134 488D65F0 lea rsp, [rbp-10H] IN0049: 000138 5E pop rsi IN004a: 000139 5F pop rdi IN004b: 00013A 5D pop rbp IN004c: 00013B C3 ret Allocated method code size = 316 , actual size = 316 *************** After end code gen, before unwindEmit() G_M3588_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN003b: 000000 push rbp IN003c: 000001 push rdi IN003d: 000002 push rsi IN003e: 000003 sub rsp, 112 IN003f: 000007 vzeroupper IN0040: 00000A lea rbp, [rsp+80H] IN0041: 000012 mov rsi, rcx IN0042: 000015 lea rdi, [rbp-58H] IN0043: 000019 mov ecx, 18 IN0044: 00001E xor rax, rax IN0045: 000020 rep stosd IN0046: 000022 mov rcx, rsi IN0047: 000025 mov gword ptr [V00 rbp+10H], rcx G_M3588_IG02: ; offs=000029H, size=000EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz IN0001: 000029 cmp dword ptr [(reloc 0x7ff826874428)], 0 IN0002: 000030 je SHORT G_M3588_IG03 IN0003: 000032 call CORINFO_HELP_DBG_IS_JUST_MY_CODE G_M3588_IG03: ; offs=000037H, size=00FDH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0004: 000037 nop IN0005: 000038 mov rcx, 0x1C599BB9538 IN0006: 000042 mov rcx, gword ptr [rcx] IN0007: 000045 call System.Console:WriteLine(ref) IN0008: 00004A nop IN0009: 00004B mov rcx, 0x1C599BB5F78 IN000a: 000055 mov rcx, gword ptr [rcx] IN000b: 000058 vmovupd xmm0, xmmword ptr [rcx+8] IN000c: 00005E vextractps xmm0, ecx, 1 IN000d: 000064 vmovd xmm0, ecx IN000e: 000069 vmovss dword ptr [V02 rbp-18H], xmm0 IN000f: 00006F vmovss xmm0, dword ptr [V02 rbp-18H] IN0010: 000075 vmovss dword ptr [V01 rbp-14H], xmm0 IN0011: 00007B mov rcx, 0x1C599BB9538 IN0012: 000085 mov rcx, gword ptr [rcx] IN0013: 000088 call System.Console:WriteLine(ref) IN0014: 00008D nop IN0015: 00008E mov rcx, gword ptr [V00 rbp+10H] IN0016: 000092 cmp dword ptr [rcx], ecx IN0017: 000094 mov rcx, gword ptr [V00 rbp+10H] IN0018: 000098 add rcx, 32 IN0019: 00009C call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single]:get_outArrayPtr():long:this IN001a: 0000A1 mov qword ptr [V03 rbp-20H], rax IN001b: 0000A5 mov rcx, qword ptr [V03 rbp-20H] IN001c: 0000A9 vmovss xmm1, dword ptr [V01 rbp-14H] IN001d: 0000AF call System.Runtime.CompilerServices.Unsafe:Write(long,float) IN001e: 0000B4 nop IN001f: 0000B5 mov rcx, 0x1C599BB9538 IN0020: 0000BF mov rcx, gword ptr [rcx] IN0021: 0000C2 call System.Console:WriteLine(ref) IN0022: 0000C7 nop IN0023: 0000C8 mov rcx, 0x1C599BB5F78 IN0024: 0000D2 mov rcx, gword ptr [rcx] IN0025: 0000D5 vmovupd xmm0, xmmword ptr [rcx+8] IN0026: 0000DB vmovapd xmmword ptr [V04 rbp-30H], xmm0 IN0027: 0000E1 mov rcx, gword ptr [V00 rbp+10H] IN0028: 0000E5 mov gword ptr [V05 rbp-38H], rcx IN0029: 0000E9 mov rcx, gword ptr [V00 rbp+10H] IN002a: 0000ED cmp dword ptr [rcx], ecx IN002b: 0000EF mov rcx, gword ptr [V00 rbp+10H] IN002c: 0000F3 add rcx, 32 IN002d: 0000F7 call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__DataTable`2[Single,Single][System.Single,System.Single]:get_outArrayPtr():long:this IN002e: 0000FC mov qword ptr [V06 rbp-40H], rax IN002f: 000100 mov rcx, gword ptr [V05 rbp-38H] IN0030: 000104 mov gword ptr [V08 rbp-58H], rcx IN0031: 000108 vmovapd xmm0, xmmword ptr [V04 rbp-30H] IN0032: 00010E vmovapd xmmword ptr [V07 rbp-50H], xmm0 IN0033: 000114 mov rcx, gword ptr [V08 rbp-58H] IN0034: 000118 lea rdx, bword ptr [V07 rbp-50H] IN0035: 00011C mov r9, 0x1C599BB9540 IN0036: 000126 mov r9, gword ptr [r9] IN0037: 000129 mov r8, qword ptr [V06 rbp-40H] IN0038: 00012D call JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:ValidateResult(struct,long,ref):this IN0039: 000132 nop IN003a: 000133 nop G_M3588_IG04: ; offs=000134H, size=0008H, epilog, nogc, emitadd IN0048: 000134 lea rsp, [rbp-10H] IN0049: 000138 pop rsi IN004a: 000139 pop rdi IN004b: 00013A pop rbp IN004c: 00013B ret Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x00013c (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x07 CountOfUnwindCodes: 4 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x07 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 13 * 8 + 8 = 112 = 0x70 CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00007FF82699D340, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x13c, unwindSize=0xc, pUnwindBlock=0x000001C587BDA0AC, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 26 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs NO_MAP : 0x00000029 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000037 ( STACK_EMPTY ) IL offs 0x0001 : 0x00000038 ( STACK_EMPTY ) IL offs 0x0006 : 0x00000045 ( CALL_INSTRUCTION ) IL offs 0x000B : 0x0000004A ( STACK_EMPTY ) IL offs 0x000C : 0x0000004B ( STACK_EMPTY ) IL offs 0x0017 : 0x0000006F IL offs 0x0018 : 0x0000007B ( STACK_EMPTY ) IL offs 0x001D : 0x00000088 ( CALL_INSTRUCTION ) IL offs 0x0022 : 0x0000008D ( STACK_EMPTY ) IL offs 0x0023 : 0x0000008E ( STACK_EMPTY ) IL offs 0x0029 : 0x0000009C ( CALL_INSTRUCTION ) IL offs 0x002E : 0x000000A5 IL offs 0x002F : 0x000000AF ( CALL_INSTRUCTION ) IL offs 0x0034 : 0x000000B4 ( STACK_EMPTY ) IL offs 0x0035 : 0x000000B5 ( STACK_EMPTY ) IL offs 0x003A : 0x000000C2 ( CALL_INSTRUCTION ) IL offs 0x003F : 0x000000C7 ( STACK_EMPTY ) IL offs 0x0040 : 0x000000C8 ( STACK_EMPTY ) IL offs 0x004C : 0x000000F7 ( CALL_INSTRUCTION ) IL offs 0x0051 : 0x00000100 IL offs 0x0056 : 0x0000012D ( CALL_INSTRUCTION ) IL offs 0x005B : 0x00000132 ( STACK_EMPTY ) IL offs 0x005C : 0x00000133 ( STACK_EMPTY ) IL offs EPILOG : 0x00000134 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 3 *************** Variable debug info 3 vars 0( UNKNOWN) : From 00000000h to 00000029h, in rcx 1( UNKNOWN) : From 00000037h to 00000134h, in rbp[-20] (1 slot) 0( UNKNOWN) : From 00000037h to 00000134h, in rbp[16] (1 slot) *************** In gcInfoBlockHdrSave() Set code length to 316. Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 32. Stack slot id for offset 16 (0x10) (frame) (untracked) = 0. Stack slot id for offset -56 (0xffffffc8) (frame) (untracked) = 1. Stack slot id for offset -88 (0xffffffa8) (frame) (untracked) = 2. Register slot id for reg rcx = 3. Register slot id for reg rcx (byref) = 4. Register slot id for reg rdx (byref) = 5. Register slot id for reg r9 = 6. Set state of slot 3 at instr offset 0x45 to Live. Set state of slot 3 at instr offset 0x4a to Dead. Set state of slot 3 at instr offset 0x58 to Live. Set state of slot 3 at instr offset 0x85 to Dead. Set state of slot 3 at instr offset 0x88 to Live. Set state of slot 3 at instr offset 0x8d to Dead. Set state of slot 3 at instr offset 0x92 to Live. Set state of slot 3 at instr offset 0x9c to Dead. Set state of slot 4 at instr offset 0x9c to Live. Set state of slot 4 at instr offset 0xa1 to Dead. Set state of slot 3 at instr offset 0xc2 to Live. Set state of slot 3 at instr offset 0xc7 to Dead. Set state of slot 3 at instr offset 0xd5 to Live. Set state of slot 3 at instr offset 0xf7 to Dead. Set state of slot 4 at instr offset 0xf7 to Live. Set state of slot 4 at instr offset 0xfc to Dead. Set state of slot 3 at instr offset 0x104 to Live. Set state of slot 5 at instr offset 0x11c to Live. Set state of slot 6 at instr offset 0x129 to Live. Set state of slot 3 at instr offset 0x132 to Dead. Set state of slot 6 at instr offset 0x132 to Dead. Set state of slot 5 at instr offset 0x132 to Dead. Defining interruptible range: [0x29, 0x134). Method code size: 316 Allocations for JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this (MethodHash=37eaf1fb) count: 1099, size: 87231, max = 2616 allocateMemory: 131072, nraUsed: 101552 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 0 | 0.00% ASTNode | 21200 | 24.30% InstDesc | 7156 | 8.20% ImpStack | 0 | 0.00% BasicBlock | 1984 | 2.27% fgArgInfo | 616 | 0.71% fgArgInfoPtrArr | 88 | 0.10% FlowList | 160 | 0.18% TreeStatementList | 0 | 0.00% SiScope | 200 | 0.23% FlatFPStateX87 | 0 | 0.00% DominatorMemory | 0 | 0.00% LSRA | 3568 | 4.09% LSRA_Interval | 3872 | 4.44% LSRA_RefPosition | 14848 | 17.02% Reachability | 0 | 0.00% SSA | 0 | 0.00% ValueNumber | 0 | 0.00% LvaTable | 2260 | 2.59% UnwindInfo | 0 | 0.00% hashBv | 216 | 0.25% bitset | 232 | 0.27% FixedBitVect | 0 | 0.00% Generic | 756 | 0.87% IndirAssignMap | 56 | 0.06% FieldSeqStore | 288 | 0.33% ZeroOffsetFieldMap | 56 | 0.06% ArrayInfoMap | 0 | 0.00% MemoryPhiArg | 0 | 0.00% CSE | 0 | 0.00% GC | 3660 | 4.20% CorSig | 728 | 0.83% Inlining | 0 | 0.00% ArrayStack | 0 | 0.00% DebugInfo | 1136 | 1.30% DebugOnly | 23623 | 27.08% Codegen | 0 | 0.00% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 528 | 0.61% RangeCheck | 0 | 0.00% CopyProp | 0 | 0.00% ****** DONE compiling JIT.HardwareIntrinsics.X86.SimpleUnaryOpTest__ExtractSingle1:RunClsVarScenario():this ClsVarScenario