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Update the bit field of encoding function names (#96082)
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* Update the bit field of encoding function names

* Fix merge conflicts

* update asserts as per review comments
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@kunalspathak
kunalspathak authored Dec 18, 2023
1 parent 187406e commit 435c323
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Showing 2 changed files with 40 additions and 40 deletions.
56 changes: 28 additions & 28 deletions src/coreclr/jit/emitarm64.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11616,7 +11616,7 @@ void emitter::emitIns_Call(EmitCallType callType,
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 31));
return ureg << 0;
}

Expand All @@ -11629,7 +11629,7 @@ void emitter::emitIns_Call(EmitCallType callType,
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 31));
return ureg << 5;
}

Expand All @@ -11648,28 +11648,28 @@ void emitter::emitIns_Call(EmitCallType callType,

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '21' thru '17' position.
* Return an encoding for the specified 'V' register used in '20' thru '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_21_to_17(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_V_20_to_16(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
assert((ureg >= 0) && (ureg <= 31));
return ureg << 16;
}

/*****************************************************************************
*
* Return an encoding for the specified 'R' register used in '21' thru '17' position.
* Return an encoding for the specified 'R' register used in '20' thru '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_R_21_to_17(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_R_20_to_16(regNumber reg)
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
assert((ureg >= 0) && (ureg <= 31));
return ureg << 16;
}

/*****************************************************************************
Expand All @@ -11681,7 +11681,7 @@ void emitter::emitIns_Call(EmitCallType callType,
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 31));
return ureg << 5;
}

Expand All @@ -11694,21 +11694,21 @@ void emitter::emitIns_Call(EmitCallType callType,
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 31));
return ureg << 0;
}

/*****************************************************************************
*
* Return an encoding for the specified 'P' register used in '20' thru '17' position.
* Return an encoding for the specified 'P' register used in '19' thru '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_P_20_to_17(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_P_19_to_16(regNumber reg)
{
assert(isPredicateRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_P0;
assert((ureg >= 0) && (ureg <= 15));
return ureg << 17;
return ureg << 16;
}

/*****************************************************************************
Expand Down Expand Up @@ -11752,15 +11752,15 @@ void emitter::emitIns_Call(EmitCallType callType,

/*****************************************************************************
*
* Return an encoding for the specified 'R' register used in '18' thru '17' position.
* Return an encoding for the specified 'R' register used in '17' thru '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_R_18_to_17(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_R_17_to_16(regNumber reg)
{
assert(isIntegerRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
assert((ureg >= 0) && (ureg <= 31));
return ureg << 16;
}

/*****************************************************************************
Expand Down Expand Up @@ -11814,27 +11814,27 @@ void emitter::emitIns_Call(EmitCallType callType,

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '19' thru '17' position.
* Return an encoding for the specified 'V' register used in '18' thru '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_19_to_17(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_V_18_to_16(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
return ureg << 17;
assert((ureg >= 0) && (ureg <= 7));
return ureg << 16;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '20' thru '16' position.
* Return an encoding for the specified 'V' register used in '19' thru '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodeReg_V_20_to_16(regNumber reg)
/*static*/ emitter::code_t emitter::insEncodeReg_V_19_to_16(regNumber reg)
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 15));
return ureg << 16;
}

Expand All @@ -11847,7 +11847,7 @@ void emitter::emitIns_Call(EmitCallType callType,
{
assert(isVectorRegister(reg));
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 31));
return ureg << 6;
}

Expand All @@ -11863,7 +11863,7 @@ void emitter::emitIns_Call(EmitCallType callType,
emitter::code_t ureg = (emitter::code_t)reg - (emitter::code_t)REG_V0;
assert(ureg % 2 == 0);
ureg /= 2u;
assert((ureg >= 0) && (ureg <= 32));
assert((ureg >= 0) && (ureg <= 31));
return ureg << 6;
}

Expand Down
24 changes: 12 additions & 12 deletions src/coreclr/jit/emitarm64.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -335,20 +335,20 @@ static code_t insEncodeReg_V_9_to_5(regNumber reg);
// Return an encoding for the specified 'P' register used in '12' thru '10' position.
static code_t insEncodeReg_P_12_to_10(regNumber reg);

// Return an encoding for the specified 'V' register used in '21' thru '17' position.
static code_t insEncodeReg_V_21_to_17(regNumber reg);
// Return an encoding for the specified 'V' register used in '20' thru '16' position.
static code_t insEncodeReg_V_20_to_16(regNumber reg);

// Return an encoding for the specified 'R' register used in '21' thru '17' position.
static code_t insEncodeReg_R_21_to_17(regNumber reg);
// Return an encoding for the specified 'R' register used in '20' thru '16' position.
static code_t insEncodeReg_R_20_to_16(regNumber reg);

// Return an encoding for the specified 'R' register used in '9' thru '5' position.
static code_t insEncodeReg_R_9_to_5(regNumber reg);

// Return an encoding for the specified 'R' register used in '4' thru '0' position.
static code_t insEncodeReg_R_4_to_0(regNumber reg);

// Return an encoding for the specified 'P' register used in '20' thru '17' position.
static code_t insEncodeReg_P_20_to_17(regNumber reg);
// Return an encoding for the specified 'P' register used in '19' thru '16' position.
static code_t insEncodeReg_P_19_to_16(regNumber reg);

// Return an encoding for the specified 'P' register used in '3' thru '0' position.
static code_t insEncodeReg_P_3_to_0(regNumber reg);
Expand All @@ -359,8 +359,8 @@ static code_t insEncodeReg_P_8_to_5(regNumber reg);
// Return an encoding for the specified 'P' register used in '13' thru '10' position.
static code_t insEncodeReg_P_13_to_10(regNumber reg);

// Return an encoding for the specified 'R' register used in '18' thru '17' position.
static code_t insEncodeReg_R_18_to_17(regNumber reg);
// Return an encoding for the specified 'R' register used in '17' thru '16' position.
static code_t insEncodeReg_R_17_to_16(regNumber reg);

// Return an encoding for the specified 'P' register used in '7' thru '5' position.
static code_t insEncodeReg_P_7_to_5(regNumber reg);
Expand All @@ -374,11 +374,11 @@ static code_t insEncodeReg_P_2_to_0(regNumber reg);
// Return an encoding for the specified predicate type used in '16' position.
static code_t insEncodePredQualifier_16(bool merge);

// Return an encoding for the specified 'V' register used in '19' thru '17' position.
static code_t insEncodeReg_V_19_to_17(regNumber reg);
// Return an encoding for the specified 'V' register used in '18' thru '16' position.
static code_t insEncodeReg_V_18_to_16(regNumber reg);

// Return an encoding for the specified 'V' register used in '20' thru '16' position.
static code_t insEncodeReg_V_20_to_16(regNumber reg);
// Return an encoding for the specified 'V' register used in '19' thru '16' position.
static code_t insEncodeReg_V_19_to_16(regNumber reg);

// Return an encoding for the specified 'V' register used in '9' thru '6' position.
static code_t insEncodeReg_V_9_to_6(regNumber reg);
Expand Down

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