// abs
theEmitter->emitIns_R_R_R(INS_sve_abs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ABS     <Zd>.<T>, <Pg>/M, <Zn>.<T>
// adclb
theEmitter->emitIns_R_R_R(INS_sve_adclb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADCLB   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
// adclt
theEmitter->emitIns_R_R_R(INS_sve_adclt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADCLT   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
// add
theEmitter->emitIns_R_R_R(INS_sve_add, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADD     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_add, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADD     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_add, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // ADD     <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
// addhnb
theEmitter->emitIns_R_R_R(INS_sve_addhnb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADDHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// addhnt
theEmitter->emitIns_R_R_R(INS_sve_addhnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADDHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// addp
theEmitter->emitIns_R_R_R(INS_sve_addp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADDP    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// addpl
theEmitter->emitIns_R_R_I(INS_sve_addpl, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // ADDPL   <Xd|SP>, <Xn|SP>, #<imm>
// addpt
theEmitter->emitIns_R_R_R(INS_sve_addpt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADDPT   <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
theEmitter->emitIns_R_R_R(INS_sve_addpt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADDPT   <Zd>.D, <Zn>.D, <Zm>.D
// addqv
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADDQV   <Vd>.<T>, <Pg>, <Zn>.<Tb>
// addvl
theEmitter->emitIns_R_R_I(INS_sve_addvl, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // ADDVL   <Xd|SP>, <Xn|SP>, #<imm>
// adr
theEmitter->emitIns_R_R_R(INS_sve_adr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADR     <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod><amount>}]
theEmitter->emitIns_R_R_R(INS_sve_adr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADR     <Zd>.D, [<Zn>.D, <Zm>.D, SXTW{<amount>}]
theEmitter->emitIns_R_R_R(INS_sve_adr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADR     <Zd>.D, [<Zn>.D, <Zm>.D, UXTW{<amount>}]
// aesd
theEmitter->emitIns_R_R(INS_sve_aesd, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // AESD    <Zdn>.B, <Zdn>.B, <Zm>.B
// aese
theEmitter->emitIns_R_R(INS_sve_aese, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // AESE    <Zdn>.B, <Zdn>.B, <Zm>.B
// aesimc
theEmitter->emitIns_R(INS_sve_aesimc, EA_8BYTE, REG_R0, INS_OPTS_8B);  // AESIMC  <Zdn>.B, <Zdn>.B
// aesmc
theEmitter->emitIns_R(INS_sve_aesmc, EA_8BYTE, REG_R0, INS_OPTS_8B);  // AESMC   <Zdn>.B, <Zdn>.B
// and
theEmitter->emitIns_R_R_R(INS_sve_and, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // AND     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_and, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // AND     <Zd>.D, <Zn>.D, <Zm>.D
theEmitter->emitIns_R_I(INS_sve_and, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // AND     <Zdn>.<T>, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R_R(INS_sve_and, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // AND     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// andqv
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ANDQV   <Vd>.<T>, <Pg>, <Zn>.<Tb>
// ands
theEmitter->emitIns_R_R_R_R(INS_sve_ands, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ANDS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// andv
theEmitter->emitIns_R_R_R(INS_sve_andv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ANDV    <V><d>, <Pg>, <Zn>.<T>
// asr
theEmitter->emitIns_R_R_I(INS_sve_asr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // ASR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_asr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ASR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_asr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ASR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_I(INS_sve_asr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // ASR     <Zd>.<T>, <Zn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_asr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ASR     <Zd>.<T>, <Zn>.<T>, <Zm>.D
// asrd
theEmitter->emitIns_R_R_I(INS_sve_asrd, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // ASRD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
// asrr
theEmitter->emitIns_R_R_R(INS_sve_asrr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ASRR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// bcax
theEmitter->emitIns_R_R_R(INS_sve_bcax, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BCAX    <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
// bdep
theEmitter->emitIns_R_R_R(INS_sve_bdep, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BDEP    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// bext
theEmitter->emitIns_R_R_R(INS_sve_bext, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BEXT    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// bf1cvt
theEmitter->emitIns_R_R(INS_sve_bf1cvt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // BF1CVT  <Zd>.H, <Zn>.B
// bf1cvtlt
theEmitter->emitIns_R_R(INS_sve_bf1cvtlt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // BF1CVTLT <Zd>.H, <Zn>.B
// bf2cvt
theEmitter->emitIns_R_R(INS_sve_bf2cvt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // BF2CVT  <Zd>.H, <Zn>.B
// bf2cvtlt
theEmitter->emitIns_R_R(INS_sve_bf2cvtlt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // BF2CVTLT <Zd>.H, <Zn>.B
// bfadd
theEmitter->emitIns_R_R_R(INS_sve_bfadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFADD   <Zd>.H, <Zn>.H, <Zm>.H
theEmitter->emitIns_R_R_R(INS_sve_bfadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFADD   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bfclamp
theEmitter->emitIns_R_R_R(INS_sve_bfclamp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFCLAMP <Zd>.H, <Zn>.H, <Zm>.H
// bfcvt
theEmitter->emitIns_R_R_R(INS_sve_bfcvt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFCVT   <Zd>.H, <Pg>/M, <Zn>.S
// bfcvtn
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // BFCVTN  <Zd>.B, {<Zn1>.H-<Zn2>.H }
// bfcvtnt
theEmitter->emitIns_R_R_R(INS_sve_bfcvtnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S
// bfdot
theEmitter->emitIns_R_R_R_I(INS_sve_bfdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFDOT   <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_bfdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFDOT   <Zda>.S, <Zn>.H, <Zm>.H
// bfmax
theEmitter->emitIns_R_R_R(INS_sve_bfmax, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMAX   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bfmaxnm
theEmitter->emitIns_R_R_R(INS_sve_bfmaxnm, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMAXNM <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bfmin
theEmitter->emitIns_R_R_R(INS_sve_bfmin, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMIN   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bfminnm
theEmitter->emitIns_R_R_R(INS_sve_bfminnm, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMINNM <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bfmla
theEmitter->emitIns_R_R_R_I(INS_sve_bfmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMLA   <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_R(INS_sve_bfmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BFMLA   <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H
// bfmlalb
theEmitter->emitIns_R_R_R_I(INS_sve_bfmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_bfmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMLALB <Zda>.S, <Zn>.H, <Zm>.H
// bfmlalt
theEmitter->emitIns_R_R_R_I(INS_sve_bfmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_bfmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMLALT <Zda>.S, <Zn>.H, <Zm>.H
// bfmls
theEmitter->emitIns_R_R_R_I(INS_sve_bfmls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMLS   <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_R(INS_sve_bfmls, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BFMLS   <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H
// bfmlslb
theEmitter->emitIns_R_R_R_I(INS_sve_bfmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_bfmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMLSLB <Zda>.S, <Zn>.H, <Zm>.H
// bfmlslt
theEmitter->emitIns_R_R_R_I(INS_sve_bfmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_bfmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMLSLT <Zda>.S, <Zn>.H, <Zm>.H
// bfmmla
theEmitter->emitIns_R_R_R(INS_sve_bfmmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMMLA  <Zda>.S, <Zn>.H, <Zm>.H
// bfmul
theEmitter->emitIns_R_R_R_I(INS_sve_bfmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // BFMUL   <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_bfmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMUL   <Zd>.H, <Zn>.H, <Zm>.H
theEmitter->emitIns_R_R_R(INS_sve_bfmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFMUL   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bfsub
theEmitter->emitIns_R_R_R(INS_sve_bfsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFSUB   <Zd>.H, <Zn>.H, <Zm>.H
theEmitter->emitIns_R_R_R(INS_sve_bfsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BFSUB   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
// bgrp
theEmitter->emitIns_R_R_R(INS_sve_bgrp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BGRP    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// bic
theEmitter->emitIns_R_R_R(INS_sve_bic, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BIC     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_bic, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BIC     <Zd>.D, <Zn>.D, <Zm>.D
theEmitter->emitIns_R_I(INS_sve_bic, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // BIC     <Zdn>.<T>, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R_R(INS_sve_bic, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BIC     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// bics
theEmitter->emitIns_R_R_R_R(INS_sve_bics, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BICS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// brka
theEmitter->emitIns_R_R_R(INS_sve_brka, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BRKA    <Pd>.B, <Pg>/<ZM>, <Pn>.B
// brkas
theEmitter->emitIns_R_R_R(INS_sve_brkas, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BRKAS   <Pd>.B, <Pg>/Z, <Pn>.B
// brkb
theEmitter->emitIns_R_R_R(INS_sve_brkb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BRKB    <Pd>.B, <Pg>/<ZM>, <Pn>.B
// brkbs
theEmitter->emitIns_R_R_R(INS_sve_brkbs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BRKBS   <Pd>.B, <Pg>/Z, <Pn>.B
// brkn
theEmitter->emitIns_R_R_R(INS_sve_brkn, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BRKN    <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
// brkns
theEmitter->emitIns_R_R_R(INS_sve_brkns, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BRKNS   <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
// brkpa
theEmitter->emitIns_R_R_R_R(INS_sve_brkpa, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BRKPA   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// brkpas
theEmitter->emitIns_R_R_R_R(INS_sve_brkpas, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BRKPAS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// brkpb
theEmitter->emitIns_R_R_R_R(INS_sve_brkpb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BRKPB   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// brkpbs
theEmitter->emitIns_R_R_R_R(INS_sve_brkpbs, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // BRKPBS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// bsl
theEmitter->emitIns_R_R_R(INS_sve_bsl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BSL     <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
// bsl1n
theEmitter->emitIns_R_R_R(INS_sve_bsl1n, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BSL1N   <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
// bsl2n
theEmitter->emitIns_R_R_R(INS_sve_bsl2n, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // BSL2N   <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
// cadd
theEmitter->emitIns_R_R(INS_sve_cadd, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // CADD    <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
// cdot
theEmitter->emitIns_R_R_R(INS_sve_cdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CDOT    <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_cdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>
theEmitter->emitIns_R_R_R_I(INS_sve_cdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CDOT    <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>
// clasta
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLASTA  <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLASTA  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLASTA  <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
// clastb
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLASTB  <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLASTB  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLASTB  <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
// cls
theEmitter->emitIns_R_R_R(INS_sve_cls, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLS     <Zd>.<T>, <Pg>/M, <Zn>.<T>
// clz
theEmitter->emitIns_R_R_R(INS_sve_clz, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CLZ     <Zd>.<T>, <Pg>/M, <Zn>.<T>
// cmla
theEmitter->emitIns_R_R_R(INS_sve_cmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CMLA    <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMLA    <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMLA    <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
// cmpeq
theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmpeq, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmpge
theEmitter->emitIns_R_R_R_R(INS_sve_cmpge, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmpge, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmpge, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmpgt
theEmitter->emitIns_R_R_R_R(INS_sve_cmpgt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmpgt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmpgt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmphi
theEmitter->emitIns_R_R_R_R(INS_sve_cmphi, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPHI   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmphi, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPHI   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmphi, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPHI   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmphs
theEmitter->emitIns_R_R_R_R(INS_sve_cmphs, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPHS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmphs, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPHS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmphs, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPHS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmple
theEmitter->emitIns_R_R_R_R(INS_sve_cmple, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLE   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmple, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmple, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPLE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmplo
theEmitter->emitIns_R_R_R_R(INS_sve_cmplo, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLO   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmplo, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLO   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmplo, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPLO   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmpls
theEmitter->emitIns_R_R_R_R(INS_sve_cmpls, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLS   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmpls, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmpls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPLS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmplt
theEmitter->emitIns_R_R_R_R(INS_sve_cmplt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLT   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmplt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPLT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmplt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPLT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cmpne
theEmitter->emitIns_R_R_R_R(INS_sve_cmpne, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_cmpne, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // CMPNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_R_I(INS_sve_cmpne, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // CMPNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
// cnot
theEmitter->emitIns_R_R_R(INS_sve_cnot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CNOT    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// cnt
theEmitter->emitIns_R_R_R(INS_sve_cnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CNT     <Zd>.<T>, <Pg>/M, <Zn>.<T>
// cntb
theEmitter->emitIns_R_I(INS_sve_cntb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // CNTB    <Xd>{, <pattern>{, MUL #<imm>}}
// cntd
theEmitter->emitIns_R_I(INS_sve_cntd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // CNTD    <Xd>{, <pattern>{, MUL #<imm>}}
// cnth
theEmitter->emitIns_R_I(INS_sve_cnth, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // CNTH    <Xd>{, <pattern>{, MUL #<imm>}}
// cntp
theEmitter->emitIns_R_R_R(INS_sve_cntp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CNTP    <Xd>, <Pg>, <Pn>.<T>
theEmitter->emitIns_R_R(INS_sve_cntp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // CNTP    <Xd>, <PNn>.<T>, <vl>
// cntw
theEmitter->emitIns_R_I(INS_sve_cntw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // CNTW    <Xd>{, <pattern>{, MUL #<imm>}}
// compact
theEmitter->emitIns_R_R_R(INS_sve_compact, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // COMPACT <Zd>.<T>, <Pg>, <Zn>.<T>
// cpy
theEmitter->emitIns_R_R_I(INS_sve_cpy, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // CPY     <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>}
theEmitter->emitIns_R_R_I(INS_sve_cpy, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // CPY     <Zd>.<T>, <Pg>/M, #<imm>{, <shift>}
theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CPY     <Zd>.<T>, <Pg>/M, <V><n>
theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // CPY     <Zd>.<T>, <Pg>/M, <R><n|SP>
// ctermeq
theEmitter->emitIns_R_R(INS_sve_ctermeq, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // CTERMEQ <R><n>, <R><m>
// ctermne
theEmitter->emitIns_R_R(INS_sve_ctermne, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // CTERMNE <R><n>, <R><m>
// decb
theEmitter->emitIns_R_I(INS_sve_decb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECB    <Xdn>{, <pattern>{, MUL #<imm>}}
// decd
theEmitter->emitIns_R_I(INS_sve_decd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECD    <Xdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_decd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECD    <Zdn>.D{, <pattern>{, MUL #<imm>}}
// dech
theEmitter->emitIns_R_I(INS_sve_dech, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECH    <Xdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_dech, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECH    <Zdn>.H{, <pattern>{, MUL #<imm>}}
// decp
theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // DECP    <Xdn>, <Pm>.<T>
theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // DECP    <Zdn>.<T>, <Pm>.<T>
// decw
theEmitter->emitIns_R_I(INS_sve_decw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECW    <Xdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_decw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DECW    <Zdn>.S{, <pattern>{, MUL #<imm>}}
// dup
theEmitter->emitIns_R_R_I(INS_sve_dup, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // DUP     <Zd>.<T>, <Zn>.<T>[<imm>]
theEmitter->emitIns_R_R(INS_sve_dup, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // DUP     <Zd>.<T>, <R><n|SP>
theEmitter->emitIns_R_I(INS_sve_dup, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DUP     <Zd>.<T>, #<imm>{, <shift>}
// dupm
theEmitter->emitIns_R_I(INS_sve_dupm, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // DUPM    <Zd>.<T>, #<const>
// dupq
theEmitter->emitIns_R_R_I(INS_sve_dupq, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // DUPQ    <Zd>.<T>, <Zn>.<T>[<imm>]
// eon
theEmitter->emitIns_R_I(INS_sve_eon, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // EON     <Zdn>.<T>, <Zdn>.<T>, #<const>
// eor
theEmitter->emitIns_R_R_R(INS_sve_eor, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EOR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_eor, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EOR     <Zd>.D, <Zn>.D, <Zm>.D
theEmitter->emitIns_R_I(INS_sve_eor, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // EOR     <Zdn>.<T>, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R_R(INS_sve_eor, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // EOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// eor3
theEmitter->emitIns_R_R_R(INS_sve_eor3, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EOR3    <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
// eorbt
theEmitter->emitIns_R_R_R(INS_sve_eorbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EORBT   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// eorqv
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EORQV   <Vd>.<T>, <Pg>, <Zn>.<Tb>
// eors
theEmitter->emitIns_R_R_R_R(INS_sve_eors, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // EORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// eortb
theEmitter->emitIns_R_R_R(INS_sve_eortb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EORTB   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// eorv
theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // EORV    <V><d>, <Pg>, <Zn>.<T>
// ext
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // EXT     <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // EXT     <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>
// extq
theEmitter->emitIns_R_R_I(INS_sve_extq, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // EXTQ    <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>
// f1cvt
theEmitter->emitIns_R_R(INS_sve_f1cvt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // F1CVT   <Zd>.H, <Zn>.B
// f1cvtlt
theEmitter->emitIns_R_R(INS_sve_f1cvtlt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // F1CVTLT <Zd>.H, <Zn>.B
// f2cvt
theEmitter->emitIns_R_R(INS_sve_f2cvt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // F2CVT   <Zd>.H, <Zn>.B
// f2cvtlt
theEmitter->emitIns_R_R(INS_sve_f2cvtlt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // F2CVTLT <Zd>.H, <Zn>.B
// fabd
theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FABD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fabs
theEmitter->emitIns_R_R_R(INS_sve_fabs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FABS    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// facge
theEmitter->emitIns_R_R_R_R(INS_sve_facge, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FACGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// facgt
theEmitter->emitIns_R_R_R_R(INS_sve_facgt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FACGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// facle
theEmitter->emitIns_R_R_R_R(INS_sve_facle, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FACLE   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
// faclt
theEmitter->emitIns_R_R_R_R(INS_sve_faclt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FACLT   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
// fadd
theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FADD    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FADD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fadd, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FADD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fadda
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FADDA   <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
// faddp
theEmitter->emitIns_R_R_R(INS_sve_faddp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FADDP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// faddqv
theEmitter->emitIns_R_R_R(INS_sve_faddqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FADDQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// faddv
theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FADDV   <V><d>, <Pg>, <Zn>.<T>
// famax
theEmitter->emitIns_R_R_R(INS_sve_famax, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FAMAX   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// famin
theEmitter->emitIns_R_R_R(INS_sve_famin, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FAMIN   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fcadd
theEmitter->emitIns_R_R_R(INS_sve_fcadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>
// fclamp
theEmitter->emitIns_R_R_R(INS_sve_fclamp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// fcmeq
theEmitter->emitIns_R_R_R(INS_sve_fcmeq, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCMEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
theEmitter->emitIns_R_R_R_R(INS_sve_fcmeq, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// fcmge
theEmitter->emitIns_R_R_R(INS_sve_fcmge, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCMGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
theEmitter->emitIns_R_R_R_R(INS_sve_fcmge, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// fcmgt
theEmitter->emitIns_R_R_R(INS_sve_fcmgt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCMGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
theEmitter->emitIns_R_R_R_R(INS_sve_fcmgt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// fcmla
theEmitter->emitIns_R_R_R_R(INS_sve_fcmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMLA   <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_fcmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FCMLA   <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
// fcmle
theEmitter->emitIns_R_R_R(INS_sve_fcmle, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCMLE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
theEmitter->emitIns_R_R_R_R(INS_sve_fcmle, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMLE   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
// fcmlt
theEmitter->emitIns_R_R_R(INS_sve_fcmlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCMLT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
theEmitter->emitIns_R_R_R_R(INS_sve_fcmlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMLT   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
// fcmne
theEmitter->emitIns_R_R_R(INS_sve_fcmne, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCMNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
theEmitter->emitIns_R_R_R_R(INS_sve_fcmne, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// fcmuo
theEmitter->emitIns_R_R_R_R(INS_sve_fcmuo, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FCMUO   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// fcpy
theEmitter->emitIns_R_R_I(INS_sve_fcpy, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FCPY    <Zd>.<T>, <Pg>/M, #<const>
// fcvt
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVT    <Zd>.D, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_fcvt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVT    <Zd>.S, <Pg>/M, <Zn>.D
// fcvtlt
theEmitter->emitIns_R_R_R(INS_sve_fcvtlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTLT  <Zd>.D, <Pg>/M, <Zn>.S
// fcvtn
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FCVTN   <Zd>.B, {<Zn1>.H-<Zn2>.H }
// fcvtnb
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FCVTNB  <Zd>.B, {<Zn1>.S-<Zn2>.S }
// fcvtnt
theEmitter->emitIns_R_R_R(INS_sve_fcvtnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTNT  <Zd>.S, <Pg>/M, <Zn>.D
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FCVTNT  <Zd>.B, {<Zn1>.S-<Zn2>.S }
// fcvtx
theEmitter->emitIns_R_R_R(INS_sve_fcvtx, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTX   <Zd>.S, <Pg>/M, <Zn>.D
// fcvtxnt
theEmitter->emitIns_R_R_R(INS_sve_fcvtxnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTXNT <Zd>.S, <Pg>/M, <Zn>.D
// fcvtzs
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZS  <Zd>.S, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZS  <Zd>.D, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZS  <Zd>.S, <Pg>/M, <Zn>.D
theEmitter->emitIns_R_R_R(INS_sve_fcvtzs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZS  <Zd>.D, <Pg>/M, <Zn>.D
// fcvtzu
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZU  <Zd>.S, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZU  <Zd>.D, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZU  <Zd>.S, <Pg>/M, <Zn>.D
theEmitter->emitIns_R_R_R(INS_sve_fcvtzu, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FCVTZU  <Zd>.D, <Pg>/M, <Zn>.D
// fdiv
theEmitter->emitIns_R_R_R(INS_sve_fdiv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FDIV    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fdivr
theEmitter->emitIns_R_R_R(INS_sve_fdivr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FDIVR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fdot
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FDOT    <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FDOT    <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FDOT    <Zda>.S, <Zn>.H, <Zm>.H
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FDOT    <Zda>.H, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FDOT    <Zda>.S, <Zn>.B, <Zm>.B
// fdup
theEmitter->emitIns_R_I(INS_sve_fdup, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // FDUP    <Zd>.<T>, #<const>
// fexpa
theEmitter->emitIns_R_R(INS_sve_fexpa, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FEXPA   <Zd>.<T>, <Zn>.<T>
// flogb
theEmitter->emitIns_R_R_R(INS_sve_flogb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FLOGB   <Zd>.<T>, <Pg>/M, <Zn>.<T>
// fmad
theEmitter->emitIns_R_R_R_R(INS_sve_fmad, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FMAD    <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
// fmax
theEmitter->emitIns_R_R_R(INS_sve_fmax, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fmax, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fmaxnm
theEmitter->emitIns_R_R_R(INS_sve_fmaxnm, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fmaxnm, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FMAXNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fmaxnmp
theEmitter->emitIns_R_R_R(INS_sve_fmaxnmp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fmaxnmqv
theEmitter->emitIns_R_R_R(INS_sve_fmaxnmqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
// fmaxnmv
theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXNMV <V><d>, <Pg>, <Zn>.<T>
// fmaxp
theEmitter->emitIns_R_R_R(INS_sve_fmaxp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fmaxqv
theEmitter->emitIns_R_R_R(INS_sve_fmaxqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// fmaxv
theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMAXV   <V><d>, <Pg>, <Zn>.<T>
// fmin
theEmitter->emitIns_R_R_R(INS_sve_fmin, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fmin, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fminnm
theEmitter->emitIns_R_R_R(INS_sve_fminnm, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fminnm, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FMINNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fminnmp
theEmitter->emitIns_R_R_R(INS_sve_fminnmp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fminnmqv
theEmitter->emitIns_R_R_R(INS_sve_fminnmqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
// fminnmv
theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINNMV <V><d>, <Pg>, <Zn>.<T>
// fminp
theEmitter->emitIns_R_R_R(INS_sve_fminp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fminqv
theEmitter->emitIns_R_R_R(INS_sve_fminqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// fminv
theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMINV   <V><d>, <Pg>, <Zn>.<T>
// fmla
theEmitter->emitIns_R_R_R_I(INS_sve_fmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLA    <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_fmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLA    <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
theEmitter->emitIns_R_R_R_R(INS_sve_fmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FMLA    <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
// fmlalb
theEmitter->emitIns_R_R_R_I(INS_sve_fmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALB  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALB  <Zda>.H, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_fmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALB  <Zda>.S, <Zn>.H, <Zm>.H
// fmlallbb
theEmitter->emitIns_R_R_R(INS_sve_fmlallbb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_fmlallbb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
// fmlallbt
theEmitter->emitIns_R_R_R(INS_sve_fmlallbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALLBT <Zda>.S, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_fmlallbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALLBT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
// fmlalltb
theEmitter->emitIns_R_R_R(INS_sve_fmlalltb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALLTB <Zda>.S, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_fmlalltb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALLTB <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
// fmlalltt
theEmitter->emitIns_R_R_R(INS_sve_fmlalltt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALLTT <Zda>.S, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_fmlalltt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALLTT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
// fmlalt
theEmitter->emitIns_R_R_R_I(INS_sve_fmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALT  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALT  <Zda>.H, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_fmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLALT  <Zda>.S, <Zn>.H, <Zm>.H
// fmls
theEmitter->emitIns_R_R_R_I(INS_sve_fmls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLS    <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_fmls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLS    <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
theEmitter->emitIns_R_R_R_R(INS_sve_fmls, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FMLS    <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
// fmlslb
theEmitter->emitIns_R_R_R_I(INS_sve_fmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLSLB  <Zda>.S, <Zn>.H, <Zm>.H
// fmlslt
theEmitter->emitIns_R_R_R_I(INS_sve_fmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMLSLT  <Zda>.S, <Zn>.H, <Zm>.H
// fmmla
theEmitter->emitIns_R_R_R(INS_sve_fmmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMMLA   <Zda>.D, <Zn>.D, <Zm>.D
// fmov
theEmitter->emitIns_R_R_I(INS_sve_fmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FMOV    <Zd>.<T>, <Pg>/M, #<const>
theEmitter->emitIns_R_R(INS_sve_fmov, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FMOV    <Zd>.<T>, <Pg>/M, #0.0
theEmitter->emitIns_R_I(INS_sve_fmov, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // FMOV    <Zd>.<T>, #<const>
theEmitter->emitIns_R(INS_sve_fmov, EA_8BYTE, REG_R0, INS_OPTS_8B);  // FMOV    <Zd>.<T>, #0.0
// fmsb
theEmitter->emitIns_R_R_R_R(INS_sve_fmsb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FMSB    <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
// fmul
theEmitter->emitIns_R_R_R_I(INS_sve_fmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMUL    <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_fmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // FMUL    <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_fmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMUL    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_fmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMUL    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fmul, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FMUL    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fmulx
theEmitter->emitIns_R_R_R(INS_sve_fmulx, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FMULX   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fneg
theEmitter->emitIns_R_R_R(INS_sve_fneg, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FNEG    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// fnmad
theEmitter->emitIns_R_R_R_R(INS_sve_fnmad, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FNMAD   <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
// fnmla
theEmitter->emitIns_R_R_R_R(INS_sve_fnmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FNMLA   <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
// fnmls
theEmitter->emitIns_R_R_R_R(INS_sve_fnmls, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FNMLS   <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
// fnmsb
theEmitter->emitIns_R_R_R_R(INS_sve_fnmsb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // FNMSB   <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
// frecpe
theEmitter->emitIns_R_R(INS_sve_frecpe, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FRECPE  <Zd>.<T>, <Zn>.<T>
// frecps
theEmitter->emitIns_R_R_R(INS_sve_frecps, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRECPS  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// frecpx
theEmitter->emitIns_R_R_R(INS_sve_frecpx, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRECPX  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frinta
theEmitter->emitIns_R_R_R(INS_sve_frinta, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTA  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frinti
theEmitter->emitIns_R_R_R(INS_sve_frinti, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTI  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frintm
theEmitter->emitIns_R_R_R(INS_sve_frintm, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTM  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frintn
theEmitter->emitIns_R_R_R(INS_sve_frintn, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTN  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frintp
theEmitter->emitIns_R_R_R(INS_sve_frintp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTP  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frintx
theEmitter->emitIns_R_R_R(INS_sve_frintx, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTX  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frintz
theEmitter->emitIns_R_R_R(INS_sve_frintz, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRINTZ  <Zd>.<T>, <Pg>/M, <Zn>.<T>
// frsqrte
theEmitter->emitIns_R_R(INS_sve_frsqrte, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // FRSQRTE <Zd>.<T>, <Zn>.<T>
// frsqrts
theEmitter->emitIns_R_R_R(INS_sve_frsqrts, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FRSQRTS <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// fscale
theEmitter->emitIns_R_R_R(INS_sve_fscale, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FSCALE  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// fsqrt
theEmitter->emitIns_R_R_R(INS_sve_fsqrt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FSQRT   <Zd>.<T>, <Pg>/M, <Zn>.<T>
// fsub
theEmitter->emitIns_R_R_R(INS_sve_fsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FSUB    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_fsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FSUB    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fsub, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FSUB    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// fsubr
theEmitter->emitIns_R_R_R(INS_sve_fsubr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FSUBR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_I(INS_sve_fsubr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FSUBR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
// ftmad
theEmitter->emitIns_R_R_I(INS_sve_ftmad, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // FTMAD   <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm>
// ftsmul
theEmitter->emitIns_R_R_R(INS_sve_ftsmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FTSMUL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// ftssel
theEmitter->emitIns_R_R_R(INS_sve_ftssel, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // FTSSEL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// histcnt
theEmitter->emitIns_R_R_R_R(INS_sve_histcnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // HISTCNT <Zd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// histseg
theEmitter->emitIns_R_R_R(INS_sve_histseg, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // HISTSEG <Zd>.B, <Zn>.B, <Zm>.B
// incb
theEmitter->emitIns_R_I(INS_sve_incb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCB    <Xdn>{, <pattern>{, MUL #<imm>}}
// incd
theEmitter->emitIns_R_I(INS_sve_incd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCD    <Xdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_incd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCD    <Zdn>.D{, <pattern>{, MUL #<imm>}}
// inch
theEmitter->emitIns_R_I(INS_sve_inch, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCH    <Xdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_inch, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCH    <Zdn>.H{, <pattern>{, MUL #<imm>}}
// incp
theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // INCP    <Xdn>, <Pm>.<T>
theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // INCP    <Zdn>.<T>, <Pm>.<T>
// incw
theEmitter->emitIns_R_I(INS_sve_incw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCW    <Xdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_incw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INCW    <Zdn>.S{, <pattern>{, MUL #<imm>}}
// index
theEmitter->emitIns_R_I(INS_sve_index, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // INDEX   <Zd>.<T>, #<imm1>, #<imm2>
theEmitter->emitIns_R_R_I(INS_sve_index, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // INDEX   <Zd>.<T>, #<imm>, <R><m>
theEmitter->emitIns_R_R_I(INS_sve_index, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // INDEX   <Zd>.<T>, <R><n>, #<imm>
theEmitter->emitIns_R_R_R(INS_sve_index, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // INDEX   <Zd>.<T>, <R><n>, <R><m>
// insr
theEmitter->emitIns_R_R(INS_sve_insr, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // INSR    <Zdn>.<T>, <V><m>
theEmitter->emitIns_R_R(INS_sve_insr, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // INSR    <Zdn>.<T>, <R><m>
// lasta
theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LASTA   <V><d>, <Pg>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LASTA   <R><d>, <Pg>, <Zn>.<T>
// lastb
theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LASTB   <V><d>, <Pg>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LASTB   <R><d>, <Pg>, <Zn>.<T>
// ld1b
theEmitter->emitIns_R_R_R_R(INS_sve_ld1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1B    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1B    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld1d
theEmitter->emitIns_R_R_R_I(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1D    {<Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1D    {<Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1D    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
// ld1h
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld1q
theEmitter->emitIns_R_R_R_R(INS_sve_ld1q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1Q    {<Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}]
// ld1rb
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1rd
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rd, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RD   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1rh
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1rob
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rob, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1ROB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1rob, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1ROB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld1rod
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rod, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1ROD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1rod, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1ROD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
// ld1roh
theEmitter->emitIns_R_R_R_I(INS_sve_ld1roh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1ROH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1roh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1ROH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld1row
theEmitter->emitIns_R_R_R_I(INS_sve_ld1row, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1ROW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1row, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1ROW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
// ld1rqb
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rqb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RQB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1rqb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1RQB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld1rqd
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rqd, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RQD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1rqd, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1RQD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
// ld1rqh
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rqh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RQH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1rqh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1RQH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld1rqw
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rqw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RQW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1rqw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1RQW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
// ld1rsb
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RSB  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1rsh
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RSH  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1rsw
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RSW  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1rw
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1RW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
// ld1sb
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SB   {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1SB   {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld1sh
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld1sw
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1SW   {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
// ld1w
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_R(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ld2b
theEmitter->emitIns_R_R_R_I(INS_sve_ld2b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD2B    {<Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld2b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD2B    {<Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld2d
theEmitter->emitIns_R_R_R_I(INS_sve_ld2d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD2D    {<Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld2d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD2D    {<Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
// ld2h
theEmitter->emitIns_R_R_R_I(INS_sve_ld2h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD2H    {<Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld2h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD2H    {<Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld2q
theEmitter->emitIns_R_R_R_I(INS_sve_ld2q, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld2q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
// ld2w
theEmitter->emitIns_R_R_R_I(INS_sve_ld2w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD2W    {<Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld2w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD2W    {<Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
// ld3b
theEmitter->emitIns_R_R_R_I(INS_sve_ld3b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld3b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld3d
theEmitter->emitIns_R_R_R_I(INS_sve_ld3d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld3d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
// ld3h
theEmitter->emitIns_R_R_R_I(INS_sve_ld3h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld3h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld3q
theEmitter->emitIns_R_R_R_I(INS_sve_ld3q, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld3q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
// ld3w
theEmitter->emitIns_R_R_R_I(INS_sve_ld3w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld3w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
// ld4b
theEmitter->emitIns_R_R_R_I(INS_sve_ld4b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld4b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ld4d
theEmitter->emitIns_R_R_R_I(INS_sve_ld4d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld4d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
// ld4h
theEmitter->emitIns_R_R_R_I(INS_sve_ld4h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld4h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ld4q
theEmitter->emitIns_R_R_R_I(INS_sve_ld4q, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld4q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
// ld4w
theEmitter->emitIns_R_R_R_I(INS_sve_ld4w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LD4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ld4w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LD4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
// ldff1b
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1B  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1B  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
// ldff1d
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1D  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
// ldff1h
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1H  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
// ldff1sb
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SB {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
// ldff1sh
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
// ldff1sw
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
// ldff1w
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDFF1W  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldff1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
// ldnf1b
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnf1d
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnf1h
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnf1sb
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnf1sh
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnf1sw
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnf1w
theEmitter->emitIns_R_R_R_I(INS_sve_ldnf1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
// ldnt1b
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1B  {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1B  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNT1B  {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1B  {<Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
// ldnt1d
theEmitter->emitIns_R_R_R_I(INS_sve_ldnt1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNT1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1D  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
// ldnt1h
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1H  {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1H  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNT1H  {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1H  {<Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
// ldnt1sb
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1SB {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1sb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
// ldnt1sh
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1SH {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1sh, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
// ldnt1sw
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1sw, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
// ldnt1w
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1W  {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1W  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LDNT1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_ldnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // LDNT1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
// ldr
theEmitter->emitIns_R_R_I(INS_sve_ldr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // LDR     <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_I(INS_sve_ldr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // LDR     <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
// lsl
theEmitter->emitIns_R_R_I(INS_sve_lsl, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // LSL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_I(INS_sve_lsl, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // LSL     <Zd>.<T>, <Zn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSL     <Zd>.<T>, <Zn>.<T>, <Zm>.D
// lslr
theEmitter->emitIns_R_R_R(INS_sve_lslr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSLR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// lsr
theEmitter->emitIns_R_R_I(INS_sve_lsr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // LSR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
theEmitter->emitIns_R_R_I(INS_sve_lsr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // LSR     <Zd>.<T>, <Zn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSR     <Zd>.<T>, <Zn>.<T>, <Zm>.D
// lsrr
theEmitter->emitIns_R_R_R(INS_sve_lsrr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // LSRR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// luti2
theEmitter->emitIns_R_R_R_I(INS_sve_luti2, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LUTI2   <Zd>.B, {<Zn>.B }, <Zm>[<index>]
theEmitter->emitIns_R_R_R_I(INS_sve_luti2, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LUTI2   <Zd>.H, {<Zn>.H }, <Zm>[<index>]
// luti4
theEmitter->emitIns_R_R_R_I(INS_sve_luti4, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LUTI4   <Zd>.B, {<Zn>.B }, <Zm>[<index>]
theEmitter->emitIns_R_R_R_I(INS_sve_luti4, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LUTI4   <Zd>.H, {<Zn1>.H, <Zn2>.H }, <Zm>[<index>]
theEmitter->emitIns_R_R_R_I(INS_sve_luti4, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // LUTI4   <Zd>.H, {<Zn>.H }, <Zm>[<index>]
// mad
theEmitter->emitIns_R_R_R_R(INS_sve_mad, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MAD     <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
// madpt
theEmitter->emitIns_R_R_R(INS_sve_madpt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MADPT   <Zdn>.D, <Zm>.D, <Za>.D
// match
theEmitter->emitIns_R_R_R_R(INS_sve_match, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MATCH   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// mla
theEmitter->emitIns_R_R_R_R(INS_sve_mla, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MLA     <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_I(INS_sve_mla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MLA     <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_mla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MLA     <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_mla, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MLA     <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
// mlapt
theEmitter->emitIns_R_R_R(INS_sve_mlapt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MLAPT   <Zda>.D, <Zn>.D, <Zm>.D
// mls
theEmitter->emitIns_R_R_R_R(INS_sve_mls, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MLS     <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_I(INS_sve_mls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MLS     <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_mls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MLS     <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_mls, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MLS     <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
// mov
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MOV     <Zd>.D, <Zn>.D
theEmitter->emitIns_R_I(INS_sve_mov, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // MOV     <Zd>.<T>, #<const>
theEmitter->emitIns_R_R_I(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // MOV     <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>}
theEmitter->emitIns_R_R_I(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // MOV     <Zd>.<T>, <Pg>/M, #<imm>{, <shift>}
theEmitter->emitIns_R_R_I(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // MOV     <Zd>.<T>, <Zn>.<T>[<imm>]
theEmitter->emitIns_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // MOV     <Zd>.<T>, <R><n|SP>
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MOV     <Zd>.<T>, <Pg>/M, <V><n>
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MOV     <Zd>.<T>, <Pg>/M, <R><n|SP>
theEmitter->emitIns_R_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MOV     <Zd>.<T>, <Pv>/M, <Zn>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MOV     <Pd>.B, <Pg>/Z, <Pn>.B
theEmitter->emitIns_R_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MOV     <Pd>.B, <Pg>/M, <Pn>.B
theEmitter->emitIns_R_R_R_R(INS_sve_mov, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MOV     <Pd>.B, <Pn>.B
theEmitter->emitIns_R_I(INS_sve_mov, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // MOV     <Zd>.<T>, #<imm>{, <shift>}
// movprfx
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R(INS_sve_movprfx, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // MOVPRFX <Zd>, <Zn>
// movs
theEmitter->emitIns_R_R_R_R(INS_sve_movs, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MOVS    <Pd>.B, <Pg>/Z, <Pn>.B
theEmitter->emitIns_R_R_R_R(INS_sve_movs, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MOVS    <Pd>.B, <Pn>.B
// msb
theEmitter->emitIns_R_R_R_R(INS_sve_msb, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // MSB     <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
// mul
theEmitter->emitIns_R_R_R(INS_sve_mul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MUL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_mul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // MUL     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_mul, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // MUL     <Zdn>.<T>, <Zdn>.<T>, #<imm>
theEmitter->emitIns_R_R_R_I(INS_sve_mul, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MUL     <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_mul, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MUL     <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_mul, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // MUL     <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
// nand
theEmitter->emitIns_R_R_R_R(INS_sve_nand, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NAND    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// nands
theEmitter->emitIns_R_R_R_R(INS_sve_nands, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NANDS   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// nbsl
theEmitter->emitIns_R_R_R(INS_sve_nbsl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // NBSL    <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
// neg
theEmitter->emitIns_R_R_R(INS_sve_neg, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // NEG     <Zd>.<T>, <Pg>/M, <Zn>.<T>
// nmatch
theEmitter->emitIns_R_R_R_R(INS_sve_nmatch, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NMATCH  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
// nor
theEmitter->emitIns_R_R_R_R(INS_sve_nor, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// nors
theEmitter->emitIns_R_R_R_R(INS_sve_nors, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// not
theEmitter->emitIns_R_R_R(INS_sve_not, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // NOT     <Zd>.<T>, <Pg>/M, <Zn>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_not, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NOT     <Pd>.B, <Pg>/Z, <Pn>.B
// nots
theEmitter->emitIns_R_R_R_R(INS_sve_nots, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // NOTS    <Pd>.B, <Pg>/Z, <Pn>.B
// orn
theEmitter->emitIns_R_I(INS_sve_orn, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // ORN     <Zdn>.<T>, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R_R(INS_sve_orn, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ORN     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// orns
theEmitter->emitIns_R_R_R_R(INS_sve_orns, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ORNS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// orqv
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ORQV    <Vd>.<T>, <Pg>, <Zn>.<Tb>
// orr
theEmitter->emitIns_R_R_R(INS_sve_orr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ORR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_orr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ORR     <Zd>.D, <Zn>.D, <Zm>.D
theEmitter->emitIns_R_I(INS_sve_orr, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // ORR     <Zdn>.<T>, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R_R(INS_sve_orr, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ORR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// orrs
theEmitter->emitIns_R_R_R_R(INS_sve_orrs, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ORRS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
// orv
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ORV     <V><d>, <Pg>, <Zn>.<T>
// pext
theEmitter->emitIns_R_R_I(INS_sve_pext, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PEXT    <Pd>.<T>, <PNn>[<imm>]
theEmitter->emitIns_R_R_I(INS_sve_pext, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PEXT    {<Pd1>.<T>, <Pd2>.<T>}, <PNn>[<imm>]
// pfalse
theEmitter->emitIns_R(INS_sve_pfalse, EA_8BYTE, REG_R0, INS_OPTS_8B);  // PFALSE  <Pd>.B
// pfirst
theEmitter->emitIns_R_R(INS_sve_pfirst, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PFIRST  <Pdn>.B, <Pg>, <Pdn>.B
// pmov
theEmitter->emitIns_R_R(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PMOV    <Pd>.B, <Zn>
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PMOV    <Pd>.D, <Zn>[<imm>]
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PMOV    <Pd>.H, <Zn>[<imm>]
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PMOV    <Pd>.S, <Zn>[<imm>]
theEmitter->emitIns_R_R(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PMOV    <Zd>, <Pn>.B
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PMOV    <Zd>[<imm>], <Pn>.D
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PMOV    <Zd>[<imm>], <Pn>.H
theEmitter->emitIns_R_R_I(INS_sve_pmov, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PMOV    <Zd>[<imm>], <Pn>.S
// pmul
theEmitter->emitIns_R_R_R(INS_sve_pmul, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PMUL    <Zd>.B, <Zn>.B, <Zm>.B
// pmullb
theEmitter->emitIns_R_R_R(INS_sve_pmullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R(INS_sve_pmullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PMULLB  <Zd>.Q, <Zn>.D, <Zm>.D
// pmullt
theEmitter->emitIns_R_R_R(INS_sve_pmullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R(INS_sve_pmullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PMULLT  <Zd>.Q, <Zn>.D, <Zm>.D
// pnext
theEmitter->emitIns_R_R(INS_sve_pnext, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PNEXT   <Pdn>.<T>, <Pv>, <Pdn>.<T>
// prfb
theEmitter->emitIns_R_R_R(INS_sve_prfb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R(INS_sve_prfb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R(INS_sve_prfb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_I(INS_sve_prfb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFB    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_I(INS_sve_prfb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFB    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R(INS_sve_prfb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFB    <prfop>, <Pg>, [<Xn|SP>, <Xm>]
// prfd
theEmitter->emitIns_R_R_R(INS_sve_prfd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #3]
theEmitter->emitIns_R_R_R(INS_sve_prfd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R(INS_sve_prfd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
theEmitter->emitIns_R_R_I(INS_sve_prfd, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFD    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_I(INS_sve_prfd, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFD    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R(INS_sve_prfd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFD    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
// prfh
theEmitter->emitIns_R_R_R(INS_sve_prfh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R(INS_sve_prfh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R(INS_sve_prfh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
theEmitter->emitIns_R_R_I(INS_sve_prfh, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFH    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_I(INS_sve_prfh, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFH    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R(INS_sve_prfh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFH    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
// prfw
theEmitter->emitIns_R_R_R(INS_sve_prfw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]
theEmitter->emitIns_R_R_R(INS_sve_prfw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R(INS_sve_prfw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
theEmitter->emitIns_R_R_I(INS_sve_prfw, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFW    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_I(INS_sve_prfw, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // PRFW    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R(INS_sve_prfw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // PRFW    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
// psel
theEmitter->emitIns_R_R_R_R_I(INS_sve_psel, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, 5, INS_OPTS_8B);  // PSEL    <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
// ptest
theEmitter->emitIns_R_R(INS_sve_ptest, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PTEST   <Pg>, <Pn>.B
// ptrue
theEmitter->emitIns_R(INS_sve_ptrue, EA_8BYTE, REG_R0, INS_OPTS_8B);  // PTRUE   <Pd>.<T>{, <pattern>}
theEmitter->emitIns_R(INS_sve_ptrue, EA_8BYTE, REG_R0, INS_OPTS_8B);  // PTRUE   <PNd>.<T>
// ptrues
theEmitter->emitIns_R(INS_sve_ptrues, EA_8BYTE, REG_R0, INS_OPTS_8B);  // PTRUES  <Pd>.<T>{, <pattern>}
// punpkhi
theEmitter->emitIns_R_R(INS_sve_punpkhi, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PUNPKHI <Pd>.H, <Pn>.B
// punpklo
theEmitter->emitIns_R_R(INS_sve_punpklo, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // PUNPKLO <Pd>.H, <Pn>.B
// raddhnb
theEmitter->emitIns_R_R_R(INS_sve_raddhnb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // RADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// raddhnt
theEmitter->emitIns_R_R_R(INS_sve_raddhnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // RADDHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// rax1
theEmitter->emitIns_R_R_R(INS_sve_rax1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // RAX1    <Zd>.D, <Zn>.D, <Zm>.D
// rbit
theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // RBIT    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// rdffr
theEmitter->emitIns_R_R(INS_sve_rdffr, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // RDFFR   <Pd>.B, <Pg>/Z
theEmitter->emitIns_R(INS_sve_rdffr, EA_8BYTE, REG_R0, INS_OPTS_8B);  // RDFFR   <Pd>.B
// rdffrs
theEmitter->emitIns_R_R(INS_sve_rdffrs, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // RDFFRS  <Pd>.B, <Pg>/Z
// rdvl
theEmitter->emitIns_R_I(INS_sve_rdvl, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // RDVL    <Xd>, #<imm>
// rev
theEmitter->emitIns_R_R(INS_sve_rev, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // REV     <Zd>.<T>, <Zn>.<T>
theEmitter->emitIns_R_R(INS_sve_rev, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // REV     <Pd>.<T>, <Pn>.<T>
// revb
theEmitter->emitIns_R_R_R(INS_sve_revb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // REVB    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// revd
theEmitter->emitIns_R_R_R(INS_sve_revd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // REVD    <Zd>.Q, <Pg>/M, <Zn>.Q
// revh
theEmitter->emitIns_R_R_R(INS_sve_revh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // REVH    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// revw
theEmitter->emitIns_R_R_R(INS_sve_revw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // REVW    <Zd>.D, <Pg>/M, <Zn>.D
// rshrnb
theEmitter->emitIns_R_R_I(INS_sve_rshrnb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // RSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
// rshrnt
theEmitter->emitIns_R_R_I(INS_sve_rshrnt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // RSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
// rsubhnb
theEmitter->emitIns_R_R_R(INS_sve_rsubhnb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // RSUBHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// rsubhnt
theEmitter->emitIns_R_R_R(INS_sve_rsubhnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // RSUBHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// saba
theEmitter->emitIns_R_R_R(INS_sve_saba, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SABA    <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
// sabalb
theEmitter->emitIns_R_R_R(INS_sve_sabalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SABALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sabalt
theEmitter->emitIns_R_R_R(INS_sve_sabalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SABALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sabd
theEmitter->emitIns_R_R_R(INS_sve_sabd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SABD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sabdlb
theEmitter->emitIns_R_R_R(INS_sve_sabdlb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SABDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sabdlt
theEmitter->emitIns_R_R_R(INS_sve_sabdlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SABDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sadalp
theEmitter->emitIns_R_R_R(INS_sve_sadalp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADALP  <Zda>.<T>, <Pg>/M, <Zn>.<Tb>
// saddlb
theEmitter->emitIns_R_R_R(INS_sve_saddlb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// saddlbt
theEmitter->emitIns_R_R_R(INS_sve_saddlbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADDLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// saddlt
theEmitter->emitIns_R_R_R(INS_sve_saddlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// saddv
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADDV   <Dd>, <Pg>, <Zn>.<T>
// saddwb
theEmitter->emitIns_R_R_R(INS_sve_saddwb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADDWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// saddwt
theEmitter->emitIns_R_R_R(INS_sve_saddwt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SADDWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// sbclb
theEmitter->emitIns_R_R_R(INS_sve_sbclb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SBCLB   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
// sbclt
theEmitter->emitIns_R_R_R(INS_sve_sbclt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SBCLT   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
// sclamp
theEmitter->emitIns_R_R_R(INS_sve_sclamp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// scvtf
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SCVTF   <Zd>.S, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SCVTF   <Zd>.D, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SCVTF   <Zd>.S, <Pg>/M, <Zn>.D
theEmitter->emitIns_R_R_R(INS_sve_scvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SCVTF   <Zd>.D, <Pg>/M, <Zn>.D
// sdiv
theEmitter->emitIns_R_R_R(INS_sve_sdiv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SDIV    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sdivr
theEmitter->emitIns_R_R_R(INS_sve_sdivr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SDIVR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sdot
theEmitter->emitIns_R_R_R(INS_sve_sdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SDOT    <Zda>.S, <Zn>.H, <Zm>.H
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SDOT    <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_sdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SDOT    <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SDOT    <Zda>.D, <Zn>.H, <Zm>.H[<imm>]
// sel
theEmitter->emitIns_R_R_R_R(INS_sve_sel, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // SEL     <Zd>.<T>, <Pv>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_R(INS_sve_sel, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // SEL     <Pd>.B, <Pg>, <Pn>.B, <Pm>.B
// setffr
theEmitter->emitIns_TODO(INS_sve_setffr, EA_8BYTE, , INS_OPTS_8B);  // SETFFR  
// shadd
theEmitter->emitIns_R_R_R(INS_sve_shadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SHADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// shrnb
theEmitter->emitIns_R_R_I(INS_sve_shrnb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SHRNB   <Zd>.<T>, <Zn>.<Tb>, #<const>
// shrnt
theEmitter->emitIns_R_R_I(INS_sve_shrnt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SHRNT   <Zd>.<T>, <Zn>.<Tb>, #<const>
// shsub
theEmitter->emitIns_R_R_R(INS_sve_shsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SHSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// shsubr
theEmitter->emitIns_R_R_R(INS_sve_shsubr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SHSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sli
theEmitter->emitIns_R_R_I(INS_sve_sli, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SLI     <Zd>.<T>, <Zn>.<T>, #<const>
// sm4e
theEmitter->emitIns_R_R(INS_sve_sm4e, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SM4E    <Zdn>.S, <Zdn>.S, <Zm>.S
// sm4ekey
theEmitter->emitIns_R_R_R(INS_sve_sm4ekey, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SM4EKEY <Zd>.S, <Zn>.S, <Zm>.S
// smax
theEmitter->emitIns_R_R_R(INS_sve_smax, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_smax, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SMAX    <Zdn>.<T>, <Zdn>.<T>, #<imm>
// smaxp
theEmitter->emitIns_R_R_R(INS_sve_smaxp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMAXP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// smaxqv
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// smaxv
theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMAXV   <V><d>, <Pg>, <Zn>.<T>
// smin
theEmitter->emitIns_R_R_R(INS_sve_smin, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_smin, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SMIN    <Zdn>.<T>, <Zdn>.<T>, #<imm>
// sminp
theEmitter->emitIns_R_R_R(INS_sve_sminp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMINP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sminqv
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// sminv
theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMINV   <V><d>, <Pg>, <Zn>.<T>
// smlalb
theEmitter->emitIns_R_R_R(INS_sve_smlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_smlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_smlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// smlalt
theEmitter->emitIns_R_R_R(INS_sve_smlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_smlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_smlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// smlslb
theEmitter->emitIns_R_R_R(INS_sve_smlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_smlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_smlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// smlslt
theEmitter->emitIns_R_R_R(INS_sve_smlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_smlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_smlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// smmla
theEmitter->emitIns_R_R_R(INS_sve_smmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMMLA   <Zda>.S, <Zn>.B, <Zm>.B
// smulh
theEmitter->emitIns_R_R_R(INS_sve_smulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMULH   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_smulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMULH   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// smullb
theEmitter->emitIns_R_R_R_I(INS_sve_smullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_smullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_smullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// smullt
theEmitter->emitIns_R_R_R_I(INS_sve_smullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_smullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_smullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// splice
theEmitter->emitIns_R_R_R(INS_sve_splice, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SPLICE  <Zd>.<T>, <Pv>, {<Zn1>.<T>, <Zn2>.<T>}
theEmitter->emitIns_R_R_R(INS_sve_splice, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SPLICE  <Zdn>.<T>, <Pv>, <Zdn>.<T>, <Zm>.<T>
// sqabs
theEmitter->emitIns_R_R_R(INS_sve_sqabs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQABS   <Zd>.<T>, <Pg>/M, <Zn>.<T>
// sqadd
theEmitter->emitIns_R_R_R(INS_sve_sqadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQADD   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_sqadd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQADD   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_R_R(INS_sve_sqadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqcadd
theEmitter->emitIns_R_R(INS_sve_sqcadd, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQCADD  <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
// sqcvtn
theEmitter->emitIns_R_R(INS_sve_sqcvtn, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQCVTN  <Zd>.H, {<Zn1>.S-<Zn2>.S }
// sqcvtun
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
// sqdecb
theEmitter->emitIns_R_I(INS_sve_sqdecb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECB  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
// sqdecd
theEmitter->emitIns_R_I(INS_sve_sqdecd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECD  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_sqdecd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
// sqdech
theEmitter->emitIns_R_I(INS_sve_sqdech, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECH  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_sqdech, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
// sqdecp
theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQDECP  <Xdn>, <Pm>.<T>, <Wdn>
theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQDECP  <Zdn>.<T>, <Pm>.<T>
// sqdecw
theEmitter->emitIns_R_I(INS_sve_sqdecw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECW  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_sqdecw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQDECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
// sqdmlalb
theEmitter->emitIns_R_R_R(INS_sve_sqdmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMLALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLALB <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// sqdmlalbt
theEmitter->emitIns_R_R_R(INS_sve_sqdmlalbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMLALBT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sqdmlalt
theEmitter->emitIns_R_R_R(INS_sve_sqdmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLALT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// sqdmlslb
theEmitter->emitIns_R_R_R(INS_sve_sqdmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMLSLB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// sqdmlslbt
theEmitter->emitIns_R_R_R(INS_sve_sqdmlslbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMLSLBT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sqdmlslt
theEmitter->emitIns_R_R_R(INS_sve_sqdmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMLSLT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// sqdmulh
theEmitter->emitIns_R_R_R(INS_sve_sqdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
// sqdmullb
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULLB <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULLB <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_sqdmullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sqdmullt
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULLT <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqdmullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQDMULLT <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_sqdmullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQDMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// sqincb
theEmitter->emitIns_R_I(INS_sve_sqincb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCB  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
// sqincd
theEmitter->emitIns_R_I(INS_sve_sqincd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCD  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_sqincd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
// sqinch
theEmitter->emitIns_R_I(INS_sve_sqinch, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCH  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_sqinch, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
// sqincp
theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQINCP  <Xdn>, <Pm>.<T>, <Wdn>
theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQINCP  <Zdn>.<T>, <Pm>.<T>
// sqincw
theEmitter->emitIns_R_I(INS_sve_sqincw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCW  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_sqincw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQINCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
// sqneg
theEmitter->emitIns_R_R_R(INS_sve_sqneg, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQNEG   <Zd>.<T>, <Pg>/M, <Zn>.<T>
// sqrdcmlah
theEmitter->emitIns_R_R_R(INS_sve_sqrdcmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
// sqrdmlah
theEmitter->emitIns_R_R_R(INS_sve_sqrdmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQRDMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmlah, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMLAH <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
// sqrdmlsh
theEmitter->emitIns_R_R_R(INS_sve_sqrdmlsh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQRDMLSH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmlsh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMLSH <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmlsh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMLSH <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmlsh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMLSH <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
// sqrdmulh
theEmitter->emitIns_R_R_R(INS_sve_sqrdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQRDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdmulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SQRDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
// sqrshl
theEmitter->emitIns_R_R_R(INS_sve_sqrshl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqrshlr
theEmitter->emitIns_R_R_R(INS_sve_sqrshlr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqrshrn
theEmitter->emitIns_R_R_I(INS_sve_sqrshrn, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQRSHRN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>
// sqrshrnb
theEmitter->emitIns_R_R_I(INS_sve_sqrshrnb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQRSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqrshrnt
theEmitter->emitIns_R_R_I(INS_sve_sqrshrnt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQRSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqrshrun
theEmitter->emitIns_R_R_I(INS_sve_sqrshrun, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQRSHRUN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>
// sqrshrunb
theEmitter->emitIns_R_R_I(INS_sve_sqrshrunb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQRSHRUNB <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqrshrunt
theEmitter->emitIns_R_R_I(INS_sve_sqrshrunt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQRSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqshl
theEmitter->emitIns_R_R_I(INS_sve_sqshl, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_sqshl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqshlr
theEmitter->emitIns_R_R_R(INS_sve_sqshlr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqshlu
theEmitter->emitIns_R_R_I(INS_sve_sqshlu, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQSHLU  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
// sqshrnb
theEmitter->emitIns_R_R_I(INS_sve_sqshrnb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqshrnt
theEmitter->emitIns_R_R_I(INS_sve_sqshrnt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqshrunb
theEmitter->emitIns_R_R_I(INS_sve_sqshrunb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQSHRUNB <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqshrunt
theEmitter->emitIns_R_R_I(INS_sve_sqshrunt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SQSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const>
// sqsub
theEmitter->emitIns_R_R_R(INS_sve_sqsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQSUB   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_sqsub, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SQSUB   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_R_R(INS_sve_sqsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqsubr
theEmitter->emitIns_R_R_R(INS_sve_sqsubr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SQSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sqxtnb
theEmitter->emitIns_R_R(INS_sve_sqxtnb, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQXTNB  <Zd>.<T>, <Zn>.<Tb>
// sqxtnt
theEmitter->emitIns_R_R(INS_sve_sqxtnt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQXTNT  <Zd>.<T>, <Zn>.<Tb>
// sqxtunb
theEmitter->emitIns_R_R(INS_sve_sqxtunb, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQXTUNB <Zd>.<T>, <Zn>.<Tb>
// sqxtunt
theEmitter->emitIns_R_R(INS_sve_sqxtunt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SQXTUNT <Zd>.<T>, <Zn>.<Tb>
// srhadd
theEmitter->emitIns_R_R_R(INS_sve_srhadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SRHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sri
theEmitter->emitIns_R_R_I(INS_sve_sri, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SRI     <Zd>.<T>, <Zn>.<T>, #<const>
// srshl
theEmitter->emitIns_R_R_R(INS_sve_srshl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SRSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// srshlr
theEmitter->emitIns_R_R_R(INS_sve_srshlr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SRSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// srshr
theEmitter->emitIns_R_R_I(INS_sve_srshr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SRSHR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
// srsra
theEmitter->emitIns_R_R_I(INS_sve_srsra, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SRSRA   <Zda>.<T>, <Zn>.<T>, #<const>
// sshllb
theEmitter->emitIns_R_R_I(INS_sve_sshllb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SSHLLB  <Zd>.<T>, <Zn>.<Tb>, #<const>
// sshllt
theEmitter->emitIns_R_R_I(INS_sve_sshllt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SSHLLT  <Zd>.<T>, <Zn>.<Tb>, #<const>
// ssra
theEmitter->emitIns_R_R_I(INS_sve_ssra, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // SSRA    <Zda>.<T>, <Zn>.<T>, #<const>
// ssublb
theEmitter->emitIns_R_R_R(INS_sve_ssublb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SSUBLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// ssublbt
theEmitter->emitIns_R_R_R(INS_sve_ssublbt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SSUBLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// ssublt
theEmitter->emitIns_R_R_R(INS_sve_ssublt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SSUBLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// ssubltb
theEmitter->emitIns_R_R_R(INS_sve_ssubltb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SSUBLTB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// ssubwb
theEmitter->emitIns_R_R_R(INS_sve_ssubwb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SSUBWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// ssubwt
theEmitter->emitIns_R_R_R(INS_sve_ssubwt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SSUBWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// st1b
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1B    {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1B    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1B    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1B    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1B    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1B    {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st1d
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1D    {<Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
theEmitter->emitIns_R_R_R_R(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1D    {<Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st1h
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1H    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
theEmitter->emitIns_R_R_R_R(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1H    {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st1q
theEmitter->emitIns_R_R_R_R(INS_sve_st1q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1Q    {<Zt>.Q }, <Pg>, [<Zn>.D{, <Xm>}]
// st1w
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1W    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
theEmitter->emitIns_R_R_R_R(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1W    {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST1W    {<Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st2b
theEmitter->emitIns_R_R_R_R(INS_sve_st2b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST2B    {<Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_I(INS_sve_st2b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST2B    {<Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st2d
theEmitter->emitIns_R_R_R_R(INS_sve_st2d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST2D    {<Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_I(INS_sve_st2d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST2D    {<Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st2h
theEmitter->emitIns_R_R_R_R(INS_sve_st2h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST2H    {<Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_I(INS_sve_st2h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST2H    {<Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st2q
theEmitter->emitIns_R_R_R_I(INS_sve_st2q, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_st2q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
// st2w
theEmitter->emitIns_R_R_R_R(INS_sve_st2w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST2W    {<Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_I(INS_sve_st2w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST2W    {<Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st3b
theEmitter->emitIns_R_R_R_R(INS_sve_st3b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_I(INS_sve_st3b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st3d
theEmitter->emitIns_R_R_R_R(INS_sve_st3d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_I(INS_sve_st3d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st3h
theEmitter->emitIns_R_R_R_R(INS_sve_st3h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_I(INS_sve_st3h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st3q
theEmitter->emitIns_R_R_R_I(INS_sve_st3q, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_st3q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
// st3w
theEmitter->emitIns_R_R_R_R(INS_sve_st3w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_I(INS_sve_st3w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st4b
theEmitter->emitIns_R_R_R_R(INS_sve_st4b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_I(INS_sve_st4b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st4d
theEmitter->emitIns_R_R_R_R(INS_sve_st4d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_I(INS_sve_st4d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st4h
theEmitter->emitIns_R_R_R_R(INS_sve_st4h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_I(INS_sve_st4h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// st4q
theEmitter->emitIns_R_R_R_I(INS_sve_st4q, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_R_R(INS_sve_st4q, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
// st4w
theEmitter->emitIns_R_R_R_R(INS_sve_st4w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // ST4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_I(INS_sve_st4w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // ST4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// stnt1b
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1B  {<Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1B  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1B  {<Zt>.B }, <Pg>, [<Xn|SP>, <Xm>]
theEmitter->emitIns_R_R_R_I(INS_sve_stnt1b, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // STNT1B  {<Zt>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// stnt1d
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1D  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1D  {<Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
theEmitter->emitIns_R_R_R_I(INS_sve_stnt1d, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // STNT1D  {<Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// stnt1h
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1H  {<Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1H  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1H  {<Zt>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
theEmitter->emitIns_R_R_R_I(INS_sve_stnt1h, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // STNT1H  {<Zt>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// stnt1w
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1W  {<Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1W  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
theEmitter->emitIns_R_R_R_R(INS_sve_stnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, REG_R3, INS_OPTS_8B);  // STNT1W  {<Zt>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
theEmitter->emitIns_R_R_R_I(INS_sve_stnt1w, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // STNT1W  {<Zt>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
// str
theEmitter->emitIns_R_R_I(INS_sve_str, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // STR     <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]
theEmitter->emitIns_R_R_I(INS_sve_str, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // STR     <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
// sub
theEmitter->emitIns_R_R_R(INS_sve_sub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUB     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_sub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUB     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_sub, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SUB     <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
// subhnb
theEmitter->emitIns_R_R_R(INS_sve_subhnb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUBHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// subhnt
theEmitter->emitIns_R_R_R(INS_sve_subhnt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUBHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// subpt
theEmitter->emitIns_R_R_R(INS_sve_subpt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUBPT   <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
theEmitter->emitIns_R_R_R(INS_sve_subpt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUBPT   <Zd>.D, <Zn>.D, <Zm>.D
// subr
theEmitter->emitIns_R_R_R(INS_sve_subr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUBR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_subr, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // SUBR    <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
// sudot
theEmitter->emitIns_R_R_R_I(INS_sve_sudot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // SUDOT   <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
// sunpkhi
theEmitter->emitIns_R_R(INS_sve_sunpkhi, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SUNPKHI <Zd>.<T>, <Zn>.<Tb>
// sunpklo
theEmitter->emitIns_R_R(INS_sve_sunpklo, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // SUNPKLO <Zd>.<T>, <Zn>.<Tb>
// suqadd
theEmitter->emitIns_R_R_R(INS_sve_suqadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SUQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// sxtb
theEmitter->emitIns_R_R_R(INS_sve_sxtb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SXTB    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// sxth
theEmitter->emitIns_R_R_R(INS_sve_sxth, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SXTH    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// sxtw
theEmitter->emitIns_R_R_R(INS_sve_sxtw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // SXTW    <Zd>.D, <Pg>/M, <Zn>.D
// tbl
theEmitter->emitIns_R_R_R(INS_sve_tbl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TBL     <Zd>.<T>, {<Zn>.<T>}, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_tbl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TBL     <Zd>.<T>, {<Zn1>.<T>, <Zn2>.<T>}, <Zm>.<T>
// tblq
theEmitter->emitIns_R_R_R(INS_sve_tblq, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TBLQ    <Zd>.<T>, {<Zn>.<T>}, <Zm>.<T>
// tbx
theEmitter->emitIns_R_R_R(INS_sve_tbx, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TBX     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// tbxq
theEmitter->emitIns_R_R_R(INS_sve_tbxq, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TBXQ    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// trn1
theEmitter->emitIns_R_R_R(INS_sve_trn1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TRN1    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_trn1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TRN1    <Zd>.Q, <Zn>.Q, <Zm>.Q
theEmitter->emitIns_R_R_R(INS_sve_trn1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TRN1    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
// trn2
theEmitter->emitIns_R_R_R(INS_sve_trn2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TRN2    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_trn2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TRN2    <Zd>.Q, <Zn>.Q, <Zm>.Q
theEmitter->emitIns_R_R_R(INS_sve_trn2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // TRN2    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
// uaba
theEmitter->emitIns_R_R_R(INS_sve_uaba, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UABA    <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
// uabalb
theEmitter->emitIns_R_R_R(INS_sve_uabalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UABALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uabalt
theEmitter->emitIns_R_R_R(INS_sve_uabalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UABALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uabd
theEmitter->emitIns_R_R_R(INS_sve_uabd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UABD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uabdlb
theEmitter->emitIns_R_R_R(INS_sve_uabdlb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UABDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uabdlt
theEmitter->emitIns_R_R_R(INS_sve_uabdlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UABDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uadalp
theEmitter->emitIns_R_R_R(INS_sve_uadalp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UADALP  <Zda>.<T>, <Pg>/M, <Zn>.<Tb>
// uaddlb
theEmitter->emitIns_R_R_R(INS_sve_uaddlb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UADDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uaddlt
theEmitter->emitIns_R_R_R(INS_sve_uaddlt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UADDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uaddv
theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UADDV   <Dd>, <Pg>, <Zn>.<T>
// uaddwb
theEmitter->emitIns_R_R_R(INS_sve_uaddwb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UADDWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// uaddwt
theEmitter->emitIns_R_R_R(INS_sve_uaddwt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UADDWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// uclamp
theEmitter->emitIns_R_R_R(INS_sve_uclamp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// ucvtf
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UCVTF   <Zd>.S, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UCVTF   <Zd>.D, <Pg>/M, <Zn>.S
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UCVTF   <Zd>.S, <Pg>/M, <Zn>.D
theEmitter->emitIns_R_R_R(INS_sve_ucvtf, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UCVTF   <Zd>.D, <Pg>/M, <Zn>.D
// udiv
theEmitter->emitIns_R_R_R(INS_sve_udiv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UDIV    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// udivr
theEmitter->emitIns_R_R_R(INS_sve_udivr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UDIVR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// udot
theEmitter->emitIns_R_R_R(INS_sve_udot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UDOT    <Zda>.S, <Zn>.H, <Zm>.H
theEmitter->emitIns_R_R_R_I(INS_sve_udot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UDOT    <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_udot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UDOT    <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_udot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_udot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UDOT    <Zda>.D, <Zn>.H, <Zm>.H[<imm>]
// uhadd
theEmitter->emitIns_R_R_R(INS_sve_uhadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UHADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uhsub
theEmitter->emitIns_R_R_R(INS_sve_uhsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UHSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uhsubr
theEmitter->emitIns_R_R_R(INS_sve_uhsubr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UHSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// umax
theEmitter->emitIns_R_R_R(INS_sve_umax, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_umax, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UMAX    <Zdn>.<T>, <Zdn>.<T>, #<imm>
// umaxp
theEmitter->emitIns_R_R_R(INS_sve_umaxp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMAXP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// umaxqv
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// umaxv
theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMAXV   <V><d>, <Pg>, <Zn>.<T>
// umin
theEmitter->emitIns_R_R_R(INS_sve_umin, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_umin, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UMIN    <Zdn>.<T>, <Zdn>.<T>, #<imm>
// uminp
theEmitter->emitIns_R_R_R(INS_sve_uminp, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMINP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uminqv
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
// uminv
theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMINV   <V><d>, <Pg>, <Zn>.<T>
// umlalb
theEmitter->emitIns_R_R_R(INS_sve_umlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_umlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_umlalb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// umlalt
theEmitter->emitIns_R_R_R(INS_sve_umlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_umlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_umlalt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// umlslb
theEmitter->emitIns_R_R_R(INS_sve_umlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_umlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_umlslb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// umlslt
theEmitter->emitIns_R_R_R(INS_sve_umlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
theEmitter->emitIns_R_R_R_I(INS_sve_umlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_umlslt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
// ummla
theEmitter->emitIns_R_R_R(INS_sve_ummla, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMMLA   <Zda>.S, <Zn>.B, <Zm>.B
// umulh
theEmitter->emitIns_R_R_R(INS_sve_umulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMULH   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_umulh, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMULH   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// umullb
theEmitter->emitIns_R_R_R_I(INS_sve_umullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_umullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_umullb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// umullt
theEmitter->emitIns_R_R_R_I(INS_sve_umullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
theEmitter->emitIns_R_R_R_I(INS_sve_umullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // UMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
theEmitter->emitIns_R_R_R(INS_sve_umullt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// uqadd
theEmitter->emitIns_R_R_R(INS_sve_uqadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQADD   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_uqadd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQADD   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_R_R(INS_sve_uqadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqcvtn
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQCVTN  <Zd>.H, {<Zn1>.S-<Zn2>.S }
// uqdecb
theEmitter->emitIns_R_I(INS_sve_uqdecb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECB  <Wdn>{, <pattern>{, MUL #<imm>}}
// uqdecd
theEmitter->emitIns_R_I(INS_sve_uqdecd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECD  <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_uqdecd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
// uqdech
theEmitter->emitIns_R_I(INS_sve_uqdech, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECH  <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_uqdech, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
// uqdecp
theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQDECP  <Wdn>, <Pm>.<T>
theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQDECP  <Zdn>.<T>, <Pm>.<T>
// uqdecw
theEmitter->emitIns_R_I(INS_sve_uqdecw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECW  <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_uqdecw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQDECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
// uqincb
theEmitter->emitIns_R_I(INS_sve_uqincb, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCB  <Wdn>{, <pattern>{, MUL #<imm>}}
// uqincd
theEmitter->emitIns_R_I(INS_sve_uqincd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCD  <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_uqincd, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
// uqinch
theEmitter->emitIns_R_I(INS_sve_uqinch, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCH  <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_uqinch, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
// uqincp
theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQINCP  <Wdn>, <Pm>.<T>
theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQINCP  <Zdn>.<T>, <Pm>.<T>
// uqincw
theEmitter->emitIns_R_I(INS_sve_uqincw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCW  <Wdn>{, <pattern>{, MUL #<imm>}}
theEmitter->emitIns_R_I(INS_sve_uqincw, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQINCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
// uqrshl
theEmitter->emitIns_R_R_R(INS_sve_uqrshl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqrshlr
theEmitter->emitIns_R_R_R(INS_sve_uqrshlr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqrshrn
theEmitter->emitIns_R_R_I(INS_sve_uqrshrn, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // UQRSHRN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>
// uqrshrnb
theEmitter->emitIns_R_R_I(INS_sve_uqrshrnb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // UQRSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
// uqrshrnt
theEmitter->emitIns_R_R_I(INS_sve_uqrshrnt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // UQRSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
// uqshl
theEmitter->emitIns_R_R_I(INS_sve_uqshl, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // UQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
theEmitter->emitIns_R_R_R(INS_sve_uqshl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqshlr
theEmitter->emitIns_R_R_R(INS_sve_uqshlr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqshrnb
theEmitter->emitIns_R_R_I(INS_sve_uqshrnb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // UQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
// uqshrnt
theEmitter->emitIns_R_R_I(INS_sve_uqshrnt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // UQSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
// uqsub
theEmitter->emitIns_R_R_R(INS_sve_uqsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQSUB   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_I(INS_sve_uqsub, EA_8BYTE, REG_R0, 5, INS_OPTS_8B);  // UQSUB   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
theEmitter->emitIns_R_R_R(INS_sve_uqsub, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqsubr
theEmitter->emitIns_R_R_R(INS_sve_uqsubr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UQSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// uqxtnb
theEmitter->emitIns_R_R(INS_sve_uqxtnb, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQXTNB  <Zd>.<T>, <Zn>.<Tb>
// uqxtnt
theEmitter->emitIns_R_R(INS_sve_uqxtnt, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UQXTNT  <Zd>.<T>, <Zn>.<Tb>
// urecpe
theEmitter->emitIns_R_R_R(INS_sve_urecpe, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // URECPE  <Zd>.S, <Pg>/M, <Zn>.S
// urhadd
theEmitter->emitIns_R_R_R(INS_sve_urhadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // URHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// urshl
theEmitter->emitIns_R_R_R(INS_sve_urshl, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // URSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// urshlr
theEmitter->emitIns_R_R_R(INS_sve_urshlr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // URSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// urshr
theEmitter->emitIns_R_R_I(INS_sve_urshr, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // URSHR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
// ursqrte
theEmitter->emitIns_R_R_R(INS_sve_ursqrte, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // URSQRTE <Zd>.S, <Pg>/M, <Zn>.S
// ursra
theEmitter->emitIns_R_R_I(INS_sve_ursra, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // URSRA   <Zda>.<T>, <Zn>.<T>, #<const>
// usdot
theEmitter->emitIns_R_R_R(INS_sve_usdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USDOT   <Zda>.S, <Zn>.B, <Zm>.B
theEmitter->emitIns_R_R_R_I(INS_sve_usdot, EA_8BYTE, REG_R0, REG_R1, REG_R2, 5, INS_OPTS_8B);  // USDOT   <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
// ushllb
theEmitter->emitIns_R_R_I(INS_sve_ushllb, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // USHLLB  <Zd>.<T>, <Zn>.<Tb>, #<const>
// ushllt
theEmitter->emitIns_R_R_I(INS_sve_ushllt, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // USHLLT  <Zd>.<T>, <Zn>.<Tb>, #<const>
// usmmla
theEmitter->emitIns_R_R_R(INS_sve_usmmla, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USMMLA  <Zda>.S, <Zn>.B, <Zm>.B
// usqadd
theEmitter->emitIns_R_R_R(INS_sve_usqadd, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
// usra
theEmitter->emitIns_R_R_I(INS_sve_usra, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // USRA    <Zda>.<T>, <Zn>.<T>, #<const>
// usublb
theEmitter->emitIns_R_R_R(INS_sve_usublb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USUBLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// usublt
theEmitter->emitIns_R_R_R(INS_sve_usublt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USUBLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// usubwb
theEmitter->emitIns_R_R_R(INS_sve_usubwb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USUBWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// usubwt
theEmitter->emitIns_R_R_R(INS_sve_usubwt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // USUBWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
// uunpkhi
theEmitter->emitIns_R_R(INS_sve_uunpkhi, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UUNPKHI <Zd>.<T>, <Zn>.<Tb>
// uunpklo
theEmitter->emitIns_R_R(INS_sve_uunpklo, EA_8BYTE, REG_R0, REG_R1, INS_OPTS_8B);  // UUNPKLO <Zd>.<T>, <Zn>.<Tb>
// uxtb
theEmitter->emitIns_R_R_R(INS_sve_uxtb, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UXTB    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// uxth
theEmitter->emitIns_R_R_R(INS_sve_uxth, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UXTH    <Zd>.<T>, <Pg>/M, <Zn>.<T>
// uxtw
theEmitter->emitIns_R_R_R(INS_sve_uxtw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UXTW    <Zd>.D, <Pg>/M, <Zn>.D
// uzp1
theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZP1    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZP1    <Zd>.Q, <Zn>.Q, <Zm>.Q
theEmitter->emitIns_R_R_R(INS_sve_uzp1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZP1    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
// uzp2
theEmitter->emitIns_R_R_R(INS_sve_uzp2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZP2    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_uzp2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZP2    <Zd>.Q, <Zn>.Q, <Zm>.Q
theEmitter->emitIns_R_R_R(INS_sve_uzp2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZP2    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
// uzpq1
theEmitter->emitIns_R_R_R(INS_sve_uzpq1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZPQ1   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// uzpq2
theEmitter->emitIns_R_R_R(INS_sve_uzpq2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // UZPQ2   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// whilege
theEmitter->emitIns_R_R_R(INS_sve_whilege, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEGE <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilege, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEGE {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilege, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEGE <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilegt
theEmitter->emitIns_R_R_R(INS_sve_whilegt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEGT <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilegt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEGT {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilegt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEGT <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilehi
theEmitter->emitIns_R_R_R(INS_sve_whilehi, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEHI <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilehi, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEHI {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilehi, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEHI <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilehs
theEmitter->emitIns_R_R_R(INS_sve_whilehs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEHS <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilehs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEHS {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilehs, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEHS <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilele
theEmitter->emitIns_R_R_R(INS_sve_whilele, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELE <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilele, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELE {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilele, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELE <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilelo
theEmitter->emitIns_R_R_R(INS_sve_whilelo, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELO <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilelo, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELO {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilelo, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELO <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilels
theEmitter->emitIns_R_R_R(INS_sve_whilels, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELS <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilels, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELS {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilels, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELS <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilelt
theEmitter->emitIns_R_R_R(INS_sve_whilelt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELT <Pd>.<T>, <R><n>, <R><m>
theEmitter->emitIns_R_R_R(INS_sve_whilelt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELT {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
theEmitter->emitIns_R_R_R(INS_sve_whilelt, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILELT <PNd>.<T>, <Xn>, <Xm>, <vl>
// whilerw
theEmitter->emitIns_R_R_R(INS_sve_whilerw, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILERW <Pd>.<T>, <Xn>, <Xm>
// whilewr
theEmitter->emitIns_R_R_R(INS_sve_whilewr, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // WHILEWR <Pd>.<T>, <Xn>, <Xm>
// wrffr
theEmitter->emitIns_R(INS_sve_wrffr, EA_8BYTE, REG_R0, INS_OPTS_8B);  // WRFFR   <Pn>.B
// xar
theEmitter->emitIns_R_R_I(INS_sve_xar, EA_8BYTE, REG_R0, REG_R1, 5, INS_OPTS_8B);  // XAR     <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<const>
// zip1
theEmitter->emitIns_R_R_R(INS_sve_zip1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIP1    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_zip1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIP1    <Zd>.Q, <Zn>.Q, <Zm>.Q
theEmitter->emitIns_R_R_R(INS_sve_zip1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIP1    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
// zip2
theEmitter->emitIns_R_R_R(INS_sve_zip2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIP2    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
theEmitter->emitIns_R_R_R(INS_sve_zip2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIP2    <Zd>.Q, <Zn>.Q, <Zm>.Q
theEmitter->emitIns_R_R_R(INS_sve_zip2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIP2    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
// zipq1
theEmitter->emitIns_R_R_R(INS_sve_zipq1, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIPQ1   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
// zipq2
theEmitter->emitIns_R_R_R(INS_sve_zipq2, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ZIPQ2   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>