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sim.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 04:52:15 February 10, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# sim_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY tb
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "04:52:15 FEBRUARY 10, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE sim/cells/fdr.v
set_global_assignment -name VERILOG_FILE sim/cells/fds.v
set_global_assignment -name VERILOG_FILE sim/k007232.v
set_global_assignment -name VERILOG_FILE sim/CNT3.v
set_global_assignment -name VERILOG_FILE sim/CNT2.v
set_global_assignment -name VERILOG_FILE sim/CNT1.v
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80s.vhd
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80pa.vhd
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE sim/cpu/T80/T80.vhd
set_global_assignment -name QIP_FILE sim/cpu/T80/T80.qip
set_global_assignment -name SYSTEMVERILOG_FILE sim/cpu/FX68K/uaddrPla.sv
set_global_assignment -name SYSTEMVERILOG_FILE sim/cpu/FX68K/fx68kAlu.sv
set_global_assignment -name SYSTEMVERILOG_FILE sim/cpu/FX68K/fx68k.sv
set_global_assignment -name QIP_FILE sim/cpu/FX68K/fx68k.qip
set_global_assignment -name VERILOG_FILE sim/cpu/cpu_z80.v
set_global_assignment -name VERILOG_FILE sim/cpu/cpu_68k.v
set_global_assignment -name VERILOG_FILE sim/rom.v
set_global_assignment -name VERILOG_FILE sim/tmnt.v
set_global_assignment -name VERILOG_FILE sim/tb.v
set_global_assignment -name VERILOG_FILE sim/SHIFTER.v
set_global_assignment -name VERILOG_FILE sim/ram.v
set_global_assignment -name VERILOG_FILE sim/pll.v
set_global_assignment -name VERILOG_FILE sim/mycore.v
set_global_assignment -name VERILOG_FILE sim/lfsr.v
set_global_assignment -name VERILOG_FILE sim/k051960.v
set_global_assignment -name VERILOG_FILE sim/k051937.v
set_global_assignment -name VERILOG_FILE sim/k_reg.v
set_global_assignment -name VERILOG_FILE sim/color.v
set_global_assignment -name VERILOG_FILE sim/audio.v
set_global_assignment -name VERILOG_FILE sim/k051962.v
set_global_assignment -name VERILOG_FILE sim/rom_prio.v
set_global_assignment -name VERILOG_FILE sim/cells/fdn.v
set_global_assignment -name VERILOG_FILE sim/cells/fdo.v
set_global_assignment -name VERILOG_FILE sim/cells/fdm.v
set_global_assignment -name VERILOG_FILE sim/cells/fdg.v
set_global_assignment -name VERILOG_FILE sim/cells/fde.v
set_global_assignment -name VERILOG_FILE sim/k052109.v
set_global_assignment -name VERILOG_FILE sim/planes.v
set_global_assignment -name VERILOG_FILE sim/sprites.v
set_global_assignment -name VERILOG_FILE sim/cells/t34.v
set_global_assignment -name VERILOG_FILE sim/cells/ltl.v
set_global_assignment -name VERILOG_FILE sim/cells/t5a.v
set_global_assignment -name VERILOG_FILE sim/cells/a4h.v
set_global_assignment -name VERILOG_FILE sim/cells/u24.v
set_global_assignment -name VERILOG_FILE sim/cells/de2.v
set_global_assignment -name VERILOG_FILE sim/cells/a2n.v
set_global_assignment -name VERILOG_FILE sim/cells/t2d.v
set_global_assignment -name VERILOG_FILE sim/k052109_scroll.v
set_global_assignment -name VERILOG_FILE sim/cells/c11.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top