From 21092ad11193ecf7bfec9abc75f0ee844c1a9c5d Mon Sep 17 00:00:00 2001
From: Wang Wangwang <wangwang.wang@intel.com>
Date: Tue, 18 Feb 2025 13:38:07 +0800
Subject: [PATCH 01/20] Update access modifiers for CPU impls (#28286)

### Details:
 - *Add buffer_ptr() API in gpu_buffer struct*
- *Mark the output in reorder cpu implementation as read_write to enable
the result(type is reorder) with cl_mem*


![image](https://github.com/user-attachments/assets/de724d96-4941-4ceb-80e5-78c83963297d)
When use HETERO:GPU.0,GPU.1 pipeline parallel split the llama_v2 model,
there is a `__module.model.layers.0.self_attn/prim::ListConstruct_3`
node is marked in shape_of subgraph, and it's result will pass to next
device, thus this node and it's result node can only get CPU
implementations.

In inference stage, when prepare outputs for the Result_44438, B580 dGPU
will only use cl_mem in
https://github.com/openvinotoolkit/openvino/blob/d757efd7fb3415a3dbda10941b3dae0ace0ac16e/src/plugins/intel_gpu/src/plugin/sync_infer_request.cpp#L548,
the reorder cpu impl can not set result to cl_mem.

So, we have two solutions:
1. Use this PR mark reorder output_lock in cpu impl to read_write, so it
can use cl_mem
2. In [PR28476](https://github.com/openvinotoolkit/openvino/pull/28476)
Skip mark_node for result node with reorder type

### Tickets:
 - *CVS-158971*

---------

Co-authored-by: River Li <river.li@intel.com>
---
 .../include/intel_gpu/runtime/device.hpp      |  1 +
 .../src/graph/impls/cpu/broadcast.cpp         |  2 +-
 .../intel_gpu/src/graph/impls/cpu/concat.cpp  |  2 +-
 .../src/graph/impls/cpu/fake_convert.cpp      |  2 +-
 .../intel_gpu/src/graph/impls/cpu/gather.cpp  |  2 +-
 .../intel_gpu/src/graph/impls/cpu/range.cpp   |  2 +-
 .../intel_gpu/src/graph/impls/cpu/reorder.cpp |  2 +-
 .../src/graph/impls/cpu/scatter_update.cpp    |  2 +-
 .../intel_gpu/src/graph/impls/cpu/select.cpp  |  2 +-
 .../intel_gpu/src/graph/impls/cpu/tile.cpp    |  2 +-
 .../intel_gpu/src/runtime/ocl/ocl_device.cpp  |  4 ++
 .../intel_gpu/src/runtime/ocl/ocl_device.hpp  |  2 +
 .../intel_gpu/src/runtime/ocl/ocl_memory.hpp  |  3 +
 .../tests/unit/module_tests/device_test.cpp   |  3 +
 .../test_cases/activation_simple_gpu_test.cpp | 60 +++++++++++++++++
 .../test_cases/concatenation_gpu_test.cpp     | 65 +++++++++++++++++++
 .../tests/unit/test_cases/crop_gpu_test.cpp   | 53 +++++++++++++++
 .../unit/test_cases/eltwise_gpu_test.cpp      | 21 ++++--
 .../tests/unit/test_cases/gather_gpu_test.cpp | 40 ++++++++++++
 .../unit/test_cases/reorder_gpu_test.cpp      | 36 ++++++++++
 .../unit/test_cases/shape_of_gpu_test.cpp     | 19 ++++--
 .../test_cases/strided_slice_gpu_test.cpp     | 14 ++--
 .../tests/unit/test_cases/tile_gpu_test.cpp   | 40 ++++++++++++
 .../tests/unit/test_utils/test_utils.cpp      | 23 +++++++
 .../tests/unit/test_utils/test_utils.h        |  6 ++
 25 files changed, 383 insertions(+), 25 deletions(-)

diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/device.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/device.hpp
index c393a0174b8c2e..9711cdfa1ea386 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/device.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/device.hpp
@@ -25,6 +25,7 @@ struct device {
 
     float get_gops(cldnn::data_types dt) const;
     bool use_unified_shared_memory() const;
+    virtual void set_mem_caps(memory_capabilities memory_capabilities) = 0;
 
     virtual ~device() = default;
 };
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/broadcast.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/broadcast.cpp
index 772fe2751adae0..e86c69a61b3d85 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/broadcast.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/broadcast.cpp
@@ -99,7 +99,7 @@ struct broadcast_impl : public typed_primitive_impl<broadcast> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
         output_host_tensors.push_back(make_tensor(params->output_layouts[0], output_lock.data()));
 
         OPENVINO_ASSERT(op->evaluate(output_host_tensors, input_host_tensors),
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/concat.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/concat.cpp
index ad1f4979141f56..34608a8aed6a3d 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/concat.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/concat.cpp
@@ -80,7 +80,7 @@ struct concatenation_impl : public typed_primitive_impl<concatenation> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
 
         output_host_tensors.push_back(make_tensor(params->output_layouts[0], output_lock.data()));
 
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/fake_convert.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/fake_convert.cpp
index 47a9f1ef02db99..ad6f35608a0959 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/fake_convert.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/fake_convert.cpp
@@ -74,7 +74,7 @@ struct fake_convert_impl : public typed_primitive_impl<fake_convert> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
 
         for (size_t i = 0; i < input_mem_ptrs.size(); i++)
             input_host_tensors.push_back(make_tensor(params->input_layouts[i], input_mem_ptrs[i]->lock(stream, mem_lock_type::read)));
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/gather.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/gather.cpp
index e46a9892d64cb5..09a2baa122be64 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/gather.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/gather.cpp
@@ -82,7 +82,7 @@ struct gather_impl : public typed_primitive_impl<gather> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
 
         for (size_t i = 0; i < input_mem_ptrs.size(); i++)
             input_host_tensors.push_back(make_tensor(params->input_layouts[i], input_mem_ptrs[i]->lock(stream, mem_lock_type::read)));
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/range.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/range.cpp
index c3ec254a48576b..f3c3fbcf07bada 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/range.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/range.cpp
@@ -55,7 +55,7 @@ struct range_impl : public typed_primitive_impl<range> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
 
         for (size_t i = 0; i < input_mem_ptrs.size(); i++)
             input_host_tensors.push_back(make_tensor(params->input_layouts[i], input_mem_ptrs[i]->lock(stream, mem_lock_type::read)));
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/reorder.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/reorder.cpp
index abcd6569acb9b7..6fc63f8c6eeddb 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/reorder.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/reorder.cpp
@@ -56,7 +56,7 @@ struct reorder_impl : public typed_primitive_impl<reorder> {
         auto output_mem_ptr = instance.output_memory_ptr();
 
         cldnn::mem_lock<uint8_t, mem_lock_type::read> input_lock(input_mem_ptr, stream);
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
 
         input_host_tensors.push_back(make_tensor(params->input_layouts[0], input_lock.data()));
         output_host_tensors.push_back(make_tensor(params->output_layouts[0], output_lock.data()));
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/scatter_update.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/scatter_update.cpp
index b27fe10bf64ecc..695c4781166ebe 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/scatter_update.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/scatter_update.cpp
@@ -71,7 +71,7 @@ struct scatter_update_impl : public typed_primitive_impl<scatter_update> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
 
         for (size_t i = 0; i < input_mem_ptrs.size(); i++)
             input_host_tensors.push_back(make_tensor(params->input_layouts[i], input_mem_ptrs[i]->lock(stream, mem_lock_type::read)));
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/select.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/select.cpp
index 6aa27fea1d4990..69be7bc871b734 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/select.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/select.cpp
@@ -76,7 +76,7 @@ struct select_impl : public typed_primitive_impl<select> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<uint8_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<uint8_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
         output_host_tensors.push_back(make_tensor(params->output_layouts[0], output_lock.data()));
 
         OPENVINO_ASSERT(op->evaluate(output_host_tensors, input_host_tensors),
diff --git a/src/plugins/intel_gpu/src/graph/impls/cpu/tile.cpp b/src/plugins/intel_gpu/src/graph/impls/cpu/tile.cpp
index 2650c7716546cb..1784b2d0058844 100644
--- a/src/plugins/intel_gpu/src/graph/impls/cpu/tile.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/cpu/tile.cpp
@@ -83,7 +83,7 @@ struct tile_impl : public typed_primitive_impl<tile> {
 
         auto output_mem_ptr = instance.output_memory_ptr();
 
-        cldnn::mem_lock<int32_t, mem_lock_type::read> output_lock(output_mem_ptr, stream);
+        cldnn::mem_lock<int32_t, mem_lock_type::read_write> output_lock(output_mem_ptr, stream);
         output_host_tensors.push_back(make_tensor(params->output_layouts[0], output_lock.data()));
 
         OPENVINO_ASSERT(op->evaluate(output_host_tensors, input_host_tensors),
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp
index 441494b41c4f8f..6e2e15fadd43ff 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp
@@ -391,5 +391,9 @@ bool ocl_device::is_same(const device::ptr other) {
     return _device == casted->get_device() && _platform == casted->get_platform();
 }
 
+void ocl_device::set_mem_caps(memory_capabilities memory_capabilities) {
+    _mem_caps = memory_capabilities;
+}
+
 }  // namespace ocl
 }  // namespace cldnn
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.hpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.hpp
index 72cec648ad73b1..5c2b5c1ed66bcd 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.hpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.hpp
@@ -25,6 +25,8 @@ struct ocl_device : public device {
 
     bool is_same(const device::ptr other) override;
 
+    void set_mem_caps(memory_capabilities memory_capabilities) override;
+
     ~ocl_device() = default;
 
 private:
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_memory.hpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_memory.hpp
index 2d49257845bc92..9124e0517772ed 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_memory.hpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_memory.hpp
@@ -39,6 +39,9 @@ struct gpu_buffer : public lockable_gpu_mem, public memory {
         assert(0 == _lock_count);
         return _buffer;
     }
+    void* buffer_ptr() const override {
+        return get_buffer().get();
+    }
 
     event::ptr copy_from(stream& stream, const void* data_ptr, size_t src_offset, size_t dst_offset, size_t size, bool blocking) override;
     event::ptr copy_from(stream& stream, const memory& src_mem, size_t src_offset, size_t dst_offset, size_t size, bool blocking) override;
diff --git a/src/plugins/intel_gpu/tests/unit/module_tests/device_test.cpp b/src/plugins/intel_gpu/tests/unit/module_tests/device_test.cpp
index b27275d0f03d99..c25b77400ebf1d 100644
--- a/src/plugins/intel_gpu/tests/unit/module_tests/device_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/module_tests/device_test.cpp
@@ -27,6 +27,9 @@ struct dummy_device : public device {
         return this == other.get();
     }
 
+    void set_mem_caps(memory_capabilities memory_capabilities) override {
+        _mem_caps = memory_capabilities;
+    }
     ~dummy_device() = default;
 
 private:
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/activation_simple_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/activation_simple_gpu_test.cpp
index 6248a85e155e5a..11766a78e944f7 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/activation_simple_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/activation_simple_gpu_test.cpp
@@ -156,6 +156,66 @@ TEST(activation_f32_fw_cpu_impl, dynamic_8d) {
     }
 }
 
+TEST(activation_f32_fw_cpu, not_basic_yxfb_disable_usm) {
+    //  Input:
+    //  1  0 -3  4  5
+    //  0  2  3  4 -6
+    //  3 -3  3  0  1
+    //  1  1  1 -1  0
+    //
+    //  Output:
+    //  0, 1, 0, 0, 0,
+    //  1, 0, 0, 0, 0,
+    //  0, 0, 0, 1, 0,
+    //  0, 0, 0, 0, 1
+
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, false);
+
+    auto input = engine->allocate_memory({ data_types::f32, format::yxfb, { 1, 1, 5, 4 } });
+    set_values(input,
+    { 1.0f, 0.0f, -3.0f, 4.0f, 5.0f,
+      0.0f, 2.0f, 3.0f, 4.0f, -6.0f,
+      3.0f, -3.0f, 3.0f, 0.0f, 1.0f,
+      1.0f, 1.0f, 1.0f, -1.0f, 0.0f });
+    VF<float> output_vec = {
+        0.0f, 1.0f, 0.0f, 0.0f, 0.0f,
+        1.0f, 0.0f, 0.0f, 0.0f, 0.0f,
+        0.0f, 0.0f, 0.0f, 1.0f, 0.0f,
+        0.0f, 0.0f, 0.0f, 0.0f, 1.0f };
+
+    topology topology(
+        input_layout("input", input->get_layout()),
+        activation("not", input_info("input"), activation_func::negation));
+
+    ExecutionConfig config = get_test_default_config(*engine);
+    auto forcing_map = ov::intel_gpu::ImplForcingMap{ {"not", {format::yxfb, "", impl_types::cpu}} };
+    config.set_property(ov::intel_gpu::force_implementations(forcing_map));
+
+    network network(*engine, topology, config);
+    network.set_input_data("input", input);
+    auto outputs = network.execute();
+    ASSERT_EQ(outputs.size(), size_t(1));
+    ASSERT_EQ(outputs.begin()->first, "not");
+
+    auto output_memory = outputs.at("not").get_memory();
+    auto output_layout = output_memory->get_layout();
+    cldnn::mem_lock<float> output_ptr(output_memory, get_test_stream());
+
+    int y_size = output_layout.spatial(1);
+    int x_size = output_layout.spatial(0);
+    int f_size = output_layout.feature();
+    int b_size = output_layout.batch();
+    ASSERT_EQ(output_layout.format, format::yxfb);
+    ASSERT_EQ(y_size, 4);
+    ASSERT_EQ(x_size, 5);
+    ASSERT_EQ(f_size, 1);
+    ASSERT_EQ(b_size, 1);
+
+    for (size_t i = 0; i < output_vec.size(); ++i) {
+        ASSERT_FLOAT_EQ(output_vec[i], output_ptr[i]);
+    }
+}
+
 TEST(activation_f32_fw_gpu, not_basic_yxfb) {
     //  Input:
     //  1  0 -3  4  5
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp
index dccacc1f481465..ebcad325112310 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp
@@ -91,6 +91,71 @@ TEST(concat_gpu, mixed_input_types) {
     }
 }
 
+TEST(concat_cpu, disable_usm) {
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, false);
+
+    auto input0 = engine->allocate_memory({ data_types::i8, format::bfyx, { 1, 1, 4, 3 } });
+    auto input1 = engine->allocate_memory({ data_types::i8, format::bfyx, { 1, 1, 4, 3 } });
+    auto input2 = engine->allocate_memory({ data_types::i8, format::bfyx, { 1, 1, 4, 3 } });
+    auto input3 = engine->allocate_memory({ data_types::i8, format::bfyx, { 1, 1, 4, 3 } });
+    auto input4 = engine->allocate_memory({ data_types::i8, format::bfyx, { 1, 1, 4, 3 } });
+
+    set_values<int8_t>(input0, { 1, 2, 3, 4, 2, 2, 3, 4, 3, 3, 3, 5 });
+    set_values<int8_t>(input1, { 11, 12, 13, 14, 12, 12, 13, 14, 13, 13, 13, 15 });
+    set_values<int8_t>(input2, { 21, 22, 23, 24, 22, 22, 23, 24, 23, 23, 23, 25 });
+    set_values<int8_t>(input3, { 31, 32, 33, 34, 32, 32, 33, 34, 33, 33, 33, 35 });
+    set_values<int8_t>(input4, { 41, 42, 43, 44, 42, 42, 43, 44, 43, 43, 43, 45 });
+
+    std::vector<int8_t> output_vec = {
+            1, 2, 3, 4, 2, 2, 3, 4, 3, 3, 3, 5,
+            11, 12, 13, 14, 12, 12, 13, 14, 13, 13, 13, 15,
+            21, 22, 23, 24, 22, 22, 23, 24, 23, 23, 23, 25,
+            31, 32, 33, 34, 32, 32, 33, 34, 33, 33, 33, 35,
+            41, 42, 43, 44, 42, 42, 43, 44, 43, 43, 43, 45 };
+
+    topology topology(
+            input_layout("input0", input0->get_layout()),
+            input_layout("input1", input1->get_layout()),
+            input_layout("input2", input2->get_layout()),
+            input_layout("input3", input3->get_layout()),
+            input_layout("input4", input4->get_layout()),
+            concatenation("concat",
+                          { input_info("input0"), input_info("input1"), input_info("input2"), input_info("input3"), input_info("input4") },
+                          1,
+                          data_types::i8)
+    );
+    ExecutionConfig cfg = get_test_default_config(*engine);
+    cfg.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"concat", {format::bfyx, "", impl_types::cpu}} }));
+    network network(*engine, topology, cfg);
+    network.set_input_data("input0", input0);
+    network.set_input_data("input1", input1);
+    network.set_input_data("input2", input2);
+    network.set_input_data("input3", input3);
+    network.set_input_data("input4", input4);
+
+    auto outputs = network.execute();
+    ASSERT_EQ(outputs.size(), size_t(1));
+    ASSERT_EQ(outputs.begin()->first, "concat");
+
+    auto output_memory = outputs.at("concat").get_memory();
+    auto output_layout = output_memory->get_layout();
+    cldnn::mem_lock<int8_t> output_ptr(output_memory, get_test_stream());
+
+    int y_size = output_layout.spatial(1);
+    int x_size = output_layout.spatial(0);
+    int f_size = output_layout.feature();
+    int b_size = output_layout.batch();
+    ASSERT_EQ(output_layout.format, format::bfyx);
+    ASSERT_EQ(y_size, 3);
+    ASSERT_EQ(x_size, 4);
+    ASSERT_EQ(f_size, 5);
+    ASSERT_EQ(b_size, 1);
+
+    for (size_t x = 0; x < output_layout.count(); ++x) {
+        ASSERT_EQ(output_vec[x], output_ptr[x]);
+    }
+}
+
 void start_concat_test_dynamic(impl_types impl_type = impl_types::any);
 void start_concat_test_dynamic(impl_types impl_type) {
     auto& engine = get_test_engine();
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp
index 72a52675377405..385c6bf812cd41 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp
@@ -1341,6 +1341,59 @@ INSTANTIATE_TEST_SUITE_P(crop_test, crop_gpu_dynamic,
                                 ::testing::ValuesIn(impls)
                                 ));
 
+TEST(crop_cpu, basic_in2x3x2x2_crop_all_bfyx_disable_usm) {
+    //  Reference  : 3x1x2x2
+    //  Input      : 6x2x4x3
+    //  Output     : 3x1x2x2
+
+    tests::random_generator rg(GET_SUITE_NAME);
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, false);
+
+    auto batch_num = 6;
+    auto feature_num = 2;
+    auto x_size = 4;
+    auto y_size = 3;
+
+    auto crop_batch_num = batch_num - 3;
+    auto crop_feature_num = feature_num - 1;
+    auto crop_x_size = x_size - 2;
+    auto crop_y_size = y_size - 1;
+
+    auto input = engine->allocate_memory({ data_types::f32,format::bfyx,{ batch_num, feature_num, x_size, y_size } });
+
+    topology topology;
+    topology.add(input_layout("input", input->get_layout()));
+    topology.add(crop("crop", input_info("input"), { crop_batch_num, crop_feature_num, crop_x_size, crop_y_size }, {0, 0, 0, 0} ));
+
+    std::vector<float> input_vec = rg.generate_random_1d<float>(input->count(), -10, 10);
+    set_values(input, input_vec);
+
+    ExecutionConfig config = get_test_default_config(*engine);
+    config.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"crop", {format::bfyx, "", impl_types::cpu}} }));
+
+    network network(*engine, topology, config);
+
+    network.set_input_data("input", input);
+
+    auto outputs = network.execute();
+
+    auto output = outputs.at("crop").get_memory();
+    cldnn::mem_lock<float> output_ptr(output, get_test_stream());
+    std::vector<float> a;
+    for (int b = 0; b < crop_batch_num; ++b) { //B
+        for (int f = 0; f < crop_feature_num; ++f) { //F
+            for (int y = 0; y < crop_y_size; ++y) { //Y
+                for (int x = 0; x < crop_x_size; ++x) { //X
+                    int linear_id = x + x_size * (y + y_size * (f + feature_num * b));
+                    int output_linear_id = x + crop_x_size * (y + crop_y_size * (f + crop_feature_num * b));
+                    a.push_back(output_ptr[output_linear_id]);
+                    ASSERT_EQ(output_ptr[output_linear_id], input_vec[linear_id]);
+                }
+            }
+        }
+    }
+}
+
 TEST(crop_gpu, dynamic_in1x4x1x1_split) {
     auto& engine = get_test_engine();
 
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp
index bdb9bbdbfe2051..47d1af9667c67c 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp
@@ -1751,11 +1751,12 @@ TEST(eltwise_gpu_f32, add_basic_8d) {
     }
 }
 
-TEST(eltwise_cpu_impl_f32, add_basic_8d) {
-    auto& engine = get_test_engine();
+void eltwise_cpu_impl_f32(bool disable_usm = false);
+void eltwise_cpu_impl_f32(bool disable_usm) {
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, !disable_usm);
 
-    auto input1 = engine.allocate_memory({{1, 3, 2, 2, 2, 3, 2, 3}, data_types::f32, format::bfvuwzyx });
-    auto input2 = engine.allocate_memory({{1, 3, 2, 2, 2, 3, 2, 3}, data_types::f32, format::bfvuwzyx });
+    auto input1 = engine->allocate_memory({{1, 3, 2, 2, 2, 3, 2, 3}, data_types::f32, format::bfvuwzyx });
+    auto input2 = engine->allocate_memory({{1, 3, 2, 2, 2, 3, 2, 3}, data_types::f32, format::bfvuwzyx });
 
     topology topology;
     topology.add(input_layout("input1", input1->get_layout()));
@@ -1770,11 +1771,11 @@ TEST(eltwise_cpu_impl_f32, add_basic_8d) {
         std::iota(lock2.begin(), lock2.end(), 0);
     }
 
-    auto config = get_test_default_config(engine);
+    auto config = get_test_default_config(*engine);
     auto forcing_map = ov::intel_gpu::ImplForcingMap{ {"eltwise", {format::bfvuwzyx, "", impl_types::cpu}} };
     config.set_property(ov::intel_gpu::force_implementations(forcing_map));
     config.set_property(ov::intel_gpu::allow_new_shape_infer(true));
-    network network(engine, topology, config);
+    network network(*engine, topology, config);
 
     network.set_input_data("input1", input1);
     network.set_input_data("input2", input2);
@@ -1794,6 +1795,14 @@ TEST(eltwise_cpu_impl_f32, add_basic_8d) {
     }
 }
 
+TEST(eltwise_cpu_impl_f32, add_basic_8d) {
+    eltwise_cpu_impl_f32();
+}
+
+TEST(eltwise_cpu_impl_f32, add_basic_8d_disable_usm) {
+    eltwise_cpu_impl_f32(true);
+}
+
 TEST(eltwise_gpu_f32, add_basic_in4x4x2x2) {
     //  Input2   : 2x2x2
     //  Input  : 2x2x2x2
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/gather_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/gather_gpu_test.cpp
index a2127a66dc6f0c..0eade851b2ac0d 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/gather_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/gather_gpu_test.cpp
@@ -2049,6 +2049,46 @@ TEST(gather_cpu_impl_fp32, dynamic_322_axisF) {
     }
 }
 
+TEST(gather_cpu_fp32, indice_out_of_bound_disable_usm) {
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, false);
+
+    ov::Shape in1_shape = { 3, 3 };
+    ov::Shape in2_shape = { 2, 2 };
+    auto in1_layout = layout{in1_shape, data_types::f32, format::bfyx};
+    auto in2_layout = layout{in2_shape, data_types::i32, format::bfyx};
+    auto input1 = engine->allocate_memory(layout{ov::PartialShape(in1_shape), data_types::f32, format::bfyx}); // data
+    auto input2 = engine->allocate_memory(layout{ov::PartialShape(in2_shape), data_types::i32, format::bfyx}); // Indexes
+
+    int64_t axis = 1;
+    set_values(input1, {0, 1, 2, 10, 11, 12, 20, 21, 22 });
+    set_values(input2, {1, 0, 2, 3});
+
+    topology topology;
+    topology.add(input_layout("input1", in1_layout));
+    topology.add(input_layout("input2", in2_layout));
+    topology.add(gather("gather", input_info("input1"), input_info("input2"), axis, 0, ov::Shape{}, 0, true));
+
+    ExecutionConfig config = get_test_default_config(*engine);
+    config.set_property(ov::intel_gpu::allow_new_shape_infer(true));
+    config.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"gather", {format::bfyx, "", impl_types::cpu}} }));
+
+    network network(*engine, topology, config);
+    network.set_input_data("input1", input1);
+    network.set_input_data("input2", input2);
+
+    auto outputs = network.execute();
+
+    auto output = outputs.at("gather").get_memory();
+    cldnn::mem_lock<int> output_ptr(output, get_test_stream());
+
+    std::vector<int> expected_results = {1, 0, 2, 0,  11, 10, 12, 0,  21, 20, 22, 0};
+
+    ASSERT_EQ(expected_results.size(), output_ptr.size());
+    for (size_t i = 0; i < expected_results.size(); ++i) {
+        ASSERT_EQ(expected_results[i], output_ptr[i]) << i;
+    }
+}
+
 template <typename T>
 void test_gather_gpu_u8_322_axisF(bool is_caching_test) {
     //  Dictionary : 3x3x1x1
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp
index d3b3d8fea5b615..60fc52135f2068 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp
@@ -2731,6 +2731,42 @@ TEST(reorder_gpu, any_format) {
     }
 }
 
+void reorder_cpu_any_format(bool disable_usm = false);
+void reorder_cpu_any_format(bool disable_usm) {
+    tests::random_generator rg(GET_SUITE_NAME);
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, !disable_usm);
+
+    auto input = engine->allocate_memory(layout(data_types::f32, format::yxfb, tensor(5, 7, 13, 9)));
+
+    topology topo;
+    topo.add(input_layout("in", input->get_layout()));
+    topo.add(reorder("reorder", input_info("in"), format::any, data_types::f32));
+    ExecutionConfig config = get_test_default_config(*engine);
+    config.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"reorder", {format::any, "", impl_types::cpu}} }));
+
+    network net(*engine, topo, config);
+
+    auto data = rg.generate_random_1d<float>(input->count(), -1, 1);
+    set_values(input, data);
+    net.set_input_data("in", input);
+
+    auto outputs = net.execute();
+    auto out_mem = outputs.at("reorder").get_memory();
+    cldnn::mem_lock<float> output(out_mem, get_test_stream());
+
+    for (size_t i = 0; i < data.size(); ++i) {
+        ASSERT_EQ(output[i], data[i]) << "i = " << i;
+    }
+}
+
+TEST(reorder_cpu, any_format) {
+    reorder_cpu_any_format();
+}
+
+TEST(reorder_cpu, any_format_disable_usm) {
+    reorder_cpu_any_format(true);
+}
+
 TEST(reorder_image2d_rgba_to_bfyx_gpu, basic)
 {
     auto& engine = get_test_engine();
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/shape_of_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/shape_of_gpu_test.cpp
index b18a1386dfed06..ebb62dc769c40a 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/shape_of_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/shape_of_gpu_test.cpp
@@ -66,19 +66,20 @@ TEST(shape_of_gpu, bfyx_i64) {
     }
 }
 
-TEST(shape_of_cpu_impl, bfyx_i64) {
-    auto& engine = get_test_engine();
+void shape_of_cpu_impl_bfyx_i64(bool disable_usm = false);
+void shape_of_cpu_impl_bfyx_i64(bool disable_usm) {
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, !disable_usm);
 
-    auto input = engine.allocate_memory({data_types::f32, format::bfyx, tensor{1, 2, 3, 3}});
+    auto input = engine->allocate_memory({data_types::f32, format::bfyx, tensor{1, 2, 3, 3}});
 
     topology topology;
     topology.add(input_layout("input", input->get_layout()));
     topology.add(shape_of("shape_of", input_info("input"), data_types::i64));
 
-    ExecutionConfig config = get_test_default_config(engine);
+    ExecutionConfig config = get_test_default_config(*engine);
     config.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"shape_of", {format::bfyx, "", impl_types::cpu}} }));
 
-    network network(engine, topology, config);
+    network network(*engine, topology, config);
 
     network.set_input_data("input", input);
 
@@ -94,6 +95,14 @@ TEST(shape_of_cpu_impl, bfyx_i64) {
     }
 }
 
+TEST(shape_of_cpu_impl, bfyx_i64) {
+    shape_of_cpu_impl_bfyx_i64();
+}
+
+TEST(shape_of_cpu_impl, bfyx_i64_disable_usm) {
+    shape_of_cpu_impl_bfyx_i64(true);
+}
+
 TEST(shape_of_gpu, yxfb) {
     auto& engine = get_test_engine();
 
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/strided_slice_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/strided_slice_gpu_test.cpp
index bfb4a416c16c5d..fa9fce6b6b46e5 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/strided_slice_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/strided_slice_gpu_test.cpp
@@ -584,12 +584,12 @@ class strided_slice_gpu: public ::testing::Test {
         }
     }
 
-    void test_2x2x1x1(bool is_caching_test, impl_types impl_type = impl_types::any) {
+    void test_2x2x1x1(bool is_caching_test, impl_types impl_type = impl_types::any, bool disable_usm = false) {
         // Input (BFYX): 2x2x1x1
         // Output (BFYX): 2x2x1x1
 
-        auto& engine = get_test_engine();
-        auto input = engine.allocate_memory({ data_types::f32, format::bfyx, { 2, 2, 1, 1 } });
+        auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, !disable_usm);
+        auto input = engine->allocate_memory({ data_types::f32, format::bfyx, { 2, 2, 1, 1 } });
 
         set_values(input, {
                 0.0f, 1.0f, 2.0f, 3.0f
@@ -602,11 +602,11 @@ class strided_slice_gpu: public ::testing::Test {
         topology.add(input_layout("input", input->get_layout()));
         topology.add(strided_slice("strided_slice", input_info("input"), begin_data, end_data, strides_data, {1, 0}, {}, {}, {}, {}, {2, 2, 1, 1}));
 
-        auto config = get_test_default_config(engine);
+        auto config = get_test_default_config(*engine);
         if (impl_type != impl_types::any)
             config.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"strided_slice", {format::bfyx, "", impl_types::cpu}} }));
 
-        cldnn::network::ptr network = get_network(engine, topology, config, get_test_stream_ptr(), is_caching_test);
+        cldnn::network::ptr network = get_network(*engine, topology, config, get_test_stream_ptr(), is_caching_test);
 
         network->set_input_data("input", input);
 
@@ -2758,6 +2758,10 @@ TEST_F(strided_slice_cpu_impl, test_2x2x1x1) {
     this->test_2x2x1x1(false, impl_types::cpu);
 }
 
+TEST_F(strided_slice_cpu_impl, test_2x2x1x1_disable_usm) {
+    this->test_2x2x1x1(false, impl_types::cpu, true);
+}
+
 TEST_F(strided_slice_cpu_impl, test_2x2x2x1x1_2) {
     this->test_2x2x2x1x1_2(false, impl_types::cpu);
 }
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/tile_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/tile_gpu_test.cpp
index fe99ef6da3514d..b22efae70a23a5 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/tile_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/tile_gpu_test.cpp
@@ -382,6 +382,46 @@ TEST_F(tile_cpu_impl, dynamic) {
     this->test_dynamic_1x2x2x2_axis_f(impl_types::cpu);
 }
 
+TEST(tile_cpu_imp_test, disable_usm) {
+    auto engine = create_test_engine(engine_types::ocl, runtime_types::ocl, false);
+
+    auto input = engine->allocate_memory({ data_types::f32, format::bfzyx,{ 1, 2, 2, 2, 2 } });
+    auto output_ref = engine->allocate_memory({ data_types::f32, format::bfzyx,{ 1, 2, 2, 2, 4 } });
+
+    topology topology;
+    topology.add(input_layout("input", input->get_layout()));
+    topology.add(tile("tile", input_info("input"), std::vector<int64_t>{ 1, 1, 2, 1, 1 }));
+
+    std::vector<float> input_vec = {
+        1.f, 0.f,
+        5.f, 1.5f,
+        2.f, 0.f,
+        6.f, 5.2f,
+        1.f, 0.f,
+        5.f, 1.5f,
+        2.f, 0.f,
+        6.f, 5.2f
+    };
+    set_values(input, input_vec);
+    tile_ref<float>(input, output_ref, 2, 2);
+
+    auto config = get_test_default_config(*engine);
+    config.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ {"tile", {format::bfzyx, "", impl_types::cpu}} }));
+
+    cldnn::network::ptr network = get_network(*engine, topology, config, get_test_stream_ptr(), false);
+    network->set_input_data("input", input);
+
+    auto outputs = network->execute();
+
+    auto output = outputs.at("tile").get_memory();
+    cldnn::mem_lock<float> output_ptr(output, get_test_stream());
+    cldnn::mem_lock<float> output_ref_ptr(output_ref, get_test_stream());
+
+    for (unsigned int i = 0; i < output_ref->count(); ++i) {
+        ASSERT_EQ(output_ptr[i], output_ref_ptr[i]) << "Index=" << i;
+    }
+}
+
 namespace {
 template<typename T>
 struct Params {
diff --git a/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp b/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp
index 6af8572d323907..8536813a4481c6 100644
--- a/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp
@@ -310,6 +310,29 @@ std::shared_ptr<cldnn::engine> create_test_engine() {
     return ret;
 }
 
+std::shared_ptr<cldnn::engine> create_test_engine(cldnn::engine_types engine_type,
+                                                  cldnn::runtime_types runtime_type,
+                                                  bool allow_usm_mem) {
+    device_query query(engine_type, runtime_type);
+    auto devices = query.get_available_devices();
+
+    OPENVINO_ASSERT(!devices.empty(), "[GPU] Can't create ", engine_type, " engine for ", runtime_type, " runtime as no suitable devices are found\n"
+                                      "[GPU] Please check OpenVINO documentation for GPU drivers setup guide.\n");
+
+    auto iter = devices.find(std::to_string(device_query::device_id));
+    auto& device = iter != devices.end() ? iter->second : devices.begin()->second;
+
+    if (!allow_usm_mem)
+        device->set_mem_caps(cldnn::memory_capabilities({}));
+
+    auto ret = engine::create(engine_type, runtime_type, device);
+#ifdef ENABLE_ONEDNN_FOR_GPU
+    if (ret->get_device_info().supports_immad)
+        ret->create_onednn_engine({});
+#endif
+    return ret;
+}
+
 cldnn::engine& get_test_engine() {
     static std::shared_ptr<cldnn::engine> test_engine = nullptr;
     if (!test_engine) {
diff --git a/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.h b/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.h
index d1f85714d00ea0..055c169f32d157 100644
--- a/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.h
+++ b/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.h
@@ -29,6 +29,9 @@
 #include <intel_gpu/primitives/input_layout.hpp>
 #include <intel_gpu/primitives/data.hpp>
 #include "intel_gpu/graph/serialization/utils.hpp"
+#include "intel_gpu/runtime/device_query.hpp"
+#include "intel_gpu/runtime/engine_configuration.hpp"
+#include "intel_gpu/runtime/memory_caps.hpp"
 
 #include <gtest/gtest.h>
 #include <gmock/gmock.h>
@@ -50,6 +53,9 @@
 namespace tests {
 
 std::shared_ptr<cldnn::engine> create_test_engine();
+std::shared_ptr<cldnn::engine> create_test_engine(cldnn::engine_types engine_type,
+                                                  cldnn::runtime_types runtime_type,
+                                                  bool allow_usm_mem = true);
 cldnn::engine& get_test_engine();
 cldnn::stream_ptr get_test_stream_ptr(cldnn::ExecutionConfig cfg);
 cldnn::stream_ptr get_test_stream_ptr();

From e9f13c9c96ff191bb36a6cfcded43a739449b50c Mon Sep 17 00:00:00 2001
From: Vasily Yakovlev <vasily.yakovlev@intel.com>
Date: Tue, 18 Feb 2025 06:49:16 +0100
Subject: [PATCH 02/20] Enable XeTLA LSTM for GPU (#28932)

### Details:
- Add Intel XeTLA (Xe Templates for Linear Algebra) library to OpenVINO
GPU plugin. Required SDL process is passed.
- Preprocess XeTLA headers with available cpp compiler during cmake
build process and add results to CM batch headers.
 - Enable XeTLA based LSTM implementation for Intel Xe2 architectures.

---------

Co-authored-by: Jakub Kasprzak <jakub.kasprzak@intel.com>
---
 .../intel_gpu/src/graph/impls/cm/lstm_seq.cpp |   96 +
 .../intel_gpu/src/graph/impls/cm/lstm_seq.hpp |  105 ++
 .../src/graph/impls/ocl/kernels_cache.hpp     |    1 +
 .../graph/impls/registry/lstm_seq_impls.cpp   |    5 +
 src/plugins/intel_gpu/src/graph/lstm_seq.cpp  |    4 +-
 .../src/kernel_selector/CMakeLists.txt        |   27 +-
 .../include/batch_headers/cm_xetla.h          |    5 +
 .../cm_kernels/include/xetla_lstm.h           |  605 ++++++
 .../cm_kernels/xetla_lstm_gemm.cpp            |   59 +
 .../cm_kernels/xetla_lstm_loop.cpp            |   60 +
 .../src/kernel_selector/kernel_base_cm.h      |   16 +-
 .../kernels/lstm/cm/lstm_seq_cm.cpp           |  178 ++
 .../kernels/lstm/cm/lstm_seq_cm.h             |   26 +
 .../lstm/cm/lstm_seq_cm_kernel_selector.cpp   |   17 +
 .../lstm/cm/lstm_seq_cm_kernel_selector.h     |   23 +
 .../src/plugin/transformations_pipeline.cpp   |   45 +
 .../single_layer_tests/lstm_sequence.cpp      |   24 +
 .../intel_gpu/thirdparty/CMakeLists.txt       |    2 +
 .../intel_gpu/thirdparty/xetla/LICENSE        |  193 ++
 .../intel_gpu/thirdparty/xetla/README.md      |   26 +
 .../intel_gpu/thirdparty/xetla/SECURITY.md    |    6 +
 .../xetla/include/common/common.hpp           |   23 +
 .../include/common/core/cm/arch_config.hpp    |   93 +
 .../xetla/include/common/core/cm/barrier.hpp  |   73 +
 .../include/common/core/cm/base_consts.hpp    |   35 +
 .../xetla/include/common/core/cm/base_ops.hpp |   70 +
 .../include/common/core/cm/base_types.hpp     |  242 +++
 .../common/core/cm/bit_mask_manipulation.hpp  |  287 +++
 .../xetla/include/common/core/cm/common.hpp   |  227 +++
 .../xetla/include/common/core/cm/core.hpp     |   97 +
 .../xetla/include/common/core/cm/debug.hpp    |   45 +
 .../include/common/core/cm/explicit_conv.hpp  |  158 ++
 .../xetla/include/common/core/cm/math_fma.hpp |   35 +
 .../include/common/core/cm/math_general.hpp   |  624 +++++++
 .../xetla/include/common/core/cm/math_mma.hpp |  147 ++
 .../xetla/include/common/core/cm/memory.hpp   |  605 ++++++
 .../xetla/include/common/core/cm/misc.hpp     |   39 +
 .../xetla/include/common/core/cm/raw_send.hpp |  154 ++
 .../xetla/include/common/core/core.hpp        |    1 +
 .../xetla/include/common/utils/cm/common.hpp  |  248 +++
 .../xetla/include/common/utils/cm/dict.hpp    |  247 +++
 .../include/common/utils/cm/fastmath.hpp      |  118 ++
 .../include/common/utils/cm/limitation.hpp    |  157 ++
 .../common/utils/cm/memory_descriptor.hpp     |  363 ++++
 .../xetla/include/common/utils/cm/misc.hpp    |  181 ++
 .../xetla/include/common/utils/cm/nd_item.hpp |   95 +
 .../xetla/include/common/utils/cm/rand.hpp    |  170 ++
 .../common/utils/cm/raw_send_load_store.hpp   |  386 ++++
 .../common/utils/cm/raw_send_nbarrier.hpp     |   90 +
 .../common/utils/cm/tensor_descriptor.hpp     |   99 +
 .../xetla/include/common/utils/cm/utils.hpp   |   65 +
 .../include/common/utils/cm/work_group.hpp    |   56 +
 .../xetla/include/common/utils/utils.hpp      |    1 +
 .../include/group/cooperative_reduction.hpp   |  221 +++
 .../xetla/include/group/epilogue/api.hpp      |   39 +
 .../xetla/include/group/epilogue/common.hpp   |   32 +
 .../xetla/include/group/epilogue/epilogue.hpp |   30 +
 .../group/epilogue/epilogue_policy.hpp        |   40 +
 .../group/epilogue/impl/tile_op_xe.hpp        |  137 ++
 .../xetla/include/group/gemm/api.hpp          |   80 +
 .../xetla/include/group/gemm/common.hpp       |   66 +
 .../include/group/gemm/compute_policy.hpp     |  103 ++
 .../xetla/include/group/gemm/gemm.hpp         |   32 +
 .../group/gemm/impl/default_xmx_xe.hpp        |  370 ++++
 .../group/gemm/impl/pre_processing_xe.hpp     |   54 +
 .../include/group/gemm/impl/selector_xe.hpp   |   74 +
 .../xetla/include/group/global_reduction.hpp  |  460 +++++
 .../thirdparty/xetla/include/group/group.hpp  |   25 +
 .../xetla/include/group/tile_shape.hpp        |   51 +
 .../xetla/include/kernel/gemm/api.hpp         |   43 +
 .../xetla/include/kernel/gemm/common.hpp      |   29 +
 .../include/kernel/gemm/dispatch_policy.hpp   |   70 +
 .../xetla/include/kernel/gemm/gemm.hpp        |   28 +
 .../include/kernel/gemm/impl/kslicing_xe.hpp  |  394 ++++
 .../xetla/include/kernel/kernel.hpp           |   22 +
 .../xetla/include/subgroup/subgroup.hpp       |   22 +
 .../xetla/include/subgroup/tile/api.hpp       |  125 ++
 .../include/subgroup/tile/chained_tile_op.hpp |  126 ++
 .../xetla/include/subgroup/tile/common.hpp    |  331 ++++
 .../include/subgroup/tile/impl/fma_xe.hpp     |  255 +++
 .../include/subgroup/tile/impl/load_xe.hpp    |  926 ++++++++++
 .../include/subgroup/tile/impl/mma_xe.hpp     |  260 +++
 .../subgroup/tile/impl/op_function.hpp        |  657 +++++++
 .../include/subgroup/tile/impl/payload_xe.hpp | 1615 +++++++++++++++++
 .../subgroup/tile/impl/prefetch_xe.hpp        |  119 ++
 .../include/subgroup/tile/impl/reduction.hpp  |  375 ++++
 .../include/subgroup/tile/impl/store_xe.hpp   |  790 ++++++++
 .../subgroup/tile/impl/tile_op_functor.hpp    | 1506 +++++++++++++++
 .../xetla/include/subgroup/tile/tile.hpp      |   33 +
 .../thirdparty/xetla/include/xetla.hpp        |   28 +
 90 files changed, 16315 insertions(+), 7 deletions(-)
 create mode 100644 src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.cpp
 create mode 100644 src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.hpp
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/batch_headers/cm_xetla.h
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/xetla_lstm.h
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_gemm.cpp
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_loop.cpp
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.cpp
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.h
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.cpp
 create mode 100644 src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.h
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/LICENSE
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/README.md
 create mode 100755 src/plugins/intel_gpu/thirdparty/xetla/SECURITY.md
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/arch_config.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/barrier.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_consts.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_ops.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_types.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/bit_mask_manipulation.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/core.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/debug.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/explicit_conv.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_fma.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_general.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_mma.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/memory.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/misc.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/raw_send.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/core/core.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/dict.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/fastmath.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/limitation.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/memory_descriptor.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/misc.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/nd_item.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/rand.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_load_store.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_nbarrier.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/tensor_descriptor.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/utils.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/work_group.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/utils.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/cooperative_reduction.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/api.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue_policy.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/impl/tile_op_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/api.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/compute_policy.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/gemm.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/default_xmx_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/pre_processing_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/selector_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/global_reduction.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/group.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/group/tile_shape.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/api.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/dispatch_policy.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/gemm.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/impl/kslicing_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/kernel/kernel.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/subgroup.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/api.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/chained_tile_op.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/common.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/fma_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/load_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/mma_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/op_function.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/payload_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/prefetch_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/reduction.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/store_xe.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/tile_op_functor.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/tile.hpp
 create mode 100644 src/plugins/intel_gpu/thirdparty/xetla/include/xetla.hpp

diff --git a/src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.cpp b/src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.cpp
new file mode 100644
index 00000000000000..d5477cc62e4100
--- /dev/null
+++ b/src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.cpp
@@ -0,0 +1,96 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "impls/ocl/primitive_base.hpp"
+
+#include "lstm_seq.hpp"
+#include "lstm/cm/lstm_seq_cm_kernel_selector.h"
+#include "lstm/lstm_kernel_base.h"
+#include "openvino/op/lstm_sequence.hpp"
+#include "impls/registry/implementation_manager.hpp"
+
+namespace cldnn {
+namespace cm {
+
+struct lstm_seq_impl : ocl::typed_primitive_impl_ocl<lstm_seq> {
+    using parent = ocl::typed_primitive_impl_ocl<lstm_seq>;
+    using parent::parent;
+    using kernel_selector_t = kernel_selector::lstm_seq_cm_kernel_selector;
+    using kernel_params_t = kernel_selector::lstm_params;
+
+    DECLARE_OBJECT_TYPE_SERIALIZATION(cldnn::cm::lstm_seq_impl)
+
+    std::unique_ptr<primitive_impl> clone() const override {
+        return std::make_unique<lstm_seq_impl>(*this);
+    }
+
+protected:
+    kernel_arguments_data get_arguments(const typed_primitive_inst<lstm_seq>& instance) const override {
+        kernel_arguments_data args;
+        for (size_t i = 0; i < instance.inputs_memory_count(); i++) {
+            args.inputs.push_back(instance.input_memory_ptr(i));
+        }
+
+        for (size_t i = 0; i < instance.outputs_memory_count(); i++) {
+            args.outputs.push_back(instance.output_memory_ptr(i));
+        }
+        return args;
+    }
+
+public:
+    static kernel_params_t get_kernel_params(const kernel_impl_params& impl_param) {
+        const auto& primitive = impl_param.typed_desc<lstm_seq>();
+        auto params = get_default_params<kernel_selector::lstm_params>(impl_param);
+        for (size_t i = 1; i < impl_param.input_layouts.size(); ++i) {
+            params.inputs.push_back(convert_data_tensor(impl_param.get_input_layout(i)));
+        }
+
+        if (!primitive->activations.empty()) {
+            auto a_sz = primitive->activations.size();
+            auto param_sz = primitive->activation_params.size();
+            OPENVINO_ASSERT(param_sz == 0|| a_sz == param_sz, "[GPU] Unexpected activation params count in lstm_seq impl: ", param_sz);
+            for (size_t i = 0; i < a_sz; i++) {
+                params.activations.emplace_back(get_kernel_selector_activation_param(primitive->activations[i]),
+                                                         param_sz ? primitive->activation_params[i].a : 0.0f,
+                                                         param_sz ? primitive->activation_params[i].b : 0.0f);
+            }
+        }
+
+        if (primitive->clip > 0.0f) {
+            params.activations.emplace_back(get_kernel_selector_activation_param(activation_func::clamp), -primitive->clip, primitive->clip);
+        }
+
+        params.SetOffsetOrder(static_cast<int32_t>(primitive->offset_order));
+        params.clip = primitive->clip;
+        params.direction = primitive->direction;
+        //Legacy multi-output
+        params.outputs.push_back(convert_data_tensor(impl_param.input_layouts[1]));
+        if (!primitive->initial_cell_state.pid.empty()) {
+            params.outputs.push_back(convert_data_tensor(impl_param.input_layouts[1]));
+        }
+        return params;
+    }
+
+    static kernel_impl_params static_canonicalize_shapes(const kernel_impl_params& impl_params) {
+        if (impl_params.get_input_layout().get_partial_shape().size() != 3) {
+            return primitive_impl::static_canonicalize_shapes(impl_params);
+        }
+        auto updated_impl_params = canonicalize_fused_shapes(impl_params);
+        return updated_impl_params;
+    }
+
+    kernel_impl_params canonicalize_shapes(const kernel_impl_params& impl_params) const override {
+        return static_canonicalize_shapes(impl_params);
+    }
+};
+
+std::unique_ptr<primitive_impl> LSTMSeqImplementationManager::create_impl(const program_node& node, const kernel_impl_params& params) const {
+    OPENVINO_ASSERT(node.is_type<lstm_seq>());
+    return ocl::typed_primitive_impl_ocl<lstm_seq>::create<lstm_seq_impl>(static_cast<const lstm_seq_node&>(node), params);
+}
+
+}  // namespace cm
+}  // namespace cldnn
+
+BIND_BINARY_BUFFER_WITH_TYPE(cldnn::cm::lstm_seq_impl)
diff --git a/src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.hpp b/src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.hpp
new file mode 100644
index 00000000000000..83ff241944a5e1
--- /dev/null
+++ b/src/plugins/intel_gpu/src/graph/impls/cm/lstm_seq.hpp
@@ -0,0 +1,105 @@
+// Copyright (C) 2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include <memory>
+
+#include "impls/registry/implementation_manager.hpp"
+#include "intel_gpu/runtime/layout.hpp"
+#include "lstm_seq_inst.h"
+namespace cldnn {
+namespace cm {
+
+struct LSTMSeqImplementationManager : public ImplementationManager {
+    OV_GPU_PRIMITIVE_IMPL("cm::lstm_seq")
+    LSTMSeqImplementationManager(shape_types shape_type, ValidateFunc vf = nullptr)
+        : ImplementationManager(impl_types::cm, shape_type, vf) {}
+
+    in_out_fmts_t query_formats(const program_node& node) const override {
+        assert(node.is_type<lstm_seq>());
+        std::vector<format::type> in_fmts(node.get_dependencies().size(), format::any);
+        std::vector<format::type> out_fmts(node.get_outputs_count(), format::any);
+
+        for (size_t idx = 0; idx < node.get_dependencies().size(); idx++) {
+            in_fmts[idx] = format::bfyx;
+        }
+        out_fmts[0] = format::byfx;
+        for (size_t idx = 1; idx < node.get_outputs_count(); idx++) {
+            out_fmts[idx] = format::bfyx;
+        }
+
+        return {in_fmts, out_fmts};
+    }
+
+    std::unique_ptr<primitive_impl> create_impl(const program_node& node,
+                                                const kernel_impl_params& params) const override;
+
+    bool validate_impl(const program_node& node) const override {
+        assert(node.is_type<lstm_seq>());
+
+        auto &engine = node.get_program().get_engine();
+        auto &config = node.get_program().get_config();
+        const auto& info = engine.get_device_info();
+
+        // XeTLA LSTM optimized for Xe2 architectures
+        if (!check_cm_jit_support(engine, config) || info.arch != gpu_arch::xe2) {
+            return false;
+        }
+
+        const auto& lstm_node = node.as<lstm_seq>();
+        const auto& lstm_prim = lstm_node.get_primitive();
+        if (lstm_prim->clip > 0.0f) {
+            return false;
+        }
+
+        if (lstm_prim->activations.size() != 3 ||
+            lstm_prim->activations[0] != activation_func::logistic ||
+            lstm_prim->activations[1] != activation_func::hyperbolic_tan ||
+            lstm_prim->activations[2] != activation_func::hyperbolic_tan) {
+            return false;
+        }
+
+        auto in_layouts = node.get_input_layouts();
+        if (node.is_dynamic()) {
+            return false;
+        }
+        unsigned int expected_inputs = 7;
+        if (in_layouts.size() != expected_inputs) {
+            return false;
+        }
+        {
+            auto &seq_lengths = in_layouts[expected_inputs-1];
+            if (seq_lengths.format != format::bfyx || seq_lengths.data_type != data_types::i32) {
+                    return false;
+                }
+            in_layouts.pop_back();
+        }
+
+
+        auto out_layouts = node.get_output_layouts();
+        for (auto &layout : in_layouts) {
+            if (layout.format != format::bfyx || layout.data_type != data_types::f16) {
+                return false;
+            }
+        }
+        for (auto &layout : out_layouts) {
+            if (layout.data_type != data_types::f16) {
+                return false;
+            }
+        }
+
+        auto num_gates = 4;
+        auto batch_size = in_layouts[0].get_shape()[0];
+        auto input_size = in_layouts[0].get_shape()[2];
+        auto hidden_size = in_layouts[3].get_shape()[1] / num_gates;
+        auto num_dir = in_layouts[3].get_shape()[0];
+        if (hidden_size != 128 || batch_size != 1 || num_dir != 2 || (input_size != 64 && input_size != 256)) {
+            return false;
+        }
+
+        return true;
+    }
+};
+
+}  // namespace cm
+}  // namespace cldnn
diff --git a/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp b/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp
index 56459b93d2481c..79ccfd050f4a93 100644
--- a/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp
@@ -86,6 +86,7 @@ class kernels_cache {
                     }
                 }
             } else {
+                source.push_back("#include <cm/cm.h>\n#include <cm/cmtl.h>\n");
             for (const auto& kv : batch_headers)
                 source.push_back(kv.second);
             }
diff --git a/src/plugins/intel_gpu/src/graph/impls/registry/lstm_seq_impls.cpp b/src/plugins/intel_gpu/src/graph/impls/registry/lstm_seq_impls.cpp
index 42114c892a48f0..5cd25b7f62a035 100644
--- a/src/plugins/intel_gpu/src/graph/impls/registry/lstm_seq_impls.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/registry/lstm_seq_impls.cpp
@@ -10,6 +10,10 @@
     #include "impls/ocl/rnn_seq.hpp"
 #endif
 
+#if OV_GPU_WITH_CM
+    #include "impls/cm/lstm_seq.hpp"
+#endif
+
 #if OV_GPU_WITH_ONEDNN
     #include "impls/onednn/lstm_seq_onednn.hpp"
 #endif
@@ -20,6 +24,7 @@ using namespace cldnn;
 
 const std::vector<std::shared_ptr<cldnn::ImplementationManager>>& Registry<lstm_seq>::get_implementations() {
     static const std::vector<std::shared_ptr<ImplementationManager>> impls = {
+        OV_GPU_CREATE_INSTANCE_CM(cm::LSTMSeqImplementationManager, shape_types::static_shape)
         OV_GPU_CREATE_INSTANCE_ONEDNN(onednn::LSTMSeqImplementationManager, shape_types::static_shape)
         OV_GPU_CREATE_INSTANCE_OCL(ocl::RNNSeqImplementationManager, shape_types::static_shape)
     };
diff --git a/src/plugins/intel_gpu/src/graph/lstm_seq.cpp b/src/plugins/intel_gpu/src/graph/lstm_seq.cpp
index 55e25672300cfd..c17a387ad27a6b 100644
--- a/src/plugins/intel_gpu/src/graph/lstm_seq.cpp
+++ b/src/plugins/intel_gpu/src/graph/lstm_seq.cpp
@@ -20,7 +20,7 @@ layout lstm_seq_inst::calc_output_layout(lstm_seq_node const& node, kernel_impl_
     const auto& lstm_hidden_size = input_pshape_hidden[2];
 
     auto first_out_fmt = cldnn::format::bfyx;
-    if (node.get_preferred_impl_type() == impl_types::onednn && node.get_preferred_output_fmt() != format::any) {
+    if (node.get_preferred_output_fmt() != format::any) {
         first_out_fmt = node.get_preferred_output_fmt();
     }
 
@@ -41,7 +41,7 @@ std::vector<layout> lstm_seq_inst::calc_output_layouts(lstm_seq_node const& node
     auto first_out_fmt = cldnn::format::bfyx;
     auto second_out_fmt = input_layout.format;
     auto third_out_fmt = input_layout.format;
-    if (node.get_preferred_impl_type() == impl_types::onednn && node.get_preferred_output_fmt() != format::any) {
+    if (node.get_preferred_output_fmt() != format::any) {
         first_out_fmt = node.get_preferred_output_fmt();
         second_out_fmt = node.get_preferred_output_fmt(1);
         third_out_fmt = node.get_preferred_output_fmt(2);
diff --git a/src/plugins/intel_gpu/src/kernel_selector/CMakeLists.txt b/src/plugins/intel_gpu/src/kernel_selector/CMakeLists.txt
index 1e585714bf7836..b12711ca42e9e1 100644
--- a/src/plugins/intel_gpu/src/kernel_selector/CMakeLists.txt
+++ b/src/plugins/intel_gpu/src/kernel_selector/CMakeLists.txt
@@ -18,7 +18,9 @@ file(GLOB_RECURSE KERNELS
   )
 
 file(GLOB_RECURSE CM_KERNELS
-  "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels/*"
+  "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels/*.h"
+  "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels/*.hpp"
+  "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels/*.cpp"
 )
 
 # Path which points to root directory where code generated elements are created
@@ -61,12 +63,31 @@ add_custom_command(OUTPUT "${CODEGEN_INCDIR}/${PRIM_DB}"
   COMMENT "Updating file if the file changed (${PRIM_DB}) ..."
 )
 
+set(XETLA_HEADER "cm_xetla.h")
+if(WIN32)
+    add_custom_command(OUTPUT "${CODEGEN_CACHE_DIR}/cm_kernels"
+        COMMAND "${CMAKE_COMMAND}" -E copy_directory "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels/" "${CODEGEN_CACHE_DIR}/cm_kernels"
+        COMMAND "${CMAKE_CXX_COMPILER}" "${CODEGEN_CACHE_DIR}/cm_kernels/include/batch_headers/${XETLA_HEADER}" -I ${XETLA_INCLUDE_DIR} -D _WIN32 -EP > "${CODEGEN_CACHE_DIR}/${XETLA_HEADER}"
+        COMMAND "${CMAKE_COMMAND}" -E rename "${CODEGEN_CACHE_DIR}/${XETLA_HEADER}" "${CODEGEN_CACHE_DIR}/cm_kernels/include/batch_headers/${XETLA_HEADER}"
+        DEPENDS "${CM_KERNELS}" "${CODEGEN_INCDIR}/${PRIM_DB}"
+        COMMENT "Copying CM sources and preprocessing XeTLA headers ..."
+    )
+else()
+    add_custom_command(OUTPUT "${CODEGEN_CACHE_DIR}/cm_kernels"
+        COMMAND "${CMAKE_COMMAND}" -E copy_directory "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels/" "${CODEGEN_CACHE_DIR}/cm_kernels"
+        COMMAND "${CMAKE_CXX_COMPILER}" "${CODEGEN_CACHE_DIR}/cm_kernels/include/batch_headers/${XETLA_HEADER}" -I ${XETLA_INCLUDE_DIR} -E -P > "${CODEGEN_CACHE_DIR}/${XETLA_HEADER}"
+        COMMAND "${CMAKE_COMMAND}" -E rename "${CODEGEN_CACHE_DIR}/${XETLA_HEADER}" "${CODEGEN_CACHE_DIR}/cm_kernels/include/batch_headers/${XETLA_HEADER}"
+        DEPENDS "${CM_KERNELS}" "${CODEGEN_INCDIR}/${PRIM_DB}"
+        COMMENT "Copying CM sources and preprocessing XeTLA headers ..."
+    )
+endif()
+
 add_custom_command(OUTPUT "${CODEGEN_CACHE_DIR}/${CM_PRIM_DB}"
   COMMAND "${Python3_EXECUTABLE}" "${CODEGEN_SCRIPT}" -out_path "${CODEGEN_CACHE_DIR}"
                                                       -out_file_name_prim_db "${CM_PRIM_DB}"
                                                       -out_file_name_batch_headers "${CM_PRIM_DB_BATCH_HEADERS}"
-                                                      -kernels "${CMAKE_CURRENT_SOURCE_DIR}/cm_kernels" -cm
-  DEPENDS ${CM_KERNELS} "${CODEGEN_SCRIPT}" "${CODEGEN_INCDIR}/${PRIM_DB}"
+                                                      -kernels "${CODEGEN_CACHE_DIR}/cm_kernels" -cm
+  DEPENDS ${CM_KERNELS} "${CODEGEN_SCRIPT}" "${CODEGEN_CACHE_DIR}/cm_kernels" "${CODEGEN_INCDIR}/${PRIM_DB}"
   COMMENT "Generating ${CODEGEN_CACHE_DIR}/${CM_PRIM_DB} ..."
 )
 
diff --git a/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/batch_headers/cm_xetla.h b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/batch_headers/cm_xetla.h
new file mode 100644
index 00000000000000..27a5a4f3da014c
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/batch_headers/cm_xetla.h
@@ -0,0 +1,5 @@
+// This file is to be preprocessed by the cpp compiler before adding to batch headers db for cm
+
+#define XETLA_CODE_BASE __CM__
+#define XETLA_NO_CM_INCLUDE
+#include <xetla.hpp>
diff --git a/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/xetla_lstm.h b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/xetla_lstm.h
new file mode 100644
index 00000000000000..d208e924efa9d9
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/include/xetla_lstm.h
@@ -0,0 +1,605 @@
+/*******************************************************************************
+* Copyright (c) 2022-2025 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+using namespace gpu::xetla;
+using namespace gpu::xetla::group;
+using namespace gpu::xetla::kernel;
+using namespace gpu::xetla::subgroup;
+
+template <typename dtype_a, typename dtype_b, typename dtype_c,
+        typename dtype_acc, uint32_t wg_m, uint32_t wg_n, uint32_t sg_m,
+        uint32_t sg_n, uint32_t sg_k, mem_layout layout_a, mem_layout layout_b,
+        mem_layout layout_c, mem_space mem_space_a, mem_space mem_space_b,
+        mem_space mem_space_c, mma_engine engine, uint32_t local_kslicing,
+        gpu_arch arch_tag>
+struct gemm_universal {
+    using tile_shape = group::tile_shape_t<wg_n, wg_m, sg_n, sg_m>;
+    static constexpr uint32_t periodic_sync_interval = 0;
+    static constexpr uint32_t prefetch_distance = 2;
+
+    using gemm_t = typename group::gemm_selector_t<dtype_a, dtype_b, layout_a,
+            layout_b, mem_space_a, mem_space_b, 8, 8, dtype_acc, tile_shape,
+            sg_k, mma_engine::xmx, arch_tag, prefetch_distance,
+            periodic_sync_interval>::gemm;
+
+    using bias_op_t = subgroup::bias_add_op_t<dtype_b, arch_tag>;
+    using tile_op_t = subgroup::chained_tile_op_t<bias_op_t>;
+    using epilogue_t = epilogue_t<epilogue_policy_tile_op<tile_op_t, arch_tag>,
+            tile_shape, mem_desc_t<dtype_c, layout_c, mem_space_c>>;
+    using epilogue_args_t = typename epilogue_t::arguments_t;
+
+    using group_swizzle_t = kernel::group_swizzle_default<arch_tag>;
+
+    using gemm_op_t = kernel::gemm_universal_t<
+            kernel::dispatch_policy_kslicing<group_swizzle_t, 1,
+                    local_kslicing>,
+            gemm_t, epilogue_t>;
+
+    using gemm_acc_t = typename gemm_t::matAcc_t;
+
+    static constexpr uint32_t barrier_count = gemm_op_t::get_barrier_count();
+    static constexpr uint32_t slm_size = gemm_op_t::get_slm_size();
+
+    inline void operator()(sycl::nd_item<3> &item, dtype_a *a,
+            dtype_b *b, dtype_b *bias,
+            typename epilogue_t::mem_desc_c_t::base_t c, uint32_t mat_m,
+            uint32_t mat_n, uint32_t mat_k, uint32_t lda, uint32_t ldb,
+            uint32_t ldc) {
+        gemm_op_t gemm_op;
+
+        typename bias_op_t::shape_t bias_add_shape(mat_n, 1, mat_n);
+        epilogue_args_t epilogue_args;
+
+        uint64_t matrix_size_a = mat_m * mat_k;
+        uint64_t matrix_size_b = mat_k * mat_n;
+        uint64_t matrix_size_c = mat_m * mat_n;
+
+        epilogue_args.init({{bias, bias_add_shape}});
+        typename gemm_op_t::arguments_t arg(mat_m, mat_k, mat_n, a,
+                layout_a == mem_layout::col_major ? mat_m : mat_k, b,
+                layout_b == mem_layout::col_major ? mat_k : mat_n, c.base,
+                mat_n, nullptr, nullptr, epilogue_args);
+        gemm_op(item, arg);
+    }
+};
+
+template <typename dtype_a, typename dtype_b, typename dtype_c,
+        typename dtype_acc, uint32_t wg_m, uint32_t wg_n, uint32_t sg_m,
+        uint32_t sg_n, uint32_t sg_k, mem_layout mem_layout_a,
+        mem_layout mem_layout_b, mem_layout mem_layout_c, mem_space mem_space_a,
+        mem_space mem_space_b, mem_space mem_space_c, mma_engine engine,
+        uint32_t k_size, gpu_arch arch_tag>
+struct gemm_persistent {
+    static_assert(engine == mma_engine::fpu);
+    static_assert(group::detail::check_2d_block_pitch_alignment<dtype_a,
+            dtype_b, 8, 8, arch_tag>::value);
+
+    static constexpr uint32_t periodic_sync_interval = 0;
+    static constexpr uint32_t prefetch_distance = 0;
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = 0;
+
+    using tile_shape = group::tile_shape_t<wg_n, wg_m, sg_n, sg_m>;
+    using work_group_t = typename tile_shape::work_group_t;
+
+    using mem_desc_a_t = mem_desc_t<dtype_a, mem_layout_a, mem_space_a, 8>;
+    using mem_desc_b_t = mem_desc_t<dtype_b, mem_layout_b, mem_space_b, 8>;
+
+    using compute_attr_t
+            = group::compute_attr_t<dtype_acc, dtype_acc, dtype_acc>;
+    using perf_tuning_knob_t = group::perf_tuning_knob_t<sg_k,
+            prefetch_distance, periodic_sync_interval>;
+    using compute_policy_t = group::compute_policy_default_fpu<compute_attr_t,
+            perf_tuning_knob_t, arch_tag>;
+
+    using group_swizzle_t = kernel::group_swizzle_default<arch_tag>;
+
+    using dtype_mma_acc = typename compute_policy_t::dtype_mma_acc;
+    using dtype_mma_a = typename compute_policy_t::dtype_mma_a;
+    using dtype_mma_b = typename compute_policy_t::dtype_mma_b;
+
+    using check_dtype
+            = group::gemm<gpu_arch::Xe>::default_fpu::check_dtype_default<
+                    dtype_a, dtype_b, dtype_mma_a, dtype_mma_b, dtype_mma_acc>;
+
+    using check_memory
+            = group::gemm<gpu_arch::Xe>::default_fpu::check_memory_default<
+                    mem_layout_a, mem_layout_b, mem_space_a, mem_space_b>;
+
+    static constexpr uint32_t tile_size_x_a = compute_policy_t::k_stride;
+    static constexpr uint32_t tile_size_y_a = tile_shape::sg_tile_size_y;
+    static constexpr uint32_t tile_size_x_b = tile_shape::sg_tile_size_x;
+    static constexpr uint32_t tile_size_y_b = compute_policy_t::k_stride;
+    static constexpr uint32_t tile_size_x_c = tile_shape::sg_tile_size_x;
+    static constexpr uint32_t tile_size_y_c = tile_shape::sg_tile_size_y;
+
+    static constexpr uint32_t block_size_x_a
+            = (compute_policy_t::block_size_x_a > tile_size_x_a)
+            ? tile_size_x_a
+            : compute_policy_t::block_size_x_a;
+    static constexpr uint32_t block_size_y_a
+            = (compute_policy_t::block_size_y_a > tile_size_y_a)
+            ? tile_size_y_a
+            : compute_policy_t::block_size_y_a;
+    static constexpr uint32_t block_size_x_b
+            = (compute_policy_t::block_size_x_b > tile_size_x_b)
+            ? tile_size_x_b
+            : compute_policy_t::block_size_x_b;
+    static constexpr uint32_t block_size_y_b
+            = (compute_policy_t::block_size_y_b > tile_size_y_b)
+            ? tile_size_y_b
+            : compute_policy_t::block_size_y_b;
+
+    static constexpr reg_layout reg_layout_a = reg_layout::tiled;
+    using matA_tile_desc_t
+            = subgroup::tile_desc_t<k_size, 1, k_size, 1, reg_layout_a>;
+    using matA_t = subgroup::tile_t<dtype_a, matA_tile_desc_t>;
+    using matA_payload_t = subgroup::mem_payload_t<mem_desc_a_t,
+            matA_tile_desc_t,
+            subgroup::msg_type_v<matA_tile_desc_t, mem_space_a>, arch_tag>;
+    using matA_acc_t = subgroup::tile_t<dtype_mma_a, matA_tile_desc_t>;
+
+    static constexpr reg_layout reg_layout_b = reg_layout::tiled;
+    using matB_tile_desc_t = subgroup::tile_desc_t<tile_size_x_b, tile_size_y_b,
+            block_size_x_b, block_size_y_b, reg_layout_b>;
+    using matB_t = subgroup::tile_t<dtype_b, matB_tile_desc_t>;
+    using matB_payload_t = subgroup::mem_payload_t<mem_desc_b_t,
+            matB_tile_desc_t, msg_type::block_2d, arch_tag>;
+    using matB_acc_t = subgroup::tile_t<dtype_mma_b, matB_tile_desc_t>;
+
+    using matAcc_tile_desc_t = subgroup::tile_desc_t<tile_size_x_c,
+            tile_size_y_c, block_size_x_b, block_size_y_a, reg_layout::tiled>;
+    using matAcc_t = subgroup::tile_t<dtype_mma_acc, matAcc_tile_desc_t>;
+
+    using tile_mma = subgroup::tile_mma_t<matAcc_t, matAcc_t, matB_acc_t,
+            matA_acc_t, mma_engine::fpu, arch_tag>;
+
+    static constexpr bool is_col_major_a
+            = mem_layout_a == mem_layout::col_major;
+    static constexpr bool is_col_major_b
+            = mem_layout_b == mem_layout::col_major;
+
+    static constexpr tdesc_update_dir update_dir_a = is_col_major_a
+            ? tdesc_update_dir::y_dir
+            : tdesc_update_dir::x_dir;
+    static constexpr tdesc_update_dir update_dir_b = is_col_major_b
+            ? tdesc_update_dir::x_dir
+            : tdesc_update_dir::y_dir;
+
+    mem_desc_a_t mem_desc_a;
+    static_assert(k_size % compute_policy_t::k_stride == 0);
+    static constexpr uint32_t k_steps = k_size / compute_policy_t::k_stride;
+    matB_acc_t matB_acc[k_steps];
+
+    inline void init(sycl::nd_item<3> &item,
+            typename mem_desc_a_t::base_t a, dtype_b *b, uint32_t mat_m,
+            uint32_t mat_n, uint32_t mat_k, uint32_t lda, uint32_t ldb,
+            uint32_t ldc) {
+        work_group_t g(item.get_local_linear_id() % work_group_t::size);
+        uint32_t wg_id = item.get_local_linear_id() / work_group_t::size;
+
+        group_swizzle_t group_swizzle;
+        int start_m = group_swizzle.template get_tile_idx<1>(item)
+                * tile_shape::wg_tile_size_y;
+        int start_n = group_swizzle.template get_tile_idx<2>(item)
+                * tile_shape::wg_tile_size_x;
+        int start_k = 0;
+
+        uint32_t wg_tile_k = mat_k;
+        uint32_t boundary_n = (start_n + tile_shape::wg_tile_size_x)
+                        > tile_shape::wg_tile_size_x
+                ? mat_n
+                : (start_n + tile_shape::wg_tile_size_x);
+        uint32_t boundary_m = (start_m + tile_shape::wg_tile_size_y)
+                        > tile_shape::wg_tile_size_y
+                ? mat_m
+                : (start_m + tile_shape::wg_tile_size_y);
+        uint32_t boundary_k = wg_tile_k;
+
+        mem_desc_b_t mem_desc_b;
+
+        mem_desc_a.init(a, {boundary_k, boundary_m, lda}, {start_k, start_m});
+        mem_desc_b.init(b, {boundary_n, boundary_k, ldb}, {start_n, start_k});
+
+        int32_t sg_idx = g.get_id() % tile_shape::wg_size_x;
+        int32_t sg_idy = g.get_id() / tile_shape::wg_size_x;
+        int32_t tile_offset_n = sg_idx * tile_shape::sg_tile_size_x;
+        int32_t tile_offset_m = sg_idy * tile_shape::sg_tile_size_y;
+
+        mem_desc_a.update_coord_y(tile_offset_m);
+        mem_desc_b.update_coord_x(tile_offset_n);
+
+        matB_payload_t matB_payload(mem_desc_b);
+        matB_t matB[k_steps];
+
+#pragma unroll
+        for (int i = 0; i < k_steps; i++) {
+            subgroup::tile_load<cache_hint::uncached, cache_hint::uncached>(
+                    matB[i], matB_payload);
+            matB_payload.template update_tdesc<update_dir_b>(
+                    matB_t::tile_size_y);
+            subgroup::elemwise_cvt(matB_acc[i], matB[i]);
+        }
+
+#pragma unroll
+        for (int i = 0; i < k_steps; i++) {
+            subgroup::tile_store<cache_hint::uncached, cache_hint::uncached>(
+                    matB_acc[i], matB_payload);
+        }
+    }
+
+    inline void run(matAcc_t &result) {
+
+        matAcc_t part_res[k_steps];
+        matA_t matA;
+        matA_acc_t matA_acc;
+        matA_payload_t matA_payload(mem_desc_a);
+
+        subgroup::tile_load<cache_hint::cached, cache_hint::cached>(
+                matA, matA_payload);
+        subgroup::elemwise_cvt(matA_acc, matA);
+
+        cm_fence(CM_SW_BARRIER);
+
+#pragma unroll
+        for (int i = 0; i < k_steps; i++) {
+            part_res[i].init(0);
+#pragma unroll
+            for (int j = 0; j < sg_k; j++) {
+                vector<float, k_size> tempA = matA_acc.reg;
+                float a = tempA[j + i * sg_k];
+                vector<float, sg_n *sg_k> tempB = matB_acc[i].reg;
+                vector<float, sg_n> tempB_simd
+                        = tempB.select<sg_n, 1>(j * sg_n);
+                part_res[i].reg += a * tempB_simd;
+            }
+        }
+        cm_fence(CM_SW_BARRIER);
+        result.init(0);
+#pragma unroll
+        for (int i = 0; i < k_steps; i++) {
+            result.reg += part_res[i].reg;
+        }
+    }
+};
+
+template <typename dtype_a, typename dtype_b, typename dtype_c,
+        typename dtype_acc, uint32_t input_size, uint32_t hidden_size,
+        uint32_t directions, mem_layout mem_layout_x, mem_layout mem_layout_w,
+        mem_layout mem_layout_out, mem_space mem_space_x, mem_space mem_space_w,
+        mem_space mem_space_out, gpu_arch arch_tag>
+struct __xetla_kernel_lstm_gemm {
+    static_assert(directions == 1 || directions == 2);
+
+    static constexpr uint32_t wg_m = 40;
+    static constexpr uint32_t wg_n = 256;
+
+    static constexpr uint32_t sg_m = 24;
+    static constexpr uint32_t sg_n = 32;
+    static constexpr uint32_t sg_k = 32;
+    static constexpr uint32_t local_kslicing = 1;
+
+    using gemm_t = gemm_universal<dtype_a, dtype_b, dtype_c, dtype_acc, wg_m,
+            wg_n, sg_m, sg_n, sg_k, mem_layout_x, mem_layout_w, mem_layout_x,
+            mem_space_x, mem_space_w, mem_space_x, mma_engine::xmx,
+            local_kslicing, arch_tag>;
+
+    static inline void init() {
+        if constexpr (gemm_t::barrier_count != 0) {
+            xetla_nbarrier_init<gemm_t::barrier_count>();
+        }
+        if constexpr (gemm_t::slm_size != 0) {
+            xetla_local_init<gemm_t::slm_size>();
+        }
+    }
+
+    static inline void run(sycl::nd_item<3> &item, dtype_a *x, dtype_b *W,
+            dtype_b *B, int *sequence_lengths, dtype_acc *out) {
+        uint32_t seq_len = sequence_lengths[0];
+        uint32_t matrix_m = seq_len;
+        uint32_t matrix_k = input_size;
+        uint32_t matrix_n = hidden_size * 4;
+
+        size_t lda
+                = mem_layout_x == mem_layout::col_major ? matrix_m : matrix_k;
+        size_t ldb
+                = mem_layout_w == mem_layout::col_major ? matrix_k : matrix_n;
+        size_t ldc = matrix_n;
+
+        int dir_id = item.get_group(0);
+
+        dtype_b *w_dir = W + matrix_k * matrix_n * dir_id;
+        dtype_b *bias_dir = B + matrix_n * dir_id;
+        dtype_c *x_dir = out + matrix_m * matrix_n * dir_id;
+
+        gemm_t gemm = gemm_t();
+        gemm(item, x, w_dir, bias_dir, x_dir, matrix_m, matrix_n, matrix_k, lda,
+                ldb, ldc);
+    }
+};
+
+template <typename dtype_a, typename dtype_b, typename dtype_c,
+        typename dtype_acc, uint32_t input_size, uint32_t hidden_size,
+        uint32_t directions, mem_layout mem_layout_x, mem_layout mem_layout_w,
+        mem_layout mem_layout_out, mem_space mem_space_x, mem_space mem_space_w,
+        mem_space mem_space_out, gpu_arch arch_tag>
+struct __xetla_kernel_lstm_loop {
+    static_assert(directions == 1 || directions == 2);
+    static_assert(hidden_size == 128);
+    static_assert(hidden_size % 4 == 0);
+
+    static constexpr uint32_t SIMD = 16;
+    static constexpr uint32_t num_threads = 32;
+    static constexpr uint32_t gates = 4;
+
+    static constexpr uint32_t wg_m = 1;
+    static constexpr uint32_t wg_n = hidden_size * gates;
+
+    static constexpr uint32_t sg_m = 1;
+    static constexpr uint32_t sg_n = SIMD;
+    static constexpr uint32_t sg_k = hidden_size / 4;
+
+    static constexpr uint32_t matrix_m = 1;
+    static constexpr uint32_t matrix_k = hidden_size;
+    static constexpr uint32_t matrix_n = hidden_size * gates;
+
+    static constexpr size_t lda
+            = mem_layout_x == mem_layout::col_major ? matrix_m : matrix_k;
+    static constexpr size_t ldb
+            = mem_layout_w == mem_layout::col_major ? matrix_k : matrix_n;
+    static constexpr size_t ldc = matrix_n;
+
+    using gemm_t = gemm_persistent<dtype_a, dtype_b, dtype_acc, dtype_acc, wg_m,
+            wg_n, sg_m, sg_n, sg_k, mem_layout::row_major, mem_layout_w,
+            mem_layout::row_major, mem_space::local, mem_space_w,
+            mem_space::local, mma_engine::fpu, hidden_size, arch_tag>;
+
+    static constexpr uint32_t barrier_count = gemm_t::barrier_count + 1;
+    static constexpr uint32_t context_size_bytes
+            = hidden_size * sizeof(dtype_acc);
+    static constexpr uint32_t figo_size = gates * hidden_size;
+    static constexpr uint32_t figo_size_bytes = figo_size * sizeof(dtype_acc);
+    static constexpr uint32_t slm_size
+            = context_size_bytes * 2 + figo_size_bytes + gemm_t::slm_size;
+
+    static inline void init() {
+        if constexpr (barrier_count != 0) {
+            xetla_nbarrier_init<barrier_count>();
+        }
+        if constexpr (slm_size != 0) { xetla_local_init<slm_size>(); }
+    }
+
+    static inline void run(sycl::nd_item<3> &item, dtype_a *x,
+            dtype_b *initial_hidden_state, dtype_b *initial_cell_state,
+            dtype_b *R, int *sequence_lengths, dtype_c *hidden_history,
+            dtype_c *hidden_state, dtype_c *cell_state) {
+        xetla_nbarrier_t<num_threads, num_threads, arch_tag> nbarrier;
+        nbarrier.init_nbarrier(
+                barrier_count - 1, nbarrier_role::producer_consumer);
+
+        int dir_id = item.get_group(0);
+        uint32_t seq_len = sequence_lengths[0];
+
+        dtype_a *x_dir = x + seq_len * hidden_size * gates * dir_id;
+        dtype_b *r_dir = R + matrix_k * matrix_n * dir_id;
+        dtype_b *context_h_init = initial_hidden_state + hidden_size * dir_id;
+        dtype_b *context_c_init = initial_cell_state + hidden_size * dir_id;
+        dtype_c *context_h_out = hidden_state + hidden_size * dir_id;
+        dtype_c *context_c_out = cell_state + hidden_size * dir_id;
+
+        constexpr uint32_t slm_figo_offset = gemm_t::slm_size;
+        constexpr uint32_t slm_h_offset = slm_figo_offset + figo_size_bytes;
+        constexpr uint32_t slm_c_offset = slm_h_offset + context_size_bytes;
+
+        gemm_t gemm = gemm_t();
+        gemm.init(item, slm_h_offset, r_dir, matrix_m, matrix_n, matrix_k, lda,
+                ldb, ldc);
+
+        using tile_desc_t
+                = subgroup::tile_desc_t<SIMD, 1, SIMD, 1, reg_layout::tiled>;
+
+        using tile_acc_t = subgroup::tile_t<dtype_acc, tile_desc_t>;
+        using tile_a_t = subgroup::tile_t<dtype_a, tile_desc_t>;
+        using tile_b_t = subgroup::tile_t<dtype_b, tile_desc_t>;
+        using tile_c_t = subgroup::tile_t<dtype_c, tile_desc_t>;
+
+        using local_acc_payload_t = subgroup::mem_payload_t<
+                mem_desc_t<dtype_acc, mem_layout::row_major, mem_space::local>,
+                tile_desc_t,
+                subgroup::msg_type_v<tile_desc_t, mem_space::local>, arch_tag>;
+
+        using global_acc_payload_t = subgroup::mem_payload_t<
+                mem_desc_t<dtype_acc, mem_layout::row_major, mem_space::global>,
+                tile_desc_t,
+                subgroup::msg_type_v<tile_desc_t, mem_space::global>, arch_tag>;
+
+        using global_a_payload_t = subgroup::mem_payload_t<
+                mem_desc_t<dtype_a, mem_layout::row_major, mem_space::global>,
+                tile_desc_t,
+                subgroup::msg_type_v<tile_desc_t, mem_space::global>, arch_tag>;
+
+        using global_b_payload_t = subgroup::mem_payload_t<
+                mem_desc_t<dtype_b, mem_layout::row_major, mem_space::global>,
+                tile_desc_t,
+                subgroup::msg_type_v<tile_desc_t, mem_space::global>, arch_tag>;
+
+        using global_c_payload_t = subgroup::mem_payload_t<
+                mem_desc_t<dtype_c, mem_layout::row_major, mem_space::global>,
+                tile_desc_t,
+                subgroup::msg_type_v<tile_desc_t, mem_space::global>, arch_tag>;
+
+        const int seq_inc = 1 - (2 * dir_id);
+        const int seq_start_y = (seq_len - 1) * dir_id;
+        const uint32_t local_id = item.get_local_linear_id();
+        const uint32_t minigroup_offset
+                = (local_id % ((hidden_size + SIMD - 1) / SIMD)) * SIMD;
+
+        tile_a_t x_tile;
+        global_a_payload_t x_tile_payload;
+        x_tile_payload.init(x_dir, figo_size, seq_len, figo_size,
+                local_id * SIMD, seq_start_y);
+
+        tile_acc_t h_tile;
+        local_acc_payload_t h_tile_payload;
+        h_tile_payload.init(
+                slm_h_offset, hidden_size, 1, hidden_size, minigroup_offset, 0);
+
+        tile_acc_t c_tile;
+        local_acc_payload_t c_tile_payload;
+        c_tile_payload.init(
+                slm_c_offset, hidden_size, 1, hidden_size, minigroup_offset, 0);
+
+        if (local_id < (hidden_size / SIMD)) {
+            tile_b_t h_tile_init;
+            global_b_payload_t h_tile_payload_init;
+            h_tile_payload_init.init(context_h_init, hidden_size, 1,
+                    hidden_size, minigroup_offset, 0);
+
+            tile_b_t c_tile_init;
+            global_b_payload_t c_tile_payload_init;
+            c_tile_payload_init.init(context_c_init, hidden_size, 1,
+                    hidden_size, minigroup_offset, 0);
+
+            tile_load<cache_hint::uncached, cache_hint::uncached>(
+                    h_tile_init, h_tile_payload_init);
+            tile_load<cache_hint::uncached, cache_hint::uncached>(
+                    c_tile_init, c_tile_payload_init);
+            h_tile.reg = xetla_cvt<dtype_acc, dtype_b, SIMD>(h_tile_init.reg);
+            c_tile.reg = xetla_cvt<dtype_acc, dtype_b, SIMD>(c_tile_init.reg);
+            tile_store(h_tile, h_tile_payload);
+            tile_store(c_tile, c_tile_payload);
+        }
+        xetla_fence<memory_kind::untyped_global>();
+        nbarrier.arrive_wait();
+
+        tile_c_t out_tile;
+        global_c_payload_t out_tile_payload;
+        out_tile_payload.init(hidden_history, hidden_size, seq_len,
+                hidden_size * directions,
+                hidden_size * dir_id + minigroup_offset, seq_start_y);
+
+        tile_acc_t figo_tile;
+        local_acc_payload_t figo_tile_payload;
+        figo_tile_payload.init(
+                slm_figo_offset, figo_size, 1, figo_size, local_id * SIMD, 0);
+
+        tile_acc_t f_tile;
+        local_acc_payload_t f_tile_payload;
+        f_tile_payload.init(slm_figo_offset, hidden_size, 1, hidden_size,
+                minigroup_offset, 0);
+
+        tile_acc_t i_tile;
+        local_acc_payload_t i_tile_payload;
+        i_tile_payload.init(slm_figo_offset + hidden_size * sizeof(dtype_acc),
+                hidden_size, 1, hidden_size, minigroup_offset, 0);
+
+        tile_acc_t g_tile;
+        local_acc_payload_t g_tile_payload;
+        g_tile_payload.init(
+                slm_figo_offset + hidden_size * 2 * sizeof(dtype_acc),
+                hidden_size, 1, hidden_size, minigroup_offset, 0);
+
+        tile_acc_t o_tile;
+        local_acc_payload_t o_tile_payload;
+        o_tile_payload.init(
+                slm_figo_offset + hidden_size * 3 * sizeof(dtype_acc),
+                hidden_size, 1, hidden_size, minigroup_offset, 0);
+
+#ifdef UNROLL_SEQ_LEN
+        for (int iii = 0; iii < seq_len / UNROLL_SEQ_LEN; iii++) {
+#pragma unroll
+            for (int ii = 0; ii < UNROLL_SEQ_LEN; ii++) {
+                int i = ii * UNROLL_SEQ_LEN + iii;
+#else
+        for (int i = 0; i < seq_len; i++) {
+#endif
+                tile_load<cache_hint::uncached, cache_hint::cached>(
+                        x_tile, x_tile_payload);
+                x_tile_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                        seq_inc);
+
+                typename gemm_t::matAcc_t matAcc;
+                gemm.run(matAcc);
+
+                figo_tile.reg = matAcc.reg + x_tile.reg;
+                if (local_id < (hidden_size * 2 / SIMD)
+                        || local_id >= (hidden_size * 3 / SIMD)) {
+                    figo_tile.reg
+                            = xetla_sigmoid<dtype_acc, SIMD>(figo_tile.reg);
+                } else {
+                    figo_tile.reg = xetla_tanh<dtype_acc, SIMD>(figo_tile.reg);
+                }
+                tile_store(figo_tile, figo_tile_payload);
+                xetla_fence<memory_kind::shared_local>();
+                nbarrier.arrive_wait();
+
+                if (local_id < (hidden_size / SIMD)) {
+                    tile_load(f_tile, f_tile_payload);
+                    tile_load(i_tile, i_tile_payload);
+                    tile_load(g_tile, g_tile_payload);
+                    tile_load(o_tile, o_tile_payload);
+
+                    tile_load(c_tile, c_tile_payload);
+
+                    c_tile.reg *= f_tile.reg;
+                    i_tile.reg *= g_tile.reg;
+                    c_tile.reg += i_tile.reg;
+
+                    tile_store(c_tile, c_tile_payload);
+
+                    h_tile.reg = xetla_tanh<dtype_acc, SIMD>(c_tile.reg)
+                            * o_tile.reg;
+
+                    tile_store(h_tile, h_tile_payload);
+
+                    out_tile.reg
+                            = xetla_cvt<dtype_c, dtype_acc, SIMD>(h_tile.reg);
+                    tile_store<cache_hint::write_back, cache_hint::write_back>(
+                            out_tile, out_tile_payload);
+                    out_tile_payload
+                            .template update_tdesc<tdesc_update_dir::y_dir>(
+                                    seq_inc);
+                }
+                xetla_fence<memory_kind::shared_local>();
+                nbarrier.arrive_wait();
+            }
+#ifdef UNROLL_SEQ_LEN
+        }
+#endif
+        if (local_id < (hidden_size / SIMD)) {
+            tile_load(h_tile, h_tile_payload);
+            tile_load(c_tile, c_tile_payload);
+
+            tile_c_t h_tile_out;
+            global_c_payload_t h_tile_payload_out;
+            h_tile_payload_out.init(context_h_out, hidden_size, 1, hidden_size,
+                    minigroup_offset, 0);
+
+            tile_c_t c_tile_out;
+            global_c_payload_t c_tile_payload_out;
+            c_tile_payload_out.init(context_c_out, hidden_size, 1, hidden_size,
+                    minigroup_offset, 0);
+
+            h_tile_out.reg = xetla_cvt<dtype_c, dtype_acc, SIMD>(h_tile.reg);
+            c_tile_out.reg = xetla_cvt<dtype_c, dtype_acc, SIMD>(c_tile.reg);
+
+            tile_store<cache_hint::write_back, cache_hint::write_back>(
+                    h_tile_out, h_tile_payload_out);
+            tile_store<cache_hint::write_back, cache_hint::write_back>(
+                    c_tile_out, c_tile_payload_out);
+        }
+    }
+};
diff --git a/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_gemm.cpp b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_gemm.cpp
new file mode 100644
index 00000000000000..4d1f1867e13ce9
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_gemm.cpp
@@ -0,0 +1,59 @@
+/*******************************************************************************
+ * Copyright (c) 2022-2025 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *******************************************************************************/
+
+namespace KERNEL_NAME {
+
+#include "include/xetla_lstm.h"
+
+#define dtype_a fp16
+#define dtype_b fp16
+#define dtype_c float
+#define dtype_acc float
+
+//#define INPUT_SIZE 64 // or 256
+#define hidden_size 128
+#define directions 2
+
+#define mem_layout_x mem_layout::row_major
+#define mem_layout_w mem_layout::col_major
+#define mem_layout_out mem_layout::row_major
+
+#define mem_space_x mem_space::global
+#define mem_space_w mem_space::global
+#define mem_space_out mem_space::global
+
+#define arch_tag gpu_arch::Xe
+
+_GENX_MAIN_ void KERNEL_NAME(
+        dtype_a *x [[type("svmptr_t")]],
+        dtype_b *W [[type("svmptr_t")]], 
+        dtype_b *B [[type("svmptr_t")]],
+        int *sequence_lengths [[type("svmptr_t")]],
+        dtype_acc *out [[type("svmptr_t")]]) {
+    sycl::nd_item<3> item;
+    using gemm_t = __xetla_kernel_lstm_gemm<dtype_a, dtype_b, dtype_c,
+            dtype_acc, INPUT_SIZE, hidden_size, directions, mem_layout_x,
+            mem_layout_w, mem_layout_out, mem_space_x, mem_space_w,
+            mem_space_out, arch_tag>;
+    if constexpr (gemm_t::gemm_t::barrier_count != 0) {
+        cm_nbarrier_init(gemm_t::gemm_t::barrier_count);
+    }
+    if constexpr (gemm_t::gemm_t::slm_size != 0) {
+        cm_slm_init(gemm_t::gemm_t::slm_size);
+    }
+    gemm_t::run(item, x, W, B, sequence_lengths, out);
+}
+}
diff --git a/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_loop.cpp b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_loop.cpp
new file mode 100644
index 00000000000000..84eb4a88444e96
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/cm_kernels/xetla_lstm_loop.cpp
@@ -0,0 +1,60 @@
+/*******************************************************************************
+ * Copyright (c) 2022-2025 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *******************************************************************************/
+
+namespace KERNEL_NAME {
+
+#include "include/xetla_lstm.h"
+
+#define dtype_a float
+#define dtype_b fp16
+#define dtype_c fp16
+#define dtype_acc float
+
+//#define INPUT_SIZE 64 // or 256
+#define hidden_size 128
+#define directions 2
+
+#define mem_layout_x mem_layout::row_major
+#define mem_layout_r mem_layout::col_major
+#define mem_layout_out mem_layout::row_major
+
+#define mem_space_x mem_space::global
+#define mem_space_r mem_space::global
+#define mem_space_out mem_space::global
+
+#define arch_tag gpu_arch::Xe
+
+_GENX_MAIN_ void KERNEL_NAME(dtype_a *x [[type("svmptr_t")]],
+        dtype_b *initial_hidden_state [[type("svmptr_t")]],
+        dtype_b *initial_cell_state [[type("svmptr_t")]],
+        dtype_b *R [[type("svmptr_t")]],
+        int *sequence_lengths [[type("svmptr_t")]],
+        dtype_c *hidden_history [[type("svmptr_t")]],
+        dtype_c *hidden_state [[type("svmptr_t")]],
+        dtype_c *cell_state [[type("svmptr_t")]]) {
+    sycl::nd_item<3> item;
+    using loop_t = __xetla_kernel_lstm_loop<dtype_a, dtype_b, dtype_c,
+            dtype_acc, INPUT_SIZE, hidden_size, directions, mem_layout_x,
+            mem_layout_r, mem_layout_out, mem_space_x, mem_space_r,
+            mem_space_out, arch_tag>;
+    if constexpr (loop_t::barrier_count != 0) {
+        cm_nbarrier_init(loop_t::barrier_count);
+    }
+    if constexpr (loop_t::slm_size != 0) { cm_slm_init(loop_t::slm_size); }
+    loop_t::run(item, x, initial_hidden_state, initial_cell_state, R,
+            sequence_lengths, hidden_history, hidden_state, cell_state);
+}
+}
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernel_base_cm.h b/src/plugins/intel_gpu/src/kernel_selector/kernel_base_cm.h
index 6e2c8e00fe5833..0d46cf7b4bfd61 100644
--- a/src/plugins/intel_gpu/src/kernel_selector/kernel_base_cm.h
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernel_base_cm.h
@@ -27,8 +27,7 @@ class KernelBaseCM : public KernelBase {
 
         if (codes.size()) {
             kernel_string->str = codes[0];
-            kernel_string->jit = "#include <cm/cm.h>\n#include <cm/cmtl.h>\n";
-            kernel_string->jit += jit.first;
+            kernel_string->jit = jit.first;
             kernel_string->undefs = jit.second;
             kernel_string->options = " -cmc ";
 
@@ -39,5 +38,18 @@ class KernelBaseCM : public KernelBase {
 
         return kernel_string;
     }
+    std::pair<std::string, std::string> CreateJit(const JitConstants& constants) const {
+        std::string defs, undefs;
+        for (auto& definition : constants.GetDefinitions()) {
+            auto &name = definition.first;
+            auto &value = definition.second;
+            defs += "\n#define " + name + " " + value + "\n";
+            undefs += "\n#ifdef " + name + "\n";
+            undefs += "\n#undef " + name + "\n";
+            undefs += "\n#endif\n";
+        }
+
+        return std::pair<std::string, std::string>(defs, undefs);
+    }
 };
 }  // namespace kernel_selector
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.cpp b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.cpp
new file mode 100644
index 00000000000000..35170e0b19da1a
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.cpp
@@ -0,0 +1,178 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "lstm_seq_cm.h"
+#include "kernel_selector_utils.h"
+#include "common_tools.h"
+
+namespace kernel_selector {
+
+ParamsKey LSTMSeqKernel_CM::GetSupportedKey() const {
+    ParamsKey k;
+    k.EnableInputDataType(Datatype::INT32);
+    k.EnableInputDataType(Datatype::F16);
+    k.EnableInputDataType(Datatype::F32);
+    k.EnableOutputDataType(Datatype::F16);
+    k.EnableOutputDataType(Datatype::F32);
+    k.EnableDifferentTypes();
+    k.EnableInputLayout(DataLayout::bfyx);
+    k.EnableAllOutputLayout();
+    k.EnableTensorOffset();
+    k.EnableTensorPitches();
+    k.EnableBatching();
+    return k;
+}
+
+KernelsData LSTMSeqKernel_CM::GetKernelsData(const Params& params) const {
+    if (!Validate(params)) {
+        return {};
+    }
+    auto shape = GetShape(params);
+
+    KernelData kd = KernelData::Default<lstm_params>(params, 2);
+    auto options = std::string(" -Qxcm_jit_option=-DPASTokenReduction "
+              " -mllvm --vc-disable-indvars-opt=true "
+              " /Qxcm_jit_option=-enableBCR "
+              " -fcm-pointer /Qxcm_doubleGRF "
+              " -DXETLA_CODE_BASE=__CM__ ");
+    auto shape_key = std::string {"is"} + std::to_string(shape.input_size);
+    auto gemm_entry_point = std::string {"xetla_lstm_gemm_"} + shape_key;
+    auto loop_entry_point = std::string {"xetla_lstm_loop_"} + shape_key;
+
+    auto constants = JitConstants{};
+    constants.AddConstant({MakeJitConstant("INPUT_SIZE", std::to_string(shape.input_size))});
+
+    constants.AddConstant({MakeJitConstant("KERNEL_NAME", gemm_entry_point)});
+    auto gemm_jit = CreateJit(constants);
+
+    constants.RemoveConstant("KERNEL_NAME");
+    constants.AddConstant({MakeJitConstant("KERNEL_NAME", loop_entry_point)});
+    auto loop_jit = CreateJit(constants);
+
+
+    // Request temporary buffers
+    kd.internalBufferDataType = Datatype::F32;
+    auto temp_buffer_size = shape.num_dir * shape.seq_len * shape.batch_size * shape.hidden_size * shape.num_gates * sizeof(float);
+    kd.internalBufferSizes.push_back(temp_buffer_size);
+
+    auto& gemm_part = kd.kernels[0];
+    gemm_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 0});
+    gemm_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 3});
+    gemm_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 5});
+    gemm_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 6});
+    gemm_part.params.arguments.push_back({ArgumentDescriptor::Types::INTERNAL_BUFFER, 0});
+
+    // Calc gws, lws
+    {
+        size_t matrix_m_ih = shape.seq_len;
+        size_t matrix_n_ih = shape.hidden_size * shape.num_gates;
+
+        size_t wg_m_ih = 40;
+        size_t wg_n_ih = 256;
+
+        size_t sg_m_ih = 24;
+        size_t sg_n_ih = 32;
+
+        size_t local_kslicing_ih = 1;
+        size_t subgroup_range_m = (wg_m_ih + sg_m_ih - 1) / sg_m_ih;
+        size_t subgroup_range_n = (wg_n_ih + sg_n_ih - 1) / sg_n_ih;
+
+        size_t group_range_m = (matrix_m_ih + wg_m_ih - 1) / wg_m_ih;
+        size_t group_range_n = (matrix_n_ih + wg_n_ih - 1) / wg_n_ih;
+
+        gemm_part.params.workGroups.local = {subgroup_range_n, subgroup_range_m, local_kslicing_ih};
+        gemm_part.params.workGroups.global = {group_range_n*subgroup_range_n, group_range_m*subgroup_range_m, shape.num_dir*local_kslicing_ih};
+    }
+    gemm_part.code.kernelString = GetKernelString("xetla_lstm_gemm", gemm_jit, gemm_entry_point);
+    gemm_part.code.kernelString->options += options;
+    gemm_part.code.kernelString->batch_compilation = true;
+
+    auto& loop_part = kd.kernels[1];
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::INTERNAL_BUFFER, 0});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 1});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 2});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 4});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::INPUT, 6});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::OUTPUT, 0});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::OUTPUT, 1});
+    loop_part.params.arguments.push_back({ArgumentDescriptor::Types::OUTPUT, 2});
+
+    // Calc gws, lws
+    {
+        size_t wg_m_hh = 1;
+        size_t wg_n_hh = shape.hidden_size * shape.num_gates;
+
+        size_t sg_m_hh = 1;
+        size_t sg_n_hh = 16;
+
+        size_t matrix_m_hh = 1;
+        size_t matrix_n_hh = shape.hidden_size * shape.num_gates;
+
+        size_t group_range_m = (matrix_m_hh + wg_m_hh - 1) / wg_m_hh;
+        size_t group_range_n = (matrix_n_hh + wg_n_hh - 1) / wg_n_hh;
+        size_t subgroup_range_m = (wg_m_hh + sg_m_hh - 1) / sg_m_hh;
+        size_t subgroup_range_n = (wg_n_hh + sg_n_hh - 1) / sg_n_hh;
+
+        loop_part.params.workGroups.local = {subgroup_range_n, subgroup_range_m, 1};
+        loop_part.params.workGroups.global = {group_range_n*subgroup_range_n, group_range_m*subgroup_range_m, shape.num_dir};
+    }
+    loop_part.code.kernelString = GetKernelString("xetla_lstm_loop", loop_jit, loop_entry_point);
+    loop_part.code.kernelString->options += options;
+    loop_part.code.kernelString->batch_compilation = true;
+
+    return {kd};
+}
+
+KernelsPriority LSTMSeqKernel_CM::GetKernelsPriority(const Params& /*params*/) const {
+    return FORCE_PRIORITY_1;
+}
+
+bool LSTMSeqKernel_CM::Validate(const Params& p) const {
+    const lstm_params& orgParams = static_cast<const lstm_params&>(p);
+    const auto expected_inputs = 7;
+
+    const auto &seq_lengths = orgParams.inputs[expected_inputs-1];
+    if (seq_lengths.GetLayout() != DataLayout::bfyx || seq_lengths.GetDType() != kernel_selector::Datatype::INT32) {
+        return false;
+    }
+    for (int i = 0; i < expected_inputs - 1; i++) {
+        const auto &dtensor = orgParams.inputs[i];
+        if (dtensor.GetLayout() != DataLayout::bfyx || dtensor.GetDType() != kernel_selector::Datatype::F16) {
+            return false;
+        }
+    }
+
+    if (orgParams.activations.size() != 3 ||
+        orgParams.activations[0].function != ActivationFunction::LOGISTIC ||
+        orgParams.activations[1].function != ActivationFunction::HYPERBOLIC_TAN ||
+        orgParams.activations[2].function != ActivationFunction::HYPERBOLIC_TAN) {
+            return false;
+    }
+
+    auto shape = GetShape(p);
+    if (shape.hidden_size != 128 || shape.batch_size != 1 || shape.num_dir != 2 ||
+        (shape.input_size != 64 && shape.input_size != 256)) {
+        return false;
+    }
+
+    return true;
+}
+LSTMSeqKernel_CM::lstm_shape LSTMSeqKernel_CM::GetShape(const Params& params) const {
+    const lstm_params& orgParams = static_cast<const lstm_params&>(params);
+    const auto &x = orgParams.inputs[0];
+    const auto &ini_hidden = orgParams.inputs[1];
+    const auto &out = orgParams.outputs[0];
+
+    lstm_shape shape;
+    shape.num_gates = 4; // always 4
+    shape.batch_size = x.Batch().v;
+    shape.hidden_size = ini_hidden.Y().v;
+    shape.input_size = x.Y().v;
+    shape.seq_len = out.Y().v;
+    shape.num_dir = ini_hidden.Feature().v;
+
+    return shape;
+}
+
+}  // namespace kernel_selector
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.h b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.h
new file mode 100644
index 00000000000000..d73fac8a167879
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm.h
@@ -0,0 +1,26 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include "kernel_base_cm.h"
+#include "lstm/lstm_kernel_base.h"
+
+namespace kernel_selector {
+class LSTMSeqKernel_CM : public KernelBaseCM {
+public:
+    LSTMSeqKernel_CM() : KernelBaseCM("lstm_gemm_loop") {}
+    virtual ~LSTMSeqKernel_CM() {}
+
+    KernelsData GetKernelsData(const Params& params) const override;
+    KernelsPriority GetKernelsPriority(const Params& params) const override;
+    ParamsKey GetSupportedKey() const override;
+    bool Validate(const Params& p) const override;
+private:
+    struct lstm_shape{
+        size_t batch_size, input_size, hidden_size, seq_len, num_dir, num_gates;
+    };
+    lstm_shape GetShape(const Params& params) const;
+};
+}  // namespace kernel_selector
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.cpp b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.cpp
new file mode 100644
index 00000000000000..de9bfec220575e
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.cpp
@@ -0,0 +1,17 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "lstm_seq_cm_kernel_selector.h"
+#include "lstm_seq_cm.h"
+
+
+namespace kernel_selector {
+lstm_seq_cm_kernel_selector::lstm_seq_cm_kernel_selector() {
+    Attach<LSTMSeqKernel_CM>();
+}
+
+KernelsData lstm_seq_cm_kernel_selector::GetBestKernels(const Params& params) const {
+    return GetNaiveBestKernel(params, KernelType::LSTM_SEQ_CELL);
+}
+}  // namespace kernel_selector
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.h b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.h
new file mode 100644
index 00000000000000..1aec010859f0f1
--- /dev/null
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernels/lstm/cm/lstm_seq_cm_kernel_selector.h
@@ -0,0 +1,23 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include "kernel_selector.h"
+
+namespace kernel_selector {
+class lstm_seq_cm_kernel_selector : public kernel_selector_base {
+public:
+    static lstm_seq_cm_kernel_selector& Instance() {
+        static lstm_seq_cm_kernel_selector instance_;
+        return instance_;
+    }
+
+    lstm_seq_cm_kernel_selector();
+
+    virtual ~lstm_seq_cm_kernel_selector() {}
+
+    KernelsData GetBestKernels(const Params& params) const override;
+};
+}  // namespace kernel_selector
diff --git a/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp b/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp
index f6bf70c77c1efc..6fe6cb14cd54c4 100644
--- a/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp
+++ b/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp
@@ -279,6 +279,7 @@ static bool is_decompression_multiply(const std::shared_ptr<const ov::Node> node
 
 namespace cldnn {
 extern bool query_microkernels_supported(cldnn::engine& e, const cldnn::ExecutionConfig& config);
+extern bool check_cm_jit_support(cldnn::engine& e, const cldnn::ExecutionConfig& config);
 }  // namespace cldnn
 
 namespace ov::intel_gpu {
@@ -531,6 +532,50 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
             manager.register_pass<ov::pass::BidirectionalRNNSequenceDecomposition>();
         }
 
+        // Disable Bidirectional LSTM decomposition if node is supported by XeTLA
+        pass_config->set_callback<ov::pass::BidirectionalLSTMSequenceDecomposition>(
+                [&](const_node_ptr &node) -> bool {
+                    const auto &lstm_seq = ov::as_type_ptr<const ov::op::v5::LSTMSequence>(node);
+
+                    auto &engine = m_context->get_engine();
+                    if (!cldnn::check_cm_jit_support(engine, config) || engine.get_device_info().arch != cldnn::gpu_arch::xe2) {
+                        return false;
+                    }
+
+                    if (lstm_seq->get_clip() > 0.f) {
+                        return false;
+                    }
+
+                    const auto &activations = lstm_seq->get_activations();
+                    if (activations.size() != 3 ||
+                        activations[0].compare("sigmoid") != 0 || activations[1].compare("tanh") != 0 || activations[2].compare("tanh") != 0) {
+                        return false;
+                    }
+
+                    if (lstm_seq->get_output_element_type(0) != ov::element::f16) {
+                        return false;
+                    }
+
+                    if (lstm_seq->is_dynamic()) {
+                        return false;
+                    }
+                    const auto &input = lstm_seq->get_input_shape(0);
+                    const auto &output = lstm_seq->get_output_shape(0);
+                    if (input.size() != 3 || output.size() != 4) {
+                        return false;
+                    }
+                    auto batch_size = input[0];
+                    auto input_size = input[2];
+                    auto num_dir = output[1];
+                    auto hidden_size = output[3];
+
+                    if (hidden_size != 128 || batch_size != 1 || num_dir != 2 || (input_size != 64 && input_size != 256)) {
+                        return false;
+                    }
+
+                    return true;
+                });
+
         manager.register_pass<ConvertShapeOf1To3>();
         manager.register_pass<ov::pass::ConvertNMS1ToNMS9>();
         manager.register_pass<ov::pass::ConvertNMS3ToNMS9>();
diff --git a/src/plugins/intel_gpu/tests/functional/shared_tests_instances/single_layer_tests/lstm_sequence.cpp b/src/plugins/intel_gpu/tests/functional/shared_tests_instances/single_layer_tests/lstm_sequence.cpp
index a9b7a0b4dca0b3..77554fd05336d9 100644
--- a/src/plugins/intel_gpu/tests/functional/shared_tests_instances/single_layer_tests/lstm_sequence.cpp
+++ b/src/plugins/intel_gpu/tests/functional/shared_tests_instances/single_layer_tests/lstm_sequence.cpp
@@ -94,4 +94,28 @@ INSTANTIATE_TEST_SUITE_P(smoke_LSTMSequenceCommonClip, LSTMSequenceTest,
                                 ::testing::Values(ov::test::utils::DEVICE_GPU)),
                         LSTMSequenceTest::getTestCaseName);
 
+
+std::vector<size_t> seq_lengths_cm{2};
+std::vector<size_t> batch_cm{1};
+std::vector<size_t> hidden_size_cm{128};
+std::vector<size_t> input_size_cm{64, 256};
+std::vector<std::vector<std::string>> activations_cm = {{"sigmoid", "tanh", "tanh"}};
+std::vector<float> clip_cm{0};
+std::vector<ov::element::Type> netPrecisions_cm = {ov::element::f16};
+
+INSTANTIATE_TEST_SUITE_P(LSTMSequenceCM, LSTMSequenceTest,
+                        ::testing::Combine(
+                                ::testing::Values(ov::test::utils::SequenceTestsMode::PURE_SEQ),
+                                ::testing::ValuesIn(seq_lengths_cm),
+                                ::testing::ValuesIn(batch_cm),
+                                ::testing::ValuesIn(hidden_size_cm),
+                                ::testing::ValuesIn(input_size_cm),
+                                ::testing::ValuesIn(activations_cm),
+                                ::testing::ValuesIn(clip_cm),
+                                ::testing::Values(ov::op::RecurrentSequenceDirection::BIDIRECTIONAL),
+                                ::testing::Values(ov::test::utils::InputLayerType::CONSTANT),
+                                ::testing::ValuesIn(netPrecisions_cm),
+                                ::testing::Values(ov::test::utils::DEVICE_GPU)),
+                        LSTMSequenceTest::getTestCaseName);
+
 }  // namespace
diff --git a/src/plugins/intel_gpu/thirdparty/CMakeLists.txt b/src/plugins/intel_gpu/thirdparty/CMakeLists.txt
index 475e9213ecf9f0..b4c1e3f71a7aaf 100644
--- a/src/plugins/intel_gpu/thirdparty/CMakeLists.txt
+++ b/src/plugins/intel_gpu/thirdparty/CMakeLists.txt
@@ -2,6 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
+set(XETLA_INCLUDE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/xetla/include/" CACHE PATH "Path to XeTLA headers")
+
 #
 # oneDNN for GPU plugin
 #
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/LICENSE b/src/plugins/intel_gpu/thirdparty/xetla/LICENSE
new file mode 100644
index 00000000000000..46808898b73642
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/LICENSE
@@ -0,0 +1,193 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
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+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
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+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
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+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
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+   3. Grant of Patent License. Subject to the terms and conditions of
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+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
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+      Contribution(s) alone or by combination of their Contribution(s)
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+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
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+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
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+      on Your own behalf and on Your sole responsibility, not on behalf
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+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   ============================================================================   
+
+   Copyright (c) 2022-2023 Intel Corporation
+
+   
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/README.md b/src/plugins/intel_gpu/thirdparty/xetla/README.md
new file mode 100644
index 00000000000000..d124ba902d251d
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/README.md
@@ -0,0 +1,26 @@
+# Intel® Xe Templates for Linear Algebra
+
+This is the bare-bones version of Intel® Xe Templates for Linear Algebra (Intel® XeTLA) which only supports CM. If you want to contribute to XeTLA or use full version, please contact Yershov, Dmitry B.
+
+## Security
+
+See Intel's [Security Center](https://www.intel.com/content/www/us/en/security-center/default.html)
+for information on how to report a potential security issue or vulnerability.
+
+See also: [Security Policy](/SECURITY.md)
+
+## Copyright
+
+Copyright (c) 2022-2023 Intel Corporation
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+  [http://www.apache.org/licenses/LICENSE-2.0](http://www.apache.org/licenses/LICENSE-2.0)
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/SECURITY.md b/src/plugins/intel_gpu/thirdparty/xetla/SECURITY.md
new file mode 100755
index 00000000000000..c560937cc93627
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/SECURITY.md
@@ -0,0 +1,6 @@
+[README](/README.md#Security) > **Security Policy**
+# Security Policy
+Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation.
+
+## Reporting a Vulnerability
+Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/common.hpp
new file mode 100644
index 00000000000000..0fb26d30e0e878
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/common.hpp
@@ -0,0 +1,23 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "common/core/core.hpp"
+#include "common/utils/utils.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/arch_config.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/arch_config.hpp
new file mode 100644
index 00000000000000..43784d6cf90b64
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/arch_config.hpp
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_arch_config
+/// @{
+
+template <msg_type message_type, gpu_arch arch_tag>
+struct load_store_attr_t {};
+template <>
+struct load_store_attr_t<msg_type::block_2d, gpu_arch::Xe> {
+    static constexpr uint32_t max_load_height_in_elem = 32;
+    static constexpr uint32_t max_load_width_in_bytes = 64;
+    static constexpr uint32_t max_trans_load_width_in_bytes = 32;
+    static constexpr uint32_t special_trans_load_width_in_bytes = 32;
+    static constexpr uint32_t max_vnni_load_width_in_elems = 16;
+    static constexpr uint32_t min_vnni_load_height_in_bytes = 4;
+
+    static constexpr uint32_t max_store_height_in_elem = 8;
+    static constexpr uint32_t max_store_width_in_bytes = 64;
+
+    static constexpr uint32_t max_load_size_in_bytes = 2048;
+    static constexpr uint32_t max_store_size_in_bytes = 512;
+
+    static constexpr uint32_t special_prefetch_width_in_bytes = 64;
+
+    static constexpr uint32_t cache_line_size_in_bytes = 64;
+    static constexpr uint32_t alignment_in_bytes = 8;
+};
+
+template <gpu_arch arch_tag>
+struct mma_attr_t {};
+template <>
+struct mma_attr_t<gpu_arch::Xe> {
+    static constexpr uint32_t mma_m_in_elem = 8;
+    static constexpr uint32_t mma_n_in_elem = 16;
+    static constexpr uint32_t mma_k_in_bytes = 32;
+};
+
+template <grf_mode grf_num_mode, gpu_arch arch_tag>
+struct register_attr_t {};
+template <grf_mode grf_num_mode>
+struct register_attr_t<grf_num_mode, gpu_arch::Xe> {
+    static constexpr uint32_t acc_reg_in_bytes
+            = (grf_num_mode == grf_mode::normal) ? 4 * 64 : 8 * 64;
+    static constexpr uint32_t grf_in_bytes
+            = (grf_num_mode == grf_mode::normal) ? 128 * 64 : 256 * 64;
+    static constexpr uint32_t reg_in_bytes = 64;
+};
+
+template <gpu_arch arch_tag>
+struct arch_attr_t {};
+template <>
+struct arch_attr_t<gpu_arch::Xe> {
+    template <msg_type message_type = msg_type::block_2d>
+    using load_store_attr = load_store_attr_t<message_type, gpu_arch::Xe>;
+
+    template <grf_mode grf_num_mode = grf_mode::double_grf>
+    using register_attr = register_attr_t<grf_num_mode, gpu_arch::Xe>;
+
+    using mma_attr = mma_attr_t<gpu_arch::Xe>;
+
+    static constexpr uint32_t max_wg_num = 64;
+};
+
+/// @} xetla_core_arch_config
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/barrier.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/barrier.hpp
new file mode 100644
index 00000000000000..37ec95b1372f1a
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/barrier.hpp
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_barrier
+/// @{
+
+/// @brief Initialize the number of named barrier index for a kernel.
+/// Available only on PVC. Only need to initialize once at the beginning.
+///
+/// @tparam NbarCount  - number of named barriers.
+template <uint8_t NbarCount>
+__XETLA_API void xetla_nbarrier_init() {
+    cm_nbarrier_init(NbarCount);
+}
+
+/// @brief Perform signal operation for the given named barrier id.
+/// Available only on PVC.
+///
+/// @param barrier_id  [in] is the named barrier id.
+///
+/// @param producer_consumer_mode  [in] is 2-bit flag to indicate if it's
+/// producer-consumer mode(0x0) or producer mode (0x1) or consumer mode (0x2).
+/// User must ensure the input value is set correctly and higher order bits are cleared.
+///
+/// @param num_producers  [in] is the number of producers.
+///
+/// @param num_consumers  [in] is the number of consumers.
+__XETLA_API void named_barrier_signal(uint8_t barrier_id,
+        uint8_t producer_consumer_mode, uint32_t num_producers,
+        uint32_t num_consumers) {
+
+    cm_nbarrier_signal((uint32_t)barrier_id, (uint32_t)producer_consumer_mode,
+            num_producers, num_consumers);
+}
+
+/// @brief Wait on a named barrier.
+/// Available only on PVC
+///
+/// @param barrier_id  [in] is the named barrier id.
+/// It’s value cannot exceed the total count of initialized named barriers.
+__XETLA_API void named_barrier_wait(uint8_t barrier_id) {
+    cm_nbarrier_wait(barrier_id);
+}
+
+/// @} xetla_core_barrier
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_consts.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_consts.hpp
new file mode 100644
index 00000000000000..338acf45add96a
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_consts.hpp
@@ -0,0 +1,35 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_base_types
+/// @{
+
+/// @} xetla_core_base_types
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_ops.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_ops.hpp
new file mode 100644
index 00000000000000..968926301333f7
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_ops.hpp
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_base_ops
+/// @{
+
+/// @brief xetla format.
+/// Alias to CM `.format<...>()`;
+/// @note usage:
+/// ```
+/// [xetla_vector|xetla_vector_ref|xetla_matrix_ref].xetla_format<type>(): returns a reference to the calling object interpreted as a new xetla_vector_ref (1D).
+///
+/// [xetla_vector|xetla_vector_ref|xetla_matrix_ref].xetla_format<type, rows, columns>(): returns a reference to the calling object interpreted as a new xetla_matrix_ref (2D).
+/// ```
+///
+#define xetla_format format
+
+/// @brief xetla select.
+/// Alias to CM `.select<...>()`;
+/// @note usage:
+/// ```
+/// [xetla_vector|xetla_vector_ref].xetla_select<size, stride>(uint16_t offset=0): returns a reference to the sub-vector starting from the offset-th element.
+///
+/// [xetla_matrix_ref].xetla_select<size_y, stride_y, size_x, stride_x>(uint16_t offset_y=0, uint16_t offset_x=0): returns a reference to the sub-matrix starting from the (offset_y, offset_x)-th element.
+/// ```
+///
+#define xetla_select select
+
+/// @brief xetla merge.
+/// Alias to `.merge(...)`. Replaces part of the underlying data with the one taken from the other object according to a mask.
+/// @note usage:
+/// ```
+/// [xetla_vector|xetla_vector_ref].xetla_merge(xetla_vector<Ty, N>Val, xetla_mask<N>mask): only elements in lanes with non-zero mask predicate are assigned from corresponding Val elements.
+///
+/// [xetla_vector|xetla_vector_ref].xetla_merge(xetla_vector<Ty, N>Val1, xetla_vector<Ty, N>Val2, xetla_mask<N>mask): non-zero in a mask's lane tells to take corresponding element from Val1, zero - from Val2.
+/// ```
+///
+#define xetla_merge merge
+
+// TODO add replicate, iselect
+
+/// @} xetla_core_base_ops
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_types.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_types.hpp
new file mode 100644
index 00000000000000..297cd941623be9
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/base_types.hpp
@@ -0,0 +1,242 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_base_types
+/// @{
+
+/// @brief xetla bf16 data type.
+/// The difference between bf16 and fp32 is:
+///
+/// fp32: 0_00000000_00000000000000000000000
+///
+/// bf16: 0_00000000_0000000
+/// @note
+/// The member function in bf16 class is only used in host side.
+/// For device side, we will automatically convert it to its native type.
+/// @see native_type_t
+///
+struct bf16 {
+    uint16_t data;
+
+    operator float() const {
+        uint32_t temp = data;
+        temp = temp << 0x10;
+        return *reinterpret_cast<float *>(&temp);
+    }
+    bf16() = default;
+    bf16(float val) { data = (*reinterpret_cast<uint32_t *>(&val)) >> 0x10; }
+
+    bf16 &operator=(float val) {
+        this->data = (*reinterpret_cast<uint32_t *>(&val)) >> 0x10;
+        return *this;
+    }
+};
+
+using fp16 = half;
+
+/// @brief xetla tf32 data type.
+/// The difference between tf32 and fp32 is:
+///
+/// fp32: 0_00000000_00000000000000000000000
+///
+/// tf32: 0_00000000_0000000000
+/// @note
+/// The member function in tf32 class is only used in host side.
+/// For device side, we will automatically convert it to its native type.
+/// @see native_type_t
+///
+struct tf32 {
+    uint32_t data;
+    operator float() const {
+        uint32_t temp = data;
+        return *reinterpret_cast<float *>(&temp);
+    }
+
+    tf32(float val) {
+        data = (*reinterpret_cast<uint32_t *>(&val)) & 0xFFFFE000;
+    }
+
+    tf32 &operator=(float val) {
+        this->data = (*reinterpret_cast<uint32_t *>(&val)) & 0xFFFFE000;
+        return *this;
+    }
+};
+
+template <typename T>
+struct get_packed_num {
+    static constexpr uint32_t value = 1;
+};
+
+/// @brief Used to check if the type is xetla internal data type
+/// @tparam T is the data type
+template <typename T>
+struct is_internal_type {
+    static constexpr bool value = std::is_same<remove_const_t<T>, bf16>::value
+            || std::is_same<remove_const_t<T>, tf32>::value;
+};
+
+/// @brief Used to check if the type is floating_point.
+/// @tparam T is the data type
+template <typename T>
+struct is_floating_point {
+    static constexpr bool value = std::is_same<remove_const_t<T>, bf16>::value
+            || std::is_same<remove_const_t<T>, fp16>::value
+            || std::is_same<remove_const_t<T>, tf32>::value
+            || std::is_same<remove_const_t<T>, float>::value
+            || std::is_same<remove_const_t<T>, double>::value;
+};
+
+/// @brief Used to check if the type is floating_point.
+/// @tparam T is the data type
+template <typename T>
+struct is_integral {
+    static constexpr bool value = std::is_same<remove_const_t<T>, int8_t>::value
+            || std::is_same<remove_const_t<T>, uint8_t>::value
+            || std::is_same<remove_const_t<T>, int16_t>::value
+            || std::is_same<remove_const_t<T>, uint16_t>::value
+            || std::is_same<remove_const_t<T>, int32_t>::value
+            || std::is_same<remove_const_t<T>, uint32_t>::value
+            || std::is_same<remove_const_t<T>, int64_t>::value
+            || std::is_same<remove_const_t<T>, uint64_t>::value;
+};
+
+/// @brief Set the native data type of T
+/// @tparam T is the data type
+template <typename T>
+struct native_type {
+    using type = T;
+};
+
+/// @brief Set bfloat16 as the native data type of bf16
+template <>
+struct native_type<bf16> {
+    using type = short;
+};
+
+/// @brief Set uint32_t as the native data type of tf32
+template <>
+struct native_type<tf32> {
+    using type = int;
+};
+
+/// @brief Return the native data type of T
+template <typename T>
+using native_type_t = typename native_type<T>::type;
+
+/// @brief Get the unit representation of type T
+template <typename T>
+struct uint_type {
+    static constexpr bool is_uint8 = sizeof(T) == 1;
+    static constexpr bool is_uint16 = sizeof(T) == 2;
+    static constexpr bool is_uint32 = sizeof(T) == 4;
+    static constexpr bool is_uint64 = sizeof(T) == 8;
+    using type = typename std::conditional<is_uint8, uint8_t,
+            typename std::conditional<is_uint16, uint16_t,
+                    typename std::conditional<is_uint32, uint32_t,
+                            typename std::conditional<is_uint64, uint64_t,
+                                    void>::type>::type>::type>::type;
+};
+
+/// @brief Get the unit representation based on Size
+template <int Size>
+struct get_uint_type {
+    static constexpr bool is_uint8 = Size == 1;
+    static constexpr bool is_uint16 = Size == 2;
+    static constexpr bool is_uint32 = Size == 4;
+    static constexpr bool is_uint64 = Size == 8;
+    using type = typename std::conditional<is_uint8, uint8_t,
+            typename std::conditional<is_uint16, uint16_t,
+                    typename std::conditional<is_uint32, uint32_t,
+                            typename std::conditional<is_uint64, uint64_t,
+                                    void>::type>::type>::type>::type;
+};
+/// @brief Return the uint representation of type T
+template <typename T>
+using uint_type_t = typename uint_type<T>::type;
+
+/// @brief Return the uint representation based on Size
+template <int Size>
+using get_uint_type_t = typename get_uint_type<Size>::type;
+
+/// @brief wrapper for xetla_vector.
+/// Alias to CM `vector`.
+/// @tparam Ty data type in xetla_vector.
+/// @tparam N  data length in xetla_vector.
+///
+template <typename Ty, uint32_t N>
+using xetla_vector = vector<native_type_t<Ty>, N>;
+
+/// @brief wrapper for xetla_mask.
+/// Alias to CM `vector<uint16_t, N>`.
+/// @tparam N  data length in xetla_mask.
+///
+template <uint32_t N>
+using xetla_mask = vector<uint16_t, N>;
+
+/// @brief wrapper for xetla_mask_int.
+/// Alias to CM integer as packed mask.
+/// @tparam N  number of bits as mask in xetla_mask_int.
+///
+template <uint32_t N>
+using xetla_mask_int = uint32_t;
+
+/// Alias to `(empty)` if go with CM path.
+/// @see gpu::xetla::core::xetla_matrix_ref gpu::xetla::core::xetla_vector_ref
+#define __REF__
+
+/// @brief wrapper for xetla_vector_ref.
+/// Alias to `vector_ref` if go with CM path.
+/// @note Need to be used together with `__REF__`, i.e. `"xetla_vector_ref __REF__"` is the full declaration of xetla vector reference.
+/// @tparam Ty data type in xetla_vector.
+/// @tparam N  data length in xetla_vector.
+///
+template <typename Ty, uint32_t N>
+using xetla_vector_ref = vector_ref<native_type_t<Ty>, N>;
+
+///
+/// @brief Description of nd tensor descriptor for load and store.
+///
+using xetla_tdescriptor = xetla_vector<uint32_t, 16>;
+
+/// @brief Alias to xetla_vector<uint32_t, 16> reference.
+#define xetla_tdescriptor_ref xetla_vector_ref<uint32_t, 16> __REF__
+
+/// @brief wrapper for xetla_matrix_ref.
+/// Alias to `matrix_ref` if go with CM path.
+/// @note Need to be used together with `__REF__`, i.e. `"xetla_matrix_ref __REF__"` is the full declaration of xetla matrix reference.
+/// @tparam Ty data type in xetla_matrix_ref.
+/// @tparam N1 row num in xetla_matrix_ref.
+/// @tparam N2 col num in xetla_matrix_ref.
+///
+template <typename Ty, uint32_t N1, uint32_t N2>
+using xetla_matrix_ref = matrix_ref<native_type_t<Ty>, N1, N2>;
+
+/// @} xetla_core_base_types
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/bit_mask_manipulation.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/bit_mask_manipulation.hpp
new file mode 100644
index 00000000000000..6e17aa558fe210
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/bit_mask_manipulation.hpp
@@ -0,0 +1,287 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_bit_manipulation
+/// @{
+
+/// Shift left operation (vector version)
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vector.
+/// @tparam U type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input vector.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of shifted left values.
+template <typename T0, typename T1, int SZ, typename U,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T0, SZ> xetla_shl(
+        xetla_vector<T1, SZ> src0, U src1, Sat sat = {}) {
+    return cm_shl<T0, T1, SZ, U>(src0, src1, Sat::value);
+}
+
+/// Shift left operation (scalar version)
+/// @tparam T0 element type of the returned value. Must be any integer type.
+/// @tparam T1 element type of the input value. Must be any integer type.
+/// @tparam T2 type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input value.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return shifted left value.
+template <typename T0, typename T1, typename T2,
+        class Sat = xetla_saturation_off_tag>
+typename std::remove_const<T0>::type xetla_shl(T1 src0, T2 src1, Sat sat = {}) {
+    return cm_shl<T0, T1, T2>(src0, src1, Sat::value);
+}
+
+/// Shift right operation (vector version)
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vector.
+/// @tparam U type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input vector.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of shifted right values.
+template <typename T0, typename T1, int SZ, typename U,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T0, SZ> xetla_shr(
+        xetla_vector<T1, SZ> src0, U src1, Sat sat = {}) {
+    return cm_shr<T0, T1, SZ, U>(src0, src1, Sat::value);
+}
+
+/// Shift right operation (scalar version)
+/// @tparam T0 element type of the returned value. Must be any integer type.
+/// @tparam T1 element type of the input value. Must be any integer type.
+/// @tparam T2 type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input value.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return shifted right value.
+template <typename T0, typename T1, typename T2,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API typename std::remove_const<T0>::type xetla_shr(
+        T1 src0, T2 src1, Sat sat = {}) {
+    return cm_shr<T0, T1, T2>(src0, src1, Sat::value);
+}
+
+/// Rotate left operation with two vector inputs
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the vector with number of bit positions by which the elements of
+/// the input vector \p src0 shall be rotated.
+/// @return vector of rotated elements.
+template <typename T0, typename T1, int SZ>
+__XETLA_API xetla_vector<T0, SZ> xetla_rol(
+        xetla_vector<T1, SZ> src0, xetla_vector<T1, SZ> src1) {
+    return cm_rol<T0, T1, SZ>(src0, src1);
+}
+
+/// Rotate left operation with a vector and a scalar inputs
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vectors.
+/// @tparam U type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input vector.
+/// @param src1 the number of bit positions the input vector shall be rotated.
+/// @return vector of rotated elements.
+template <typename T0, typename T1, int SZ, typename U>
+__XETLA_API std::enable_if_t<std::is_integral<T0>::value
+                && std::is_integral<T1>::value && std::is_integral<U>::value
+                && is_xetla_scalar<U>::value,
+        xetla_vector<T0, SZ>>
+xetla_rol(xetla_vector<T1, SZ> src0, U src1) {
+    return cm_rol<T0, T1, SZ, U>(src0, src1);
+}
+
+/// Rotate left operation with two scalar inputs
+/// @tparam T0 element type of the returned value. Must be any integer type.
+/// @tparam T1 element type of the input value. Must be any integer type.
+/// @tparam T2 type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input value.
+/// @param src1 the number of bit positions the input vector shall be rotated.
+/// @return rotated left value.
+template <typename T0, typename T1, typename T2>
+__XETLA_API std::enable_if_t<std::is_integral<T0>::value
+                && std::is_integral<T1>::value && std::is_integral<T2>::value,
+        remove_const_t<T0>>
+xetla_rol(T1 src0, T2 src1) {
+    return cm_rol<T0, T1, T2>(src0, src1);
+}
+
+/// Rotate right operation with two vector inputs
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the vector with number of bit positions by which the elements of
+/// the input vector \p src0 shall be rotated.
+/// @return vector of rotated elements.
+template <typename T0, typename T1, int SZ>
+__XETLA_API xetla_vector<T0, SZ> xetla_ror(
+        xetla_vector<T1, SZ> src0, xetla_vector<T1, SZ> src1) {
+    return cm_ror<T0, T1, SZ>(src0, src1);
+}
+
+/// Rotate right operation with a vector and a scalar inputs
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vectors.
+/// @tparam U type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input vector.
+/// @param src1 the number of bit positions the input vector shall be rotated.
+/// @return vector of rotated elements.
+template <typename T0, typename T1, int SZ, typename U>
+__XETLA_API std::enable_if_t<std::is_integral<T0>::value
+                && std::is_integral<T1>::value && std::is_integral<U>::value
+                && is_xetla_scalar<U>::value,
+        xetla_vector<T0, SZ>>
+xetla_ror(xetla_vector<T1, SZ> src0, U src1) {
+    return cm_ror<T0, T1, SZ, U>(src0, src1);
+}
+
+/// Rotate right operation with two scalar inputs
+/// @tparam T0 element type of the returned value. Must be any integer type.
+/// @tparam T1 element type of the input value. Must be any integer type.
+/// @tparam T2 type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input value.
+/// @param src1 the number of bit positions the input vector shall be rotated.
+/// @return rotated right value.
+template <typename T0, typename T1, typename T2>
+__XETLA_API std::enable_if_t<std::is_integral<T0>::value
+                && std::is_integral<T1>::value && std::is_integral<T2>::value,
+        remove_const_t<T0>>
+xetla_ror(T1 src0, T2 src1) {
+    return cm_ror<T0, T1, T2>(src0, src1);
+}
+
+/// Logical Shift Right (vector version)
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vectors.
+/// @tparam U type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input vector.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of shifted elements.
+template <typename T0, typename T1, int SZ, typename U,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T0, SZ> xetla_lsr(
+        xetla_vector<T1, SZ> src0, U src1, Sat sat = {}) {
+    return cm_lsr<T0, T1, SZ, U>(src0, src1, Sat::value);
+}
+
+/// Logical Shift Right (scalar version)
+/// @tparam T0 element type of the returned value. Must be any integer type.
+/// @tparam T1 element type of the input value \p src0. Must be any integer
+/// type.
+/// @tparam T2 type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input value.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return shifted value.
+template <typename T0, typename T1, typename T2,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API typename std::remove_const<T0>::type xetla_lsr(
+        T1 src0, T2 src1, Sat sat = {}) {
+    return cm_lsr<T0, T1, T2>(src0, src1, Sat::value);
+}
+
+/// Arithmetical Shift Right (vector version)
+/// @tparam T0 element type of the returned vector. Must be any integer type.
+/// @tparam T1 element type of the input vector. Must be any integer type.
+/// @tparam SZ size of the input and returned vectors.
+/// @tparam U type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input vector.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of shifted elements.
+template <typename T0, typename T1, int SZ, typename U,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T0, SZ> xetla_asr(
+        xetla_vector<T1, SZ> src0, U src1, Sat sat = {}) {
+    return cm_asr<T0, T1, SZ, U>(src0, src1, Sat::value);
+}
+
+/// Arithmetical Shift Right (scalar version)
+/// @tparam T0 element type of the returned value. Must be any integer type.
+/// @tparam T1 element type of the input value \p src0. Must be any integer
+/// type.
+/// @tparam T2 type of scalar operand \p src1. Must be any integer type.
+/// @param src0 the input value.
+/// @param src1 the number of bit positions the input vector shall be shifted.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return shifted value.
+template <typename T0, typename T1, typename T2,
+        class Sat = xetla_saturation_off_tag>
+__XETLA_API typename std::remove_const<T0>::type xetla_asr(
+        T1 src0, T2 src1, Sat sat = {}) {
+    return cm_asr<T0, T1, T2>(src0, src1, Sat::value);
+}
+
+/// Pack a xetla_mask into a single unsigned 32-bit integer value.
+/// i'th bit in the returned value is set to the result of comparison of the
+/// i'th element of the input argument to zero. "equals to zero" gives \c 0,
+/// "not equal to zero" gives \c 1. Remaining (if any) bits if the result are
+/// filled with \c 0.
+/// @tparam N Size of the input mask.
+/// @param src0 The input mask.
+/// @return The packed mask as an <code> unsigned int</code> 32-bit value.
+template <int N>
+__XETLA_API uint32_t xetla_pack_mask(xetla_mask<N> src0) {
+    return cm_pack_mask<N>(src0);
+}
+
+/// Unpack an unsigned 32-bit integer value into a xetla_mask. Only \c N least
+/// significant bits are used, where \c N is the number of elements in the
+/// result mask. Each input bit is stored into the corresponding vector element
+/// of the output mask.
+/// @tparam N Size of the output mask.
+/// @param src0 The input packed mask.
+/// @return The unpacked mask as a xetla_mask object.
+template <int N>
+__XETLA_API xetla_mask<N> xetla_unpack_mask(uint32_t src0) {
+    return cm_unpack_mask<uint16_t, N>(src0);
+}
+
+/// @} xetla_core_bit_manipulation
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/common.hpp
new file mode 100644
index 00000000000000..d385b5b5b51e9c
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/common.hpp
@@ -0,0 +1,227 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifndef XETLA_NO_CM_INCLUDE
+#include <cm/cm.h>
+#include <cm/cmtl.h>
+#endif
+
+template <class T>
+using remove_const_t = typename std::remove_const<T>::type;
+
+/// @addtogroup xetla_core
+/// @{
+
+/// @brief KERNEL_MAIN macro.
+/// Alias to CM `"_GENX_MAIN_"`.
+///
+#define KERNEL_MAIN _GENX_MAIN_
+
+/// @brief KERNEL_FUNC macro.
+/// Alias to empty.
+///
+#define KERNEL_FUNC
+
+/// @} xetla_core
+
+#define __XETLA_API inline
+
+#define XETLA_WARNING(msg) CM_STATIC_WARNING(0, msg)
+
+#define XETLA_MARKER(message) [[deprecated(message)]]
+
+#define DEVICE_PRINTF(s, ...) \
+    do { \
+    } while (0)
+
+#define DEVICE_ASSERT(c, s, ...) \
+    do { \
+    } while (0);
+
+template <auto val>
+XETLA_MARKER("Help function to print value")
+inline constexpr void XETLA_PRINT() {}
+template <typename type>
+XETLA_MARKER("Help function to print type")
+inline constexpr void XETLA_PRINT() {}
+
+namespace gpu::xetla {
+
+enum class gpu_arch : uint8_t { Xe = 0 };
+enum class grf_mode : uint8_t { normal = 0, double_grf = 1 };
+
+enum class mem_layout : uint8_t {
+    row_major = 0,
+    col_major = 1,
+    nhwc = 2,
+    hwio = 3,
+};
+enum class mem_space : uint8_t { global = 0, local = 1 };
+enum class msg_type : uint8_t {
+    block_2d = 0,
+    block_1d = 1,
+    scatter = 2,
+    atomic_add = 3,
+    unaligned_2d = 4
+    // prefetch_2d = 4,
+    // prefetch_1d = 5
+};
+/// L1 or L2 cache hint kinds.
+enum class cache_hint : uint8_t {
+    none = 0,
+    uncached = 1,
+    cached = 2,
+    write_back = 3,
+    write_through = 4,
+    streaming = 5,
+    read_invalidate = 6
+};
+
+/// Data size or format to read or store
+enum class data_size : uint8_t {
+    default_size = 0,
+    u8 = 1,
+    u16 = 2,
+    u32 = 3,
+    u64 = 4,
+    u8u32 = 5, /// load 8b, zero extend to 32b; store the opposite
+    u16u32 = 6, /// load 16b, zero extend to 32b; store the opposite
+    u16u32h = 7, /// load 16b into high 16 of each 32b; store the high 16
+};
+
+/// The specific LSC shared function to fence with xetla_fence
+enum class memory_kind : uint8_t {
+    untyped_global = 0, /// untyped global memory
+    untyped_global_low_pri = 1, /// low-priority untyped global memory
+    typed_global = 2, /// typed global memory
+    shared_local = 3, /// shared local memory
+};
+
+/// The xetla_fence operation to apply to caches
+enum class fence_op : uint8_t {
+    none = 0, /// no operation
+    evict = 1, /// dirty lines evicted and invalidated from L1
+    invalidate = 2, /// invalidate all clean lines
+    discard = 3, /// direct and clean lines are discarded w/o eviction
+    clean = 4, /// dirty lines are written to memory, but retained in cache
+    /// in clean state
+    flushl2 = 5, /// flush only L2
+};
+/// The scope that xetla_fence operation should apply to
+enum class fence_scope : uint8_t {
+    group = 0, /// flush out to the threadgroup's scope
+    local = 1, /// flush out to the local scope
+    tile = 2, /// tile, flush out to several DSSs
+    gpu = 3, /// entire GPU, flush out to the GPUs LLC
+    gpus = 4, /// all GPUs in the system, flush out to memory shared by all GPUs
+    system = 5, /// the entire system memory space
+    sysacq = 6, /// the entire system memory space with system-acquire semantics
+};
+
+/// Represents an atomic operation. Operations always return the old value(s) of
+/// the target memory location(s) as it was before the operation was applied.
+enum class atomic_op : uint8_t {
+    /// Atomic increment of memory data and return the old value.
+    iinc = 0x0,
+    /// Atomic decrement of memory data and return the old value.
+    idec = 0x1,
+    /// Atomic signed int add of src1 from memory data and return the old value.
+    iadd = 0x2,
+    /// Atomic signed int subtract of src1 from memory data and return the old value.
+    isub = 0x3,
+    /// Atomic store the signed int min of src1 and memory data and return the old value.
+    smin = 0x4,
+    /// Atomic store the signed int max of src1 and memory data and return the old value.
+    smax = 0x5,
+    /// Atomic bit-compare src1_X and memory data and replace if equal with src1_Y. Returns the old value.
+    cmpxchg = 0x6,
+    /// Atomic float add of src1 from memory data and return the old value.
+    fadd = 0x7,
+    /// Atomic float subtract of src1 from memory data and return the old value.
+    fsub = 0x8,
+    /// Atomic store the float min of src1 and memory data and return the old value.
+    fmin = 0x9,
+    /// Atomic store the float max of src1 and memory data and return the old value.
+    fmax = 0xa,
+    /// Atomic float compare src1_X and memory data and replace if equal with src1_Y. Returns the old value.
+    fcmpxchg = 0xb,
+    /// Atomic store the unsigned int min of src1 and memory data and return the old value.
+    umin = 0xc,
+    /// Atomic store the unsigned int max of src1 and memory data and return the old value.
+    umax = 0xd,
+    /// Atomic store the bitwise AND of src1 and memory data and return the old value.
+    bit_and = 0xe,
+    /// Atomic store the bitwise OR of src1 and memory data and return the old value.
+    bit_or = 0xf,
+    /// Atomic store the bitwise XOR of src1 and memory data and return the old value.
+    bit_xor = 0x10,
+    /// Atomic read of the memory data value, without modifying the data.
+    load = 0x11,
+    /// Atomic store untyped data to memory.
+    store = 0x12
+};
+
+/// xetla dpas argument typ
+enum class argument_type : uint8_t {
+    U2 = 2, // unsigned 2 bits
+    S2 = 3, // signed 2 bits
+    U4 = 4, // unsigned 4 bits
+    S4 = 5, // signed 4 bits
+    U8 = 6, // unsigned 8 bits
+    S8 = 7, // signed 8 bits
+    BF16 = 8, // bfloat 16
+    FP16 = 9, // half float
+    TF32 = 12, // tensorfloat 32
+    DF = 13, // double (64bits)
+    NUM_ARG_TYPES = 14
+};
+
+// Saturation tag
+class xetla_saturation_on_tag {
+public:
+    static constexpr int value = _GENX_SAT;
+};
+
+class xetla_saturation_off_tag {
+public:
+    static constexpr int value = _GENX_NOSAT;
+};
+
+template <typename T>
+using is_xetla_scalar = typename details::is_cm_scalar<T>;
+
+/// xetla reduce op
+enum class reduce_op : uint8_t {
+    sum = 0, // performance reduce_sum
+    prod = 1, // performance reduce_prod
+    min = 2, // performance reduce_min
+    max = 3, // performance reduce_max
+};
+
+/// SW_BARRIER, insert software scheduling barrier, for better code control
+///
+#define SW_BARRIER() cm_fence(CM_SW_BARRIER)
+
+__XETLA_API void xetla_wait(uint16_t val) {
+    __cm_builtin_dummy_mov(val);
+}
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/core.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/core.hpp
new file mode 100644
index 00000000000000..695e2e36cfb27c
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/core.hpp
@@ -0,0 +1,97 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+/// @defgroup xetla_core XeTLA Core
+
+/// Some terminologies used in the API documentation:
+/// - *word* - 2 bytes.
+/// - *dword* ("double word") - 4 bytes.
+/// - *qword* ("quad word") - 8 bytes.
+/// - *oword* ("octal word") - 16 bytes.
+///
+
+/// @addtogroup xetla_core
+/// @{
+
+/// @defgroup xetla_core_base_types Base types
+/// Defines vector, vector reference and matrix reference data types.
+
+/// @defgroup xetla_core_base_ops Base ops
+/// Defines base ops for vector, vector reference and matrix reference data types.
+
+/// @defgroup xetla_core_memory Memory access APIs
+/// Defines XeTLA APIs to access memory, including read, write and atomic.
+
+/// @defgroup xetla_core_barrier Synchronization APIs
+/// Defines XeTLA APIs for synchronization primitives.
+
+/// @defgroup xetla_core_math Math operation APIs
+/// Defines math operations on XeTLA vector data types.
+
+/// @defgroup xetla_core_bit_manipulation Bit and mask manipulation APIs
+/// Defines bitwise operations.
+
+/// @defgroup xetla_core_conv Explicit conversion APIs
+/// Defines explicit conversions (with and without saturation), truncation etc. between XeTLA vector types.
+
+/// @defgroup xetla_core_raw_send Raw send APIs
+/// Implements the \c send instruction to send messages to variaous components
+/// of the Intel(R) processor graphics, as defined in the documentation at [here](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol02a-commandreference-instructions_2.pdf)
+
+/// @defgroup xetla_core_misc Miscellaneous XeTLA convenience functions
+/// Wraps some useful functions.
+
+/// @defgroup xetla_core_arch_config Arch config information
+/// Defines some hardware arch related information, mainly used to do HW limitation check.
+
+/// @} xetla_core
+
+#ifdef _WIN32
+#include "../../../common/core/cm/arch_config.hpp"
+#include "../../../common/core/cm/barrier.hpp"
+#include "../../../common/core/cm/base_consts.hpp"
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/bit_mask_manipulation.hpp"
+#include "../../../common/core/cm/debug.hpp"
+#include "../../../common/core/cm/explicit_conv.hpp"
+#include "../../../common/core/cm/math_fma.hpp"
+#include "../../../common/core/cm/math_general.hpp"
+#include "../../../common/core/cm/math_mma.hpp"
+#include "../../../common/core/cm/memory.hpp"
+#include "../../../common/core/cm/misc.hpp"
+#include "../../../common/core/cm/raw_send.hpp"
+#else
+#include "common/core/cm/arch_config.hpp"
+#include "common/core/cm/barrier.hpp"
+#include "common/core/cm/base_consts.hpp"
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/bit_mask_manipulation.hpp"
+#include "common/core/cm/debug.hpp"
+#include "common/core/cm/explicit_conv.hpp"
+#include "common/core/cm/math_fma.hpp"
+#include "common/core/cm/math_general.hpp"
+#include "common/core/cm/math_mma.hpp"
+#include "common/core/cm/memory.hpp"
+#include "common/core/cm/misc.hpp"
+#include "common/core/cm/raw_send.hpp"
+#endif
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/debug.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/debug.hpp
new file mode 100644
index 00000000000000..c4176597080829
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/debug.hpp
@@ -0,0 +1,45 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#include "../../../common/core/cm/math_general.hpp"
+#else
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#include "common/core/cm/math_general.hpp"
+#endif
+
+namespace gpu::xetla {
+
+#define XETLA_PRINTF(s, ...) \
+    do { \
+    } while (0)
+
+#define XETLA_ASSERT(c, s, ...) \
+    do { \
+    } while (0)
+
+#define DEBUG_INVOKE(level, ...) \
+    do { \
+    } while (0)
+
+} // namespace gpu::xetla
\ No newline at end of file
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/explicit_conv.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/explicit_conv.hpp
new file mode 100644
index 00000000000000..867d933dd8ca8c
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/explicit_conv.hpp
@@ -0,0 +1,158 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#include "../../../common/core/cm/math_general.hpp"
+#else
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#include "common/core/cm/math_general.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_conv
+/// @{
+
+//template <typename T_dst, typename T_src, int N>
+//__XETLA_API xetla_vector<T_dst, N> xetla_cvt(xetla_vector<T_src, N> src) {}
+
+/// @brief xetla explicit data conversion for standard data types(integer,float,half)
+/// @tparam T_dst is the destination data type.
+/// @tparam T_src is the source data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<!(is_internal_type<T_dst>::value)
+                && !(is_internal_type<T_src>::value),
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src) {
+    xetla_vector<T_dst, N> dst = src;
+    return dst;
+}
+
+/// @brief xetla explicit data conversion, fp32->bf16.
+/// @tparam T_dst is the float32 data type.
+/// @tparam T_src is the bfloat16 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, bf16>::value
+                && std::is_same<T_src, float>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src) {
+    return cm_bf_cvt<half, T_src, N>(src).xetla_format<native_type_t<T_dst>>();
+}
+
+/// @brief xetla explicit data conversion, bf16->fp32.
+/// @tparam T_dst is the bfloat16 data type.
+/// @tparam T_src is the float32 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, float>::value
+                && std::is_same<T_src, bf16>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src) {
+    return cm_bf_cvt<T_dst, half, N>(src.xetla_format<half>());
+}
+
+/// @brief xetla explicit data conversion, fp32->tf32.
+/// @tparam T_dst is the float32 data type.
+/// @tparam T_src is the tensor_float32 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, tf32>::value
+                && std::is_same<T_src, float>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src) {
+    return cm_tf32_cvt<native_type_t<T_dst>, T_src, N>(src);
+}
+
+/// @brief xetla explicit data conversion, tf32->fp32.
+/// @tparam T_dst is the tensor_float32 data type.
+/// @tparam T_src is the float32 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, float>::value
+                && std::is_same<T_src, tf32>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src) {
+    return src.xetla_format<float>();
+}
+
+/// @brief xetpp explicit data conversion with scaling, int32->fp16.
+/// @tparam T_dst is the half data type.
+/// @tparam T_src is the int32 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, fp16>::value
+                && std::is_same<T_src, int32_t>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src, float scaling_value) {
+    xetla_vector<T_dst, N> dst = scaling_value * src;
+    return dst;
+}
+
+/// @brief xetpp explicit data conversion with re-quantization, int32->int8.
+/// @tparam T_dst is the int32 data type.
+/// @tparam T_src is the int8 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, int8_t>::value
+                && std::is_same<T_src, int32_t>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src, float scaling_value) {
+    auto dst = xetla_vector<T_dst, N>(
+            xetla_rnde<float>(scaling_value * src), SAT);
+    return dst;
+}
+
+/// @brief xetpp explicit data conversion with scaling and quantization, float32->int8.
+/// @tparam T_dst is the int8 data type.
+/// @tparam T_src is the float32 data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, int8_t>::value
+                && std::is_same<T_src, float>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src, float scaling_value) {
+    auto dst = xetla_vector<T_dst, N>(
+            xetla_rnde<float>(scaling_value * src), SAT);
+    return dst;
+}
+
+/// @brief xetla explicit data conversion, same type.
+/// @tparam T_dst is the dst data type.
+/// @tparam T_src is the src data type.
+/// @tparam N is the element number in xetla_vector.
+template <typename T_dst, typename T_src, int N>
+__XETLA_API typename std::enable_if_t<std::is_same<T_dst, T_src>::value
+                && is_internal_type<T_src>::value,
+        xetla_vector<T_dst, N>>
+xetla_cvt(xetla_vector<T_src, N> src) {
+    return src;
+}
+
+/// @} xetla_core_conv
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_fma.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_fma.hpp
new file mode 100644
index 00000000000000..098bd1dbd9f589
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_fma.hpp
@@ -0,0 +1,35 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_math
+/// @{
+
+/// @} xetla_core_math
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_general.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_general.hpp
new file mode 100644
index 00000000000000..1c0fb305a6be04
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_general.hpp
@@ -0,0 +1,624 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_math
+/// @{
+
+/// Get absolute value (vector version)
+/// @tparam T0 element type of the returned vector.
+/// @tparam T1 element type of the input vector.
+/// @tparam SZ size of the input and returned vector.
+/// @param src0 the input vector.
+/// @return vector of absolute values.
+template <typename T0, typename T1, int SZ>
+__XETLA_API xetla_vector<T0, SZ> xetla_abs(xetla_vector<T1, SZ> src0) {
+    static_assert(!(is_internal_type<T0>::value || is_internal_type<T1>::value),
+            "The internal types are not yet supported!");
+    return cm_abs<T0, T1, SZ>(src0);
+}
+
+/// Get absolute value (scalar version)
+/// @tparam T0 element type of the returned value.
+/// @tparam T1 element type of the input value.
+/// @param src0 the source operand.
+/// @return absolute value.
+template <typename T0, typename T1>
+std::enable_if_t<!std::is_same<remove_const_t<T0>, remove_const_t<T1>>::value,
+        remove_const_t<T0>>
+        __XETLA_API xetla_abs(T1 src0) {
+    static_assert(!(is_internal_type<T0>::value || is_internal_type<T1>::value),
+            "The internal types are not yet supported!");
+    return cm_abs<T0, T1>(src0);
+}
+
+/// Get absolute value (vector version). This is a specialization of a version
+/// with three template parameters, where the element types of the input and
+/// output vector are the same.
+/// @tparam T1 element type of the input and output vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @return vector of absolute values.
+template <typename T1, int SZ>
+__XETLA_API xetla_vector<T1, SZ> xetla_abs(xetla_vector<T1, SZ> src0) {
+    static_assert(!(is_internal_type<T1>::value),
+            "The internal types are not yet supported!");
+    return cm_abs<T1, SZ>(src0);
+}
+
+/// Get absolute value (scalar version). This is a specialization of a version
+/// with two template parameters, where the types of the input and output value
+/// are the same.
+/// @tparam T1 element type of the input and output value.
+/// @param src0 the source operand.
+/// @return absolute value.
+template <typename T1>
+__XETLA_API typename std::remove_const<T1>::type xetla_abs(T1 src0) {
+    static_assert(!(is_internal_type<T1>::value),
+            "The internal types are not yet supported!");
+    return cm_abs<T1>(src0);
+}
+
+/// Selects component-wise the maximum of the two vectors.
+/// The source operands must be both of integer or both of floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise maximum elements.
+
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_max(
+        xetla_vector<T, SZ> src0, xetla_vector<T, SZ> src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_max<T, T, SZ, xetla_vector<T, SZ>>(src0, src1, Sat::value);
+}
+
+/// Selects maximums for each element of the input vector and a scalar.
+/// The source operands must be both of integer or both of
+/// floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the scalar value.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise maximum elements.
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_max(
+        xetla_vector<T, SZ> src0, T src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_max<T, T, SZ, T>(src0, src1, Sat::value);
+}
+
+/// Selects maximums for each element of the input scalar and a vector.
+/// The source operands must be both of integer or both of
+/// floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the scalar value.
+/// @param src1 the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise maximum elements.
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_max(
+        T src0, xetla_vector<T, SZ> src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_max<T, T, xetla_vector<T, SZ>>(src0, src1, Sat::value);
+}
+
+/// Selects maximum between two scalar values.
+/// The source operands must be both of integer or both of floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @param src0 the scalar value.
+/// @param src1 the scalar value.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return maximum value between the two inputs.
+template <typename T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_max(T src0, T src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_max<T, T, T>(src0, src1, Sat::value);
+}
+
+/// Selects component-wise the minimum of the two vectors.
+/// The source operands must be both of integer or both of floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise minimum elements.
+
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_min(
+        xetla_vector<T, SZ> src0, xetla_vector<T, SZ> src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_min<T, T, SZ, xetla_vector<T, SZ>>(src0, src1, Sat::value);
+}
+
+/// Selects minimums for each element of the input vector and a scalar.
+/// The source operands must be both of integer or both of
+/// floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the scalar value.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise minimum elements.
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_min(
+        xetla_vector<T, SZ> src0, T src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_min<T, T, SZ, T>(src0, src1, Sat::value);
+}
+
+/// Selects minimums for each element of the input scalar and a vector.
+/// The source operands must be both of integer or both of
+/// floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the scalar value.
+/// @param src1 the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise minimum elements.
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_min(
+        T src0, xetla_vector<T, SZ> src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_min<T, T, xetla_vector<T, SZ>>(src0, src1, Sat::value);
+}
+
+/// Selects minimum between two scalar values.
+/// The source operands must be both of integer or both of floating-point type.
+/// @tparam T element type of the input and return vectors.
+/// @param src0 the scalar value.
+/// @param src1 the scalar value.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return minimum value between the two inputs.
+template <typename T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_min(T src0, T src1, Sat sat = {}) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_min<T, T, T>(src0, src1, Sat::value);
+}
+
+/// @brief Calculate exponent value for each element of the input vector, the base is e.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise exponent elements.
+template <class T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_exp(
+        xetla_vector<T, SZ> src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    constexpr float log2e = 1.442695f;
+    return cm_exp<SZ>(xetla_vector<T, SZ>(src * log2e), Sat::value);
+}
+
+/// @brief Calculate exponent value of a scalar, the base is e.
+/// @tparam T element type of the input and return a scalar.
+/// @param src the scalar value.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return exponent value.
+template <class T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_exp(T src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    constexpr float log2e = 1.442695f;
+    return cm_exp(T(src * log2e), Sat::value);
+}
+
+/// @brief Calculate exponent value for each element of the input vector, the base is 2.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise exponent elements.
+template <class T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_exp2(
+        xetla_vector<T, SZ> src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_exp<SZ>(src, Sat::value);
+}
+
+/// @brief Calculate exponent value of a scalar, the base is 2.
+/// @tparam T element type of the input and return a scalar.
+/// @param src the scalar value.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return exponent value.
+template <class T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_exp2(T src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_exp(src, Sat::value);
+}
+
+/// @brief Calculate the inversion, i.e. 1/x (vector version).
+/// @tparam T Is the element data type
+/// @tparam SZ Is the element num in the vector
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of 1/x
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_inv(
+        xetla_vector<T, SZ> src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_inv(src, Sat::value);
+}
+
+/// @brief Calculate the inversion, i.e. 1/x (scalar version).
+/// @tparam T Is the element data type
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input scalar.
+/// @return Returns the result of 1/x
+template <typename T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_inv(T src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_inv(src, Sat::value);
+}
+
+/// @brief Calculate the square root, i.e. x^(1/2), this is not IEEE754-compatible (vector version).
+/// @tparam T Is the element data type
+/// @tparam SZ Is the element num in the vector
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of x^(1/2)
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_sqrt(
+        xetla_vector<T, SZ> src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_sqrt(src, Sat::value);
+}
+
+/// @brief Calculate the square root, i.e. x^(1/2), this is not IEEE754-compatible (scalar version).
+/// @tparam T Is the element data type
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of x^(1/2)
+template <typename T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_sqrt(T src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_sqrt(src, Sat::value);
+}
+
+/// @brief Calculate the square root, i.e. x^(1/2), IEEE754-compatible (vector version).
+/// @tparam T Is the element data type
+/// @tparam SZ Is the element num in the vector
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of x^(1/2)
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_sqrt_ieee(
+        xetla_vector<T, SZ> src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, double>::value),
+            "Only support fp32 and fp16");
+    return cm_sqrt_ieee(src, Sat::value);
+}
+
+/// @brief Calculate the square root, i.e. x^(1/2), IEEE754-compatible (scalar version).
+/// @tparam T Is the element data type
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of x^(1/2)
+template <typename T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_sqrt_ieee(T src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, double>::value),
+            "Only support fp32 and fp16");
+    return cm_sqrt_ieee(src, Sat::value);
+}
+
+/// @brief Calculate the inversion of square root, i.e. 1/sqrt(x) (vector version).
+/// @tparam T Is the element data type
+/// @tparam SZ Is the element num in the vector
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of 1/sqrt(x)
+template <typename T, int SZ, typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, SZ> xetla_rsqrt(
+        xetla_vector<T, SZ> src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_rsqrt(src, Sat::value);
+}
+
+/// @brief Calculate the inversion of square root, i.e. 1/sqrt(x) (scalar version).
+/// @tparam T Is the element data type
+/// @tparam Sat Is the saturation flag(off by default). Possible values: saturation_on/saturation_off.
+/// @param src Is the input vector.
+/// @return Returns the result of 1/sqrt(x)
+template <typename T, typename Sat = xetla_saturation_off_tag>
+__XETLA_API T xetla_rsqrt(T src, Sat sat = {}) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    return cm_rsqrt(src, Sat::value);
+}
+
+/// @brief Calculate the tanh (vector version).
+/// @tparam T Is the element data type
+/// @tparam SZ Is the element num in the vector
+/// @param src Is the input vector.
+/// @return Returns the result of tanh(x)
+template <typename T, int SZ>
+__XETLA_API xetla_vector<T, SZ> xetla_tanh(xetla_vector<T, SZ> src) {
+    static_assert(std::is_same<remove_const_t<T>, float>::value,
+            "Only support fp32! ");
+    constexpr uint32_t flag_elems = 8 * 16;
+    xetla_vector<T, SZ> ret;
+#pragma unroll
+    for (int i = 0; i < SZ / flag_elems; i++) {
+        auto src_sub = src.xetla_select<flag_elems, 1>(i * flag_elems);
+        auto ret_sub = ret.xetla_select<flag_elems, 1>(i * flag_elems);
+        xetla_mask<flag_elems> mask = src_sub >= 10;
+        xetla_vector<T, flag_elems> exp2x
+                = xetla_exp<T, flag_elems>(src_sub * 2.f);
+        ret_sub = (exp2x - 1.f) / (exp2x + 1.f);
+        xetla_vector<T, flag_elems> ones(1);
+        ret_sub.xetla_merge(ones, mask);
+    }
+    if constexpr (SZ % flag_elems != 0) {
+        constexpr uint32_t start_pos = SZ / flag_elems * flag_elems;
+        constexpr uint32_t remain_elems = SZ % flag_elems;
+
+        auto src_sub = src.xetla_select<remain_elems, 1>(start_pos);
+        auto ret_sub = ret.xetla_select<remain_elems, 1>(start_pos);
+        xetla_mask<remain_elems> mask = src_sub >= 10;
+        xetla_vector<T, remain_elems> exp2x
+                = xetla_exp<T, remain_elems>(src_sub * 2.f);
+        ret_sub = (exp2x - 1.f) / (exp2x + 1.f);
+        xetla_vector<T, remain_elems> ones(1);
+        ret_sub.xetla_merge(ones, mask);
+    }
+
+    return ret;
+}
+
+/// @brief Calculate the tanh (scalar version).
+/// @tparam T Is the element data type
+/// @tparam SZ Is the element num in the vector
+/// @param src Is the input vector.
+/// @return Returns the result of tanh(x)
+template <typename T>
+__XETLA_API T xetla_tanh(T src) {
+    static_assert(std::is_same<remove_const_t<T>, float>::value,
+            "Only support fp32! ");
+    T exp2x = xetla_exp<T>(src * 2.f);
+    T ret = (exp2x - 1.f) / (exp2x + 1.f);
+    return (src >= 10) ? 1 : ret;
+}
+
+/// @brief Calculate sigmoid value for each element of the input vector.
+/// @tparam T element type of the input and return vectors.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src the input vector.
+/// @return vector of sigmoid of component-wise elements.
+template <typename T, int SZ>
+__XETLA_API xetla_vector<T, SZ> xetla_sigmoid(xetla_vector<T, SZ> src) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    xetla_mask<SZ> mask = src <= -10;
+    xetla_vector<T, SZ> exp = xetla_exp<T, SZ>(-src);
+    xetla_vector<T, SZ> ret_sub = 1.f / (exp + 1.f);
+    ret_sub.xetla_merge(0, mask);
+
+    return ret_sub;
+}
+
+/// @brief Calculate sigmoid of a scalar.
+/// @tparam T element type of the input and return a scalar.
+/// @param src the scalar value.
+/// @return sigmoid value.
+template <typename T>
+__XETLA_API T xetla_sigmoid(T src) {
+    static_assert((std::is_same<remove_const_t<T>, float>::value)
+                    || (std::is_same<remove_const_t<T>, fp16>::value),
+            "Only support fp32 and fp16");
+    T exp = xetla_exp<T>(-src);
+    T ret = 1.f / (exp + 1.f);
+    return (src <= -10) ? 0 : ret;
+}
+
+/// Add two unsigned integer vectors, return the result and in-place update the carry.
+/// @tparam T element type of the src, should be uint32_t.
+/// @tparam SZ element num of the vector.
+/// @param src0 is the src0 of the add operation.
+/// @param src1 is the src1 of the add operation.
+/// @param carry is the carry of the add operation.
+/// @return result of the src0 + src1.
+template <typename T, int SZ>
+__XETLA_API xetla_vector<T, SZ> xetla_add_c(xetla_vector<T, SZ> src0,
+        xetla_vector<T, SZ> src1, xetla_vector_ref<T, SZ> __REF__ carry) {
+    static_assert((std::is_same<remove_const_t<T>, uint32_t>::value),
+            "For addc, only uint32_t is supported");
+    return cm_addc(src0, src1, carry);
+}
+
+/// Add one unsigned integer vectors with a scalar, return the result and in-place update the carry.
+/// @tparam T element type of the src, should be uint32_t.
+/// @tparam SZ element num of the vector.
+/// @param src0 is the src0 of the add operation.
+/// @param src1 is the src1 of the add operation.
+/// @param carry is the carry of the add operation.
+/// @return result of the src0 + src1.
+template <typename T, int SZ>
+__XETLA_API xetla_vector<T, SZ> xetla_add_c(xetla_vector<T, SZ> src0, T src1,
+        xetla_vector_ref<T, SZ> __REF__ carry) {
+    static_assert((std::is_same<remove_const_t<T>, uint32_t>::value),
+            "For addc, only uint32_t is supported");
+    return cm_addc(src0, src1, carry);
+}
+
+/// @brief Multiply src0 with src1, return the hi part and in-place update the lo part.
+/// @tparam T0 Return data type, should be 32 bit integer.
+/// @tparam T1 Type of src0, should be 32 bit integer.
+/// @tparam T2 Type of src1, should be 32 bit integer.
+/// @tparam SZ Element num of the vector.
+/// @param lo is the low 32 bit part of the result.
+/// @param src0 is the src0 of the mul operation.
+/// @param src1 is the src1 of the mul operation.
+/// @return return the high 32 bit part of the result.
+template <typename T0, typename T1, typename T2, int SZ>
+__XETLA_API xetla_vector<T0, SZ> xetla_imul(xetla_vector_ref<T0, SZ> __REF__ lo,
+        xetla_vector<T1, SZ> src0, T2 src1) {
+    return cm_imul(lo, src0, src1);
+}
+
+/// Performs reduction over elements of the input vector.
+/// @tparam T0 type of the return value.
+/// @tparam T1 element type of the input vector.
+/// @tparam SZ size of the input vector.
+/// @tparam BinaryOperation type representing the operation. Can be an
+///   instantion of one of the following types:
+///   \li \c reduce_op::sum, performs reduce sum operation
+///   \li \c reduce_op::prod, performs reduce prod operation
+///   \li \c reduce_op::min, performs reduce min operation
+///   \li \c reduce_op::max, performs reduce max operation
+/// @param v the vector to perform reduction on
+/// @return result of the reduction
+template <typename T0, typename T1, int SZ, reduce_op BinaryOperation>
+__XETLA_API T0 xetla_reduce(xetla_vector<T1, SZ> v) {
+    if constexpr (BinaryOperation == reduce_op::sum) {
+        return cm_sum<T0, T1, SZ>(v);
+    } else if constexpr (BinaryOperation == reduce_op::prod) {
+        return cm_prod<T0, T1, SZ>(v);
+    } else if constexpr (BinaryOperation == reduce_op::min) {
+        return cm_reduced_min<T0, T1, SZ>(v);
+    } else if constexpr (BinaryOperation == reduce_op::max) {
+        return cm_reduced_max<T0, T1, SZ>(v);
+    }
+}
+
+/// Get rounded value
+/// @tparam T element type of the input vector.
+/// @tparam SZ size of the input and returned vector.
+/// @param src0 the input vector.
+/// @return vector of rounded values.
+template <typename T, int SZ>
+__XETLA_API xetla_vector<T, SZ> xetla_rnde(xetla_vector<T, SZ> src0) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_rnde<T, SZ>(src0);
+}
+
+/// Adds two vectors with saturation
+/// The source operands must be  both of floating-point type.
+/// @tparam T0 element type of the input vectors.
+/// @tparam T1 element type of the return vector.
+/// @tparam SZ size of the input and returned vectors.
+/// @param src0 the input vector.
+/// @param src1 the input vector.
+/// @param sat enables/disables the saturation (off by default). Possible
+/// values: saturation_on/saturation_off.
+/// @return vector of component-wise additive elements.
+template <typename T1, typename T0, int SZ,
+        typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T1, SZ> xetla_add(
+        xetla_vector<T0, SZ> src0, xetla_vector<T0, SZ> src1, Sat sat = {}) {
+    static_assert(
+            !((is_internal_type<T0>::value) || (is_internal_type<T1>::value)),
+            "The internal types are not yet supported!");
+    return cm_add<T1>(src0, src1, sat.value);
+}
+
+/// Saturation function.
+/// @tparam T0 element type of the input vectors.
+/// @tparam T1 element type of the return vector.
+/// @tparam SZ size of the input and returned vectors.
+template <typename T1, typename T0, int SZ>
+__XETLA_API xetla_vector<T1, SZ> xetla_sat(xetla_vector<T0, SZ> src) {
+    static_assert(
+            !((is_internal_type<T0>::value) || (is_internal_type<T1>::value)),
+            "The internal types are not yet supported!");
+    return xetla_vector<T1, SZ>(src, SAT);
+}
+
+/// Count number of bits set in the source operand per element.
+/// @param src0 the source operand to count bits in.
+/// @return a vector of \c uint32_t, where each element is set to bit count of
+///     the corresponding element of the source operand.
+template <typename T, int N>
+__XETLA_API std::enable_if_t<std::is_integral<T>::value && (sizeof(T) <= 4),
+        xetla_vector<uint32_t, N>>
+xetla_cbit(xetla_vector<T, N> src) {
+    return cm_cbit<T, N>(src);
+}
+
+/// Scalar version of \c cbit - both input and output are scalars rather
+/// than vectors.
+template <typename T>
+__XETLA_API std::enable_if_t<std::is_integral<T>::value && (sizeof(T) <= 4),
+        uint32_t>
+xetla_cbit(T src) {
+    return cm_cbit<T>(src);
+}
+
+/// @} xetla_core_math
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_mma.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_mma.hpp
new file mode 100644
index 00000000000000..601620f83de8c6
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/math_mma.hpp
@@ -0,0 +1,147 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+namespace detail {
+
+///
+///@brief convert normal data type to dpas argument type
+///
+///
+template <typename dtype>
+constexpr gpu::xetla::argument_type mma_argument_type() {
+    return gpu::xetla::argument_type::U2;
+}
+
+template <>
+constexpr gpu::xetla::argument_type mma_argument_type<tf32>() {
+    return gpu::xetla::argument_type::TF32;
+}
+
+template <>
+constexpr gpu::xetla::argument_type mma_argument_type<float>() {
+    return gpu::xetla::argument_type::TF32;
+}
+
+template <>
+constexpr gpu::xetla::argument_type mma_argument_type<int8_t>() {
+    return gpu::xetla::argument_type::S8;
+}
+
+template <>
+constexpr gpu::xetla::argument_type mma_argument_type<uint8_t>() {
+    return gpu::xetla::argument_type::U8;
+}
+
+template <>
+constexpr gpu::xetla::argument_type mma_argument_type<bf16>() {
+    return gpu::xetla::argument_type::BF16;
+}
+
+template <>
+constexpr gpu::xetla::argument_type mma_argument_type<fp16>() {
+    return gpu::xetla::argument_type::FP16;
+}
+
+/// @brief lookup table for dpas argument type
+///
+///
+template <gpu::xetla::argument_type arg_type>
+constexpr CmPrecisionType get_argument_type() {
+    static_assert(arg_type == gpu::xetla::argument_type::U2
+                    || arg_type == gpu::xetla::argument_type::S2
+                    || arg_type == gpu::xetla::argument_type::U4
+                    || arg_type == gpu::xetla::argument_type::S4
+                    || arg_type == gpu::xetla::argument_type::U8
+                    || arg_type == gpu::xetla::argument_type::S8
+                    || arg_type == gpu::xetla::argument_type::FP16
+                    || arg_type == gpu::xetla::argument_type::BF16
+                    || arg_type == gpu::xetla::argument_type::TF32,
+            "Unsupported argument type");
+    switch (arg_type) {
+        case gpu::xetla::argument_type::U2:
+            return CmPrecisionType::CM_Precision_U2;
+        case gpu::xetla::argument_type::S2:
+            return CmPrecisionType::CM_Precision_S2;
+        case gpu::xetla::argument_type::U4:
+            return CmPrecisionType::CM_Precision_U4;
+        case gpu::xetla::argument_type::S4:
+            return CmPrecisionType::CM_Precision_S4;
+        case gpu::xetla::argument_type::U8:
+            return CmPrecisionType::CM_Precision_U8;
+        case gpu::xetla::argument_type::S8:
+            return CmPrecisionType::CM_Precision_S8;
+        case gpu::xetla::argument_type::BF16:
+            return CmPrecisionType::CM_Precision_BF16;
+        case gpu::xetla::argument_type::FP16:
+            return CmPrecisionType::CM_Precision_FP16;
+        case gpu::xetla::argument_type::TF32:
+            return CmPrecisionType::CM_Precision_TF32;
+        default:;
+    }
+}
+} // namespace detail
+
+/// @addtogroup xetla_core_math
+/// @{
+
+///
+///@brief description of xetla mma
+/// perform matrix multiply add operation
+///@tparam src1_precision is the data precision of src1
+///@tparam src2_precision is the data precision of src2
+///@tparam systolic_depth is the depth of mma (i.e k dimension size in dword)
+///@tparam repeat_count is the row (m) of mma (mxkxn)
+///@tparam T is the data type of src0 and dst
+///@tparam T1 is the data type of src1
+///@tparam T2 is the data type of src2
+///@tparam N is the total number of elements in src0 and dst
+///@tparam N1 is the total number of elements in src1
+///@tparam N2 is the total number of elements in src2
+///@tparam Sat is saturation flag
+///@param src0 [in] is src0
+///@param src1 [in] is src1
+///@param src2 [in] is src2
+///@param sat  [in] is saturation flag
+///@return is dst, a xetla_vector of  type T and element size of N
+///
+
+/// todo: we need to remove argument_type and get the currect precision based on data type
+template <argument_type src1_precision, argument_type src2_precision,
+        int systolic_depth, int repeat_count, typename T, typename T1,
+        typename T2, int N, int N1, int N2,
+        typename Sat = xetla_saturation_off_tag>
+__XETLA_API xetla_vector<T, N> xetla_mma(xetla_vector<T, N> src0,
+        xetla_vector<T1, N1> src1, xetla_vector<T2, N2> src2, Sat sat = {}) {
+    return cm_dpas<detail::get_argument_type<src1_precision>(),
+            detail::get_argument_type<src2_precision>(), systolic_depth,
+            repeat_count>(src0, src1, src2, Sat::value);
+}
+
+/// @} xetla_core_math
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/memory.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/memory.hpp
new file mode 100644
index 00000000000000..e405cc2848b88e
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/memory.hpp
@@ -0,0 +1,605 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#include "../../../common/utils/cm/limitation.hpp"
+
+#else
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#include "common/utils/cm/limitation.hpp"
+#endif
+
+namespace gpu::xetla {
+
+namespace detail {
+
+/// @brief lookup table for cache hint.
+///
+///
+constexpr CacheHint get_cache_hint(gpu::xetla::cache_hint ch) {
+    switch (ch) {
+        case gpu::xetla::cache_hint::none: return CacheHint::Default;
+        case gpu::xetla::cache_hint::uncached: return CacheHint::Uncached;
+        case gpu::xetla::cache_hint::cached: return CacheHint::Cached;
+        case gpu::xetla::cache_hint::write_back: return CacheHint::WriteBack;
+        case gpu::xetla::cache_hint::write_through:
+            return CacheHint::WriteThrough;
+        case gpu::xetla::cache_hint::streaming: return CacheHint::Streaming;
+        case gpu::xetla::cache_hint::read_invalidate:
+            return CacheHint::ReadInvalidate;
+    }
+}
+
+/// @brief lookup table for data size.
+///
+///
+constexpr DataSize get_data_size(gpu::xetla::data_size ds) {
+    switch (ds) {
+        case gpu::xetla::data_size::default_size: return DataSize::Default;
+        case gpu::xetla::data_size::u8: return DataSize::U8;
+        case gpu::xetla::data_size::u16: return DataSize::U16;
+        case gpu::xetla::data_size::u32: return DataSize::U32;
+        case gpu::xetla::data_size::u64: return DataSize::U64;
+        case gpu::xetla::data_size::u8u32: return DataSize::U8U32;
+        case gpu::xetla::data_size::u16u32: return DataSize::U16U32;
+        case gpu::xetla::data_size::u16u32h: return DataSize::U16U32H;
+    }
+}
+
+/// @brief lookup table for memory kind.
+///
+///
+constexpr LSC_SFID get_memory_kind(gpu::xetla::memory_kind mk) {
+    switch (mk) {
+        case gpu::xetla::memory_kind::untyped_global: return LSC_SFID::LSC_UGM;
+        case gpu::xetla::memory_kind::untyped_global_low_pri:
+            return LSC_SFID::LSC_UGML;
+        case gpu::xetla::memory_kind::typed_global: return LSC_SFID::LSC_TGM;
+        case gpu::xetla::memory_kind::shared_local: return LSC_SFID::LSC_SLM;
+    }
+}
+
+/// @brief lookup table for fence op.
+///
+///
+constexpr LSC_FENCE_OP get_fence_op(gpu::xetla::fence_op fo) {
+    switch (fo) {
+        case gpu::xetla::fence_op::none: return LSC_FENCE_OP::LSC_FENCE_OP_NONE;
+        case gpu::xetla::fence_op::evict:
+            return LSC_FENCE_OP::LSC_FENCE_OP_EVICT;
+        case gpu::xetla::fence_op::invalidate:
+            return LSC_FENCE_OP::LSC_FENCE_OP_INVALIDATE;
+        case gpu::xetla::fence_op::discard:
+            return LSC_FENCE_OP::LSC_FENCE_OP_DISCARD;
+        case gpu::xetla::fence_op::clean:
+            return LSC_FENCE_OP::LSC_FENCE_OP_CLEAN;
+        case gpu::xetla::fence_op::flushl2:
+            return LSC_FENCE_OP::LSC_FENCE_OP_FLUSHL3;
+    }
+}
+
+/// @brief lookup table for fence scope.
+///
+///
+constexpr LSC_SCOPE get_fence_scope(gpu::xetla::fence_scope fs) {
+    switch (fs) {
+        case gpu::xetla::fence_scope::group: return LSC_SCOPE::LSC_SCOPE_GROUP;
+        case gpu::xetla::fence_scope::local: return LSC_SCOPE::LSC_SCOPE_LOCAL;
+        case gpu::xetla::fence_scope::tile: return LSC_SCOPE::LSC_SCOPE_TILE;
+        case gpu::xetla::fence_scope::gpu: return LSC_SCOPE::LSC_SCOPE_GPU;
+        case gpu::xetla::fence_scope::gpus: return LSC_SCOPE::LSC_SCOPE_GPUS;
+        case gpu::xetla::fence_scope::system:
+            return LSC_SCOPE::LSC_SCOPE_SYSTEM;
+        case gpu::xetla::fence_scope::sysacq:
+            return LSC_SCOPE::LSC_SCOPE_SYSACQ;
+    }
+}
+
+/// @brief lookup table for atomic op.
+///
+///
+constexpr AtomicOp get_atomic_op(gpu::xetla::atomic_op ao) {
+    switch (ao) {
+        case gpu::xetla::atomic_op::iinc: return AtomicOp::IINC;
+        case gpu::xetla::atomic_op::idec: return AtomicOp::IDEC;
+        case gpu::xetla::atomic_op::iadd: return AtomicOp::IADD;
+        case gpu::xetla::atomic_op::isub: return AtomicOp::ISUB;
+        case gpu::xetla::atomic_op::smin: return AtomicOp::SMIN;
+        case gpu::xetla::atomic_op::smax: return AtomicOp::SMAX;
+        case gpu::xetla::atomic_op::cmpxchg: return AtomicOp::ICAS;
+        case gpu::xetla::atomic_op::fadd: return AtomicOp::FADD;
+        case gpu::xetla::atomic_op::fsub: return AtomicOp::FSUB;
+        case gpu::xetla::atomic_op::fmin: return AtomicOp::FMIN;
+        case gpu::xetla::atomic_op::fmax: return AtomicOp::FMAX;
+        case gpu::xetla::atomic_op::fcmpxchg: return AtomicOp::FCAS;
+        case gpu::xetla::atomic_op::umin: return AtomicOp::UMIN;
+        case gpu::xetla::atomic_op::umax: return AtomicOp::UMAX;
+        case gpu::xetla::atomic_op::bit_and: return AtomicOp::AND;
+        case gpu::xetla::atomic_op::bit_or: return AtomicOp::OR;
+        case gpu::xetla::atomic_op::bit_xor: return AtomicOp::XOR;
+        case gpu::xetla::atomic_op::load: return AtomicOp::LOAD;
+        case gpu::xetla::atomic_op::store: return AtomicOp::STORE;
+        default: return AtomicOp::STORE;
+    }
+}
+} // namespace detail
+
+/// @addtogroup xetla_core_memory
+/// @{
+
+/// @brief Stateless scattered prefetch.
+/// Prefetches elements located at specified address.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_load.ugm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to prefetch per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @param p       [in] is the base pointer.
+/// @param offsets [in] is the zero-based offsets in bytes.
+/// @param pred    [in] is predicates.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::cached,
+        cache_hint L2H = cache_hint::cached, int N>
+__XETLA_API void xetla_prefetch_global(
+        Ty *p, xetla_vector<uint32_t, N> offsets, xetla_mask<N> pred = 1) {
+    using T = native_type_t<Ty>;
+    constexpr DataSize _DS = details::lsc_expand_ds(
+            details::lsc_data_size<T, gpu::xetla::detail::get_data_size(DS)>());
+    cm_ptr_prefetch<details::lsc_vector_size<NElts>(), _DS,
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H), N>(
+            (const unsigned *const)p, offsets, pred);
+}
+
+/// @brief Stateless block prefetch (transposed gather with 1 channel).
+/// Prefetches elements located at specified address.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_load.ugm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to prefetch per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param p      [in] is the base pointer.
+/// @param offset [in] is the zero-based offset in bytes.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::cached,
+        cache_hint L2H = cache_hint::cached>
+__XETLA_API void xetla_prefetch_global(Ty *p, uint64_t offset = 0) {
+    using T = native_type_t<Ty>;
+    constexpr DataSize _DS = details::lsc_expand_ds(
+            details::lsc_data_size<T, gpu::xetla::detail::get_data_size(DS)>());
+    cm_ptr_prefetch<NElts, _DS, gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H)>(
+            (const unsigned *const)p, offset);
+}
+
+/// @brief Stateless scattered load.
+/// Collects elements located at specified address and returns them
+/// to a single \ref xetla_vector object.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_load.ugm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to load per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @param p       [in] is the base pointer.
+/// @param offsets [in] is the zero-based offsets in bytes.
+/// @param pred    [in] is predicates.
+/// @return  is a xetla_vector of type T and size N * NElts.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none,
+        int N, typename Toffset = uint32_t>
+__XETLA_API xetla_vector<Ty, N * NElts> xetla_load_global(
+        Ty *p, xetla_vector<Toffset, N> offsets, xetla_mask<N> pred = 1) {
+    using T = native_type_t<Ty>;
+    return cm_ptr_load<T, details::lsc_vector_size<NElts>(),
+            gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H), N>((T *)p, offsets, pred);
+}
+
+/// @brief Stateless block load (transposed gather with 1 channel).
+/// Collects elements located at specified address and returns them
+/// to a single \ref xetla_vector object.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_load.ugm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to load per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param p      [in] is the base pointer.
+/// @param offset [in] is the zero-based offset in bytes.
+/// @return is a xetla_vector of type T and size NElts.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none>
+__XETLA_API xetla_vector<Ty, NElts> xetla_load_global(
+        Ty *p, uint64_t offset = 0) {
+    using T = native_type_t<Ty>;
+    return cm_ptr_load<T, NElts, gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H)>((T *)p, offset);
+}
+
+/// @brief Stateless scattered store.
+/// Writes elements to specific address.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_store.ugm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to store per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @param p       [in] is the base pointer.
+/// @param offsets [in] is the zero-based offsets in bytes.
+/// @param vals    [in] is values to store.
+/// @param pred    [in] is predicates.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none,
+        int N>
+__XETLA_API void xetla_store_global(Ty *p, xetla_vector<uint32_t, N> offsets,
+        xetla_vector<Ty, N * NElts> vals, xetla_mask<N> pred = 1) {
+    using T = native_type_t<Ty>;
+    cm_ptr_store<T, details::lsc_vector_size<NElts>(),
+            gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H), N>(
+            (T *)p, offsets, vals, pred);
+}
+
+/// @brief Stateless block store (transposed scatter with 1 channel).
+/// Writes elements to specific address.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_store.ugm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to store per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param p      [in] is the base pointer.
+/// @param offset [in] is the zero-based offset in bytes.
+/// @param vals   [in] is values to store.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none>
+__XETLA_API void xetla_store_global(
+        Ty *p, uint64_t offset, xetla_vector<Ty, NElts> vals) {
+    using T = native_type_t<Ty>;
+    cm_ptr_store<T, NElts, gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H)>((T *)p, offset, vals);
+}
+
+/// @brief Stateless scattered atomic (0 src).
+/// Supported platforms: DG2, PVC
+/// VISA instruction: lsc_atomic_<OP>.ugm
+///
+/// @tparam Op is operation type.
+/// @tparam T is element type.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param p       [in] is the base pointer.
+/// @param offsets [in] is the zero-based offsets.
+/// @param pred    [in] is predicates.
+///
+template <atomic_op Op, typename T, int N,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none>
+__XETLA_API xetla_vector<T, N> xetla_atomic_global(
+        T *p, xetla_vector<uint32_t, N> offsets, xetla_mask<N> pred) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_ptr_atomic<gpu::xetla::detail::get_atomic_op(Op), T,
+            VectorSize::N1, gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H)>(p, offsets, pred);
+}
+
+/// @brief Stateless scattered atomic (1 src).
+/// Supported platforms: DG2, PVC
+/// VISA instruction: lsc_atomic_<OP>.ugm
+///
+/// @tparam Op is operation type.
+/// @tparam T is element type.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param p       [in] is the base pointer.
+/// @param offsets [in] is the zero-based offsets.
+/// @param src0    [in] is the first atomic operand.
+/// @param pred    [in] is predicates.
+///
+template <atomic_op Op, typename T, int N,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none>
+__XETLA_API xetla_vector<T, N> xetla_atomic_global(T *p,
+        xetla_vector<uint32_t, N> offsets, xetla_vector<T, N> src0,
+        xetla_mask<N> pred) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_ptr_atomic<gpu::xetla::detail::get_atomic_op(Op), T,
+            VectorSize::N1, gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H)>(p, offsets, src0, pred);
+}
+
+/// @brief Stateless scattered atomic (2 src).
+/// Supported platforms: DG2, PVC
+/// VISA instruction: lsc_atomic_<OP>.ugm
+///
+/// @tparam Op is operation type.
+/// @tparam T is element type.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @tparam DS is the data size.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param p       [in] is the base pointer.
+/// @param offsets [in] is the zero-based offsets.
+/// @param src0    [in] is the first atomic operand.
+/// @param src1    [in] is the second atomic operand.
+/// @param pred    [in] is predicates.
+///
+template <atomic_op Op, typename T, int N,
+        data_size DS = data_size::default_size,
+        cache_hint L1H = cache_hint::none, cache_hint L2H = cache_hint::none>
+__XETLA_API xetla_vector<T, N> xetla_atomic_global(T *p,
+        xetla_vector<uint32_t, N> offsets, xetla_vector<T, N> src0,
+        xetla_vector<T, N> src1, xetla_mask<N> pred) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_ptr_atomic<gpu::xetla::detail::get_atomic_op(Op), T,
+            VectorSize::N1, gpu::xetla::detail::get_data_size(DS),
+            gpu::xetla::detail::get_cache_hint(L1H),
+            gpu::xetla::detail::get_cache_hint(L2H)>(
+            p, offsets, src0, src1, pred);
+}
+/// @brief Declare per-work-group slm size.
+/// @tparam SLMSize  Shared Local Memory (SLM) size (in Bytes).
+template <uint32_t SLMSize>
+__XETLA_API void xetla_local_init() {
+    cm_slm_init(SLMSize);
+}
+
+/// @brief SLM scattered load.
+/// Collects elements located at slm and returns them as a single \ref xetla_vector object.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_load.slm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to load per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @param offsets [in] is the zero-based offsets for SLM buffer in bytes.
+/// @param pred    [in] is predicates.
+/// @return is a xetla_vector of type T and size N * NElts.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size, int N>
+__XETLA_API xetla_vector<Ty, N * NElts> xetla_load_local(
+        xetla_vector<uint32_t, N> offsets, xetla_mask<N> pred = 1) {
+    using T = native_type_t<Ty>;
+    return cm_load_slm<T, details::lsc_vector_size<NElts>(),
+            gpu::xetla::detail::get_data_size(DS), N>(offsets, pred);
+}
+
+/// @brief SLM block load. (transposed gather with 1 channel).
+/// Collects elements located at slm and returns them as a single \ref xetla_vector object.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_load.slm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to load per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @param offset [in] is the zero-based offset for SLM buffer in bytes.
+/// @return is a xetla_vector of type T and size NElts.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size>
+__XETLA_API xetla_vector<Ty, NElts> xetla_load_local(uint32_t offset) {
+    using T = native_type_t<Ty>;
+    return cm_load_slm<T, NElts, gpu::xetla::detail::get_data_size(DS)>(offset);
+}
+
+/// @brief SLM scattered store.
+/// Scatters elements located to slm.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_store.slm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to store per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @param offsets [in] is the zero-based offsets for SLM buffer in bytes.
+/// @param vals    [in] is values to store.
+/// @param pred    [in] is predicates.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size, int N>
+__XETLA_API void xetla_store_local(xetla_vector<uint32_t, N> offsets,
+        xetla_vector<Ty, N * NElts> vals, xetla_mask<N> pred = 1) {
+    using T = native_type_t<Ty>;
+    cm_store_slm<T, details::lsc_vector_size<NElts>(),
+            gpu::xetla::detail::get_data_size(DS), N>(offsets, vals, pred);
+}
+
+/// @brief SLM block store (transposed SLM scatter with 1 channel).
+/// Scatters elements located to slm.
+///
+/// Supported platforms: DG2, PVC
+///
+/// VISA instruction: lsc_store.slm
+///
+/// @tparam Ty is element type.
+/// @tparam NElts is the number of elements to store per address (i.e. vector_size per SIMD channel).
+/// @tparam DS is the data size.
+/// @param offset [in] is the zero-based offset for SLM buffer in bytes.
+/// @param vals   [in] is values to store.
+///
+template <typename Ty, uint8_t NElts = 1,
+        data_size DS = data_size::default_size>
+__XETLA_API void xetla_store_local(
+        uint32_t offset, xetla_vector<Ty, NElts> vals) {
+    using T = native_type_t<Ty>;
+    cm_store_slm<T, NElts, gpu::xetla::detail::get_data_size(DS)>(offset, vals);
+}
+
+/// @brief SLM scattered atomic (0 src).
+/// Supported platforms: DG2, PVC
+/// VISA instruction: lsc_atomic_<OP>.slm
+///
+/// @tparam Op is operation type.
+/// @tparam T is element type.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @tparam DS is the data size.
+/// @param offsets [in] is the zero-based offsets.
+/// @param pred    [in] is predicates.
+///
+template <atomic_op Op, typename T, int N,
+        data_size DS = data_size::default_size>
+__XETLA_API xetla_vector<T, N> xetla_atomic_local(
+        xetla_vector<uint32_t, N> offsets, xetla_mask<N> pred) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_atomic_slm<gpu::xetla::detail::get_atomic_op(Op), T,
+            VectorSize::N1, gpu::xetla::detail::get_data_size(DS),
+            CacheHint::Default, CacheHint::Default, N>(offsets, pred);
+}
+
+/// @brief SLM scattered atomic (1 src).
+/// Supported platforms: DG2, PVC
+/// VISA instruction: lsc_atomic_<OP>.slm
+///
+/// @tparam Op is operation type.
+/// @tparam T is element type.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @tparam DS is the data size.
+/// @param offsets [in] is the zero-based offsets.
+/// @param src0    [in] is the first atomic operand.
+/// @param pred    [in] is predicates.
+///
+template <atomic_op Op, typename T, int N,
+        data_size DS = data_size::default_size>
+__XETLA_API xetla_vector<T, N> xetla_atomic_local(
+        xetla_vector<uint32_t, N> offsets, xetla_vector<T, N> src0,
+        xetla_mask<N> pred) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_atomic_slm<gpu::xetla::detail::get_atomic_op(Op), T,
+            VectorSize::N1, gpu::xetla::detail::get_data_size(DS),
+            CacheHint::Default, CacheHint::Default, N>(offsets, src0, pred);
+}
+
+/// @brief SLM scattered atomic (2 src).
+/// Supported platforms: DG2, PVC
+/// VISA instruction: lsc_atomic_<OP>.slm
+///
+/// @tparam Op is operation type.
+/// @tparam T is element type.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @tparam DS is the data size.
+/// @param offsets [in] is the zero-based offsets.
+/// @param src0    [in] is the first atomic operand.
+/// @param src1    [in] is the second atomic operand.
+/// @param pred    [in] is predicates.
+///
+template <atomic_op Op, typename T, int N,
+        data_size DS = data_size::default_size>
+__XETLA_API xetla_vector<T, N> xetla_atomic_local(
+        xetla_vector<uint32_t, N> offsets, xetla_vector<T, N> src0,
+        xetla_vector<T, N> src1, xetla_mask<N> pred) {
+    static_assert(!(is_internal_type<T>::value),
+            "The internal types are not yet supported!");
+    return cm_atomic_slm<gpu::xetla::detail::get_atomic_op(Op), T,
+            VectorSize::N1, gpu::xetla::detail::get_data_size(DS),
+            CacheHint::Default, CacheHint::Default, N>(
+            offsets, src0, src1, pred);
+}
+
+/// @brief Memory fence.
+/// Supported platforms: DG2, PVC
+///
+/// @tparam Kind is the Sfid shaded function.
+/// @tparam FenceOp is the fence operation.
+/// @tparam Scope is the operation scope.
+/// @tparam N is the number of SIMD channels (platform dependent).
+/// @param pred is predicates.
+template <memory_kind Kind = memory_kind::untyped_global,
+        fence_op FenceOp = fence_op::none,
+        fence_scope Scope = fence_scope::group, int N = 16>
+__XETLA_API void xetla_fence(xetla_mask<N> pred = 1) {
+    cm_fence<gpu::xetla::detail::get_memory_kind(Kind),
+            gpu::xetla::detail::get_fence_op(FenceOp),
+            gpu::xetla::detail::get_fence_scope(Scope), N>();
+}
+
+/// @} xetla_core_memory
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/misc.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/misc.hpp
new file mode 100644
index 00000000000000..1d7e4b4fc5a4d9
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/misc.hpp
@@ -0,0 +1,39 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_misc
+/// @{
+
+/// @} xetla_core_misc
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/raw_send.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/raw_send.hpp
new file mode 100644
index 00000000000000..5b7e6375de56e3
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/cm/raw_send.hpp
@@ -0,0 +1,154 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/base_ops.hpp"
+#include "../../../common/core/cm/base_types.hpp"
+#include "../../../common/core/cm/common.hpp"
+#else
+#include "common/core/cm/base_ops.hpp"
+#include "common/core/cm/base_types.hpp"
+#include "common/core/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_core_raw_send
+/// @{
+
+/// @brief Raw send with one source operand and one destination operand.
+///
+/// @tparam T1 is the data type of the msgDst.
+/// @tparam n1 is the data length of the msgDst.
+/// @tparam T2 is the data type of the msgSrc0.
+/// @tparam n2 is the data length of the msgSrc0.
+/// @tparam execSize is the execution size.
+/// @tparam sfid is the shared function ID.
+/// @tparam numSrc0 is the number of GRFs for source-0.
+/// @tparam numDst is the number of GRFs for destination.
+/// @tparam isEOT is the flag that indicates whether this is an EOT message (optional - default to 0).
+/// @tparam isSendc is the flag that indicates whether sendc should be used (optional - default to 0).
+/// @tparam N is the SIMD channel num of the mask (optional - default to 16).
+/// @param msgDst  [in|out] is the destination operand of the send message.
+/// @param msgSrc0 [in] is the first source operand of the send message.
+/// @param exDesc  [in] is the extended message descriptor.
+/// @param msgDesc [in] is the message descriptor.
+/// @param mask    [in] is the predicate to specify enabled channels (optional - default to on).
+///
+template <typename T1, uint32_t n1, typename T2, uint32_t n2, uint8_t execSize,
+        uint8_t sfid, uint8_t numSrc0, uint8_t numDst, uint8_t isEOT = 0,
+        uint8_t isSendc = 0, int N = 16>
+__XETLA_API void xetla_raw_send(xetla_vector_ref<T1, n1> __REF__ msgDst,
+        xetla_vector<T2, n2> msgSrc0, uint32_t exDesc, uint32_t msgDesc,
+        xetla_mask<N> mask = 1) {
+    cm_raw_send(msgDst, msgSrc0, 0, exDesc, msgDesc, execSize, sfid, numSrc0, 0,
+            numDst, isEOT, isSendc, mask);
+}
+
+/// @brief Raw send with two source operands and one destination operand.
+///
+/// @tparam T1 is the data type of the msgDst.
+/// @tparam n1 is the data length of the msgDst.
+/// @tparam T2 is the data type of the msgSrc0.
+/// @tparam n2 is the data length of the msgSrc0.
+/// @tparam T3 is the data type of the msgSrc1.
+/// @tparam n3 is the data length of the msgSrc1.
+/// @tparam execSize is the execution size.
+/// @tparam sfid is the shared function ID.
+/// @tparam numSrc0 is the number of GRFs for source-0.
+/// @tparam numSrc1 is the number of GRFs for source-1.
+/// @tparam numDst is the number of GRFs for destination.
+/// @tparam isEOT is the flag that indicates whether this is an EOT message (optional - default to 0).
+/// @tparam isSendc is the flag that indicates whether sendc should be used (optional - default to 0).
+/// @tparam N is the SIMD channel num of the mask (optional - default to 16).
+/// @param msgDst  [in|out] is the destination operand of the send message.
+/// @param msgSrc0 [in] is the first source operand of the send message.
+/// @param msgSrc1 [in] is the second source operand of the send message.
+/// @param exDesc  [in] is the extended message descriptor.
+/// @param msgDesc [in] is the message descriptor.
+/// @param mask    [in] is the predicate to specify enabled channels (optional - default to on).
+///
+template <typename T1, uint32_t n1, typename T2, uint32_t n2, typename T3,
+        uint32_t n3, uint8_t execSize, uint8_t sfid, uint8_t numSrc0,
+        uint8_t numSrc1, uint8_t numDst, uint8_t isEOT = 0, uint8_t isSendc = 0,
+        int N = 16>
+__XETLA_API void xetla_raw_send(xetla_vector_ref<T1, n1> __REF__ msgDst,
+        xetla_vector<T2, n2> msgSrc0, xetla_vector<T3, n3> msgSrc1,
+        uint32_t exDesc, uint32_t msgDesc, xetla_mask<N> mask = 1) {
+    cm_raw_send(msgDst, msgSrc0, msgSrc1, exDesc, msgDesc, execSize, sfid,
+            numSrc0, numSrc1, numDst, isEOT, isSendc, mask);
+}
+
+/// @brief Raw send with one source operand and no return.
+///
+/// @tparam T1 is the data type of the msgSrc0.
+/// @tparam n1 is the data length of the msgSrc0.
+/// @tparam execSize is the execution size.
+/// @tparam sfid is the shared function ID.
+/// @tparam numSrc0 is the number of GRFs for source-0.
+/// @tparam isEOT is the flag that indicates whether this is an EOT message (optional - default to 0).
+/// @tparam isSendc is the flag that indicates whether sendc should be used (optional - default to 0).
+/// @tparam N is the SIMD channel num of the mask (optional - default to 16).
+/// @param msgSrc0 [in] is the first source operand of the send message.
+/// @param exDesc  [in] is the extended message descriptor.
+/// @param msgDesc [in] is the message descriptor.
+/// @param mask    [in] is the predicate to specify enabled channels (optional - default to on).
+///
+template <typename T1, uint32_t n1, uint8_t execSize, uint8_t sfid,
+        uint8_t numSrc0, uint8_t isEOT = 0, uint8_t isSendc = 0, int N = 16>
+__XETLA_API void xetla_raw_send(xetla_vector<T1, n1> msgSrc0, uint32_t exDesc,
+        uint32_t msgDesc, xetla_mask<N> mask = 1) {
+    cm_raw_send(0, msgSrc0, 0, exDesc, msgDesc, execSize, sfid, numSrc0, 0, 0,
+            isEOT, isSendc, mask);
+}
+
+/// @brief Raw send with two source operands and no return.
+///
+/// @tparam T1 is the data type of the msgSrc0.
+/// @tparam n1 is the data length of the msgSrc0.
+/// @tparam T2 is the data type of the msgSrc1.
+/// @tparam n2 is the data length of the msgSrc1.
+/// @tparam execSize is the execution size.
+/// @tparam sfid is the shared function ID.
+/// @tparam numSrc0 is the number of GRFs for source-0.
+/// @tparam numSrc1 is the number of GRFs for source-1.
+/// @tparam isEOT is the flag that indicates whether this is an EOT message (optional - default to 0).
+/// @tparam isSendc is the flag that indicates whether sendc should be used (optional - default to 0).
+/// @tparam N is the SIMD channel num of the mask (optional - default to 16).
+/// @param msgSrc0 [in] is the first source operand of the send message.
+/// @param msgSrc1 [in] is the second source operand of the send message.
+/// @param exDesc  [in] is the extended message descriptor.
+/// @param msgDesc [in] is the message descriptor.
+/// @param mask    [in] is the predicate to specify enabled channels (optional - default to on).
+///
+template <typename T1, uint32_t n1, typename T2, uint32_t n2, uint8_t execSize,
+        uint8_t sfid, uint8_t numSrc0, uint8_t numSrc1, uint8_t isEOT = 0,
+        uint8_t isSendc = 0, int N = 16>
+__XETLA_API void xetla_raw_send(xetla_vector<T1, n1> msgSrc0,
+        xetla_vector<T2, n2> msgSrc1, uint32_t exDesc, uint32_t msgDesc,
+        xetla_mask<N> mask = 1) {
+    cm_raw_send(0, msgSrc0, msgSrc1, exDesc, msgDesc, execSize, sfid, numSrc0,
+            numSrc1, 0, isEOT, isSendc, mask);
+}
+
+/// @} xetla_core_raw_send
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/core.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/core.hpp
new file mode 100644
index 00000000000000..9b590ea30543ce
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/core/core.hpp
@@ -0,0 +1 @@
+#include "common/core/cm/core.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/common.hpp
new file mode 100644
index 00000000000000..a4b2478955ad04
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/common.hpp
@@ -0,0 +1,248 @@
+/*******************************************************************************
+ * Copyright (c) 2022-2023 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/core.hpp"
+#else
+#include "common/core/cm/core.hpp"
+#endif
+
+#ifndef XETLA_NO_CM_INCLUDE
+#include <cm/cmtl.h>
+#endif
+
+namespace gpu::xetla {
+namespace detail {
+
+///
+///@brief Get the element size code object
+///
+///@param element_size
+///@return constexpr uint32_t
+///
+template <uint32_t element_size>
+constexpr uint32_t get_element_size_code() {
+    static_assert(element_size == 1 || element_size == 2 || element_size == 4
+                    || element_size == 8,
+            "element_size not supported!");
+    switch (element_size) {
+        case 1: return 0;
+        case 2: return 1;
+        case 4: return 2;
+        case 8: return 3;
+    }
+}
+
+enum class lsc_action { prefetch, load, store, atomic };
+
+template <lsc_action Action, cache_hint L1H, cache_hint L2H, gpu_arch arch_tag>
+constexpr std::enable_if_t<arch_tag == gpu_arch::Xe, void>
+check_lsc_cache_hint() {
+    if constexpr (Action == lsc_action::prefetch) {
+        static_assert(
+                ((L2H == cache_hint::uncached || L2H == cache_hint::cached)
+                        && (L1H == cache_hint::uncached
+                                || L1H == cache_hint::cached
+                                || L1H == cache_hint::streaming)),
+                "cache hint type not supported!");
+    } else if constexpr (Action == lsc_action::load) {
+        static_assert((L1H == cache_hint::none && L2H == cache_hint::none)
+                        || ((L2H == cache_hint::uncached)
+                                && (L1H == cache_hint::uncached
+                                        || L1H == cache_hint::cached
+                                        || L1H == cache_hint::streaming))
+                        || ((L2H == cache_hint::cached)
+                                && (L1H == cache_hint::uncached
+                                        || L1H == cache_hint::cached
+                                        || L1H == cache_hint::streaming
+                                        || L1H == cache_hint::read_invalidate)),
+                "unsupported cache hint!");
+    } else if constexpr (Action == lsc_action::store) {
+        static_assert((L1H == cache_hint::none && L2H == cache_hint::none)
+                        || ((L2H == cache_hint::uncached)
+                                && (L1H == cache_hint::uncached
+                                        || L1H == cache_hint::write_through
+                                        || L1H == cache_hint::streaming))
+                        || ((L2H == cache_hint::write_back)
+                                && (L1H == cache_hint::uncached
+                                        || L1H == cache_hint::write_through
+                                        || L1H == cache_hint::streaming
+                                        || L1H == cache_hint::write_back)),
+                "unsupported cache hint!");
+    } else if constexpr (Action == lsc_action::atomic) {
+        static_assert((L1H == cache_hint::none && L2H == cache_hint::none)
+                        || (L1H == cache_hint::uncached
+                                && (L2H == cache_hint::uncached
+                                        || L2H == cache_hint::write_back)),
+                "unsupported cache hint!");
+    }
+}
+
+template <cache_hint L1H, cache_hint L2H, gpu_arch arch_tag>
+constexpr std::enable_if_t<arch_tag == gpu_arch::Xe, uint32_t>
+get_load_cache_hint_code() {
+    check_lsc_cache_hint<lsc_action::load, L1H, L2H, arch_tag>();
+    if (L1H == cache_hint::none && L2H == cache_hint::none) {
+        return 0;
+    } else if (L2H == cache_hint::uncached) {
+        if (L1H == cache_hint::uncached) { return 1; }
+        if (L1H == cache_hint::cached) { return 3; }
+        if (L1H == cache_hint::streaming) { return 5; }
+    } else if (L2H == cache_hint::cached) {
+        if (L1H == cache_hint::uncached) { return 2; }
+        if (L1H == cache_hint::cached) { return 4; }
+        if (L1H == cache_hint::streaming) { return 6; }
+        if (L1H == cache_hint::read_invalidate) { return 7; }
+    }
+}
+
+template <cache_hint L1H, cache_hint L2H, gpu_arch arch_tag>
+constexpr std::enable_if_t<arch_tag == gpu_arch::Xe, uint32_t>
+get_prefetch_cache_hint_code() {
+    check_lsc_cache_hint<lsc_action::prefetch, L1H, L2H, arch_tag>();
+    if (L2H == cache_hint::uncached) {
+        if (L1H == cache_hint::uncached) { return 1; }
+        if (L1H == cache_hint::cached) { return 3; }
+        if (L1H == cache_hint::streaming) { return 5; }
+    } else if (L2H == cache_hint::cached) {
+        if (L1H == cache_hint::uncached) { return 2; }
+        if (L1H == cache_hint::cached) { return 4; }
+        if (L1H == cache_hint::streaming) { return 6; }
+    }
+}
+
+template <cache_hint L1H, cache_hint L2H, gpu_arch arch_tag>
+constexpr std::enable_if_t<arch_tag == gpu_arch::Xe, uint32_t>
+get_store_cache_hint_code() {
+    check_lsc_cache_hint<lsc_action::store, L1H, L2H, arch_tag>();
+    if (L1H == cache_hint::none && L2H == cache_hint::none) {
+        return 0;
+    } else if (L2H == cache_hint::uncached) {
+        if (L1H == cache_hint::uncached) { return 1; }
+        if (L1H == cache_hint::write_through) { return 3; }
+        if (L1H == cache_hint::streaming) { return 5; }
+    } else if (L2H == cache_hint::write_back) {
+        if (L1H == cache_hint::uncached) { return 2; }
+        if (L1H == cache_hint::write_through) { return 4; }
+        if (L1H == cache_hint::streaming) { return 6; }
+        if (L1H == cache_hint::write_back) { return 7; }
+    }
+}
+
+template <cache_hint L1H, cache_hint L2H, gpu_arch arch_tag>
+constexpr std::enable_if_t<arch_tag == gpu_arch::Xe, uint32_t>
+get_atomic_cache_hint_code() {
+    check_lsc_cache_hint<lsc_action::atomic, L1H, L2H, arch_tag>();
+    if (L1H == cache_hint::none && L2H == cache_hint::none) {
+        return 0;
+    } else if (L2H == cache_hint::uncached) {
+        if (L1H == cache_hint::uncached) { return 1; }
+        if (L1H == cache_hint::write_through) { return 3; }
+        if (L1H == cache_hint::streaming) { return 5; }
+    } else if (L2H == cache_hint::write_back) {
+        if (L1H == cache_hint::uncached) { return 2; }
+        if (L1H == cache_hint::write_through) { return 4; }
+        if (L1H == cache_hint::streaming) { return 6; }
+        if (L1H == cache_hint::write_back) { return 7; }
+    }
+}
+
+template <uint32_t num_channel>
+constexpr uint32_t get_execSize_code() {
+    static_assert(num_channel == 1 || num_channel == 2 || num_channel == 4
+                    || num_channel == 8 || num_channel == 16
+                    || num_channel == 32,
+            "num_channel not supported!");
+    switch (num_channel) {
+        case 1: return 0;
+        case 2: return 1;
+        case 4: return 2;
+        case 8: return 3;
+        case 16: return 4;
+        case 32: return 5;
+    }
+}
+
+template <atomic_op Op>
+constexpr uint32_t get_atomic_opcode() {
+    static_assert(Op == atomic_op::fadd || Op == atomic_op::fmax
+                    || Op == atomic_op::iadd,
+            "Other atomic op didn't added");
+    switch (Op) {
+        case atomic_op::fadd: return 19;
+        case atomic_op::fmax: return 22;
+        case atomic_op::iadd: return 12;
+    }
+}
+
+} // namespace detail
+
+///
+///@brief tile layout in register
+/// linear: linear layout with one tile
+/// tiled: 2d block stacked in raster order
+/// vnni_tiled: vnni pack with 2d block and 2d block stacked in raster order
+/// for dword and qword, there is no impact
+/// for word, two rows are interleaved, i.e.
+/// a0 b0 c0 d0 ==> a0 a1 b0 b1 c0 c1 d0 d1
+/// a1 b1 c1 d1
+/// for byte, four rows are interleaved and formed one row, i.e.
+/// a0 b0 c0 d0 ==> a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3
+/// a1 b1 c1 d1
+/// a2 b2 c2 d2
+/// a3 b3 c3 d3
+///
+enum class reg_layout : uint8_t {
+    linear = 0,
+    tiled = 1,
+    vnni_tiled = 2,
+    transpose_tiled = 3,
+    /// this is vnni tiled format, but for each block, they are stored in col
+    /// major order
+    vnni_tiled_col_major = 4
+};
+enum class store_op : uint8_t {
+    normal = 0,
+    atomic_fadd = 1,
+    atomic_iadd = 2,
+    scattered_transpose = 3,
+    block_1d = 4
+};
+enum class mma_engine : uint8_t { xmx = 0, fpu = 1 };
+// enum class trans_mode : uint8_t { none = 0, transpose = 1 };
+enum class memory_op : uint8_t { load = 0, store = 1 };
+enum class tdesc_update_dir : uint8_t { x_dir = 0, y_dir = 1 };
+enum class post_kind : uint8_t {
+    none = 0,
+    relu = 1,
+    gelu = 2,
+    gelu_bwd_w = 3,
+    sigmoid = 4,
+    tanh = 5
+};
+enum class pre_kind : uint8_t { none = 0, bias_add = 1, res_add = 2 };
+enum class offset_mode : uint8_t {
+    const_offset = 0,
+    cyclic_offset = 1,
+    acyclic_offset = 2
+};
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/dict.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/dict.hpp
new file mode 100644
index 00000000000000..1eaeee49dab026
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/dict.hpp
@@ -0,0 +1,247 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+// meta_value type
+
+namespace impl {
+struct meta_impl_base {
+    struct _default {};
+};
+
+static constexpr meta_impl_base::_default meta_impl_base_default;
+
+template <typename T, auto value_>
+struct meta_value_impl : meta_impl_base {
+    using type = T;
+    static constexpr T value = value_;
+};
+
+template <typename T = meta_impl_base::_default>
+struct meta_type_impl : meta_impl_base {
+    using type = T;
+};
+} // namespace impl
+
+template <auto d_ = impl::meta_impl_base_default, typename T = decltype(d_)>
+using meta_value = impl::meta_value_impl<T, d_>;
+
+template <auto d_ = impl::meta_impl_base_default, typename T = decltype(d_)>
+using meta_value_t = typename meta_value<d_, T>::type;
+
+template <typename T = impl::meta_impl_base::_default>
+using meta_type = impl::meta_type_impl<T>;
+
+template <typename T>
+using meta_type_t = typename T::type;
+
+// shape type
+
+template <auto... dims>
+struct shape {
+    static constexpr size_t size = sizeof...(dims);
+
+    struct impl {
+        template <size_t i_, size_t cur_, auto... dims_>
+        struct dim_impl;
+
+        template <size_t i_, auto dim, auto... dims_>
+        struct dim_impl<i_, i_, dim, dims_...> {
+            static constexpr auto value = dim;
+        };
+
+        template <size_t i_, size_t cur_, auto dim, auto... dims_>
+        struct dim_impl<i_, cur_, dim, dims_...>
+            : dim_impl<i_, cur_ + 1, dims_...> {
+            static_assert(i_ < size, "i_ exceeded shape size");
+            static_assert(cur_ < size, "cur_ exceeded shape size");
+        };
+    };
+
+    template <size_t i>
+    static constexpr auto dim() {
+        return impl::template dim_impl<i, 0, dims...>::value;
+    }
+};
+
+template <auto... dims>
+static inline constexpr auto shape_v = shape<dims...> {};
+
+// dict type
+
+template <auto key_, typename val_>
+struct elem_t {
+    static constexpr auto key = key_;
+    using value = val_;
+};
+
+template <auto key_, typename T>
+struct elem_t_t : elem_t<key_, meta_type<T>> {};
+
+template <auto key_, auto val_, typename T = decltype(val_)>
+struct elem_v_t : elem_t<key_, meta_value<val_, T>> {};
+
+template <typename... Args>
+struct dict_t {
+    static constexpr size_t arg_size = sizeof...(Args);
+
+    struct impl {
+        template <typename T>
+        struct type_identity {
+            using type = T;
+        };
+
+        struct empty_dict : type_identity<dict_t<>> {};
+        using this_t = dict_t<Args...>;
+
+        static constexpr int key_not_found = -1;
+
+        template <auto value_, typename type_>
+        struct find_elem_impl_ret_type {
+            static constexpr auto value = value_;
+            using type = type_;
+        };
+
+        template <auto key_, size_t cur_, typename... Elems>
+        struct find_elem_impl;
+
+        template <auto key_, size_t cur_, typename elem_, typename... Elems>
+        struct find_elem_impl<key_, cur_, elem_, Elems...> {
+            static constexpr bool match_key = (key_ == elem_::key);
+            using ret = typename std::conditional<match_key,
+                    find_elem_impl_ret_type<cur_, elem_>,
+                    find_elem_impl<key_, cur_ + 1, Elems...>>::type;
+            static constexpr int value = ret::value;
+            using type = typename ret::type;
+        };
+
+        template <auto key_, size_t cur_>
+        struct find_elem_impl<key_, cur_> {
+            static constexpr int value = key_not_found;
+            using type = void;
+        };
+
+        template <auto key_>
+        static constexpr int find_elem_index
+                = find_elem_impl<key_, 0, Args...>::value;
+
+        template <auto key_>
+        struct find_elem : find_elem_impl<key_, 0, Args...>::type {};
+
+        template <typename... Elems>
+        struct prepend_key_impl : type_identity<dict_t<Elems..., Args...>> {};
+
+        template <typename... Elems>
+        struct append_key_impl : type_identity<dict_t<Args..., Elems...>> {};
+
+        template <typename dict_t_>
+        struct merge_dict_impl;
+
+        template <typename... Elems>
+        struct merge_dict_impl<dict_t<Elems...>> : append_key_impl<Elems...> {};
+
+        template <typename dict_t_, int cur_i, int begin_i, int end_i>
+        struct slicing_key_impl : empty_dict {};
+
+        template <int cur_i, int begin_i, int end_i, typename e_,
+                typename... Elems>
+        struct slicing_key_impl<dict_t<e_, Elems...>, cur_i, begin_i, end_i> {
+            using nxt_dict = typename std::conditional<(cur_i + 1 < end_i)
+                            && (sizeof...(Elems) > 0),
+                    slicing_key_impl<dict_t<Elems...>, cur_i + 1, begin_i,
+                            end_i>,
+                    empty_dict>::type::type;
+            using type = typename std::conditional<(begin_i <= cur_i)
+                            && (cur_i < end_i),
+                    typename nxt_dict::impl::template prepend_key_impl<e_>,
+                    type_identity<nxt_dict>>::type::type;
+        };
+
+        template <typename dict_t_, typename e_, int e_index>
+        struct replace_key_impl {
+            using pre_dict = typename slicing_key_impl<dict_t_, 0, 0,
+                    e_index>::type::impl::template append_key_impl<e_>::type;
+            using post_dict = typename slicing_key_impl<dict_t_, 0, e_index + 1,
+                    dict_t_::arg_size>::type;
+            using type = typename pre_dict::impl::template merge_dict_impl<
+                    post_dict>::type;
+        };
+
+        template <typename dict_t_, typename... Elems>
+        struct update_dict_impl : type_identity<dict_t_> {};
+
+        template <typename dict_t_, typename e_, typename... Elems>
+        struct update_dict_impl<dict_t_, e_, Elems...>
+            : update_dict_impl<typename update_dict_impl<dict_t_, e_>::type,
+                      Elems...> {};
+
+        template <typename dict_t_, typename e_, typename... Elems>
+        struct update_dict_impl<dict_t_, dict_t<e_, Elems...>>
+            : update_dict_impl<dict_t_, e_, Elems...> {};
+
+        template <typename dict_t_, typename e_>
+        struct update_dict_impl<dict_t_, e_> {
+            static constexpr int e_index
+                    = dict_t_::impl::template find_elem_index<e_::key>;
+            using type = typename std::conditional<e_index != key_not_found,
+                    replace_key_impl<dict_t_, e_, e_index>,
+                    typename dict_t_::impl::template append_key_impl<e_>>::
+                    type::type;
+        };
+
+        template <typename U, template <typename> typename G>
+        struct update_generator_impl {
+            using res_t = typename G<U>::type;
+            using type = typename update_dict_impl<this_t, res_t>::type;
+        };
+    };
+
+    template <auto key_>
+    using find_elem_t = typename impl::template find_elem<key_>::value;
+
+    template <auto key_>
+    using find_elem_v_type = decltype(find_elem_t<key_>::value);
+
+    template <auto key_>
+    static inline constexpr find_elem_v_type<key_> find_elem_v
+            = find_elem_t<key_>::value;
+
+    template <typename e_, typename... Elems>
+    using update_t =
+            typename impl::template update_dict_impl<typename impl::this_t, e_,
+                    Elems...>::type;
+
+    template <typename T>
+    using update_dict_t =
+            typename impl::template update_dict_impl<typename impl::this_t,
+                    T>::type;
+
+    template <template <typename> typename G>
+    using update_generator_t =
+            typename impl::template update_generator_impl<typename impl::this_t,
+                    G>::type;
+};
+
+} // namespace gpu::xetla
\ No newline at end of file
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/fastmath.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/fastmath.hpp
new file mode 100644
index 00000000000000..cc411cc98aef1b
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/fastmath.hpp
@@ -0,0 +1,118 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+///@brief Host side utility function to compute number of leading zeros in the binary representation
+inline int clz(int x) {
+
+    for (int i = 31; i >= 0; i--) {
+
+        if ((1 << i) & x) { return (31 - i); }
+    }
+    return 32;
+}
+
+///@brief Host side utility function to compute log2 function
+inline int find_log2(int x) {
+
+    int a = int(31 - clz(x));
+    a = a + ((x & (x - 1)) != 0);
+    return a;
+}
+
+///Fast division + modulus operation
+///Host code pre-computes values to avoid expensive operations in kernel code
+struct FastDivMod {
+
+    int divisor;
+    unsigned int multiplier;
+    unsigned int shift_right;
+
+    ///Constructor, called in Hostcode to pre-compute multiplier and shift_right;
+    inline FastDivMod() : divisor(0), multiplier(0), shift_right(0) {}
+
+    inline FastDivMod(
+            uint32_t divisor_, uint32_t multiplier_, uint32_t shift_right_)
+        : divisor(divisor_)
+        , multiplier(multiplier_)
+        , shift_right(shift_right_) {}
+
+    inline FastDivMod(int divisor_) : divisor(divisor_) {
+
+        if (divisor != 1) {
+            unsigned int p = 31 + find_log2(divisor);
+            unsigned m = unsigned(
+                    ((1ull << p) + unsigned(divisor) - 1) / unsigned(divisor));
+
+            multiplier = m;
+            shift_right = p - 32;
+        } else {
+
+            multiplier = 0;
+            shift_right = 0;
+        }
+    }
+
+    inline void query_all(int &divisor_, unsigned int &multiplier_,
+            unsigned int &shift_right_) const {
+        divisor_ = divisor;
+        multiplier_ = multiplier;
+        shift_right_ = shift_right;
+    }
+
+    operator int() const { return divisor; }
+
+    __XETLA_API KERNEL_FUNC void set_divmod(
+            int divisor_, unsigned int multiplier_, unsigned int shift_right_) {
+        divisor = divisor_;
+        multiplier = multiplier_;
+        shift_right = shift_right_;
+    }
+
+    ///@brief Kernel side function to find quotient and remainder
+    __XETLA_API KERNEL_FUNC void fast_divmod(
+            int &quotient, int &remainder, int dividend) const {
+
+        quotient = int((divisor != 1)
+                        ? int(((int64_t)dividend * multiplier) >> 32)
+                                >> shift_right
+                        : dividend);
+
+        remainder = dividend - (quotient * divisor);
+    }
+
+    ///@brief kernel side utility functions for query of quotient
+    __XETLA_API KERNEL_FUNC int div(int dividend) const {
+
+        int quotient, remainder;
+        fast_divmod(quotient, remainder, dividend);
+        return quotient;
+    }
+};
+
+} // namespace gpu::xetla
\ No newline at end of file
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/limitation.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/limitation.hpp
new file mode 100644
index 00000000000000..004e0ff733550f
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/limitation.hpp
@@ -0,0 +1,157 @@
+/*******************************************************************************
+ * Copyright (c) 2022-2023 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/common.hpp"
+#include "../../../common/utils/cm/tensor_descriptor.hpp"
+#else
+#include "common/core/cm/common.hpp"
+#include "common/utils/cm/tensor_descriptor.hpp"
+#endif
+
+#define IN_RANGE(x, l, r) ((x) >= (l) && (x) <= (r))
+
+namespace gpu::xetla {
+
+typedef uint64_t size_t;
+
+namespace core {
+template <gpu_arch arch, typename T>
+struct general_1d {
+    template <uint8_t NElts>
+    static inline bool check_restriction(uint64_t offset, uint64_t p = 0) {
+        return true;
+    }
+
+    template <uint8_t NElts, int N, typename Toffset = uint32_t>
+    static inline bool check_restriction(
+            xetla_vector<Toffset, N> offsets, uint64_t p = 0) {
+        return true;
+    }
+};
+
+template <gpu_arch arch, typename T>
+class block_2d {
+public:
+    template <bool transpose, bool vnni_transform>
+    static inline bool check_load(xetla_tdescriptor tdesc) {
+        return true;
+    }
+
+    static inline bool check_store(xetla_tdescriptor tdesc) { return true; }
+
+    static inline bool check_tensor(
+            uint64_t base, uint32_t width, uint32_t height, uint32_t pitch) {
+        return true;
+    }
+};
+} // namespace core
+
+namespace subgroup {
+template <gpu_arch arch, typename dtype, typename mem_dtype>
+struct check_load {
+    template <bool mem_transform, size_t block_size_x>
+    struct global_2d {};
+
+    struct global_1d {};
+
+    template <bool mem_transform, size_t block_size_x>
+    struct unaligned_2d {};
+
+    template <mem_layout memory_layout, size_t block_size_x, size_t tile_bytes,
+            size_t min_bytes, size_t block_bytes, size_t num_channel_x,
+            size_t num_channel>
+    struct local_scatter {};
+
+    struct local_1d {};
+};
+
+template <gpu_arch arch, typename dtype, typename mem_dtype = uint32_t>
+struct check_store {
+    template <size_t block_size_x>
+    struct global_2d {};
+
+    struct global_1d {};
+
+    template <size_t block_size_x>
+    struct unaligned_2d {};
+
+    template <size_t tile_bytes, size_t min_store_bytes, size_t block_bytes,
+            size_t num_channel_x, size_t num_channel>
+    struct global_atomic {};
+
+    template <size_t tile_bytes, size_t min_bytes, size_t block_bytes,
+            size_t num_channel_x, size_t num_channel>
+    struct local_scatter {};
+
+    template <size_t tile_bytes, size_t min_store_bytes, size_t block_bytes,
+            size_t num_channel_x, size_t num_channel>
+    struct local_scatter_vnni_col {};
+
+    struct local_1d {};
+};
+} // namespace subgroup
+
+namespace group {
+
+template <gpu_arch arch>
+struct gemm {
+    struct default_fpu {
+        template <typename dtype_a, typename dtype_b, typename dtype_mma_a,
+                typename dtype_mma_b, typename dtype_mma_acc>
+        struct check_dtype_default {};
+
+        template <mem_layout mem_layout_a, mem_layout mem_layout_b,
+                mem_space mem_space_a, mem_space mem_space_b>
+        struct check_memory_default {};
+
+        template <typename dtype_mma, int tile_size_x_a, int tile_size_y_a,
+                int block_size_x_a, int block_size_y_a, int tile_size_x_b,
+                int tile_size_y_b, int block_size_x_b, int block_size_y_b>
+        struct check_tile_size_default {};
+    };
+
+    struct default_xmx {
+        template <typename dtype_a, typename dtype_b, typename dtype_mma_a,
+                typename dtype_mma_b>
+        struct check_dtype_default {};
+
+        template <mem_layout mem_layout_a, mem_layout mem_layout_b,
+                mem_space mem_space_a, mem_space mem_space_b>
+        struct check_memory_default {};
+
+        template <typename dtype_mma, int tile_size_x_a, int tile_size_y_a,
+                int block_size_x_a, int block_size_y_a, int tile_size_x_b,
+                int tile_size_y_b, int block_size_x_b, int block_size_y_b>
+        struct check_tile_size_default {};
+    };
+};
+} // namespace group
+
+namespace kernel {
+template <gpu_arch arch, typename T>
+class general_1d {
+public:
+    static inline bool check_alignment(T *base, uint32_t pitch) { return true; }
+};
+} // namespace kernel
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/memory_descriptor.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/memory_descriptor.hpp
new file mode 100644
index 00000000000000..ebb631b3ab16d4
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/memory_descriptor.hpp
@@ -0,0 +1,363 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#include "../../../common/utils/cm/raw_send_load_store.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#include "common/utils/cm/raw_send_load_store.hpp"
+#endif
+
+namespace gpu::xetla {
+
+template <int dim = 2>
+struct mem_coord_t {};
+template <>
+struct mem_coord_t<2> {
+    int x;
+    int y;
+    inline mem_coord_t(int x_, int y_) : x(x_), y(y_) {}
+    inline mem_coord_t() = default;
+    inline mem_coord_t(const mem_coord_t<2> &coord) {
+        this->x = coord.x;
+        this->y = coord.y;
+    }
+    inline mem_coord_t<2> &operator=(const mem_coord_t<2> &coord) {
+        this->x = coord.x;
+        this->y = coord.y;
+        return *this;
+    }
+    inline void init(int x_, int y_) {
+        this->x = x_;
+        this->y = y_;
+    }
+};
+
+template <>
+struct mem_coord_t<4> {
+    int x;
+    int y;
+    int z;
+    int w;
+};
+
+template <int dim = 2>
+struct mem_shape_t {};
+template <>
+struct mem_shape_t<2> {
+    uint32_t x;
+    uint32_t y;
+    uint32_t stride_x;
+    inline mem_shape_t() = default;
+    inline mem_shape_t(
+            uint32_t shape_x_, uint32_t shape_y_, uint32_t row_stride_)
+        : x(shape_x_), y(shape_y_), stride_x(row_stride_) {}
+    inline mem_shape_t(const mem_shape_t<2> &shape) {
+        this->x = shape.x;
+        this->y = shape.y;
+        this->stride_x = shape.stride_x;
+    }
+    inline mem_shape_t<2> &operator=(const mem_shape_t<2> &shape) {
+        this->x = shape.x;
+        this->y = shape.y;
+        this->stride_x = shape.stride_x;
+        return *this;
+    }
+    inline void init(
+            uint32_t shape_x_, uint32_t shape_y_, uint32_t row_stride_) {
+        this->x = shape_x_;
+        this->y = shape_y_;
+        this->stride_x = row_stride_;
+    }
+};
+
+template <>
+struct mem_shape_t<4> {
+    uint32_t x = 0;
+    uint32_t y = 0;
+    uint32_t z = 0;
+    uint32_t w = 0;
+    uint32_t stride_x = 0;
+    uint32_t stride_y = 0;
+    uint32_t stride_z = 0;
+
+    inline mem_shape_t() = default;
+    inline mem_shape_t(uint32_t size0_, uint32_t size1_, uint32_t size2_,
+            uint32_t size3_, uint32_t stride0_, uint32_t stride1_,
+            uint32_t stride2_)
+        : x(size0_)
+        , y(size1_)
+        , z(size2_)
+        , w(size3_)
+        , stride_x(stride0_)
+        , stride_y(stride1_)
+        , stride_z(stride2_) {}
+    inline mem_shape_t(
+            uint32_t size0_, uint32_t size1_, uint32_t size2_, uint32_t size3_)
+        : x(size0_)
+        , y(size1_)
+        , z(size2_)
+        , w(size3_)
+        , stride_x(size0_)
+        , stride_y(size1_)
+        , stride_z(size2_) {}
+    // these methods are here because without them cm produces this error
+    // "warning:  undefined value is referenced after decomposition"
+    inline mem_shape_t(const mem_shape_t<4> &shape)
+        : x(shape.x)
+        , y(shape.y)
+        , z(shape.z)
+        , w(shape.w)
+        , stride_x(shape.stride_x)
+        , stride_y(shape.stride_y)
+        , stride_z(shape.stride_z) {}
+    inline mem_shape_t<4> &operator=(const mem_shape_t<4> &shape) {
+        this->x = shape.x;
+        this->y = shape.y;
+        this->z = shape.z;
+        this->w = shape.w;
+        this->stride_x = shape.stride_x;
+        this->stride_y = shape.stride_y;
+        this->stride_z = shape.stride_z;
+        return *this;
+    }
+};
+
+template <typename dtype_, mem_space space_>
+struct mem_base_t {};
+template <typename dtype_>
+struct mem_base_t<dtype_, mem_space::global> {
+    using dtype = dtype_;
+    dtype *base;
+    inline mem_base_t() = default;
+    inline mem_base_t(dtype *base_) : base(base_) {}
+    inline mem_base_t(const mem_base_t<dtype, mem_space::global> &mem_base)
+        : base(mem_base.base) {}
+    inline mem_base_t<dtype, mem_space::global> &operator=(
+            const mem_base_t<dtype, mem_space::global> &mem_base) {
+        this->base = mem_base.base;
+        return *this;
+    }
+    inline void init(dtype *base_) { base = base_; }
+    inline void update(int offset) { base = base + offset; }
+};
+template <typename dtype_>
+struct mem_base_t<dtype_, mem_space::local> {
+    using dtype = dtype_;
+    uint32_t base;
+    inline mem_base_t() = default;
+    inline mem_base_t(uint32_t base_) : base(base_) {}
+    inline mem_base_t(const mem_base_t<dtype, mem_space::local> &mem_base)
+        : base(mem_base.base) {}
+    inline mem_base_t<dtype, mem_space::local> &operator=(
+            const mem_base_t<dtype, mem_space::local> &mem_base) {
+        this->base = mem_base.base;
+        return *this;
+    }
+    inline void init(uint32_t base_) { base = base_; }
+    inline void update(int offset) { base = base + offset * sizeof(dtype); }
+};
+
+template <typename dtype_, mem_layout layout_, mem_space space_,
+        uint32_t alignment_ = 8, int dim_ = 2>
+struct mem_desc_t {};
+
+template <typename dtype_, mem_layout layout_, mem_space space_,
+        uint32_t alignment_>
+struct mem_desc_t<dtype_, layout_, space_, alignment_, 2> {
+    using dtype = dtype_;
+    static constexpr mem_layout layout = layout_;
+    static constexpr mem_space space = space_;
+    static constexpr int dim = 2;
+    static constexpr uint32_t alignment = alignment_;
+    static constexpr uint32_t alignment_in_bytes = alignment_ * sizeof(dtype);
+
+    static constexpr bool is_col_major = layout == mem_layout::col_major;
+    static constexpr bool is_local = space == mem_space::local;
+    using shape_t = mem_shape_t<dim>;
+    using coord_t = mem_coord_t<dim>;
+    using base_t = mem_base_t<dtype, space>;
+
+    using this_type_t = mem_desc_t<dtype, layout_, space_, alignment, 2>;
+
+    inline mem_desc_t() = default;
+    inline mem_desc_t(base_t base_, shape_t shape_, coord_t coord_)
+        : base(base_), shape(shape_), coord(coord_) {}
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // inline ~mem_desc_t(){}
+    inline mem_desc_t(const this_type_t &mem_desc)
+        : base(mem_desc.base), shape(mem_desc.shape), coord(mem_desc.coord) {}
+
+    inline this_type_t &operator=(const this_type_t &mem_desc) {
+        this->base = mem_desc.base;
+        this->shape = mem_desc.shape;
+        this->coord = mem_desc.coord;
+        return *this;
+    }
+    inline void init(base_t base_, shape_t shape_, coord_t coord_) {
+        base = base_;
+        shape = shape_;
+        coord = coord_;
+    }
+    inline void update_coord(int offset_x, int offset_y) {
+        coord.x += offset_x;
+        coord.y += offset_y;
+    }
+
+    inline void set_coord(int offset_x, int offset_y) {
+        coord.x = offset_x;
+        coord.y = offset_y;
+    }
+
+    inline void update_coord_x(int offset_x) { coord.x += offset_x; }
+    inline void update_coord_y(int offset_y) { coord.y += offset_y; }
+    inline xetla_tdescriptor get_tdesc() {
+        uint32_t width = is_col_major ? shape.y : shape.x;
+        uint32_t height = is_col_major ? shape.x : shape.y;
+        uint32_t pitch = shape.stride_x;
+        int coord_x = is_col_major ? coord.y : coord.x;
+        int coord_y = is_col_major ? coord.x : coord.y;
+        return xetla_get_tdesc<dtype>(
+                base.base, width, height, pitch, coord_x, coord_y);
+    }
+
+    shape_t shape;
+    coord_t coord;
+    base_t base;
+};
+
+template <typename dtype_, mem_layout layout_, mem_space space_,
+        uint32_t alignment_>
+struct mem_desc_t<dtype_, layout_, space_, alignment_, 4> {
+    using dtype = dtype_;
+    static constexpr mem_layout layout = layout_;
+    static constexpr mem_space space = space_;
+    static constexpr uint32_t alignment = alignment_;
+    static constexpr uint32_t alignment_in_bytes = alignment * sizeof(dtype);
+    static constexpr int dim = 4;
+
+    static constexpr bool is_local = (space == mem_space::local);
+    using shape_t = mem_shape_t<dim>;
+    using coord_t = mem_coord_t<dim>;
+    using base_t = mem_base_t<dtype, space>;
+
+    using this_type_t = mem_desc_t<dtype, layout_, space_, alignment, 4>;
+
+    // without this constructor some compiler versions can incorrectly
+    // initialize  the struct, probably due to some bug
+    inline mem_desc_t(base_t base_, shape_t shape_, coord_t coord_)
+        : base(base_), shape(shape_), coord(coord_) {};
+
+    inline void update_coord(
+            int offset_x, int offset_y, int offset_z, int offset_w) {
+        coord.x += offset_x;
+        coord.y += offset_y;
+        coord.z += offset_z;
+        coord.w += offset_w;
+    }
+    inline void update_coord_x(int offset_x) { coord.x += offset_x; }
+    inline void update_coord_y(int offset_y) { coord.y += offset_y; }
+    inline void update_coord_z(int offset_z) { coord.z += offset_z; }
+    inline void update_coord_w(int offset_w) { coord.w += offset_w; }
+    inline xetla_tdescriptor get_tdesc() {
+        uint32_t width = shape.x; // in NHWC this is C
+        uint32_t height = shape.y; // in NHWC this is W
+        uint32_t pitch = shape.stride_x;
+        int coord_x = coord.x; // in NHWC this is offset in channels
+        int coord_y = coord.y; // in NHWC this is offset in width
+
+        dtype *base_ptr = base.base;
+        return xetla_get_tdesc<dtype>(
+                base_ptr, width, height, pitch, coord_x, coord_y);
+    }
+    inline uint32_t get_shape_x(void) { return shape.x; }
+    inline uint32_t get_shape_y(void) { return shape.y; }
+    inline uint32_t get_shape_z(void) { return shape.z; }
+    inline uint32_t get_shape_w(void) { return shape.w; }
+
+    inline uint32_t get_stride_x(void) { return shape.stride_x; }
+    inline uint32_t get_stride_y(void) { return shape.stride_y; }
+    inline uint32_t get_stride_z(void) { return shape.stride_z; }
+
+    inline int32_t get_coord_x(void) { return coord.x; }
+    inline int32_t get_coord_y(void) { return coord.y; }
+    inline int32_t get_coord_z(void) { return coord.z; }
+    inline int32_t get_coord_w(void) { return coord.w; }
+
+    template <int32_t N>
+    inline xetla_vector<int32_t, N> get_base_offset_from_z(
+            xetla_vector<int32_t, N> offset) {
+        xetla_vector<int32_t, N> ret
+                = (offset + coord.z) * (shape.stride_x * shape.stride_y);
+        return ret;
+    }
+
+    inline int32_t get_base_offset_from_z(int32_t offset) {
+        int32_t ret = (offset + coord.z) * shape.stride_x * shape.stride_y;
+        return ret;
+    }
+
+    template <int32_t N>
+    inline xetla_mask<N> get_mask_from_z(xetla_vector<int32_t, N> offset) {
+        xetla_mask<N> mask
+                = (offset + coord.z >= 0) & (offset + coord.z < shape.z);
+        return mask;
+    }
+
+    inline int get_mask_from_z(int32_t offset) {
+        int mask = (offset + coord.z >= 0) & (offset + coord.z < shape.z);
+        return mask;
+    }
+
+    inline int32_t get_base_offset_from_w(int32_t offset) {
+        int32_t ret = (offset + coord.w) * shape.stride_x * shape.stride_y
+                * shape.stride_z;
+        return ret;
+    }
+
+    template <int32_t N>
+    inline xetla_vector<int32_t, N> get_base_offset_from_w(
+            xetla_vector<int32_t, N> offset) {
+        xetla_vector<int32_t, N> ret = (offset + coord.w) * shape.stride_x
+                * shape.stride_y * shape.stride_z;
+        return ret;
+    }
+
+    template <int32_t N>
+    inline xetla_mask<N> get_mask_from_w(xetla_vector<int32_t, N> offset) {
+        xetla_mask<N> mask
+                = (offset + coord.w >= 0) & (offset + coord.w < shape.w);
+        return mask;
+    }
+
+    inline int get_mask_from_w(int32_t offset) {
+        int mask = (offset + coord.w >= 0) & (offset + coord.w < shape.w);
+        return mask;
+    }
+
+    base_t base;
+    shape_t shape;
+    coord_t coord;
+};
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/misc.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/misc.hpp
new file mode 100644
index 00000000000000..b4134764bd15c0
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/misc.hpp
@@ -0,0 +1,181 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#include "../../../common/utils/cm/nd_item.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#include "common/utils/cm/nd_item.hpp"
+#endif
+
+__XETLA_API constexpr uint32_t div_round_up(uint32_t n, uint32_t d) {
+    return (n + d - 1) / d;
+}
+
+__XETLA_API constexpr int div_round_down(int n, int d) {
+    // Numbers are rounded down towards the next lowest number
+    // e.g. -2.0/3.0 ~ -0.666 -> -1.
+    return (n - (((n % d) + d) % d)) / d;
+}
+
+__XETLA_API constexpr int modulo(int n, int d) {
+    // Calculates modulo based on definition that uses floored divison.
+    // Result has the same sign as d.
+    return (d + (n % d)) % d;
+}
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_util_misc
+/// @{
+
+/// @brief Returns time stamp
+///
+/// @return vecotor <uint32_t, 4> contain time stamp
+///
+__XETLA_API xetla_vector<uint32_t, 4> get_time_stamp() {
+    return cm_rdtsc();
+}
+
+///
+/// @brief xetla_vector generation.
+/// Commonly used to generate simd channel id.
+///
+/// @tparam Ty is type of xetla_vector generated. Only `int` type(or types that can be implicitly converted to int) is allowed.
+/// @tparam N is the number of elements in xetla_vector generated.
+/// @param InitVal [in] is the starting value of xetla_vector generation.
+/// @param Step [in] is the step value between adjacent elements.
+/// @return xetla_vector<Ty, N> [out] is the return vector.
+///
+template <typename Ty, int N>
+__XETLA_API xetla_vector<Ty, N> xetla_vector_gen(int InitVal, int Step) {
+    xetla_vector<Ty, N> tmp;
+    cmtl::cm_vector_assign(tmp, InitVal, Step);
+    return tmp;
+}
+
+template <uint32_t N>
+__XETLA_API xetla_mask_int<N> xetla_mask_int_gen(uint32_t mask_val) {
+    return mask_val;
+}
+
+template <typename dtype_acc, uint32_t N, uint32_t num_flag = 4,
+        typename dtype_mask = uint8_t>
+__XETLA_API xetla_vector<dtype_acc, N> drop_out(xetla_vector<dtype_acc, N> in,
+        xetla_vector<dtype_mask, N> mask, dtype_acc scale) {
+    xetla_vector<dtype_acc, N> out = in * scale;
+    constexpr uint32_t unroll_size = num_flag * 16;
+    SW_BARRIER();
+#pragma unroll
+    for (int i = 0; i < N / unroll_size; i++) {
+        xetla_mask<unroll_size> mask_flag
+                = mask.xetla_select<unroll_size, 1>(i * unroll_size) > 0;
+        out.xetla_select<unroll_size, 1>(i * unroll_size)
+                .xetla_merge(0, mask_flag);
+    }
+    if constexpr (N % unroll_size != 0) {
+        constexpr uint32_t remain_len = N % unroll_size;
+        constexpr uint32_t remain_start = N / unroll_size * unroll_size;
+        xetla_mask<remain_len> mask_flag
+                = mask.xetla_select<remain_len, 1>(remain_start) > 0;
+        out.xetla_select<remain_len, 1>(remain_start).xetla_merge(0, mask_flag);
+    }
+    return out;
+}
+
+template <reduce_op reduce_kind, typename dtype, int size>
+__XETLA_API typename std::enable_if_t<reduce_kind == reduce_op::sum,
+        xetla_vector<dtype, size>>
+reduce_helper(xetla_vector<dtype, size> a, xetla_vector<dtype, size> b) {
+    return a + b;
+}
+
+template <reduce_op reduce_kind, typename dtype, int size>
+__XETLA_API typename std::enable_if_t<reduce_kind == reduce_op::prod,
+        xetla_vector<dtype, size>>
+reduce_helper(xetla_vector<dtype, size> a, xetla_vector<dtype, size> b) {
+    return a * b;
+}
+
+template <reduce_op reduce_kind, typename dtype, int size>
+__XETLA_API typename std::enable_if_t<reduce_kind == reduce_op::max,
+        xetla_vector<dtype, size>>
+reduce_helper(xetla_vector<dtype, size> a, xetla_vector<dtype, size> b) {
+    xetla_vector<dtype, size> out;
+    xetla_mask<size> mask = a > b;
+    out.xetla_merge(a, b, mask);
+    return out;
+}
+
+template <reduce_op reduce_kind, typename dtype, int size>
+__XETLA_API typename std::enable_if_t<reduce_kind == reduce_op::min,
+        xetla_vector<dtype, size>>
+reduce_helper(xetla_vector<dtype, size> a, xetla_vector<dtype, size> b) {
+    xetla_vector<dtype, size> out;
+    xetla_mask<size> mask = a < b;
+    out.xetla_merge(a, b, mask);
+    return out;
+}
+
+template <reduce_op reduce_kind, typename dtype, int N_x, int N_y>
+__XETLA_API typename std::enable_if_t<N_y == 1, xetla_vector<dtype, N_x>>
+recur_row_reduce(xetla_vector<dtype, N_x> in) {
+    return in;
+}
+template <reduce_op reduce_kind, typename dtype, int N_x, int N_y>
+__XETLA_API typename std::enable_if_t<(N_y > 1), xetla_vector<dtype, N_x>>
+recur_row_reduce(xetla_vector<dtype, N_x * N_y> in) {
+    static_assert(((N_y) & (N_y - 1)) == 0, "N_y should be power of 2");
+    xetla_vector<dtype, N_x * N_y / 2> temp;
+    temp = reduce_helper<reduce_kind, dtype, N_x * N_y / 2>(
+            in.xetla_select<N_x * N_y / 2, 1>(0),
+            in.xetla_select<N_x * N_y / 2, 1>(N_x * N_y / 2));
+
+    return recur_row_reduce<reduce_kind, dtype, N_x, N_y / 2>(temp);
+}
+
+template <reduce_op reduce_kind, typename dtype, int N_x, int N_y>
+__XETLA_API typename std::enable_if_t<N_x == 1, xetla_vector<dtype, N_y>>
+recur_col_reduce(xetla_vector<dtype, N_y> in) {
+    return in;
+}
+template <reduce_op reduce_kind, typename dtype, int N_x, int N_y>
+__XETLA_API typename std::enable_if_t<(N_x > 1), xetla_vector<dtype, N_y>>
+recur_col_reduce(xetla_vector<dtype, N_x * N_y> in) {
+    static_assert(((N_x) & (N_x - 1)) == 0, "N_x should be power of 2");
+    xetla_vector<dtype, N_x * N_y / 2> temp;
+    auto in_2d = in.xetla_format<dtype, N_y, N_x>();
+    temp = reduce_helper<reduce_kind, dtype, N_y * N_x / 2>(
+            in_2d.xetla_select<N_y, 1, N_x / 2, 1>(0, 0),
+            in_2d.xetla_select<N_y, 1, N_x / 2, 1>(0, N_x / 2));
+
+    return recur_col_reduce<reduce_kind, dtype, N_x / 2, N_y>(temp);
+}
+
+/// @brief get linear group id of the last two dimensions.
+/// @tparam item Is the given sycl::nd_item<3>.
+__XETLA_API uint32_t get_2d_group_linear_id(sycl::nd_item<3> &item) {
+    return item.get_group(2) + item.get_group(1) * item.get_group_range(2);
+}
+/// @} xetla_util_misc
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/nd_item.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/nd_item.hpp
new file mode 100644
index 00000000000000..37adcb901285d2
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/nd_item.hpp
@@ -0,0 +1,95 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#endif
+
+namespace sycl {
+
+/// @brief  The item struct to explict identify the group / local id information
+///
+/// @tparam dims The dimension for the execution item
+///
+template <int dims = 1>
+class nd_item {
+public:
+    inline nd_item() = default;
+    /// @brief Returns the group id for the requested dimensions.
+    ///
+    /// @param dimension The requested dimension
+    /// @return uint32_t The group id
+    ///
+    inline uint32_t get_group(int dimension) const {
+        return cm_group_id(dims - 1 - dimension);
+    }
+
+    /// @brief Returns local id in the work group for the requested dimensions
+    ///
+    /// @param dimension The requested dimension
+    /// @return uint32_t The local id
+    ///
+    inline uint32_t get_local_id(int dimension) const {
+        return cm_local_id(dims - 1 - dimension);
+    }
+
+    /// @brief Returns local size in the work group for the requested dimensions
+    ///
+    /// @param dimension The requested dimension
+    /// @return uint32_t The local size
+    ///
+    inline uint32_t get_local_range(int dimension) const {
+        return cm_local_size(dims - 1 - dimension);
+    }
+
+    /// @brief Returns local linear id in the work group
+    /// @note The right-most term in the object’s range varies fastest in the linearization.
+    /// @return uint32_t The local linear id
+    ///
+    inline uint32_t get_local_linear_id() const {
+        if constexpr (dims == 1) { return get_local_id(0); }
+        if constexpr (dims == 2) {
+            return get_local_id(1) + get_local_id(0) * get_local_range(1);
+        }
+        if constexpr (dims == 3) {
+            return get_local_id(2) + get_local_id(1) * get_local_range(2)
+                    + get_local_id(0) * get_local_range(1) * get_local_range(2);
+        }
+    }
+
+    /// @brief Returns global linear id
+    ///
+    /// @return uint32_t The global linear id
+    ///
+    inline uint32_t get_global_linear_id() const {
+        return cm_linear_global_id();
+    }
+
+    inline uint32_t get_group_range(int dimension) const {
+        return cm_group_count(dims - 1 - dimension);
+    }
+
+    inline uint32_t get_group_linear_id() const { return cm_linear_group_id(); }
+};
+
+} // namespace sycl
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/rand.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/rand.hpp
new file mode 100644
index 00000000000000..6329d81da9df4a
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/rand.hpp
@@ -0,0 +1,170 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_util_rand
+/// @{
+
+template <uint32_t SIMD = 16, uint32_t round = 7>
+struct xetla_rand_t {
+    xetla_vector<uint32_t, 2 * SIMD> key;
+    xetla_vector<uint32_t, 4 * SIMD> counter;
+    static constexpr uint32_t kPhilox10A = 0x9E3779B9;
+    static constexpr uint32_t kPhilox10B = 0xBB67AE85;
+    static constexpr uint32_t kPhiloxSA = 0xD2511F53;
+    static constexpr uint32_t kPhiloxSB = 0xCD9E8D57;
+
+    __XETLA_API void init(uint64_t seed, uint64_t subseq, uint64_t offset) {
+        xetla_vector<uint64_t, 1> seed_v = seed;
+        xetla_vector<uint64_t, 1> offset_v = offset;
+        xetla_vector<uint64_t, 1> subseq_v = subseq * SIMD;
+
+        auto key_2d = key.xetla_format<uint32_t, 2, SIMD>();
+        key_2d.row(0) = uint32_t(seed_v.xetla_format<uint32_t>()[0]);
+        key_2d.row(1) = uint32_t(seed_v.xetla_format<uint32_t>()[1]);
+
+        xetla_vector<uint32_t, SIMD> channel_id
+                = xetla_vector_gen<uint32_t, SIMD>(0, 1);
+        auto counter_2d = counter.xetla_format<uint32_t, 4, SIMD>();
+        counter_2d.row(0) = uint32_t(offset_v.xetla_format<uint32_t>()[0]);
+        counter_2d.row(1) = uint32_t(offset_v.xetla_format<uint32_t>()[1]);
+        counter_2d.row(2) = uint32_t(subseq_v.xetla_format<uint32_t>()[0]);
+        counter_2d.row(3) = uint32_t(subseq_v.xetla_format<uint32_t>()[1]);
+        counter_2d.row(2) += channel_id;
+    }
+
+    __XETLA_API xetla_vector<uint32_t, 4 * SIMD> rand() {
+        xetla_vector<uint32_t, 2 *SIMD> key_ = key;
+        xetla_vector<uint32_t, 4 *SIMD> counter_ = counter;
+        auto key_2d_ = key_.xetla_format<uint32_t, 2, SIMD>();
+
+#pragma unroll
+        for (int i = 0; i < round; i++) {
+            counter_ = single_round(counter_, key_);
+            key_2d_.row(0) += kPhilox10A;
+            key_2d_.row(1) += kPhilox10B;
+        }
+        xetla_vector<uint32_t, 4 *SIMD> output = single_round(counter_, key_);
+        incr();
+        return output;
+    }
+
+private:
+    __XETLA_API xetla_vector<uint32_t, 4 * SIMD> single_round(
+            xetla_vector<uint32_t, 4 * SIMD> counter_,
+            xetla_vector<uint32_t, 2 * SIMD> key_) {
+        xetla_vector<uint32_t, 4 * SIMD> ret;
+        auto ret_2d = ret.xetla_format<uint32_t, 4, SIMD>();
+        auto key_2d_ = key_.xetla_format<uint32_t, 2, SIMD>();
+        auto counter_2d_ = counter_.xetla_format<uint32_t, 4, SIMD>();
+
+        xetla_vector<uint32_t, SIMD> res0_lo;
+        xetla_vector<uint32_t, SIMD> res1_lo;
+        xetla_vector<uint32_t, SIMD> res0_hi
+                = xetla_imul<uint32_t, uint32_t, uint32_t, SIMD>(
+                        res0_lo.xetla_format<uint32_t>(), counter_2d_.row(0),
+                        kPhiloxSA);
+        xetla_vector<uint32_t, SIMD> res1_hi
+                = xetla_imul<uint32_t, uint32_t, uint32_t, SIMD>(
+                        res1_lo.xetla_format<uint32_t>(), counter_2d_.row(2),
+                        kPhiloxSB);
+
+        ret_2d.row(0) = res1_hi ^ counter_2d_.row(1) ^ key_2d_.row(0);
+        ret_2d.row(1) = res1_lo;
+        ret_2d.row(2) = res0_hi ^ counter_2d_.row(3) ^ key_2d_.row(1);
+        ret_2d.row(3) = res0_lo;
+
+        return ret;
+    }
+
+    __XETLA_API void incr() {
+        auto counter_2d = counter.xetla_format<uint32_t, 4, SIMD>();
+        xetla_vector<uint32_t, SIMD> carry;
+
+        counter_2d.row(0) = xetla_add_c<uint32_t, SIMD>(
+                counter_2d.row(0), 1, carry.xetla_format<uint32_t>());
+        counter_2d.row(1) = xetla_add_c<uint32_t, SIMD>(
+                counter_2d.row(1), carry, carry.xetla_format<uint32_t>());
+        counter_2d.row(2) = xetla_add_c<uint32_t, SIMD>(
+                counter_2d.row(2), carry, carry.xetla_format<uint32_t>());
+        counter_2d.row(3) += carry;
+    }
+};
+
+template <uint32_t SZ, typename dtype_mask = uint8_t, uint32_t random_simd = 16>
+struct dropout_fwd_t {
+    static constexpr uint32_t random_len = 4 * random_simd;
+    xetla_rand_t<random_simd> rand_gen;
+    xetla_vector<dtype_mask, SZ> mask;
+    uint32_t threshold;
+    float scale;
+
+    __XETLA_API void init(uint64_t seed, uint64_t subseq, uint64_t offset,
+            uint32_t threshold_, float scale_) {
+        rand_gen.init(seed, subseq, offset);
+        this->threshold = threshold_;
+        this->scale = scale_;
+    }
+
+    template <typename dtype>
+    __XETLA_API xetla_vector<dtype, SZ> process(xetla_vector<dtype, SZ> input) {
+        xetla_vector<dtype, SZ> output = input;
+#pragma unroll
+        for (int i = 0; i < SZ / random_len; i++) {
+            auto out_sub = output.xetla_select<random_len, 1>(i * random_len);
+            auto mask_sub = mask.xetla_select<random_len, 1>(i * random_len);
+            xetla_vector<uint32_t, random_len> rand_val = rand_gen.rand();
+            xetla_mask<random_len> mask_flag = rand_val < threshold;
+            out_sub.xetla_merge(0, mask_flag);
+            mask_sub.xetla_merge(1, 0, mask_flag);
+            out_sub = out_sub * scale;
+        }
+        if constexpr (SZ % random_len != 0) {
+            constexpr uint32_t remain_len = SZ % random_len;
+            constexpr uint32_t remain_start = SZ / random_len * random_len;
+            auto out_sub = output.xetla_select<remain_len, 1>(remain_start);
+            auto mask_sub = mask.xetla_select<remain_len, 1>(remain_start);
+            // dropout, still generate random_len
+            xetla_vector<uint32_t, random_len> rand_val = rand_gen.rand();
+            xetla_mask<random_len> mask_flag = rand_val < threshold;
+            out_sub.xetla_merge(0, mask_flag.xetla_select<remain_len, 1>(0));
+            mask_sub.xetla_merge(
+                    1, 0, mask_flag.xetla_select<remain_len, 1>(0));
+            out_sub = out_sub * scale;
+        }
+        return output;
+    }
+
+    __XETLA_API xetla_vector<dtype_mask, SZ> get_mask() {
+        return mask;
+    }
+};
+
+/// @} xetla_util_rand
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_load_store.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_load_store.hpp
new file mode 100644
index 00000000000000..12f6317e138035
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_load_store.hpp
@@ -0,0 +1,386 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#include "../../../common/utils/cm/limitation.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#include "common/utils/cm/limitation.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_util_tensor_load_store
+/// @{
+
+/// @} xetla_util_tensor_load_store
+
+/// @addtogroup xetla_util_tensor_load_store
+/// @{
+
+/// @brief Tensor descriptor construction(global memory version).
+/// Constructs a tensor descriptor based on the given arguments.
+/// @tparam Ty is the data type per element.
+/// @tparam block_width is the width of the block to be loaded.
+/// @tparam block_height is the height of the block to be loaded.
+/// @tparam array_len is the array length of the block to be loaded.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param p [in] is the base address pointer of the tensor.
+/// @param tensor_width [in] is the width of the tensor.
+/// @param tensor_height [in] is the height of the tensor.
+/// @param tensor_pitch [in] is the pitch(physical width of tensor in memory).
+/// @param offset_x [in] is the x coordinate of the start point.
+/// @param offset_y [in] is the y coordinate of the start point.
+///
+template <typename Ty, uint32_t block_width = 1, uint32_t block_height = 1,
+        uint8_t array_len = 1>
+__XETLA_API void xetla_fill_tdesc(xetla_tdescriptor_ref tdesc, Ty *p,
+        int tensor_width, int tensor_height, int tensor_pitch, int offset_x,
+        int offset_y) {
+    detail::xetla_set_tensor_base_address(tdesc, (uint64_t)p);
+    detail::xetla_set_tensor_width_x(tdesc, tensor_width * sizeof(Ty) - 1);
+    detail::xetla_set_tensor_width_y(tdesc, tensor_height - 1);
+    detail::xetla_set_tensor_pitch_x(tdesc, tensor_pitch * sizeof(Ty) - 1);
+    detail::xetla_set_tensor_offset_x(tdesc, offset_x);
+    detail::xetla_set_tensor_offset_y(tdesc, offset_y);
+    uint32_t block_widthx_widthy_arrlen = (block_width - 1)
+            | ((block_height - 1) << 8) | ((array_len - 1) << 16);
+    detail::xetla_set_block_widthx_widthy_arrlen(
+            tdesc, block_widthx_widthy_arrlen);
+}
+
+/// @brief Tensor descriptor construction(local memory version).
+/// Constructs a tensor descriptor based on the given arguments, keep the same format as the global memory version.
+/// @tparam Ty is the data type per element.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param base_address [in] is the local memory base address of the tensor.
+/// @param tensor_width [in] is the width of the tensor.
+/// @param tensor_height [in] is the height of the tensor.
+/// @param tensor_pitch [in] is the pitch(physical width of tensor in memory).
+/// @param offset_x [in] is the x coordinate of the start point.
+/// @param offset_y [in] is the y coordinate of the start point.
+///
+template <typename Ty>
+__XETLA_API void xetla_fill_tdesc(xetla_tdescriptor_ref tdesc,
+        uint32_t base_address, int tensor_width, int tensor_height,
+        int tensor_pitch, int offset_x, int offset_y) {
+    detail::xetla_set_tensor_base_address(tdesc, base_address);
+    detail::xetla_set_tensor_width_x(tdesc, tensor_width * sizeof(Ty));
+    detail::xetla_set_tensor_width_y(tdesc, tensor_height);
+    detail::xetla_set_tensor_pitch_x(tdesc, tensor_pitch * sizeof(Ty));
+    detail::xetla_set_tensor_offset_x(tdesc, offset_x);
+    detail::xetla_set_tensor_offset_y(tdesc, offset_y);
+}
+
+/// @brief Generate a new tensor descriptor(global memory version).
+/// Generate a tensor descriptor based on the given arguments.
+/// @tparam Ty is the data type per element.
+/// @tparam block_width is the width of the block to be loaded.
+/// @tparam block_height is the height of the block to be loaded.
+/// @tparam array_len is the array length of the block to be loaded.
+/// @param p [in] is the base address pointer of the tensor.
+/// @param tensor_width [in] is the width of the tensor.
+/// @param tensor_height [in] is the height of the tensor.
+/// @param tensor_pitch [in] is the pitch(physical width of tensor in memory).
+/// @param offset_x [in] is the x coordinate of the start point.
+/// @param offset_y [in] is the y coordinate of the start point.
+/// @return return a new tensor
+///
+template <typename Ty, uint32_t block_width = 1, uint32_t block_height = 1,
+        uint8_t array_len = 1>
+__XETLA_API xetla_tdescriptor xetla_get_tdesc(Ty *p, int tensor_width,
+        int tensor_height, int tensor_pitch, int offset_x, int offset_y) {
+    xetla_tdescriptor tdesc;
+    auto tdesc_ref = tdesc.xetla_format<uint32_t>();
+    detail::xetla_set_tensor_base_address(tdesc_ref, (uint64_t)p);
+    detail::xetla_set_tensor_width_x(tdesc_ref, tensor_width * sizeof(Ty) - 1);
+    detail::xetla_set_tensor_width_y(tdesc_ref, tensor_height - 1);
+    detail::xetla_set_tensor_pitch_x(tdesc_ref, tensor_pitch * sizeof(Ty) - 1);
+    detail::xetla_set_tensor_offset_x(tdesc_ref, offset_x);
+    detail::xetla_set_tensor_offset_y(tdesc_ref, offset_y);
+    uint32_t block_widthx_widthy_arrlen = (block_width - 1)
+            | ((block_height - 1) << 8) | ((array_len - 1) << 16);
+    detail::xetla_set_block_widthx_widthy_arrlen(
+            tdesc_ref, block_widthx_widthy_arrlen);
+    return tdesc;
+}
+
+/// @brief Generate a new tensor descriptor(local memory version).
+/// Constructs a tensor descriptor based on the given arguments, keep the same format as the global memory version.
+/// @tparam Ty is the data type per element.
+/// @param base_address [in] is the local memory base address of the tensor.
+/// @param tensor_width [in] is the width of the tensor.
+/// @param tensor_height [in] is the height of the tensor.
+/// @param tensor_pitch [in] is the pitch(physical width of tensor in memory).
+/// @param offset_x [in] is the x coordinate of the start point.
+/// @param offset_y [in] is the y coordinate of the start point.
+/// @return return a new tensor descriptor
+///
+template <typename Ty>
+__XETLA_API xetla_tdescriptor xetla_get_tdesc(uint32_t base_address,
+        int tensor_width, int tensor_height, int tensor_pitch, int offset_x,
+        int offset_y) {
+    xetla_tdescriptor tdesc;
+    auto tdesc_ref = tdesc.xetla_format<uint32_t>();
+    detail::xetla_set_tensor_base_address(tdesc_ref, base_address);
+    detail::xetla_set_tensor_width_x(tdesc_ref, tensor_width * sizeof(Ty));
+    detail::xetla_set_tensor_width_y(tdesc_ref, tensor_height);
+    detail::xetla_set_tensor_pitch_x(tdesc_ref, tensor_pitch * sizeof(Ty));
+    detail::xetla_set_tensor_offset_x(tdesc_ref, offset_x);
+    detail::xetla_set_tensor_offset_y(tdesc_ref, offset_y);
+    return tdesc;
+}
+
+/// @brief Update the x coordinate in the given tensor descriptor.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param doffset_x [in] is the offset (in number of data elements) in x direction.
+__XETLA_API void xetla_update_tdesc_offsetx(
+        xetla_tdescriptor_ref tdesc, int32_t doffset_x) {
+    detail::xetla_set_tensor_offset_x(
+            tdesc, detail::xetla_get_tensor_offset_x(tdesc) + doffset_x);
+}
+
+/// @brief Update the y coordinate in the given tensor descriptor.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param doffset_y [in] is the offset (in number of data elements) in y direction.
+__XETLA_API void xetla_update_tdesc_offsety(
+        xetla_tdescriptor_ref tdesc, int32_t doffset_y) {
+    detail::xetla_set_tensor_offset_y(
+            tdesc, detail::xetla_get_tensor_offset_y(tdesc) + doffset_y);
+}
+
+/// @brief Update the base in the given tensor descriptor.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param base_offset [in] is the offset to update base address.
+__XETLA_API void xetla_update_tdesc_base_address(
+        xetla_tdescriptor_ref tdesc, int32_t base_offset) {
+    detail::xetla_set_tensor_base_address(
+            tdesc, detail::xetla_get_tensor_base_address(tdesc) + base_offset);
+}
+
+/// @brief Set width in the given tensor descriptor.
+/// @tparam Ty is the data type per element.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param size [in] is the new width.
+template <typename Ty>
+__XETLA_API void xetla_set_tdesc_width(
+        xetla_tdescriptor_ref tdesc, int32_t size) {
+    detail::xetla_set_tensor_width_x(tdesc, size * sizeof(Ty) - 1);
+}
+
+/// @brief Set pitch in the given tensor descriptor.
+/// @tparam Ty is the data type per element.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param size [in] is the new pitch.
+template <typename Ty>
+__XETLA_API void xetla_set_tdesc_pitch(
+        xetla_tdescriptor_ref tdesc, int32_t size) {
+    detail::xetla_set_tensor_pitch_x(tdesc, size * sizeof(Ty) - 1);
+}
+
+/// @brief Set height in the given tensor descriptor.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param size [in] is the new height.
+__XETLA_API void xetla_set_tdesc_height(
+        xetla_tdescriptor_ref tdesc, int32_t size) {
+    detail::xetla_set_tensor_width_y(tdesc, size - 1);
+}
+
+/// @brief mask tdesc load_store op. If mask is 1 tdesc is unchanged. If mask is 0 then using this
+/// tdesc for load would produce zero result, using this tdesc for store preforms no mem update.
+/// @param tdesc [in|out] is the reference of tensor descriptor.
+/// @param mask [in] is the mask.
+__XETLA_API void xetla_tdesc_mask_op(
+        xetla_tdescriptor_ref tdesc, uint16_t mask) {
+    // +1 here since width is -1 encoded in tdesc
+    uint32_t width = detail::xetla_get_tensor_width_x(tdesc) + 1;
+
+    // adding width to offset_x if mask is 0 would produce zero on load and no memory update
+    // on store
+
+    // if mask is 0 then mask-1 is 0xFFFFFFFF and doing & with width update the offset.
+    // if mask is 1 then mask-1 is 0x00000000 and doing & with width keeps tdesc as is.
+    xetla_update_tdesc_offsetx(tdesc, width & (uint32_t)(mask - 1));
+}
+
+///
+/// @brief Tensor load API.
+/// This is tensor load API from global to registers.
+/// @tparam Ty is the data type per element.
+/// @tparam N is the total number of elements to load.
+/// @tparam L1H is L1$ cache hint.
+/// @tparam L2H is L2$ cache hint.
+/// @tparam transpose is a flag to indicate whether the data is transposed during load.
+/// @tparam transform is a flag to indicate whether the data is transformed (data pack inside dword) during load.
+/// @param tdesc [in] is tensor descriptor including tensor base address, tensor dimensions, block size, etc.
+/// @return __XETLA_API xetla_vector is data returned from the load.
+///
+template <typename Ty, uint32_t N, cache_hint L1H = cache_hint::none,
+        cache_hint L2H = cache_hint::none, bool transpose = false,
+        bool transform = false, gpu_arch arch_tag = gpu_arch::Xe>
+__XETLA_API std::enable_if_t<arch_tag == gpu_arch::Xe, xetla_vector<Ty, N>>
+xetla_tload_global(xetla_tdescriptor tdesc) {
+
+    constexpr uint32_t numDst = 31 < ((N * sizeof(Ty) + 63) / 64)
+            ? 31
+            : ((N * sizeof(Ty) + 63) / 64);
+    uint32_t msg_desc = 3;
+    msg_desc |= (transform ? 1 : 0) << 7;
+    msg_desc |= detail::get_element_size_code<sizeof(Ty)>() << 9;
+    msg_desc |= (transpose ? 1 : 0) << 15;
+    msg_desc |= detail::get_load_cache_hint_code<L1H, L2H, arch_tag>() << 17;
+    msg_desc |= 1 << 25;
+    msg_desc |= numDst << 20;
+
+    constexpr uint32_t numSrc0 = 1;
+    constexpr uint32_t execSize = 0;
+    constexpr uint32_t sfid = 0xF;
+    constexpr uint32_t exDesc = 0;
+
+    constexpr uint32_t ret_N = (N * sizeof(Ty)) >= 32 ? N : 32 / sizeof(Ty);
+    xetla_vector<Ty, ret_N> ret;
+
+    xetla_raw_send<Ty, ret_N, uint32_t, 16, execSize, sfid, numSrc0, numDst>(
+            ret.xetla_format<native_type_t<Ty>>(), tdesc, exDesc, msg_desc);
+
+    return ret.xetla_select<N, 1>(0);
+}
+
+///
+/// @brief Tensor store API.
+/// Tensor store API is to store a n-d (e.g. n=2) tensor into global using tensor descriptor.
+/// @tparam Ty is the data type per element.
+/// @tparam N is the number of elements to store.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @param tdesc [in] is tensor descriptor including tensor base address, tensor dimensions, block size, etc.
+/// @param data [in] is tensor data to store.
+/// @return __XETLA_API none.
+///
+template <typename Ty, uint32_t N, cache_hint L1H = cache_hint::none,
+        cache_hint L2H = cache_hint::none, gpu_arch arch_tag = gpu_arch::Xe>
+__XETLA_API std::enable_if_t<arch_tag == gpu_arch::Xe, void>
+xetla_tstore_global(xetla_tdescriptor tdesc, xetla_vector<Ty, N> data) {
+
+    uint32_t msg_desc = 7; // store operation
+    msg_desc |= detail::get_element_size_code<sizeof(Ty)>() << 9;
+    msg_desc |= detail::get_store_cache_hint_code<L1H, L2H, arch_tag>() << 17;
+    msg_desc |= 1 << 25;
+
+    constexpr uint32_t numSrc1 = (N * sizeof(Ty) + 63) / 64;
+    constexpr uint32_t numSrc0 = 1;
+    constexpr uint32_t execSize = 0;
+    constexpr uint32_t sfid = 0xF;
+    constexpr uint32_t exDesc = 0;
+
+    xetla_raw_send<uint32_t, 16, Ty, N, execSize, sfid, numSrc0, numSrc1>(
+            tdesc, data, exDesc, msg_desc);
+}
+
+///
+/// @brief Tensor prefetch API.
+/// This is tensor prefetch API from global memory to L1$/L2$.
+/// @tparam Ty is the data type per element.
+/// @tparam L1H is L1$ cache hit.
+/// @tparam L2H is L2$ cache hit.
+/// @param tdesc is tensor descriptor including tensor base address, tensor dimensions, block size, etc.
+/// @return __XETLA_API none.
+///
+template <typename Ty, cache_hint L1H = cache_hint::cached,
+        cache_hint L2H = cache_hint::cached, gpu_arch arch_tag = gpu_arch::Xe>
+__XETLA_API std::enable_if_t<arch_tag == gpu_arch::Xe, void>
+xetla_tprefetch_global(xetla_tdescriptor tdesc, uint16_t pred = 1) {
+
+    uint32_t msg_desc = 3;
+    msg_desc |= 0 << 7;
+    msg_desc |= detail::get_element_size_code<sizeof(Ty)>() << 9;
+    msg_desc |= 0 << 15;
+    msg_desc |= detail::get_prefetch_cache_hint_code<L1H, L2H, arch_tag>()
+            << 17;
+    msg_desc |= 1 << 25;
+
+    constexpr uint32_t numSrc0 = 1;
+    constexpr uint32_t execSize = 0;
+    constexpr uint32_t sfid = 0xF;
+    constexpr uint32_t exDesc = 0;
+
+    xetla_mask<16> mask = pred;
+
+    xetla_raw_send<uint32_t, 16, execSize, sfid, numSrc0>(
+            tdesc, exDesc, msg_desc, mask);
+}
+
+///
+/// @brief Tensor atomic store API.
+/// Tensor atomic store API is to store a n-d (e.g. n=2) tensor into global.
+/// @tparam Ty is the data type per element.
+/// @tparam N is the number of elements to store.
+/// @tparam L1H is L1 cache hint.
+/// @tparam L2H is L2 cache hint.
+/// @tparam Toffset is the offset data type.
+/// @param base_address [in] is the 64bit base address of the surface.
+/// @param offset [in] is the address offset for each channel, default is 32bits.
+/// @param data [in] is tensor data to store.
+/// @return none.
+///
+template <typename Ty, uint32_t N, cache_hint L1H = cache_hint::none,
+        cache_hint L2H = cache_hint::none, atomic_op Op,
+        gpu_arch arch_tag = gpu_arch::Xe, typename Toffset = uint32_t>
+__XETLA_API std::enable_if_t<arch_tag == gpu_arch::Xe, void>
+xetla_tatomic_store_global(uint64_t base_address,
+        xetla_vector<Toffset, N> offset, xetla_vector<Ty, N> data,
+        xetla_mask<N> pred = 1) {
+
+    constexpr uint32_t numSrc0 = (N * sizeof(uint64_t) + 63) / 64;
+    constexpr uint32_t numSrc1 = (N * sizeof(Ty) + 63) / 64;
+    constexpr uint32_t num_dest = (N * sizeof(Ty) + 63) / 64;
+
+    // disable u16 for now, since there is no usage
+    static_assert(
+            sizeof(Ty) == 4 || sizeof(Ty) == 8, "element_size not supported!");
+    uint32_t element_size_code;
+    if constexpr (sizeof(Ty) == 4) {
+        element_size_code = 2;
+    } else if constexpr (sizeof(Ty) == 8) {
+        element_size_code = 3;
+    }
+
+    uint32_t msg_desc = detail::get_atomic_opcode<Op>();
+    ///only support 64bit address
+    msg_desc |= 3 << 7;
+    msg_desc |= element_size_code << 9;
+    msg_desc |= detail::get_atomic_cache_hint_code<L1H, L2H, arch_tag>() << 17;
+    msg_desc |= numSrc0 << 25;
+
+    constexpr uint32_t execSize = gpu::xetla::detail::get_execSize_code<N>();
+    constexpr uint32_t sfid = 0xF;
+    constexpr uint32_t exDesc = 0;
+
+    xetla_vector<uint64_t, N> address = base_address + offset;
+
+    xetla_raw_send<uint64_t, N, Ty, N, execSize, sfid, numSrc0, numSrc1>(
+            address, data, exDesc, msg_desc, pred);
+}
+
+/// @} xetla_util_tensor_load_store
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_nbarrier.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_nbarrier.hpp
new file mode 100644
index 00000000000000..32773eb3e8e22a
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/raw_send_nbarrier.hpp
@@ -0,0 +1,90 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_util_named_barrier
+/// @{
+
+enum class nbarrier_role : uint8_t {
+    producer_consumer = 0,
+    producer = 1,
+    consumer = 2
+};
+
+///
+/// @brief xetla nbarrier definition API.
+///  This is the API to define a named barrier within subgroup.
+/// @tparam num_producers is the number of subgroups participating the barrier as producer.
+/// @tparam num_consumers is the number of subgroups participating the barrier as consumer.
+///
+template <uint8_t num_producers = 1, uint8_t num_consumers = 1,
+        gpu_arch arch_tag = gpu_arch::Xe>
+struct xetla_nbarrier_t {
+    ///
+    /// @brief Description of named barrier objection.
+    ///
+    xetla_vector<uint32_t, 16> nbar;
+    uint32_t barrier_id;
+
+    /// @param role is the role of subgroup when participating the barrier.
+    /// @param nbarrier_id [in] is the id of the barrier.
+    /// note:  all subgroups participating the barrier should have the same barrier_id.
+    __XETLA_API void init_nbarrier(uint8_t nbarrier_id,
+            nbarrier_role role = nbarrier_role::producer_consumer) {
+        nbar[2] = (uint32_t)nbarrier_id | uint32_t((uint8_t)role << 14)
+                | uint32_t(num_producers << 16) | uint32_t(num_consumers << 24);
+        barrier_id = nbarrier_id;
+    }
+
+    /// @brief named barrier signal from subgroup.
+    /// @param bar is the named barrier object.
+    ///
+    __XETLA_API void arrive() {
+        constexpr uint32_t sfid = 0x3;
+        constexpr uint32_t exDesc = sfid;
+        constexpr uint32_t msg_desc = 0x2000004;
+        constexpr uint32_t execSize = 0;
+
+        xetla_raw_send<uint32_t, 16, execSize, sfid, 1>(nbar, exDesc, msg_desc);
+    }
+
+    /// @brief named barrier wait within subgroup.
+    ///
+    __XETLA_API void wait() { named_barrier_wait(barrier_id); }
+
+    /// @brief named barrier signal from subgroup.
+    ///
+    __XETLA_API void arrive_wait() {
+        arrive();
+        wait();
+    }
+};
+
+/// @} xetla_util_named_barrier
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/tensor_descriptor.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/tensor_descriptor.hpp
new file mode 100644
index 00000000000000..73397231df9c38
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/tensor_descriptor.hpp
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/core/cm/core.hpp"
+#else
+#include "common/core/cm/core.hpp"
+#endif
+
+namespace gpu::xetla {
+
+namespace detail {
+__XETLA_API void xetla_set_tensor_base_address(
+        xetla_tdescriptor_ref desc, uint64_t base_address) {
+    desc.xetla_format<uint64_t>().xetla_select<1, 1>(0) = base_address;
+}
+__XETLA_API void xetla_set_tensor_base_address(
+        xetla_tdescriptor_ref desc, uint32_t base_address) {
+    desc.xetla_format<uint32_t>().xetla_select<1, 1>(0) = base_address;
+}
+__XETLA_API uint64_t xetla_get_tensor_base_address(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint64_t>().xetla_select<1, 1>(0)[0];
+}
+
+__XETLA_API void xetla_set_tensor_width_x(
+        xetla_tdescriptor_ref desc, uint32_t width_x) {
+    desc.xetla_format<uint32_t>().xetla_select<1, 1>(2) = width_x;
+}
+__XETLA_API uint32_t xetla_get_tensor_width_x(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint32_t>().xetla_select<1, 1>(2)[0];
+}
+
+__XETLA_API void xetla_set_tensor_width_y(
+        xetla_tdescriptor_ref desc, uint32_t width_y) {
+    desc.xetla_format<uint32_t>().xetla_select<1, 1>(3) = width_y;
+}
+__XETLA_API uint32_t xetla_get_tensor_width_y(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint32_t>().xetla_select<1, 1>(3)[0];
+}
+
+__XETLA_API void xetla_set_tensor_pitch_x(
+        xetla_tdescriptor_ref desc, uint32_t pitch_x) {
+    desc.xetla_format<uint32_t>().xetla_select<1, 1>(4) = pitch_x;
+}
+__XETLA_API uint32_t xetla_get_tensor_pitch_x(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint32_t>().xetla_select<1, 1>(4)[0];
+}
+
+__XETLA_API void xetla_set_tensor_offset_x(
+        xetla_tdescriptor_ref desc, int32_t offset_x) {
+    desc.xetla_format<int32_t>().xetla_select<1, 1>(5) = offset_x;
+}
+__XETLA_API int32_t xetla_get_tensor_offset_x(xetla_tdescriptor desc) {
+    return desc.xetla_format<int32_t>().xetla_select<1, 1>(5)[0];
+}
+
+__XETLA_API void xetla_set_tensor_offset_y(
+        xetla_tdescriptor_ref desc, int32_t offset_y) {
+    desc.xetla_format<int32_t>().xetla_select<1, 1>(6) = offset_y;
+}
+__XETLA_API int32_t xetla_get_tensor_offset_y(xetla_tdescriptor desc) {
+    return desc.xetla_format<int32_t>().xetla_select<1, 1>(6)[0];
+}
+
+__XETLA_API void xetla_set_block_widthx_widthy_arrlen(
+        xetla_tdescriptor_ref desc, uint32_t block_widthx_widthy_arrlen) {
+    desc.xetla_format<uint32_t>().xetla_select<1, 1>(7)
+            = block_widthx_widthy_arrlen;
+}
+__XETLA_API uint8_t xetla_get_block_width_x(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint8_t>().xetla_select<1, 1>(28)[0];
+}
+__XETLA_API uint8_t xetla_get_block_width_y(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint8_t>().xetla_select<1, 1>(29)[0];
+}
+__XETLA_API uint8_t xetla_get_block_array_len(xetla_tdescriptor desc) {
+    return desc.xetla_format<uint8_t>().xetla_select<1, 1>(30)[0];
+}
+} // namespace detail
+
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/utils.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/utils.hpp
new file mode 100644
index 00000000000000..f6346ec9ef544e
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/utils.hpp
@@ -0,0 +1,65 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#pragma once
+
+/// @defgroup xetla_util XeTLA Utility
+/// This is low level API wrapper for utility functions.
+/// Including the tensor prefetch/load/store API based on xetla_raw_send, simd_lane id generation API and so on.
+
+/// @addtogroup xetla_util
+/// @{
+
+/// @defgroup xetla_util_tensor_load_store Tensor load store API
+/// Implements the tensor load store functionality using raw send instructions.
+
+/// @defgroup xetla_util_misc Util misc API
+/// Implements some useful and commonly used APIs, such as vector generation API.
+
+/// @defgroup xetla_util_rand Random number generator API
+/// Philox rng, will generate 4 uint32_t random number per call.
+
+/// @defgroup xetla_util_group XeTLA Group
+/// This is a group API to define operation scope.
+
+/// @defgroup xetla_util_named_barrier Named barrier API
+/// This is a raw_send based named barrier API.
+
+/// @} xetla_util
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#include "../../../common/utils/cm/dict.hpp"
+#include "../../../common/utils/cm/fastmath.hpp"
+#include "../../../common/utils/cm/memory_descriptor.hpp"
+#include "../../../common/utils/cm/misc.hpp"
+#include "../../../common/utils/cm/nd_item.hpp"
+#include "../../../common/utils/cm/rand.hpp"
+#include "../../../common/utils/cm/raw_send_load_store.hpp"
+#include "../../../common/utils/cm/raw_send_nbarrier.hpp"
+#include "../../../common/utils/cm/work_group.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#include "common/utils/cm/dict.hpp"
+#include "common/utils/cm/fastmath.hpp"
+#include "common/utils/cm/memory_descriptor.hpp"
+#include "common/utils/cm/misc.hpp"
+#include "common/utils/cm/nd_item.hpp"
+#include "common/utils/cm/rand.hpp"
+#include "common/utils/cm/raw_send_load_store.hpp"
+#include "common/utils/cm/raw_send_nbarrier.hpp"
+#include "common/utils/cm/work_group.hpp"
+#endif
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/work_group.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/work_group.hpp
new file mode 100644
index 00000000000000..7929dcdd18ff7e
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/cm/work_group.hpp
@@ -0,0 +1,56 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#ifdef _WIN32
+#include "../../../common/utils/cm/common.hpp"
+#else
+#include "common/utils/cm/common.hpp"
+#endif
+
+namespace gpu::xetla {
+
+/// @addtogroup xetla_util_group
+/// @{
+
+/// @brief Define a workgroup scope for a specific problem shape.
+/// The size of the workgroup should <= group size.
+/// @tparam size_ Is the number of subgroups within a workgroup.
+template <uint32_t size_>
+struct work_group_t {
+private:
+    uint32_t sg_id;
+
+public:
+    static constexpr uint32_t size = size_;
+    __XETLA_API constexpr uint32_t get_size() { return size; }
+    __XETLA_API uint32_t get_id() { return sg_id; }
+    __XETLA_API void init(uint32_t id) { sg_id = id; }
+    inline work_group_t(uint32_t id) : sg_id(id) {}
+    inline work_group_t() = default;
+    template <uint32_t scope_size>
+    __XETLA_API work_group_t<scope_size> partition() {
+        work_group_t<scope_size> wtile;
+        wtile.init(sg_id % scope_size);
+        return wtile;
+    }
+};
+/// @} xetla_util_group
+} // namespace gpu::xetla
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/utils.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/utils.hpp
new file mode 100644
index 00000000000000..b6ef776ee06bb3
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/common/utils/utils.hpp
@@ -0,0 +1 @@
+#include "../../common/utils/cm/utils.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/cooperative_reduction.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/cooperative_reduction.hpp
new file mode 100644
index 00000000000000..dc44f076871a60
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/cooperative_reduction.hpp
@@ -0,0 +1,221 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/tile_shape.hpp"
+#include "subgroup/subgroup.hpp"
+
+namespace gpu::xetla::group {
+
+/// @brief Workgroups to do the cooperative reduction.
+/// @tparam reduce_kind Is the reduction type.
+/// @tparam tile_shape Is the group-level tile shape.
+/// @tparam matAcc_t Is the input mat type.
+/// @tparam num_cooperative_wg Is the number of workgroups to do the cooperation.
+/// @tparam arch_tag Is the HW architecture.
+template <reduce_op reduce_kind, typename tile_shape, typename matAcc_t,
+        uint32_t num_cooperative_wg, gpu_arch arch_tag,
+        mem_space space_ = mem_space::local, class enable = void>
+class cooperative_reduce_t {};
+
+/// @brief Workgroups to do the cooperative reduction. Specialized for Xe architecture.
+template <reduce_op reduce_kind, typename tile_shape_, typename matAcc_t,
+        uint32_t num_cooperative_wg, gpu_arch arch_tag_>
+class cooperative_reduce_t<reduce_kind, tile_shape_, matAcc_t,
+        num_cooperative_wg, arch_tag_, mem_space::local,
+        std::enable_if_t<((arch_tag_ == gpu_arch::Xe))
+                && (tile_shape_::dim == 2)>> {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    using tile_shape = tile_shape_;
+    using dtype = typename matAcc_t::dtype;
+
+private:
+    static constexpr uint32_t sg_tile_m = tile_shape::sg_tile_size_y;
+    static constexpr uint32_t sg_tile_n = tile_shape::sg_tile_size_x;
+    static constexpr uint32_t wg_size_x = tile_shape::wg_size_x;
+    static constexpr uint32_t wg_size_y = tile_shape::wg_size_y;
+    static constexpr uint32_t real_wg_tile_m = sg_tile_m * wg_size_y;
+    static constexpr uint32_t real_wg_tile_n = sg_tile_n * wg_size_x;
+
+    static constexpr uint32_t wg_tile_size
+            = real_wg_tile_m * real_wg_tile_n * sizeof(dtype);
+    using work_group_t = typename tile_shape::work_group_t;
+    static constexpr uint32_t work_group_size = work_group_t::size;
+    // cooperative split, y dir first
+    static_assert((num_cooperative_wg & (num_cooperative_wg - 1)) == 0,
+            "num_cooperative_wg should be power of 2");
+
+public:
+    static constexpr uint32_t coop_num_y
+            = gpu::xetla::subgroup::detail::gcd<num_cooperative_wg,
+                    sg_tile_m>::value;
+    static constexpr uint32_t coop_remain_num_x
+            = num_cooperative_wg / coop_num_y;
+    static constexpr bool has_redundant_wg
+            = (coop_remain_num_x * 16) > sg_tile_n;
+    static constexpr uint32_t tile_size_y = sg_tile_m / coop_num_y;
+    static constexpr uint32_t tile_size_x
+            = has_redundant_wg ? 16 : sg_tile_n / coop_remain_num_x;
+    static constexpr uint32_t coop_num_x = sg_tile_n / tile_size_x;
+    static constexpr uint32_t num_reduce_wg = coop_num_x * coop_num_y;
+
+private:
+    static constexpr uint32_t src_block_size_x = matAcc_t::block_size_x;
+    static constexpr uint32_t src_block_size_y = matAcc_t::block_size_y;
+
+    static constexpr uint32_t block_size_x
+            = gpu::xetla::subgroup::detail::gcd<tile_size_x,
+                    src_block_size_x>::value;
+    static constexpr uint32_t block_size_y
+            = (tile_size_y > src_block_size_y) ? src_block_size_y : tile_size_y;
+
+    using local_st_tile_desc_t = subgroup::tile_desc_t<sg_tile_n, sg_tile_m,
+            src_block_size_x, src_block_size_y, reg_layout::tiled>;
+    using local_st_tile_t = subgroup::tile_t<dtype, local_st_tile_desc_t>;
+    using local_st_payload_t = subgroup::mem_payload_t<
+            mem_desc_t<dtype, mem_layout::row_major, mem_space::local>,
+            local_st_tile_desc_t,
+            subgroup::msg_type_v<local_st_tile_desc_t, mem_space::local>,
+            arch_tag>;
+    using local_ld_tile_desc_t = subgroup::tile_desc_t<tile_size_x, tile_size_y,
+            block_size_x, block_size_y, reg_layout::tiled>;
+    using local_ld_tile_t = subgroup::tile_t<dtype, local_ld_tile_desc_t>;
+    using local_ld_payload_t = subgroup::mem_payload_t<
+            mem_desc_t<dtype, mem_layout::row_major, mem_space::local>,
+            local_ld_tile_desc_t,
+            subgroup::msg_type_v<local_ld_tile_desc_t, mem_space::local>,
+            arch_tag>;
+
+public:
+    using mat_slice_t = subgroup::tile_t<dtype, local_ld_tile_desc_t>;
+
+    static constexpr uint32_t barrier_count = work_group_size;
+    static constexpr uint32_t slm_size = wg_tile_size * num_cooperative_wg;
+
+    uint32_t coop_id;
+    uint32_t coop_id_x;
+    uint32_t coop_id_y;
+    inline cooperative_reduce_t(uint32_t coop_id_) : coop_id(coop_id_) {
+        coop_id_x = coop_id % coop_remain_num_x;
+        coop_id_y = coop_id / coop_remain_num_x;
+    }
+    inline bool is_valid_post_process_wg() { return coop_id_x < coop_num_x; }
+
+    /// @brief Cooperative workgroup reduction.
+    /// 1) each workgroup stores tile data to local memory ->
+    /// 2) cross workgroup (but still within a group) sync ->
+    /// 3) workgroups loads slice of tile data, do the reduction.
+    /// @note only workgroups with coop_id_x < coop_num_x have valid data.
+    /// @param g Is the workgroup of the current tile.
+    /// @param mat_slice Is the output of the reduction. Each workgroup only keeps part of the tile data.
+    /// @param matAcc Is the input of the reduction.
+    /// @param slm_base Is the slm base address.
+    /// @param nbarrier_base Is the named barrier base.
+    inline KERNEL_FUNC void operator()(work_group_t &g, mat_slice_t &mat_slice,
+            matAcc_t &matAcc, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        uint32_t sg_idx = g.get_id() % wg_size_x;
+        uint32_t sg_idy = g.get_id() / wg_size_x;
+
+        int32_t slm_store_offset_x = sg_idx * sg_tile_n;
+        int32_t slm_store_offset_y
+                = coop_id * real_wg_tile_m + sg_idy * sg_tile_m;
+        local_st_tile_t local_st;
+        local_st_payload_t local_st_payload(slm_base, real_wg_tile_n,
+                real_wg_tile_m * num_cooperative_wg, real_wg_tile_n,
+                slm_store_offset_x, slm_store_offset_y);
+        local_st.reg = matAcc.reg;
+        tile_store(local_st, local_st_payload);
+
+        xetla_nbarrier_t<num_cooperative_wg, num_cooperative_wg, arch_tag>
+                nbarrier;
+        uint32_t nbar_id = nbarrier_base + g.get_id();
+        nbarrier.init_nbarrier(nbar_id, nbarrier_role::producer_consumer);
+        xetla_fence<memory_kind::shared_local>();
+        nbarrier.arrive();
+        nbarrier.wait();
+
+        if (is_valid_post_process_wg()) {
+            // nbarrier.init_nbarrier(nbar_id, nbarrier_role::consumer);
+            // nbarrier.arrive();
+            int32_t slm_load_offset_x
+                    = sg_idx * sg_tile_n + coop_id_x * tile_size_x;
+            int32_t slm_load_offset_y
+                    = sg_idy * sg_tile_m + coop_id_y * tile_size_y;
+
+            local_ld_tile_t local_ld;
+            local_ld_payload_t local_ld_payload(slm_base, real_wg_tile_n,
+                    real_wg_tile_m * num_cooperative_wg, real_wg_tile_n,
+                    slm_load_offset_x, slm_load_offset_y);
+
+            tile_load(local_ld, local_ld_payload);
+            mat_slice.reg = local_ld.reg;
+#pragma unroll
+            for (int i = 1; i < num_cooperative_wg; i++) {
+                local_ld_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                        real_wg_tile_m);
+                tile_load(local_ld, local_ld_payload);
+                mat_slice.reg = reduce_helper<reduce_kind, dtype>(
+                        mat_slice.reg, local_ld.reg);
+            }
+        }
+    }
+};
+
+/// @brief Workgroups to do the cooperative reduction.
+/// Specialized for Xe architecture with 1 workgroups.
+template <reduce_op reduce_kind, typename tile_shape_, typename matAcc_t,
+        gpu_arch arch_tag_>
+class cooperative_reduce_t<reduce_kind, tile_shape_, matAcc_t, 1, arch_tag_,
+        mem_space::local,
+        std::enable_if_t<((arch_tag_ == gpu_arch::Xe))
+                && (tile_shape_::dim == 2)>> {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    using tile_shape = tile_shape_;
+    using dtype = typename matAcc_t::dtype;
+
+private:
+    using work_group_t = typename tile_shape::work_group_t;
+
+public:
+    using mat_slice_t = matAcc_t;
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = 0;
+    static constexpr uint32_t coop_num_x = 1;
+    static constexpr uint32_t coop_num_y = 1;
+    uint32_t coop_id;
+    uint32_t coop_id_x;
+    uint32_t coop_id_y;
+    inline cooperative_reduce_t(uint32_t coop_id_) {
+        coop_id = 0;
+        coop_id_x = 0;
+        coop_id_y = 0;
+    }
+    inline bool is_valid_post_process_wg() { return true; }
+
+    inline KERNEL_FUNC void operator()(work_group_t &g, mat_slice_t &mat_slice,
+            matAcc_t &matAcc, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        mat_slice.reg = matAcc.reg;
+    }
+};
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/api.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/api.hpp
new file mode 100644
index 00000000000000..c6b560b0d23c37
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/api.hpp
@@ -0,0 +1,39 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/epilogue/common.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_epilogue
+/// @{
+
+/// @brief Is the epilogue functor.
+/// @tparam epilogue_policy Is the epilogue policy.
+/// @tparam tile_shape Is the workgroup-level tile shape.
+/// @tparam mem_desc_c Is the memory descriptor of matC.
+template <typename epilogue_policy, typename tile_shape, typename mem_desc_c,
+        class enable = void>
+class epilogue_t {};
+
+/// @} xetla_epilogue
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/common.hpp
new file mode 100644
index 00000000000000..6b488decb09f37
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/common.hpp
@@ -0,0 +1,32 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/tile_shape.hpp"
+#include "subgroup/subgroup.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_epilogue
+/// @{
+
+/// @} xetla_epilogue
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue.hpp
new file mode 100644
index 00000000000000..33498d748707e0
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue.hpp
@@ -0,0 +1,30 @@
+
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+/// @defgroup xetla_epilogue XeTLA EPILOGUE
+/// This is a epilogue API to compute matC = tile_op(matAcc).
+
+#include "group/epilogue/api.hpp"
+#include "group/epilogue/common.hpp"
+#include "group/epilogue/epilogue_policy.hpp"
+#include "group/epilogue/impl/tile_op_xe.hpp"
+#include "group/tile_shape.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue_policy.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue_policy.hpp
new file mode 100644
index 00000000000000..88f1e52d79a20d
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/epilogue_policy.hpp
@@ -0,0 +1,40 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/epilogue/common.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_epilogue
+/// @{
+
+/// @brief Epilogue policy for tile_op + store C fusion.
+/// @tparam tile_op_t_ Is the tile_op functor.
+/// @tparam arch_tag_ Is the HW architecture.
+template <typename tile_op_t_, gpu_arch arch_tag_>
+struct epilogue_policy_tile_op {
+    using tile_op_t = tile_op_t_;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+};
+
+/// @} xetla_epilogue
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/impl/tile_op_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/impl/tile_op_xe.hpp
new file mode 100644
index 00000000000000..5376009508ab09
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/epilogue/impl/tile_op_xe.hpp
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/epilogue/api.hpp"
+#include "group/epilogue/common.hpp"
+#include "group/epilogue/epilogue_policy.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_epilogue
+/// @{
+
+/// @brief Is the epilogue functor specialized for epilogue_policy_tile_op and Xe architecture.
+template <typename tile_op_t_, typename tile_shape_, typename mem_desc_c_t_,
+        gpu_arch arch_tag_>
+class epilogue_t<epilogue_policy_tile_op<tile_op_t_, arch_tag_>, tile_shape_,
+        mem_desc_c_t_, std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+public:
+    using epilogue_policy = epilogue_policy_tile_op<tile_op_t_, arch_tag_>;
+    using tile_op_t = typename epilogue_policy::tile_op_t;
+    using tile_shape = tile_shape_;
+    using mem_desc_c_t = mem_desc_c_t_;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = mem_desc_c_t::is_local
+            ? tile_shape::wg_tile_size_x * tile_shape::wg_tile_size_y
+            : 0;
+
+    /// @brief Epilogue arguments.
+    struct arguments_t {
+        /// @brief Is tile_op arguments, could be a single
+        /// tile_op argument or chained_tile_op_args.
+        typename tile_op_t::arguments_t tile_op_args;
+
+        /// @brief Constructs a new arguments t object.
+        inline arguments_t() = default;
+
+        /// @brief Constructs a new arguments t object.
+        /// @param tile_op_args_ Is tile_op arguments, could be a single
+        /// tile_op argument or chained_tile_op_args.
+        inline arguments_t(typename tile_op_t::arguments_t tile_op_args_)
+            : tile_op_args(tile_op_args_) {}
+        // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+        // Please check if you need to add self-define destructor
+        // inline ~arguments_t(){}
+        inline arguments_t(const arguments_t &args)
+            : tile_op_args(args.tile_op_args) {}
+
+        inline arguments_t &operator=(const arguments_t &args) {
+            this->tile_op_args = args.tile_op_args;
+            return *this;
+        }
+
+        /// @brief Explicit initialization function.
+        /// @param tile_op_args_ Is tile_op arguments, could be a single
+        /// tile_op argument or chained_tile_op_args.
+        inline void init(typename tile_op_t::arguments_t tile_op_args_) {
+            tile_op_args = tile_op_args_;
+        }
+    };
+
+private:
+    using work_group_t = typename tile_shape::work_group_t;
+    static constexpr uint32_t sg_tile_m = tile_shape::sg_tile_size_y;
+    static constexpr uint32_t sg_tile_n = tile_shape::sg_tile_size_x;
+    static constexpr uint32_t wg_size_x = tile_shape::wg_size_x;
+    static constexpr uint32_t wg_size_y = tile_shape::wg_size_y;
+    using dtype_c = typename mem_desc_c_t::dtype;
+    static constexpr mem_layout mem_layout_c = mem_desc_c_t::layout;
+    static constexpr mem_space mem_space_c = mem_desc_c_t::space;
+
+    /// @brief Updates tile base descriptor based on the tid.
+    __XETLA_API static void update_sg_tile_tdesc(
+            work_group_t &g, mem_desc_c_t &mem_desc_c) {
+        int32_t sg_idx = g.get_id() % wg_size_x;
+        int32_t sg_idy = g.get_id() / wg_size_x;
+        int32_t tile_offset_n = sg_idx * sg_tile_n;
+        int32_t tile_offset_m = sg_idy * sg_tile_m;
+        mem_desc_c.update_coord(tile_offset_n, tile_offset_m);
+    }
+
+public:
+    static constexpr msg_type msg_type_c
+            = (mem_space_c == mem_space::global ? msg_type::block_2d
+                                                : msg_type::scatter);
+
+    /// @brief Default epilogue.
+    /// 1) Call tile_op/chained_tile_op 2) Convert dtype_acc to dtype_c
+    /// 3) Overwrite/reduce_sum to memory.
+    /// @tparam matAcc_t Is the type of the input tile.
+    /// @param g Is the workgroup of the current tile.
+    /// @param matAcc Is the input tile.
+    /// @param mem_desc_c Is the memory description of matC, including base, shape and coordinate.
+    /// @param args Is the additional arguments for epilogue.
+    /// @param slm_base Is the slm base address.
+    /// @param nbarrier_base Is the named barrier base.
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(work_group_t &g, matAcc_t &matAcc,
+            mem_desc_c_t mem_desc_c, arguments_t args = {},
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using mat_tile_desc = typename matAcc_t::tile_desc;
+        using matC_t = subgroup::tile_t<dtype_c, mat_tile_desc>;
+        using matC_payload_t = subgroup::mem_payload_t<mem_desc_c_t,
+                mat_tile_desc, msg_type_c, arch_tag>;
+        update_sg_tile_tdesc(g, mem_desc_c);
+        tile_op_t tile_op;
+        tile_op(matAcc, mem_desc_c.coord, args.tile_op_args, slm_base,
+                nbarrier_base);
+        matC_t matC;
+        matC_payload_t matC_payload(mem_desc_c);
+        subgroup::elemwise_cvt(matC, matAcc);
+        subgroup::tile_store<cache_hint::streaming, cache_hint::write_back>(
+                matC, matC_payload);
+    }
+};
+
+/// @} xetla_epilogue
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/api.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/api.hpp
new file mode 100644
index 00000000000000..56fcca4265e2e8
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/api.hpp
@@ -0,0 +1,80 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/gemm/common.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_gemm
+/// @{
+
+/// @brief Gemm default pre_processing functor.
+/// @tparam tile_shape Is the workgroup-level tile shape.
+/// @tparam arch_tag Is the HW architecture.
+template <typename tile_shape, gpu_arch arch_tag, class enable = void>
+struct pre_processing_default_t {};
+
+/// @brief Gemm pre_processing functor with applying relu op to matA.
+/// @tparam tile_shape Is the workgroup-level tile shape.
+/// @tparam arch_tag Is the HW architecture.
+template <typename tile_shape, gpu_arch arch_tag, class enable = void>
+struct pre_processing_matA_neg_filter_t {};
+
+/// @brief Gemm functor.
+/// @tparam compute_policy Is the compute algorithm of gemm implementation.
+/// @tparam tile_shape Is the workgroup-level tile shape.
+/// @tparam mem_desc_a Is the memory descriptor of matA.
+/// @tparam mem_desc_b Is the memory descriptor of matB.
+/// @tparam pre_processing Is the pre_processing functor.
+template <typename compute_policy, typename tile_shape, typename mem_desc_a,
+        typename mem_desc_b,
+        typename pre_processing
+        = pre_processing_default_t<tile_shape, compute_policy::arch_tag>,
+        typename mem_desc_as = void, typename mem_desc_bs = void,
+        class enable = void>
+class gemm_t {};
+
+/// @brief Gemm selection functor.
+/// @tparam dtype_a Is the memory data type of matA.
+/// @tparam dtype_b Is the memory data type of matB.
+/// @tparam mem_layout_a Is the memory layout of matA.
+/// @tparam mem_layout_b Is the memory layout of matB.
+/// @tparam mem_space_a Is the memory space of matA.
+/// @tparam mem_space_b Is the memory space of matB.
+/// @tparam alignment_a Is the memory alignment of matA.
+/// @tparam alignment_b Is the memory alignment of matB.
+/// @tparam dtype_acc Is the compute data type.
+/// @tparam tile_shape Is the workgroup-level tile shape.
+/// @tparam k_stride Is the accumulate stride along k-dim.
+/// @tparam engine Is the compute engine type.
+/// @tparam arch_tag Is the HW architecture.
+/// @tparam stages Is the prefetch distance.
+/// @tparam sync_freq Is the group sync frequency.
+template <typename dtype_a, typename dtype_b, mem_layout mem_layout_a,
+        mem_layout mem_layout_b, mem_space mem_space_a, mem_space mem_space_b,
+        int alignment_a, int alignment_b, typename dtype_acc,
+        typename tile_shape, int k_stride, mma_engine engine, gpu_arch arch_tag,
+        int stages = 3, int sync_freq = 0, class enable = void>
+class gemm_selector_t {};
+
+/// @} xetla_gemm
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/common.hpp
new file mode 100644
index 00000000000000..505907a55e03fe
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/common.hpp
@@ -0,0 +1,66 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "common/common.hpp"
+#include "subgroup/subgroup.hpp"
+
+namespace gpu::xetla::group {
+
+/// @brief Compute attribute for gemm.
+/// @tparam dtype_a_ Is the memory data type of matA.
+/// @tparam dtype_b_ Is the memory data type of matB.
+/// @tparam dtype_acc_ Is the compute data type.
+template <typename dtype_a_, typename dtype_b_, typename dtype_acc_,
+        typename dtype_aci_ = void, typename dtype_as_ = void,
+        typename dtype_bs_ = void, typename dtype_cs_ = void>
+struct compute_attr_t {
+    using dtype_a = dtype_a_;
+    using dtype_b = dtype_b_;
+    using dtype_acc = dtype_acc_;
+    using dtype_aci = dtype_aci_;
+    using dtype_as = dtype_as_;
+    using dtype_bs = dtype_bs_;
+    using dtype_cs = dtype_cs_;
+};
+
+/// @brief Fine-tune knobs for gemm.
+/// @tparam k_stride_ Is the accumulate stride along k-dim.
+/// @tparam stages_ Is the prefetch distance.
+/// @tparam sync_freq_ Is the group sync frequency.
+template <int k_stride_ = 8, int stages_ = 3, int sync_freq_ = 0>
+struct perf_tuning_knob_t {
+    static constexpr int k_stride = k_stride_;
+    static constexpr int stages = stages_;
+    static constexpr int sync_freq = sync_freq_;
+};
+
+template <typename mem_desc_t_a, typename tile_shape_t,
+        typename perf_tuning_knob_>
+constexpr bool is_slm_trans_a() {
+    return (mem_desc_t_a::layout == mem_layout::col_major)
+            //only for 8bit and 16bit
+            && (sizeof(typename mem_desc_t_a::dtype) <= sizeof(uint16_t)
+                    && (tile_shape_t::sg_tile_size_y % 16 == 0)
+                    && (perf_tuning_knob_::is_slm_transa)
+                    && (tile_shape_t::wg_size_x > 1));
+}
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/compute_policy.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/compute_policy.hpp
new file mode 100644
index 00000000000000..297d6eb90a72fe
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/compute_policy.hpp
@@ -0,0 +1,103 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/gemm/common.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_gemm
+/// @{
+
+/// @brief Compute policy for xmx engine.
+/// @tparam compute_attr_ Is compute-related attributes.
+/// @tparam perf_tuning_knob_ Is performance-related knobs.
+/// @tparam arch_tag_ Is the HW architecture.
+template <typename compute_attr_, typename perf_tuning_knob_,
+        gpu_arch arch_tag_>
+struct compute_policy_default_xmx {};
+
+/// @brief Specialized for Xe architecture.
+template <typename compute_attr_, typename perf_tuning_knob_>
+struct compute_policy_default_xmx<compute_attr_, perf_tuning_knob_,
+        gpu_arch::Xe> {
+    using compute_attr = compute_attr_;
+    using perf_tuning_knob = perf_tuning_knob_;
+    static constexpr int k_stride = perf_tuning_knob::k_stride;
+    static constexpr int stages = perf_tuning_knob::stages;
+    static constexpr int sync_freq = perf_tuning_knob::sync_freq;
+    static constexpr gpu_arch arch_tag = gpu_arch::Xe;
+    using dtype_mma_acc = typename compute_attr::dtype_acc;
+    using dtype_mma_a = typename compute_attr::dtype_a;
+    using dtype_mma_b = typename compute_attr::dtype_b;
+
+    using mma_attr = typename arch_attr_t<arch_tag>::mma_attr;
+
+    static constexpr uint32_t mma_k_in_bytes = mma_attr::mma_k_in_bytes;
+    static constexpr uint32_t mma_n_in_elem = mma_attr::mma_n_in_elem;
+
+    static constexpr uint32_t block_bytes_x_a = mma_k_in_bytes;
+    static constexpr uint32_t block_size_x_a
+            = block_bytes_x_a / sizeof(dtype_mma_a);
+    static constexpr uint32_t block_size_y_a = 16;
+
+    static constexpr uint32_t block_size_x_b = mma_n_in_elem;
+    static constexpr uint32_t block_bytes_y_b = mma_k_in_bytes;
+    static constexpr uint32_t block_size_y_b
+            = block_bytes_y_b / sizeof(dtype_mma_b);
+    static_assert(block_size_x_a == block_size_y_b,
+            "mat_a x need to match with mat_b y");
+};
+
+/// @brief Compute policy for fpu engine.
+/// @tparam compute_attr_ Is compute-related attributes.
+/// @tparam perf_tuning_knob_ Is performance-related knobs.
+/// @tparam arch_tag_ Is the HW architecture.
+template <typename compute_attr_, typename perf_tuning_knob_,
+        gpu_arch arch_tag_>
+struct compute_policy_default_fpu {};
+
+/// @brief Specialized for Xe architecture.
+template <typename compute_attr_, typename perf_tuning_knob_>
+struct compute_policy_default_fpu<compute_attr_, perf_tuning_knob_,
+        gpu_arch::Xe> {
+    using compute_attr = compute_attr_;
+    using perf_tuning_knob = perf_tuning_knob_;
+    static constexpr int k_stride = perf_tuning_knob::k_stride;
+    static constexpr int stages = perf_tuning_knob::stages;
+    static constexpr int sync_freq = perf_tuning_knob::sync_freq;
+    static constexpr gpu_arch arch_tag = gpu_arch::Xe;
+    using dtype_mma_acc = typename compute_attr::dtype_acc;
+    using dtype_mma_a = typename compute_attr::dtype_a;
+    using dtype_mma_b = typename compute_attr::dtype_b;
+
+    static constexpr uint32_t block_bytes_x_a = 32;
+    static constexpr uint32_t block_size_x_a
+            = block_bytes_x_a / sizeof(dtype_mma_a);
+    static constexpr uint32_t block_size_y_a = 16;
+    static constexpr uint32_t block_bytes_x_b = 64;
+    static constexpr uint32_t block_size_x_b
+            = block_bytes_x_b / sizeof(dtype_mma_b);
+    static constexpr uint32_t block_size_y_b = block_size_x_a;
+};
+
+/// @} xetla_gemm
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/gemm.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/gemm.hpp
new file mode 100644
index 00000000000000..10a54116427135
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/gemm.hpp
@@ -0,0 +1,32 @@
+
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+/// @defgroup xetla_gemm XeTLA GEMM
+/// This is a gemm API to compute matAcc = matA * matB.
+
+#include "group/gemm/api.hpp"
+#include "group/gemm/common.hpp"
+#include "group/gemm/compute_policy.hpp"
+#include "group/gemm/impl/default_xmx_xe.hpp"
+#include "group/gemm/impl/pre_processing_xe.hpp"
+#include "group/gemm/impl/selector_xe.hpp"
+#include "group/tile_shape.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/default_xmx_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/default_xmx_xe.hpp
new file mode 100644
index 00000000000000..e95442b2c0c440
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/default_xmx_xe.hpp
@@ -0,0 +1,370 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/gemm/api.hpp"
+#include "group/gemm/compute_policy.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_gemm
+/// @{
+
+/// @brief Is the gemm functor for Xe architecture and matrix engine.
+template <typename compute_attr_, typename perf_tuning_knob_,
+        typename tile_shape_, typename mem_desc_a_t_, typename mem_desc_b_t_,
+        typename pre_processing_t_, gpu_arch arch_tag_>
+class gemm_t<
+        compute_policy_default_xmx<compute_attr_, perf_tuning_knob_, arch_tag_>,
+        tile_shape_, // tile shape of workgroup-level gemm
+        mem_desc_a_t_, // memory attribute of matA
+        mem_desc_b_t_, // memory attribute of matB
+        pre_processing_t_, // pre_processing functor
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+public:
+    using mem_desc_a_t = mem_desc_a_t_;
+    using mem_desc_b_t = mem_desc_b_t_;
+    using tile_shape = tile_shape_;
+    using pre_processing_t = pre_processing_t_;
+    using compute_policy = compute_policy_default_xmx<compute_attr_,
+            perf_tuning_knob_, arch_tag_>;
+    static constexpr uint32_t k_stride = compute_policy::k_stride;
+    static constexpr uint32_t sg_tile_m = tile_shape::sg_tile_size_y;
+    static constexpr uint32_t sg_tile_n = tile_shape::sg_tile_size_x;
+    static constexpr uint32_t wg_size_x = tile_shape::wg_size_x;
+    static constexpr uint32_t wg_size_y = tile_shape::wg_size_y;
+    using work_group_t = typename tile_shape::work_group_t;
+
+    constexpr static gpu_arch arch_tag = compute_policy::arch_tag;
+
+    static constexpr mem_layout mem_layout_a = mem_desc_a_t::layout;
+    static constexpr mem_layout mem_layout_b = mem_desc_b_t::layout;
+    static constexpr bool is_col_major_a
+            = mem_layout_a == mem_layout::col_major;
+    static constexpr bool is_col_major_b
+            = mem_layout_b == mem_layout::col_major;
+
+private:
+    /******** set data type **********/
+    using dtype_a = typename mem_desc_a_t::dtype;
+    using dtype_b = typename mem_desc_b_t::dtype;
+    using dtype_mma_acc = typename compute_policy::dtype_mma_acc;
+    using dtype_mma_a = typename compute_policy::dtype_mma_a;
+    using dtype_mma_b = typename compute_policy::dtype_mma_b;
+
+    using check_dtype
+            = group::gemm<gpu_arch::Xe>::default_xmx::check_dtype_default<
+                    dtype_a, dtype_b, dtype_mma_a, dtype_mma_b>;
+
+    /******** set memory attribute **********/
+    static constexpr mem_space mem_space_a = mem_desc_a_t::space;
+    static constexpr mem_space mem_space_b = mem_desc_b_t::space;
+
+    static constexpr bool is_local_a = mem_space_a == mem_space::local;
+    static constexpr bool is_local_b = mem_space_b == mem_space::local;
+    static constexpr tdesc_update_dir update_dir_a = is_col_major_a
+            ? tdesc_update_dir::y_dir
+            : tdesc_update_dir::x_dir;
+    static constexpr tdesc_update_dir update_dir_b = is_col_major_b
+            ? tdesc_update_dir::x_dir
+            : tdesc_update_dir::y_dir;
+
+    using check_memory
+            = group::gemm<gpu_arch::Xe>::default_xmx::check_memory_default<
+                    mem_layout_a, mem_layout_b, mem_space_a, mem_space_b>;
+
+    static constexpr uint32_t stages = compute_policy::stages;
+    static constexpr uint32_t sync_freq = compute_policy::sync_freq;
+
+    /******** set tile layout && worker scope **********/
+    static constexpr uint32_t tile_size_x_a = k_stride;
+    static constexpr uint32_t tile_size_y_a = sg_tile_m;
+    static constexpr uint32_t tile_size_x_b = sg_tile_n;
+    static constexpr uint32_t tile_size_y_b = k_stride;
+    static constexpr uint32_t tile_size_x_c = sg_tile_n;
+    static constexpr uint32_t tile_size_y_c = sg_tile_m;
+    static constexpr uint32_t block_size_x_a = compute_policy::block_size_x_a;
+    static constexpr uint32_t block_size_y_a
+            = (compute_policy::block_size_y_a > tile_size_y_a)
+            ? tile_size_y_a
+            : compute_policy::block_size_y_a;
+    static constexpr uint32_t block_size_x_b = compute_policy::block_size_x_b;
+    static constexpr uint32_t block_size_y_b = compute_policy::block_size_y_b;
+
+    using check_tile_size = group::gemm<
+            gpu_arch::Xe>::default_xmx::check_tile_size_default<dtype_mma_a,
+            tile_size_x_a, tile_size_y_a, block_size_x_a, block_size_y_a,
+            tile_size_x_b, tile_size_y_b, block_size_x_b, block_size_y_b>;
+
+    /******** set tile  **********/
+    static constexpr reg_layout reg_layout_a = reg_layout::tiled;
+    using matA_tile_desc_t = subgroup::tile_desc_t<tile_size_x_a, tile_size_y_a,
+            block_size_x_a, block_size_y_a, reg_layout_a>;
+    using matA_t = subgroup::tile_t<dtype_a, matA_tile_desc_t>;
+    using matA_payload_t = subgroup::mem_payload_t<mem_desc_a_t,
+            matA_tile_desc_t,
+            is_local_a ? msg_type::scatter : msg_type::block_2d, arch_tag>;
+    using matA_acc_t = subgroup::tile_t<dtype_mma_a, matA_tile_desc_t>;
+    using matA_prefetch_payload_t = subgroup::prefetch_payload_t<mem_desc_a_t,
+            subgroup::tile_desc_t<tile_size_x_a, tile_size_y_a, 1, 1>,
+            wg_size_x, arch_tag>;
+    static constexpr reg_layout reg_layout_b
+            = sizeof(dtype_b) < sizeof(uint32_t) ? reg_layout::vnni_tiled
+                                                 : reg_layout::tiled;
+    using matB_tile_desc_t = subgroup::tile_desc_t<tile_size_x_b, tile_size_y_b,
+            block_size_x_b, block_size_y_b, reg_layout_b>;
+    using matB_t = subgroup::tile_t<dtype_b, matB_tile_desc_t>;
+    using matB_payload_t = subgroup::mem_payload_t<mem_desc_b_t,
+            matB_tile_desc_t,
+            is_local_b ? msg_type::scatter : msg_type::block_2d, arch_tag>;
+    using matB_acc_t = subgroup::tile_t<dtype_mma_b, matB_tile_desc_t>;
+    using matB_prefetch_payload_t = subgroup::prefetch_payload_t<mem_desc_b_t,
+            subgroup::tile_desc_t<tile_size_x_b, tile_size_y_b, 1, 1>,
+            wg_size_y, arch_tag>;
+
+public:
+    using matAcc_tile_desc_t = subgroup::tile_desc_t<tile_size_x_c,
+            tile_size_y_c, block_size_x_b, block_size_y_a, reg_layout::tiled>;
+    using matAcc_t = subgroup::tile_t<dtype_mma_acc, matAcc_tile_desc_t>;
+
+private:
+    using tile_mma = subgroup::tile_mma_t<matAcc_t, matAcc_t, matB_acc_t,
+            matA_acc_t, mma_engine::xmx, arch_tag>;
+    static constexpr bool enable_periodic_sync = (sync_freq != 0);
+    static constexpr uint32_t barrier_count_x = wg_size_y > 1 ? wg_size_x : 0;
+    static constexpr uint32_t barrier_count_y = wg_size_x > 1 ? wg_size_y : 0;
+
+public:
+    static constexpr uint32_t barrier_count
+            = enable_periodic_sync ? barrier_count_x + barrier_count_y : 0;
+
+    static constexpr uint32_t slm_size = 0;
+
+    static constexpr msg_type msg_type_a = matA_payload_t::message_type;
+    static constexpr msg_type msg_type_b = matB_payload_t::message_type;
+
+    using pre_processing_arg_t = typename pre_processing_t::arguments_t;
+
+    /// @brief Arguments for gemm.
+    /// User should prepare matA_base_desc, matB_base_desc, inner_loop_count...
+    struct arguments_t {
+        /// @brief Is the memory description of matA, including base, shape and coordinate.
+        mem_desc_a_t matA_base_desc;
+        /// @brief Is the memory description of matB, including base, shape and coordinate.
+        mem_desc_b_t matB_base_desc;
+        /// @brief Is the total inner loop count required to compute the entire K-dim.
+        uint32_t inner_loop_count;
+        /// @brief Is the arguments for pre-processing functor.
+        pre_processing_arg_t pre_processing_args;
+
+        /// @brief Default construct.
+        inline arguments_t() = default;
+
+        /// @brief Constructs a new arguments t object.
+        /// @param matA_desc Is the memory description of matA, including base, shape and coordinate.
+        /// @param matB_desc Is the memory description of matB, including base, shape and coordinate.
+        /// @param loop_count Is the total inner loop count required to compute the entire K-dim.
+        /// @param args Is the arguments for pre-processing functor.
+        inline arguments_t(mem_desc_a_t matA_desc, mem_desc_b_t matB_desc,
+                uint32_t loop_count, pre_processing_arg_t args = {})
+            : matA_base_desc(matA_desc)
+            , matB_base_desc(matB_desc)
+            , inner_loop_count(loop_count)
+            , pre_processing_args(args) {}
+        // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+        // Please check if you need to add self-define destructor
+        // inline ~arguments_t(){}
+        inline arguments_t(const arguments_t &args)
+            : matA_base_desc(args.matA_base_desc)
+            , matB_base_desc(args.matB_base_desc)
+            , inner_loop_count(args.inner_loop_count)
+            , pre_processing_args(args.pre_processing_args) {}
+        inline arguments_t &operator=(const arguments_t &args) {
+            this->matA_base_desc = args.matA_base_desc;
+            this->matB_base_desc = args.matB_base_desc;
+            this->inner_loop_count = args.inner_loop_count;
+            this->pre_processing_args = args.pre_processing_args;
+            return *this;
+        }
+
+        /// @brief Explicit initialization function.
+        /// @param matA_desc Is the memory description of matA, including base, shape and coordinate.
+        /// @param matB_desc Is the memory description of matB, including base, shape and coordinate.
+        /// @param loop_count Is the total inner loop count required to compute the entire K-dim.
+        /// @param args Is the arguments for pre-processing functor.
+        inline void init(mem_desc_a_t matA_desc, mem_desc_b_t matB_desc,
+                uint32_t loop_count, pre_processing_arg_t args = {}) {
+            matA_base_desc = matA_desc;
+            matB_base_desc = matB_desc;
+            inner_loop_count = loop_count;
+            pre_processing_args = args;
+        }
+    };
+
+    /// @brief Gets the subgroup-level tile offset x.
+    /// @param g Is the workgroup of the current tile.
+    /// @return Subgroup-level tile offset x.
+    __XETLA_API static int get_matC_offset_x(work_group_t &g) {
+        int32_t sg_idx = g.get_id() % wg_size_x;
+        return sg_idx * sg_tile_n;
+    }
+
+    /// @brief Gets the subgroup-level tile offset y.
+    /// @param g Is the workgroup of the current tile.
+    /// @return Subgroup-level tile offset y.
+    __XETLA_API static int get_matC_offset_y(work_group_t &g) {
+        int32_t sg_idy = g.get_id() / wg_size_x;
+        return sg_idy * sg_tile_m;
+    }
+
+    XETLA_MARKER(
+            "This release function will wait until all the  r/w and nbarrier "
+            "id used in this gemm have been committed. By default, it will "
+            "use barrier_id 0 to do the entire workgroup sync if wg_size > 1. "
+            "If you call this function, please set a free barrier id or make "
+            "sure barrier_id 0 is not being occupied and you need to allocate "
+            "one more barrier count in addition to the gemm barrier counts.")
+    __XETLA_API static void release(uint8_t nbarrier_id = 0) {
+        static constexpr bool need_local_fence
+                = (mem_space_a == mem_space::local)
+                || (mem_space_b == mem_space::local);
+        if constexpr (need_local_fence) {
+            xetla_fence<memory_kind::shared_local>();
+        }
+        xetla_fence<memory_kind::untyped_global>();
+        static constexpr uint32_t wg_size = wg_size_x * wg_size_y;
+        if constexpr (wg_size > 1) {
+            xetla_nbarrier_t<wg_size, wg_size, arch_tag> nbarrier;
+            nbarrier.init_nbarrier(
+                    nbarrier_id, nbarrier_role::producer_consumer);
+            nbarrier.arrive_wait();
+        }
+    }
+
+    /// @brief Main execution function for gemm.
+    /// The basic process is load data -> matrix multiply.
+    /// @param g Is the workgroup of the current tile.
+    /// @param matAcc Is the reference of the accumulation buffer.
+    /// @param args Is the gemm::arguments_t.
+    /// @param slm_base Is the slm base address.
+    /// @param nbarrier_base Is the named barrier base.
+    __XETLA_API KERNEL_FUNC void operator()(work_group_t &g, matAcc_t &matAcc,
+            arguments_t args, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        int32_t sg_idx = g.get_id() % wg_size_x;
+        int32_t sg_idy = g.get_id() / wg_size_x;
+
+        XETLA_ASSERT(g.get_id() < (wg_size_x * wg_size_y),
+                "Thread id(%d) should less than wg_size(%d)", g.get_id(),
+                wg_size_x * wg_size_y);
+
+        update_sg_tile_tdesc(args, sg_idx, sg_idy);
+        pre_processing_t pre_processing;
+        matA_t matA;
+        matB_t matB;
+        //  >>>>>>>>>>>>>>>>>> pre_processing init
+        pre_processing.init(g, args.pre_processing_args);
+        matA_payload_t matA_payload(args.matA_base_desc);
+        matB_payload_t matB_payload(args.matB_base_desc);
+        matA_prefetch_payload_t matA_prefetch_payload(
+                args.matA_base_desc, sg_idx);
+        matB_prefetch_payload_t matB_prefetch_payload(
+                args.matB_base_desc, sg_idy);
+        xetla_nbarrier_t<wg_size_x, wg_size_x, arch_tag> nbarrier_a;
+        nbarrier_a.init_nbarrier(
+                sg_idy + nbarrier_base, nbarrier_role::producer_consumer);
+        xetla_nbarrier_t<wg_size_y, wg_size_y, arch_tag> nbarrier_b;
+        nbarrier_b.init_nbarrier(sg_idx + barrier_count_y + nbarrier_base,
+                nbarrier_role::producer_consumer);
+
+#pragma unroll
+        for (int i = 0; i < stages; i++) {
+            subgroup::tile_prefetch<cache_hint::cached, cache_hint::cached>(
+                    matA_prefetch_payload);
+            subgroup::tile_prefetch<cache_hint::cached, cache_hint::cached>(
+                    matB_prefetch_payload);
+            matA_prefetch_payload.template update_tdesc<update_dir_a>(
+                    matA_t::tile_size_x);
+            matB_prefetch_payload.template update_tdesc<update_dir_b>(
+                    matB_t::tile_size_y);
+        }
+
+        for (int i = 0; i < args.inner_loop_count; i++) {
+            if constexpr (enable_periodic_sync) {
+                if ((i % sync_freq) == 0) {
+                    if constexpr (wg_size_x > 1) { nbarrier_a.arrive(); }
+                    if constexpr (wg_size_y > 1) { nbarrier_b.arrive(); }
+                }
+            }
+            subgroup::tile_load<cache_hint::cached, cache_hint::cached>(
+                    matB, matB_payload);
+            subgroup::tile_load<cache_hint::cached, cache_hint::cached>(
+                    matA, matA_payload);
+            if constexpr (stages != 0) {
+                subgroup::tile_prefetch<cache_hint::cached, cache_hint::cached>(
+                        matA_prefetch_payload);
+                subgroup::tile_prefetch<cache_hint::cached, cache_hint::cached>(
+                        matB_prefetch_payload);
+            }
+            SW_BARRIER();
+            matA_payload.template update_tdesc<update_dir_a>(
+                    matA_t::tile_size_x);
+            matB_payload.template update_tdesc<update_dir_b>(
+                    matB_t::tile_size_y);
+            if constexpr (stages != 0) {
+                matA_prefetch_payload.template update_tdesc<update_dir_a>(
+                        matA_t::tile_size_x);
+                matB_prefetch_payload.template update_tdesc<update_dir_b>(
+                        matB_t::tile_size_y);
+            }
+            SW_BARRIER();
+            matA_acc_t matA_acc;
+            matB_acc_t matB_acc;
+            subgroup::elemwise_cvt(matA_acc, matA);
+            subgroup::vnni_transform(matB_acc, matB);
+            pre_processing(matA_acc, matB_acc, matA, matB);
+            SW_BARRIER();
+            tile_mma::mma(matAcc, matAcc, matB_acc, matA_acc);
+            SW_BARRIER();
+            if constexpr (enable_periodic_sync) {
+                if ((i % sync_freq) == 0) {
+                    if constexpr (wg_size_x > 1) { nbarrier_a.wait(); }
+                    if constexpr (wg_size_y > 1) { nbarrier_b.wait(); }
+                }
+            }
+        }
+        SW_BARRIER();
+    }
+
+private:
+    /// @brief Updates tile base descriptor based on the tid.
+    __XETLA_API static void update_sg_tile_tdesc(
+            arguments_t &args, int32_t sg_idx, int32_t sg_idy) {
+        int32_t tile_offset_n = sg_idx * sg_tile_n;
+        int32_t tile_offset_m = sg_idy * sg_tile_m;
+
+        args.matA_base_desc.update_coord_y(tile_offset_m);
+        args.matB_base_desc.update_coord_x(tile_offset_n);
+    }
+};
+
+/// @} xetla_gemm
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/pre_processing_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/pre_processing_xe.hpp
new file mode 100644
index 00000000000000..9a871cbad11862
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/pre_processing_xe.hpp
@@ -0,0 +1,54 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/gemm/api.hpp"
+#include "group/gemm/common.hpp"
+
+namespace gpu::xetla::group {
+
+/// @addtogroup xetla_gemm
+/// @{
+
+/// @brief gemm default pre_processing functor. Specialized for Xe architecture.
+template <typename tile_shape_, gpu_arch arch_tag>
+class pre_processing_default_t<tile_shape_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using tile_shape = tile_shape_;
+    using work_group_t = typename tile_shape::work_group_t;
+
+public:
+    struct arguments_t {};
+
+    inline pre_processing_default_t() = default;
+
+    inline pre_processing_default_t(work_group_t &g, arguments_t &args) {}
+
+    inline void init(work_group_t &g, arguments_t &args) {}
+
+    template <typename matA_acc_t, typename matB_acc_t, typename matA_t,
+            typename matB_t>
+    inline KERNEL_FUNC void operator()(matA_acc_t &matA_acc,
+            matB_acc_t &matB_acc, matA_t &matA, matB_t &matB) {}
+};
+
+/// @} xetla_gemm
+
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/selector_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/selector_xe.hpp
new file mode 100644
index 00000000000000..0548386ab960a8
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/gemm/impl/selector_xe.hpp
@@ -0,0 +1,74 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/gemm/api.hpp"
+#include "group/gemm/compute_policy.hpp"
+
+namespace gpu::xetla::group {
+namespace detail {
+
+template <typename dtype_a, typename dtype_b, int alignment_a, int alignment_b,
+        gpu_arch arch_tag>
+class check_2d_block_pitch_alignment {
+    using load_store_attr = typename arch_attr_t<
+            arch_tag>::template load_store_attr<msg_type::block_2d>;
+    static constexpr int alignment_bytes = load_store_attr::alignment_in_bytes;
+    static constexpr int alignment_bytes_a = alignment_a * sizeof(dtype_a);
+    static constexpr int alignment_bytes_b = alignment_b * sizeof(dtype_b);
+
+public:
+    static constexpr bool value = (alignment_bytes_a % alignment_bytes == 0)
+            && (alignment_bytes_b % alignment_bytes == 0);
+};
+
+} // namespace detail
+
+/// @addtogroup xetla_gemm
+/// @{
+
+/// @brief Selects 2d block && xmx based gemm.
+template <typename dtype_a, typename dtype_b, mem_layout mem_layout_a,
+        mem_layout mem_layout_b, mem_space mem_space_a, mem_space mem_space_b,
+        int alignment_a, int alignment_b, typename dtype_acc,
+        typename tile_shape, int k_stride, gpu_arch arch_tag, int stages,
+        int sync_freq>
+class gemm_selector_t<dtype_a, dtype_b, mem_layout_a, mem_layout_b, mem_space_a,
+        mem_space_b, alignment_a, alignment_b, dtype_acc, tile_shape, k_stride,
+        mma_engine::xmx, arch_tag, stages, sync_freq,
+        std::enable_if_t<detail::check_2d_block_pitch_alignment<dtype_a,
+                dtype_b, alignment_a, alignment_b, arch_tag>::value>> {
+    using mem_desc_a
+            = mem_desc_t<dtype_a, mem_layout_a, mem_space_a, alignment_a>;
+    using mem_desc_b
+            = mem_desc_t<dtype_b, mem_layout_b, mem_space_b, alignment_b>;
+    using compute_attr = compute_attr_t<dtype_a, dtype_b, dtype_acc>;
+    using perf_tuning_knob = perf_tuning_knob_t<k_stride, stages, sync_freq>;
+    using compute_policy = compute_policy_default_xmx<compute_attr,
+            perf_tuning_knob, arch_tag>;
+    using pre_processing = pre_processing_default_t<tile_shape, arch_tag>;
+
+public:
+    using gemm = gemm_t<compute_policy, tile_shape, mem_desc_a, mem_desc_b,
+            pre_processing>;
+};
+
+/// @} xetla_gemm
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/global_reduction.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/global_reduction.hpp
new file mode 100644
index 00000000000000..2f93c4b40c8069
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/global_reduction.hpp
@@ -0,0 +1,460 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/tile_shape.hpp"
+#include "subgroup/subgroup.hpp"
+
+namespace gpu::xetla::group {
+
+/// @brief Cross group global reduction.
+/// @tparam reduce_kind Is the reduction type.
+/// @tparam tile_shape_acc Is the group-level tile shape for accumulation tile.
+/// @tparam tile_shape_cnt Is the group-level tile shape for counter tile.
+/// @tparam mem_desc_acc_t Is the memory descriptor of accumulation buffer.
+/// @tparam mem_desc_cnt_t Is the memory descriptor of counter buffer.
+/// @tparam num_group_reduction Is the number of workgroups to do the reduction.
+/// @tparam counter_size Is the stride to the next counter.
+/// @tparam arch_tag Is the HW architecture.
+template <reduce_op reduce_kind, typename tile_shape_acc,
+        typename tile_shape_cnt, typename mem_desc_acc_t,
+        typename mem_desc_cnt_t, uint32_t num_group_reduction,
+        uint32_t counter_size, gpu_arch arch_tag, class enable = void>
+class global_reduce_t {};
+
+/// @brief Cross group global reduction. Specialized for reduce_op::sum and Xe architecture.
+template <typename tile_shape_acc_, typename tile_shape_cnt_,
+        typename mem_desc_acc_t_, typename mem_desc_cnt_t_,
+        uint32_t num_group_reduction, uint32_t counter_size, gpu_arch arch_tag_>
+class global_reduce_t<reduce_op::sum, tile_shape_acc_, tile_shape_cnt_,
+        mem_desc_acc_t_, mem_desc_cnt_t_, num_group_reduction, counter_size,
+        arch_tag_,
+        std::enable_if_t<((arch_tag_ == gpu_arch::Xe))
+                && (tile_shape_acc_::dim == 2)>> {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    using tile_shape_acc = tile_shape_acc_;
+    using tile_shape_cnt = tile_shape_cnt_;
+    using mem_desc_acc_t = mem_desc_acc_t_;
+    using mem_desc_cnt_t = mem_desc_cnt_t_;
+    using dtype_acc = typename mem_desc_acc_t::dtype;
+    using dtype_cnt = typename mem_desc_cnt_t::dtype;
+
+private:
+    static constexpr uint32_t acc_sg_tile_y = tile_shape_acc::sg_tile_size_y;
+    static constexpr uint32_t acc_sg_tile_x = tile_shape_acc::sg_tile_size_x;
+    static constexpr uint32_t cnt_sg_tile_y = tile_shape_cnt::sg_tile_size_y;
+    static constexpr uint32_t cnt_sg_tile_x = tile_shape_cnt::sg_tile_size_x;
+    static constexpr uint32_t wg_size_x = tile_shape_acc::wg_size_x;
+    static constexpr uint32_t wg_size_y = tile_shape_acc::wg_size_y;
+    static_assert((tile_shape_acc::wg_size_x == tile_shape_cnt::wg_size_x)
+                    && (tile_shape_acc::wg_size_y == tile_shape_cnt::wg_size_y),
+            "acc and cnt wg shape need to be matched");
+    using work_group_t = typename tile_shape_acc::work_group_t;
+
+    /// @brief Updates tile base descriptor based on the tid.
+    inline void update_sg_tile_tdesc(work_group_t &g,
+            mem_desc_acc_t &mem_desc_acc, mem_desc_cnt_t &mem_desc_cnt) {
+        int32_t sg_idx = g.get_id() % wg_size_x;
+        int32_t sg_idy = g.get_id() / wg_size_x;
+        int32_t acc_tile_offset_x = sg_idx * acc_sg_tile_x;
+        int32_t acc_tile_offset_y = sg_idy * acc_sg_tile_y;
+        mem_desc_acc.update_coord(acc_tile_offset_x, acc_tile_offset_y);
+        int32_t cnt_tile_offset_x = sg_idx * cnt_sg_tile_x;
+        int32_t cnt_tile_offset_y = sg_idy * cnt_sg_tile_y;
+        mem_desc_cnt.update_coord(cnt_tile_offset_x, cnt_tile_offset_y);
+    }
+
+    inline uint32_t update_reduce_counter(mem_desc_cnt_t &mem_desc_cnt) {
+        constexpr uint32_t SIMD = 16;
+        uint32_t pitch_in_bytes = mem_desc_cnt.shape.stride_x
+                * sizeof(dtype_cnt) * counter_size;
+        uint32_t offset_x = mem_desc_cnt.coord.x;
+        uint32_t offset_y = mem_desc_cnt.coord.y;
+        uint64_t address = (uint64_t)mem_desc_cnt.base.base
+                + offset_y * pitch_in_bytes
+                + offset_x * sizeof(dtype_cnt) * counter_size;
+        xetla_vector<uint32_t, SIMD> offsets
+                = xetla_vector_gen<uint32_t, SIMD>(0, 1);
+        offsets *= sizeof(dtype_cnt);
+        xetla_mask<SIMD> pred(0);
+        pred[0] = 1;
+        xetla_vector<dtype_cnt, SIMD> ret = xetla_atomic_global<atomic_op::iinc,
+                dtype_cnt, SIMD, data_size::default_size, cache_hint::uncached,
+                cache_hint::write_back>((dtype_cnt *)address, offsets, pred);
+        return ret[0];
+    }
+
+    inline void clean_reduce_counter(mem_desc_cnt_t &mem_desc_cnt) {
+        uint32_t pitch_in_bytes = mem_desc_cnt.shape.stride_x
+                * sizeof(dtype_cnt) * counter_size;
+        uint32_t offset_x = mem_desc_cnt.coord.x;
+        uint32_t offset_y = mem_desc_cnt.coord.y;
+        uint64_t address = (uint64_t)mem_desc_cnt.base.base
+                + offset_y * pitch_in_bytes
+                + offset_x * sizeof(dtype_cnt) * counter_size;
+        xetla_vector<dtype_cnt, 1> zeros(0);
+
+        xetla_store_global<dtype_cnt, 1, data_size::default_size,
+                cache_hint::uncached, cache_hint::write_back>(
+                (dtype_cnt *)address, 0, zeros);
+    }
+
+public:
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = 0;
+    uint32_t reduce_id = 0;
+
+    inline bool is_last_group() {
+        return reduce_id == (num_group_reduction - 1);
+    }
+
+    /// @brief Global reduction.
+    /// 1) each group stores tile data to global memory by using global atomic add ->
+    /// 2) after reduction complete, update the counter by using atomic inc ->
+    /// 3) the last group load the data back to EU, and clean the accumulation buffer and counter buffer.
+    /// @note only the last group has the valid data.
+    /// @param g Is the workgroup of the current tile.
+    /// @param matAcc Is the input of the reduction.
+    /// @param mem_desc_acc Is the memory descriptor of accumulation buffer.
+    /// @param mem_desc_cnt Is the memory descriptor of counter buffer.
+    /// @param slm_base Is the slm base address.
+    /// @param nbarrier_base Is the named barrier base.
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(work_group_t &g, matAcc_t &matAcc,
+            mem_desc_acc_t mem_desc_acc, mem_desc_cnt_t mem_desc_cnt,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        static_assert(std::is_same<typename matAcc_t::dtype, dtype_acc>::value,
+                "matAcc_t::dtype should match with dtype_acc");
+        update_sg_tile_tdesc(g, mem_desc_acc, mem_desc_cnt);
+        using matAcc_tile_desc_t = typename matAcc_t::tile_desc;
+        using matAcc_store_payload_t = subgroup::mem_payload_t<mem_desc_acc_t,
+                matAcc_tile_desc_t, msg_type::atomic_add, arch_tag>;
+        matAcc_store_payload_t matAcc_store_payload(mem_desc_acc);
+        subgroup::tile_store<cache_hint::uncached, cache_hint::write_back>(
+                matAcc, matAcc_store_payload);
+        xetla_fence<memory_kind::untyped_global, fence_op::none,
+                fence_scope::tile>();
+        reduce_id = update_reduce_counter(mem_desc_cnt);
+        if (reduce_id == (num_group_reduction - 1)) {
+            using matAcc_payload_t = subgroup::mem_payload_t<mem_desc_acc_t,
+                    matAcc_tile_desc_t, msg_type::block_2d, arch_tag>;
+            matAcc_payload_t matAcc_payload(mem_desc_acc);
+            subgroup::tile_load(matAcc, matAcc_payload);
+            clean_reduce_counter(mem_desc_cnt);
+            using mat_zero_t = subgroup::tile_t<dtype_acc, matAcc_tile_desc_t>;
+            mat_zero_t mat_zero;
+            mat_zero.reg = 0;
+            subgroup::tile_store<cache_hint::uncached, cache_hint::write_back>(
+                    mat_zero, matAcc_payload);
+            SW_BARRIER();
+        }
+    }
+};
+
+/// @brief Cross group global reduction. Specialized for num_group_reduction=1 and Xe architecture.
+template <typename tile_shape_acc_, typename tile_shape_cnt_,
+        typename mem_desc_acc_t_, typename mem_desc_cnt_t_,
+        uint32_t counter_size_, gpu_arch arch_tag_>
+class global_reduce_t<reduce_op::sum, tile_shape_acc_, tile_shape_cnt_,
+        mem_desc_acc_t_, mem_desc_cnt_t_, 1, counter_size_, arch_tag_,
+        std::enable_if_t<((arch_tag_ == gpu_arch::Xe))
+                && (tile_shape_acc_::dim == 2)>> {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    using tile_shape_acc = tile_shape_acc_;
+    using tile_shape_cnt = tile_shape_cnt_;
+    using mem_desc_acc_t = mem_desc_acc_t_;
+    using mem_desc_cnt_t = mem_desc_cnt_t_;
+    using dtype_acc = typename mem_desc_acc_t::dtype;
+
+private:
+    using work_group_t = typename tile_shape_acc::work_group_t;
+
+public:
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = 0;
+    inline bool is_last_group() { return true; }
+
+    template <typename matAcc_t>
+    inline KERNEL_FUNC void operator()(work_group_t &g, matAcc_t &matAcc,
+            mem_desc_acc_t mem_desc_acc, mem_desc_cnt_t mem_desc_cnt,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {}
+};
+
+/// @brief Cross group global reduction. Specialized for reduce_op::sum and 4 dimensional tiles
+template <typename tile_shape_acc_, typename tile_shape_cnt_,
+        typename mem_desc_acc_t_, typename mem_desc_cnt_t_,
+        uint32_t num_group_reduction, uint32_t counter_size, gpu_arch arch_tag_>
+class global_reduce_t<reduce_op::sum, tile_shape_acc_, tile_shape_cnt_,
+        mem_desc_acc_t_, mem_desc_cnt_t_, num_group_reduction, counter_size,
+        arch_tag_,
+        std::enable_if_t<((arch_tag_ == gpu_arch::Xe))
+                && (tile_shape_acc_::dim == 4)>> {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    using tile_shape_acc = tile_shape_acc_;
+    using tile_shape_cnt = tile_shape_cnt_;
+    using mem_desc_acc_t = mem_desc_acc_t_;
+    using mem_desc_cnt_t = mem_desc_cnt_t_;
+    using dtype_acc = typename mem_desc_acc_t::dtype;
+    using dtype_cnt = typename mem_desc_cnt_t::dtype;
+
+private:
+    static constexpr uint32_t acc_sg_tile_n = tile_shape_acc::sg_tile_size_n;
+    static constexpr uint32_t acc_sg_tile_p = tile_shape_acc::sg_tile_size_p;
+    static constexpr uint32_t acc_sg_tile_q = tile_shape_acc::sg_tile_size_q;
+    static constexpr uint32_t acc_sg_tile_k = tile_shape_acc::sg_tile_size_k;
+
+    static constexpr uint32_t wg_size_n = tile_shape_acc::wg_size_n;
+    static constexpr uint32_t wg_size_p = tile_shape_acc::wg_size_p;
+    static constexpr uint32_t wg_size_q = tile_shape_acc::wg_size_q;
+    static constexpr uint32_t wg_size_k = tile_shape_acc::wg_size_k;
+
+    static constexpr uint32_t cnt_sg_tile_n = tile_shape_cnt::sg_tile_size_n;
+    static constexpr uint32_t cnt_sg_tile_p = tile_shape_cnt::sg_tile_size_p;
+    static constexpr uint32_t cnt_sg_tile_q = tile_shape_cnt::sg_tile_size_q;
+    static constexpr uint32_t cnt_sg_tile_k = tile_shape_cnt::sg_tile_size_k;
+
+    static_assert((tile_shape_acc::wg_size_n == tile_shape_cnt::wg_size_n),
+            "acc and cnt wg_szie_n shape need to be matched");
+    static_assert((tile_shape_acc::wg_size_p == tile_shape_cnt::wg_size_p),
+            "acc and cnt wg_szie_n shape need to be matched");
+    static_assert((tile_shape_acc::wg_size_q == tile_shape_cnt::wg_size_q),
+            "acc and cnt wg_szie_n shape need to be matched");
+    static_assert((tile_shape_acc::wg_size_k == tile_shape_cnt::wg_size_k),
+            "acc and cnt wg_szie_n shape need to be matched");
+
+    static_assert((tile_shape_acc::wg_size_n == tile_shape_cnt::wg_size_n)
+                    && (tile_shape_acc::wg_size_p == tile_shape_cnt::wg_size_p)
+                    && (tile_shape_acc::wg_size_q == tile_shape_cnt::wg_size_q)
+                    && (tile_shape_acc::wg_size_k == tile_shape_cnt::wg_size_k),
+            "acc and cnt wg shape need to be matched");
+    using work_group_t = typename tile_shape_acc::work_group_t;
+
+    /// @brief Updates tile base descriptor based on the tid.
+    inline void update_sg_tile_tdesc(work_group_t &g,
+            mem_desc_acc_t &mem_desc_acc, mem_desc_cnt_t &mem_desc_cnt) {
+        int32_t sg_idk = g.get_id() % wg_size_k;
+        int32_t sg_idq = (g.get_id() / wg_size_k) % wg_size_q;
+        int32_t sg_idp = (g.get_id() / (wg_size_k * wg_size_q)) % wg_size_p;
+        int32_t sg_idn = (g.get_id() / (wg_size_k * wg_size_q * wg_size_p))
+                % wg_size_n;
+
+        int32_t acc_tile_offset_n = sg_idn * acc_sg_tile_n;
+        int32_t acc_tile_offset_p = sg_idp * acc_sg_tile_p;
+        int32_t acc_tile_offset_q = sg_idq * acc_sg_tile_q;
+        int32_t acc_tile_offset_k = sg_idk * acc_sg_tile_k;
+        mem_desc_acc.update_coord(acc_tile_offset_k, acc_tile_offset_q,
+                acc_tile_offset_p, acc_tile_offset_n);
+
+        int32_t cnt_tile_offset_n = sg_idn * cnt_sg_tile_n;
+        int32_t cnt_tile_offset_p = sg_idp * cnt_sg_tile_p;
+        int32_t cnt_tile_offset_q = sg_idq * cnt_sg_tile_q;
+        int32_t cnt_tile_offset_k = sg_idk * cnt_sg_tile_k;
+        mem_desc_cnt.update_coord(cnt_tile_offset_k, cnt_tile_offset_q,
+                cnt_tile_offset_p, cnt_tile_offset_n);
+    }
+
+    inline uint32_t update_reduce_counter(mem_desc_cnt_t &mem_desc_cnt) {
+        constexpr uint32_t SIMD = 16;
+        mem_shape_t<4> shape = mem_desc_cnt.shape;
+        mem_coord_t<4> coord = mem_desc_cnt.coord;
+
+        uint32_t pitch_in_bytes
+                = shape.stride_x * sizeof(dtype_cnt) * counter_size;
+        uint32_t offset_x = coord.x;
+
+        uint32_t offset_y = coord.w * shape.stride_z * shape.stride_y
+                + coord.z * shape.stride_y + coord.y;
+        uint64_t address = (uint64_t)mem_desc_cnt.base.base
+                + offset_y * pitch_in_bytes
+                + offset_x * sizeof(dtype_cnt) * counter_size;
+        xetla_vector<uint32_t, SIMD> offsets
+                = xetla_vector_gen<uint32_t, SIMD>(0, 1);
+        offsets *= sizeof(dtype_cnt);
+        xetla_mask<SIMD> pred(0);
+        pred[0] = 1;
+        xetla_vector<dtype_cnt, SIMD> ret = xetla_atomic_global<atomic_op::iinc,
+                dtype_cnt, SIMD, data_size::default_size, cache_hint::uncached,
+                cache_hint::write_back>((dtype_cnt *)address, offsets, pred);
+
+        return ret[0];
+    }
+
+    inline void clean_reduce_counter(mem_desc_cnt_t &mem_desc_cnt) {
+        mem_shape_t<4> shape = mem_desc_cnt.shape;
+        mem_coord_t<4> coord = mem_desc_cnt.coord;
+
+        uint32_t pitch_in_bytes
+                = shape.stride_x * sizeof(dtype_cnt) * counter_size;
+        uint32_t offset_x = coord.x;
+
+        uint32_t offset_y = coord.w * shape.stride_z * shape.stride_y
+                + coord.z * shape.stride_y + coord.y;
+        uint64_t address = (uint64_t)mem_desc_cnt.base.base
+                + offset_y * pitch_in_bytes
+                + offset_x * sizeof(dtype_cnt) * counter_size;
+        xetla_vector<dtype_cnt, 1> zeros(0);
+
+        xetla_store_global<dtype_cnt, 1, data_size::default_size,
+                cache_hint::uncached, cache_hint::write_back>(
+                (dtype_cnt *)address, 0, zeros);
+    }
+
+public:
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = 0;
+    uint32_t reduce_id = 0;
+
+    inline bool is_last_group() {
+        return reduce_id == (num_group_reduction - 1);
+    }
+
+    /// @brief Global reduction.
+    /// 1) each group stores tile data to global memory by using global atomic add ->
+    /// 2) after reduction complete, update the counter by using atomic inc ->
+    /// 3) the last group load the data back to EU, and clean the accumulation buffer and counter buffer.
+    /// @note only the last group has the valid data.
+    /// @param g Is the workgroup of the current tile.
+    /// @param matAcc Is the input of the reduction.
+    /// @param mem_desc_acc Is the memory descriptor of accumulation buffer.
+    /// @param mem_desc_cnt Is the memory descriptor of counter buffer.
+    /// @param slm_base Is the slm base address.
+    /// @param nbarrier_base Is the named barrier base.
+    template <typename matAcc_t, int sg_tile_n, int sg_tile_p>
+    __XETLA_API KERNEL_FUNC void operator()(work_group_t &g,
+            matAcc_t matAcc[sg_tile_n][sg_tile_p], mem_desc_acc_t mem_desc_acc,
+            mem_desc_cnt_t mem_desc_cnt, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        static_assert(std::is_same<typename matAcc_t::dtype, dtype_acc>::value,
+                "matAcc_t::dtype should match with dtype_acc");
+
+        update_sg_tile_tdesc(g, mem_desc_acc, mem_desc_cnt);
+
+        using matAcc_tile_desc_t = typename matAcc_t::tile_desc;
+        using matAcc_store_payload_t = subgroup::mem_payload_t<
+                mem_desc_t<dtype_acc, mem_layout::nhwc, mem_space::global, 8,
+                        4>,
+                matAcc_tile_desc_t, msg_type::atomic_add, arch_tag>;
+
+        matAcc_store_payload_t matAcc_store_payload(mem_desc_acc);
+
+#pragma unroll
+        for (uint32_t n = 0; n < sg_tile_n; n++) {
+#pragma unroll
+            for (uint32_t p = 0; p < sg_tile_p; p++) {
+
+                int32_t offset_n = mem_desc_acc.get_base_offset_from_w(n);
+                int32_t offset_p = mem_desc_acc.get_base_offset_from_z(p);
+                int mask_n = mem_desc_acc.get_mask_from_w(n);
+                int mask_p = mem_desc_acc.get_mask_from_z(p);
+                int32_t base_offset = (offset_n + offset_p) * sizeof(dtype_acc);
+
+                matAcc_store_payload.set_tdesc_base_address_masked(
+                        (uint64_t)mem_desc_acc.base.base + base_offset,
+                        mask_n & mask_p);
+
+                subgroup::tile_store<cache_hint::uncached,
+                        cache_hint::write_back>(
+                        matAcc[n][p], matAcc_store_payload);
+            }
+        }
+
+        xetla_fence<memory_kind::untyped_global, fence_op::none,
+                fence_scope::group>();
+
+        reduce_id = update_reduce_counter(mem_desc_cnt);
+        if (reduce_id == (num_group_reduction - 1)) {
+            using matAcc_payload_t = subgroup::mem_payload_t<
+                    mem_desc_t<dtype_acc, mem_layout::nhwc, mem_space::global,
+                            8, 4>,
+                    matAcc_tile_desc_t, msg_type::block_2d, arch_tag>;
+            matAcc_payload_t matAcc_payload(mem_desc_acc);
+
+            using mat_zero_t = subgroup::tile_t<dtype_acc, matAcc_tile_desc_t>;
+            mat_zero_t mat_zero;
+            mat_zero.reg = 0;
+
+#pragma unroll
+            for (uint32_t n = 0; n < sg_tile_n; n++) {
+#pragma unroll
+                for (uint32_t p = 0; p < sg_tile_p; p++) {
+                    int32_t offset_n = mem_desc_acc.get_base_offset_from_w(n);
+                    int32_t offset_p = mem_desc_acc.get_base_offset_from_z(p);
+                    int mask_n = mem_desc_acc.get_mask_from_w(n);
+                    int mask_p = mem_desc_acc.get_mask_from_z(p);
+                    int32_t base_offset
+                            = (offset_n + offset_p) * sizeof(dtype_acc);
+
+                    matAcc_payload.set_tdesc_base_address_masked(
+                            (uint64_t)mem_desc_acc.base.base + base_offset,
+                            mask_n & mask_p);
+
+                    subgroup::tile_load(matAcc[n][p], matAcc_payload);
+                    SW_BARRIER();
+
+                    subgroup::tile_store<cache_hint::uncached,
+                            cache_hint::write_back>(mat_zero, matAcc_payload);
+                }
+            }
+
+            clean_reduce_counter(mem_desc_cnt);
+            SW_BARRIER();
+        }
+    }
+};
+
+/// @brief Cross group global reduction. Specialized for num_group_reduction=1
+template <typename tile_shape_acc_, typename tile_shape_cnt_,
+        typename mem_desc_acc_t_, typename mem_desc_cnt_t_,
+        uint32_t counter_size_, gpu_arch arch_tag_>
+class global_reduce_t<reduce_op::sum, tile_shape_acc_, tile_shape_cnt_,
+        mem_desc_acc_t_, mem_desc_cnt_t_, 1, counter_size_, arch_tag_,
+        std::enable_if_t<((arch_tag_ == gpu_arch::Xe))
+                && (tile_shape_acc_::dim == 4)>> {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    using tile_shape_acc = tile_shape_acc_;
+    using tile_shape_cnt = tile_shape_cnt_;
+    using mem_desc_acc_t = mem_desc_acc_t_;
+    using mem_desc_cnt_t = mem_desc_cnt_t_;
+    using dtype_acc = typename mem_desc_acc_t::dtype;
+
+private:
+    using work_group_t = typename tile_shape_acc::work_group_t;
+
+    static constexpr uint32_t acc_sg_tile_n = tile_shape_acc::sg_tile_size_n;
+    static constexpr uint32_t acc_sg_tile_p = tile_shape_acc::sg_tile_size_p;
+    static constexpr uint32_t acc_sg_tile_q = tile_shape_acc::sg_tile_size_q;
+    static constexpr uint32_t acc_sg_tile_k = tile_shape_acc::sg_tile_size_k;
+
+public:
+    static constexpr uint32_t barrier_count = 0;
+    static constexpr uint32_t slm_size = 0;
+    inline bool is_last_group() { return true; }
+
+    template <typename matAcc_t, int sg_tile_n, int sg_tile_p>
+    inline KERNEL_FUNC void operator()(work_group_t &g,
+            matAcc_t matAcc[sg_tile_n][sg_tile_p], mem_desc_acc_t mem_desc_acc,
+            mem_desc_cnt_t mem_desc_cnt, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {}
+};
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/group.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/group.hpp
new file mode 100644
index 00000000000000..a195daee615958
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/group.hpp
@@ -0,0 +1,25 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "group/cooperative_reduction.hpp"
+#include "group/epilogue/epilogue.hpp"
+#include "group/gemm/gemm.hpp"
+#include "group/global_reduction.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/group/tile_shape.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/group/tile_shape.hpp
new file mode 100644
index 00000000000000..a05faeee910da1
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/group/tile_shape.hpp
@@ -0,0 +1,51 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "common/common.hpp"
+
+namespace gpu::xetla::group {
+
+template <auto... Args>
+struct tile_shape_t;
+
+/// @brief Workgroup level tile shape description.
+/// Describes the task assignment and layout of subgroups in a group.
+/// @tparam wg_tile_size_x_ Is the workgroup level tile size in x direction.
+/// @tparam wg_tile_size_y_ Is the workgroup level tile size in y direction.
+/// @tparam sg_tile_size_x_ Is the subgroup level tile size in x direction.
+/// @tparam sg_tile_size_y_ Is the subgroup level tile size in y direction.
+template <uint32_t wg_tile_size_x_, uint32_t wg_tile_size_y_,
+        uint32_t sg_tile_size_x_, uint32_t sg_tile_size_y_>
+struct tile_shape_t<wg_tile_size_x_, wg_tile_size_y_, sg_tile_size_x_,
+        sg_tile_size_y_> {
+    static constexpr uint32_t dim = 2;
+    static constexpr uint32_t wg_tile_size_x = wg_tile_size_x_;
+    static constexpr uint32_t wg_tile_size_y = wg_tile_size_y_;
+    static constexpr uint32_t sg_tile_size_x = sg_tile_size_x_;
+    static constexpr uint32_t sg_tile_size_y = sg_tile_size_y_;
+
+    static constexpr uint32_t wg_size_x
+            = (wg_tile_size_x + sg_tile_size_x - 1) / sg_tile_size_x;
+    static constexpr uint32_t wg_size_y
+            = (wg_tile_size_y + sg_tile_size_y - 1) / sg_tile_size_y;
+    using work_group_t = work_group_t<wg_size_x * wg_size_y>;
+};
+} // namespace gpu::xetla::group
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/api.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/api.hpp
new file mode 100644
index 00000000000000..0d61718e37769c
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/api.hpp
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "kernel/gemm/common.hpp"
+
+namespace gpu::xetla::kernel {
+
+/// @addtogroup xetla_gemm_universal
+/// @{
+
+/// @brief GEMM_UNIVERSAL functor.
+/// The basic functionality of xetla GEMM_UNIVERSAL is to calculate the \f$C = A \times B\f$.
+///
+/// For advanced usages, xetla GEMM_UNIVERSAL can also support:
+/// - \f$C = tileOp(A \times B)\f$ by configuring the tile_op_t in epilogue.
+/// @tparam dispatch_policy Is the dispatch algorithm of the GEMM_UNIVERSAL implementation.
+/// @tparam gemm_t Is the gemm functor.
+/// @tparam epilogue_t Is the epilogue functor.
+template <typename dispatch_policy, typename gemm_t, typename epilogue_t,
+        class enable = void>
+class gemm_universal_t {};
+
+/// @} xetla_gemm_universal
+
+} // namespace gpu::xetla::kernel
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/common.hpp
new file mode 100644
index 00000000000000..584f9cba6bbf29
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/common.hpp
@@ -0,0 +1,29 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "common/common.hpp"
+#include "group/group.hpp"
+#include "subgroup/subgroup.hpp"
+
+namespace gpu::xetla::kernel {
+namespace detail {} // namespace detail
+
+} // namespace gpu::xetla::kernel
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/dispatch_policy.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/dispatch_policy.hpp
new file mode 100644
index 00000000000000..3dcabed5276b78
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/dispatch_policy.hpp
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "kernel/gemm/common.hpp"
+
+namespace gpu::xetla::kernel {
+/// @addtogroup xetla_gemm_universal
+/// @{
+
+/// @brief Default GROUP_SWIZZLE implementation.
+/// A general GROUP_SWIZZLE implementation to get an workgroup id .
+/// @tparam arch_tag_ Is the HW architecture.
+template <gpu_arch arch_tag_>
+struct group_swizzle_default {
+public:
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+    inline group_swizzle_default() = default;
+
+    template <int idx>
+    static __XETLA_API int get_tile_idx(sycl::nd_item<3> &item) {
+        return item.get_group(idx);
+    }
+    // correct group range, nothing will be done under this swizzle policy
+    static __XETLA_API void update_group_range(
+            uint32_t &group_range_m, uint32_t &group_range_n) {}
+};
+
+/// @brief Default GEMM_UNIVERSAL implementation.
+/// A general GEMM_UNIVERSAL implementation to provide a composition point of gemm_universal and epilogue.
+/// @tparam arch_tag_ Is the HW architecture.
+template <typename group_swizzle_policy_>
+struct dispatch_policy_default {
+    using group_swizzle_policy = group_swizzle_policy_;
+    static constexpr gpu_arch arch_tag = group_swizzle_policy::arch_tag;
+};
+
+/// @brief Kslicing GEMM_UNIVERSAL implementation.
+/// A special GEMM_UNIVERSAL implementation to increase the hardware occupancy by splitting the GEMM_UNIVERSAL task along k dimension.
+/// It includes inter-group reduction (by using global atomic) and intra-group reduction (by using local memory for data exchange).
+/// @tparam num_global_kslicing_ Is the k dim split ratio between groups.
+/// @tparam num_local_kslicing_ Is the k dim split ratio within a group.
+/// @tparam arch_tag_ Is the HW architecture.
+template <typename group_swizzle_policy_, int global_ratio_ = 1,
+        int local_ratio_ = 1>
+struct dispatch_policy_kslicing {
+    using group_swizzle_policy = group_swizzle_policy_;
+    static constexpr int global_ratio = global_ratio_;
+    static constexpr int local_ratio = local_ratio_;
+    static constexpr gpu_arch arch_tag = group_swizzle_policy::arch_tag;
+};
+} // namespace gpu::xetla::kernel
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/gemm.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/gemm.hpp
new file mode 100644
index 00000000000000..7807e4a36c83d9
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/gemm.hpp
@@ -0,0 +1,28 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+/// @defgroup xetla_gemm_universal XeTLA GEMM_UNIVERSAL
+/// This is a gemm_universal API built on top of xetla group level API to provide a more convenient way to compose a GEMM_UNIVERSAL kernel.
+
+#include "kernel/gemm/api.hpp"
+#include "kernel/gemm/common.hpp"
+#include "kernel/gemm/dispatch_policy.hpp"
+#include "kernel/gemm/impl/kslicing_xe.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/impl/kslicing_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/impl/kslicing_xe.hpp
new file mode 100644
index 00000000000000..87bb31421f0f54
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/gemm/impl/kslicing_xe.hpp
@@ -0,0 +1,394 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "kernel/gemm/api.hpp"
+#include "kernel/gemm/common.hpp"
+#include "kernel/gemm/dispatch_policy.hpp"
+
+namespace gpu::xetla::kernel {
+
+/// @addtogroup xetla_gemm_universal
+/// @{
+
+/// @brief Is the gemm_universal functor, specialized in kslicing dispatch policy and Xe architecture.
+///
+/// @tparam num_global_kslicing_ Is the k dim split ratio between groups.
+/// @tparam num_local_kslicing_ Is the k dim split ratio within a group.
+/// @tparam gemm_t_ Is the gemm functor to compose a GEMM_UNIVERSAL.
+/// @tparam epilogue_t_ Is the epilogue functor to compose a GEMM_UNIVERSAL.
+template <int num_global_kslicing_, int num_local_kslicing_, typename gemm_t_,
+        typename epilogue_t_, typename group_swizzle_>
+class gemm_universal_t<dispatch_policy_kslicing<group_swizzle_,
+                               num_global_kslicing_, num_local_kslicing_>,
+        gemm_t_, epilogue_t_,
+        std::enable_if_t<(group_swizzle_::arch_tag == gpu_arch::Xe)>> {
+    using gemm_t = gemm_t_;
+    using epilogue_t = epilogue_t_;
+    using gemm_args_t = typename gemm_t::arguments_t;
+    using epilogue_args_t = typename epilogue_t::arguments_t;
+    using tile_shape = typename gemm_t::tile_shape;
+    using group_swizzle_t = group_swizzle_;
+
+    static constexpr uint32_t wg_tile_m = tile_shape::wg_tile_size_y;
+    static constexpr uint32_t wg_tile_n = tile_shape::wg_tile_size_x;
+    static constexpr uint32_t sg_tile_m = tile_shape::sg_tile_size_y;
+    static constexpr uint32_t sg_tile_n = tile_shape::sg_tile_size_x;
+    static constexpr uint32_t wg_size_y = tile_shape::wg_size_y;
+    static constexpr uint32_t wg_size_x = tile_shape::wg_size_x;
+    static constexpr uint32_t real_wg_tile_m = sg_tile_m * wg_size_y;
+    static constexpr uint32_t real_wg_tile_n = sg_tile_n * wg_size_x;
+
+    static constexpr uint32_t k_stride = gemm_t::k_stride;
+    using work_group_t = typename gemm_t::work_group_t;
+    static constexpr uint32_t work_group_size = work_group_t::size;
+
+    static constexpr gpu_arch arch_tag = group_swizzle_t::arch_tag;
+    static_assert(arch_tag == gemm_t::arch_tag, "arch_tag should be the same");
+    static_assert(
+            arch_tag == epilogue_t::arch_tag, "arch_tag should be the same");
+    static_assert(std::is_same<typename gemm_t::tile_shape,
+                          typename epilogue_t::tile_shape>::value,
+            "tile_shape should be the same");
+
+    using mem_desc_a_t = typename gemm_t::mem_desc_a_t;
+    using mem_desc_b_t = typename gemm_t::mem_desc_b_t;
+    using mem_desc_c_t = typename epilogue_t::mem_desc_c_t;
+    using matA_base_t = typename mem_desc_a_t::base_t;
+    using matB_base_t = typename mem_desc_b_t::base_t;
+    using matC_base_t = typename mem_desc_c_t::base_t;
+    using dtype_a = typename mem_desc_a_t::dtype;
+    using dtype_b = typename mem_desc_b_t::dtype;
+    using dtype_c = typename mem_desc_c_t::dtype;
+    using matAcc_t = typename gemm_t::matAcc_t;
+    using dtype_acc = typename matAcc_t::dtype;
+    using mem_desc_acc_t
+            = mem_desc_t<dtype_acc, mem_layout::row_major, mem_space::global>;
+    using mem_desc_cnt_t
+            = mem_desc_t<uint32_t, mem_layout::row_major, mem_space::global>;
+    using acc_base_t = typename mem_desc_acc_t::base_t;
+    using cnt_base_t = typename mem_desc_cnt_t::base_t;
+
+    static constexpr uint32_t num_global_kslicing = num_global_kslicing_;
+    static constexpr uint32_t num_local_kslicing = num_local_kslicing_;
+    static_assert((num_global_kslicing > 0) && (num_local_kslicing > 0),
+            "min slicing ratio is 1");
+
+    static_assert((num_local_kslicing & (num_local_kslicing - 1)) == 0,
+            "num_local_kslicing should be power of 2!");
+
+    using kslicing_t = group::cooperative_reduce_t<reduce_op::sum, tile_shape,
+            matAcc_t, num_local_kslicing, arch_tag>;
+    using mat_slice_t = typename kslicing_t::mat_slice_t;
+    static constexpr uint32_t ks_coop_num_x = kslicing_t::coop_num_x;
+    static constexpr uint32_t ks_coop_num_y = kslicing_t::coop_num_y;
+
+    static constexpr uint32_t gemm_nbarr_count = gemm_t::barrier_count;
+    static constexpr uint32_t gemm_slm_size = gemm_t::slm_size;
+
+    static constexpr uint32_t epilogue_nbarr_count = epilogue_t::barrier_count;
+    static constexpr uint32_t epilogue_slm_size = epilogue_t::slm_size;
+
+    static constexpr uint32_t kslicing_nbarr_count = kslicing_t::barrier_count;
+    static constexpr uint32_t kslicing_slm_size = kslicing_t::slm_size;
+
+    static constexpr uint32_t counter_size = 8;
+
+    static constexpr uint32_t alignment = 8 / sizeof(dtype_acc);
+
+    using tile_shape_cnt = group::tile_shape_t<ks_coop_num_x * wg_size_x,
+            ks_coop_num_y * wg_size_y, ks_coop_num_x, ks_coop_num_y>;
+
+    using global_group_reduce_t = group::global_reduce_t<reduce_op::sum,
+            tile_shape, tile_shape_cnt, mem_desc_acc_t, mem_desc_cnt_t,
+            num_global_kslicing, counter_size, arch_tag>;
+
+public:
+    /// @brief GEMM_UNIVERSAL arguments.
+    /// This is the interface for users to pass the application-related runtime variables.
+    struct arguments_t {
+        /// @brief Is the size of the m dimension of the matrix multiplication (m x k x n).
+        uint32_t matrix_m;
+        /// @brief Is the size of the k dimension of the matrix multiplication (m x k x n).
+        uint32_t matrix_k;
+        /// @brief Is the size of the n dimension of the matrix multiplication (m x k x n).
+        uint32_t matrix_n;
+        /// @brief Is the base address of matrix A.
+        matA_base_t matA_base;
+        /// @brief Is the leading dimension (pitch) size of the matrix A in memory.
+        uint32_t matA_ld;
+        /// @brief Is the base address of matrix B.
+        matB_base_t matB_base;
+        /// @brief Is the leading dimension (pitch) size of the matrix B in memory.
+        uint32_t matB_ld;
+        /// @brief Is the base address of matrix C.
+        matC_base_t matC_base;
+        /// @brief Is the leading dimension (pitch) size of the matrix C in memory.
+        uint32_t matC_ld;
+        /// @brief Is the base address of accumulation buffer.
+        acc_base_t acc_base;
+        /// @brief Is the base address of counter buffer.
+        cnt_base_t cnt_base;
+        /// @brief Is the epilogue arguments.
+        epilogue_args_t epilogue_args;
+
+        /// @brief Constructs arguments with default method.
+        inline arguments_t() = default;
+
+        /// @brief Set for device copyable
+        static constexpr bool host_callable = true;
+
+        // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+        // Please check if you need to add self-define destructor
+        // ~arguments_t(){}
+
+        /// @brief Constructs arguments with initialization list.
+        /// @param matrix_m_ Is the size of the m dimension of the matrix multiplication (m x k x n).
+        /// @param matrix_k_ Is the size of the k dimension of the matrix multiplication (m x k x n).
+        /// @param matrix_n_ Is the size of the n dimension of the matrix multiplication (m x k x n).
+        /// @param matA_base_ Is the base address of matrix A.
+        /// @param matA_ld_ Is the leading dimension (pitch) size of the matrix A in memory.
+        /// @param matB_base_ Is the base address of matrix B.
+        /// @param matB_ld_ Is the leading dimension (pitch) size of the matrix B in memory.
+        /// @param matC_base_ Is the base address of matrix C.
+        /// @param matC_ld_ Is the leading dimension (pitch) size of the matrix C in memory.
+        /// @param epilogue_args_ Is the epilogue arguments.
+        inline arguments_t(uint32_t matrix_m_, uint32_t matrix_k_,
+                uint32_t matrix_n_, matA_base_t matA_base_, uint32_t matA_ld_,
+                matB_base_t matB_base_, uint32_t matB_ld_,
+                matC_base_t matC_base_, uint32_t matC_ld_,
+                acc_base_t acc_base_ = {}, cnt_base_t cnt_base_ = {},
+                epilogue_args_t epilogue_args_ = {})
+            : matrix_m(matrix_m_)
+            , matrix_k(matrix_k_)
+            , matrix_n(matrix_n_)
+            , matA_base(matA_base_)
+            , matA_ld(matA_ld_)
+            , matB_base(matB_base_)
+            , matB_ld(matB_ld_)
+            , matC_base(matC_base_)
+            , matC_ld(matC_ld_)
+            , acc_base(acc_base_)
+            , cnt_base(cnt_base_)
+            , epilogue_args(epilogue_args_) {}
+        inline arguments_t(const arguments_t &args)
+            : matrix_m(args.matrix_m)
+            , matrix_k(args.matrix_k)
+            , matrix_n(args.matrix_n)
+            , matA_base(args.matA_base)
+            , matA_ld(args.matA_ld)
+            , matB_base(args.matB_base)
+            , matB_ld(args.matB_ld)
+            , matC_base(args.matC_base)
+            , matC_ld(args.matC_ld)
+            , acc_base(args.acc_base)
+            , cnt_base(args.cnt_base)
+            , epilogue_args(args.epilogue_args) {}
+        // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+        // Please check if you need to add self-define destructor
+        // inline ~arguments_t(){}
+        inline arguments_t &operator=(const arguments_t &args) {
+            this->matrix_m = args.matrix_m;
+            this->matrix_k = args.matrix_k;
+            this->matrix_n = args.matrix_n;
+            this->matA_base = args.matA_base;
+            this->matA_ld = args.matA_ld;
+            this->matB_base = args.matB_base;
+            this->matB_ld = args.matB_ld;
+            this->matC_base = args.matC_base;
+            this->matC_ld = args.matC_ld;
+            this->acc_base = args.acc_base;
+            this->cnt_base = args.cnt_base;
+            this->epilogue_args = args.epilogue_args;
+            return *this;
+        }
+    };
+
+    /// @brief Gets named_barrier id consumption count.
+    /// Users query and get a named_barrier id consumption count in compile time.
+    /// @return The count of named barriers required.
+    __XETLA_API static constexpr uint32_t get_barrier_count() {
+        constexpr uint32_t count = gemm_nbarr_count * num_local_kslicing
+                + kslicing_nbarr_count
+                + epilogue_nbarr_count * num_local_kslicing;
+        static_assert(
+                count <= 32, "The named_barrier count should be less than 32!");
+        return count;
+    }
+
+    /// @brief Gets local memory size consumption.
+    /// Users query and get a local memory consumption size in compile time.
+    /// @return The size of local memory required.
+    __XETLA_API static constexpr uint32_t get_slm_size() {
+        constexpr uint32_t size = gemm_slm_size * num_local_kslicing
+                + kslicing_slm_size + epilogue_slm_size * num_local_kslicing;
+        static_assert(size <= (128 * 1024),
+                "The local memory size should be less than 128KB!");
+        return size;
+    }
+
+    /// @brief Main execution function for GEMM_UNIVERSAL.
+    /// The processing order is 1) set group-level base and boundary, split group to workgroups ->
+    /// 2) num_local_kslicing x gemms -> 3) local kslicing -> 4) num_local_kslicing x epilogues.
+    /// @param item Is the sycl::nd_item, returns execution related information, such as workgroup id, subgroup id...
+    /// @param args Is the GEMM_UNIVERSAL arguments for application-related runtime variables.
+    /// @param slm_base Is the slm base address.
+    /// @param nbarrier_base Is the named barrier base.
+    __XETLA_API KERNEL_FUNC void operator()(sycl::nd_item<3> &item,
+            const arguments_t &args, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) const {
+        // set up workgroup level coordinates and boundaries
+        work_group_t g(item.get_local_linear_id() % work_group_size);
+        uint32_t wg_id = item.get_local_linear_id() / work_group_size;
+        group_swizzle_t group_swizzle;
+        int start_m = group_swizzle.template get_tile_idx<1>(item) * wg_tile_m;
+        int start_n = group_swizzle.template get_tile_idx<2>(item) * wg_tile_n;
+        int start_k = 0;
+        uint32_t wg_tile_k = args.matrix_k;
+        uint32_t boundary_n = (start_n + wg_tile_n) > args.matrix_n
+                ? args.matrix_n
+                : (start_n + wg_tile_n);
+        uint32_t boundary_m = (start_m + wg_tile_m) > args.matrix_m
+                ? args.matrix_m
+                : (start_m + wg_tile_m);
+        uint32_t boundary_k = wg_tile_k;
+        if constexpr (num_global_kslicing > 1) {
+            wg_tile_k = (wg_tile_k + num_global_kslicing - 1)
+                    / num_global_kslicing;
+            start_k = start_k
+                    + group_swizzle.template get_tile_idx<0>(item) * wg_tile_k;
+            boundary_k = (start_k + wg_tile_k) > boundary_k
+                    ? boundary_k
+                    : (start_k + wg_tile_k);
+        }
+        if constexpr (num_local_kslicing > 1) {
+            wg_tile_k
+                    = (wg_tile_k + num_local_kslicing - 1) / num_local_kslicing;
+            start_k = start_k + wg_id * wg_tile_k;
+            boundary_k = (start_k + wg_tile_k) > boundary_k
+                    ? boundary_k
+                    : (start_k + wg_tile_k);
+        }
+
+        // set up arguments
+        uint32_t gemm_slm_base = slm_base;
+        uint32_t gemm_nbarr_base = nbarrier_base;
+        if constexpr (num_local_kslicing > 1) {
+            gemm_slm_base = slm_base + wg_id * gemm_slm_size;
+            gemm_nbarr_base = nbarrier_base + wg_id * gemm_nbarr_count;
+        }
+        uint32_t kslicing_slm_base
+                = slm_base + num_local_kslicing * gemm_slm_size;
+        uint32_t kslicing_nbarr_base
+                = nbarrier_base + num_local_kslicing * gemm_nbarr_count;
+        uint32_t epilogue_slm_base = kslicing_slm_base + kslicing_slm_size;
+        uint32_t epilogue_nbarr_base
+                = kslicing_nbarr_base + kslicing_nbarr_count;
+
+        mem_desc_a_t mem_desc_a;
+        mem_desc_b_t mem_desc_b;
+        mem_desc_c_t mem_desc_c;
+        //setup for matA
+        if constexpr (mem_desc_a_t::is_local) {
+            mem_desc_a.init(args.matA_base,
+                    {wg_tile_k, real_wg_tile_m, wg_tile_k}, {0, 0});
+        } else {
+            mem_desc_a.init(args.matA_base,
+                    {boundary_k, boundary_m, args.matA_ld}, {start_k, start_m});
+        }
+        //setup for matB
+        if constexpr (mem_desc_b_t::is_local) {
+            mem_desc_b.init(args.matB_base,
+                    {real_wg_tile_n, wg_tile_k, real_wg_tile_n}, {0, 0});
+        } else {
+            mem_desc_b.init(args.matB_base,
+                    {boundary_n, boundary_k, args.matB_ld}, {start_n, start_k});
+        }
+
+        uint32_t inner_loop_count = (wg_tile_k + k_stride - 1) / k_stride;
+        gemm_args_t gemm_args(mem_desc_a, mem_desc_b, inner_loop_count);
+        matAcc_t matAcc;
+        matAcc.init(0);
+        gemm_t gemm;
+        gemm(g, matAcc, gemm_args, gemm_slm_base, gemm_nbarr_base);
+
+        kslicing_t kslicing(wg_id);
+        mat_slice_t mat_slice;
+        kslicing(g, mat_slice, matAcc, kslicing_slm_base, kslicing_nbarr_base);
+        if (kslicing.is_valid_post_process_wg()) {
+            //setup for matC
+            //set up cooperative offset for matC store
+            int32_t coop_offset_x
+                    = kslicing.coop_id_x * mat_slice_t::tile_size_x;
+            int32_t coop_offset_y
+                    = kslicing.coop_id_y * mat_slice_t::tile_size_y;
+            int32_t acc_start_x = start_n + coop_offset_x;
+            int32_t acc_start_y = start_m + coop_offset_y;
+            int32_t cnt_start_x = group_swizzle.template get_tile_idx<2>(item)
+                            * tile_shape_cnt::wg_tile_size_x
+                    + kslicing.coop_id_x;
+            int32_t cnt_start_y = group_swizzle.template get_tile_idx<1>(item)
+                            * tile_shape_cnt::wg_tile_size_y
+                    + kslicing.coop_id_y;
+            uint32_t group_range_x = item.get_group_range(2);
+            uint32_t group_range_y = item.get_group_range(1);
+            uint32_t cnt_size_x
+                    = group_range_x * tile_shape_cnt::wg_tile_size_x;
+            uint32_t cnt_size_y
+                    = group_range_y * tile_shape_cnt::wg_tile_size_y;
+
+            uint32_t acc_aligned_n
+                    = (args.matrix_n + alignment - 1) / alignment * alignment;
+
+            uint32_t acc_boundary_n = (start_n + wg_tile_n) > acc_aligned_n
+                    ? acc_aligned_n
+                    : start_n + wg_tile_n;
+
+            mem_desc_acc_t mem_desc_acc(args.acc_base,
+                    {acc_boundary_n, boundary_m, acc_aligned_n},
+                    {acc_start_x, acc_start_y});
+            mem_desc_cnt_t mem_desc_cnt(args.cnt_base,
+                    {cnt_size_x, cnt_size_y, cnt_size_x},
+                    {cnt_start_x, cnt_start_y});
+
+            global_group_reduce_t global_group_reduce;
+            global_group_reduce(g, mat_slice, mem_desc_acc, mem_desc_cnt);
+
+            if (global_group_reduce.is_last_group()) {
+                if constexpr (mem_desc_c_t::is_local) {
+                    mem_desc_c.init(args.matC_base,
+                            {real_wg_tile_n, real_wg_tile_m, real_wg_tile_n},
+                            {coop_offset_x, coop_offset_y});
+                } else {
+                    mem_desc_c.init(args.matC_base,
+                            {boundary_n, boundary_m, args.matC_ld},
+                            {start_n + coop_offset_x, start_m + coop_offset_y});
+                }
+                epilogue_t epilogue;
+                epilogue(g, mat_slice, mem_desc_c, args.epilogue_args,
+                        epilogue_slm_base, epilogue_nbarr_base);
+            }
+        }
+    }
+};
+
+/// @} xetla_gemm_universal
+
+} // namespace gpu::xetla::kernel
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/kernel.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/kernel.hpp
new file mode 100644
index 00000000000000..3c04902517d325
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/kernel/kernel.hpp
@@ -0,0 +1,22 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "kernel/gemm/gemm.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/subgroup.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/subgroup.hpp
new file mode 100644
index 00000000000000..240aa7b90a7d4a
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/subgroup.hpp
@@ -0,0 +1,22 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/tile.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/api.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/api.hpp
new file mode 100644
index 00000000000000..905e901a906844
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/api.hpp
@@ -0,0 +1,125 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/common.hpp"
+
+namespace gpu::xetla::subgroup {
+
+/// @brief Is the xetla tile mma operation definition API.
+/// @tparam matAcc_dst_t Is the tile type for dst data of matC.
+/// @tparam matAcc_src_t Is the tile type for src data of matC.
+/// @tparam matB_t Is the tile type for matB.
+/// @tparam matA_t Is the tile type for matA.
+/// @tparam engine Is the compute engine, fpu or xmx.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename matAcc_dst_t, typename matAcc_src_t, typename matB_t,
+        typename matA_t, mma_engine engine, gpu_arch arch_tag,
+        typename enable = void>
+struct tile_mma_t {};
+
+template <typename matAcc_dst_t, typename matAcc_src_t, typename matB_t,
+        typename matA_t, typename matBS_t, typename matAS_t, uint32_t scalings,
+        mma_engine engine, gpu_arch arch_tag, typename enable = void>
+struct tile_bmma_t {};
+
+/// @brief Is to illustrate the memory information
+/// @tparam  mem_desc Is the memory descriptor
+/// @tparam  tile_desc Is the tile descriptor
+/// @tparam  message_type Is the form will be used to load/store
+template <typename mem_desc, typename tile_desc, msg_type message_type,
+        gpu_arch arch_tag, typename enable = void>
+struct mem_payload_t {};
+
+/// @brief Is to illustrate the memory information to prefetch data to cache.
+/// @tparam mem_desc Is the memory descriptor
+/// @tparam tile_desc_ Is the tile descriptor.
+/// @tparam cooperative_num_ Is the thread nums to prefetch data.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename mem_desc_, typename tile_desc_, uint32_t cooperative_num_,
+        gpu_arch arch_tag, typename enable = void>
+struct prefetch_payload_t {};
+
+/// @brief Is to illustrate the tile information about a sub matrix.
+/// @tparam tile_size_x_ Is the horizon tile size.
+/// @tparam tile_size_y_ Is the vertical tile size.
+/// @tparam block_size_x_ Is the horizon block size.
+/// @tparam block_size_y_ Is the vertical block size.
+/// @tparam reg_layout_ Is the register layout i.e. tiled, vnni_tiled and so on.
+/// @tparam gpu_arch_ Is the hardware architecture tag.
+template <uint32_t tile_size_x_, uint32_t tile_size_y_, uint32_t block_size_x_,
+        uint32_t block_size_y_, reg_layout reg_layout_ = reg_layout::tiled,
+        bool col_majored_ = false>
+struct tile_desc_t {
+    static constexpr uint32_t tile_size_x = tile_size_x_;
+    static constexpr uint32_t tile_size_y = tile_size_y_;
+
+    static constexpr uint32_t block_size_x = block_size_x_;
+    static constexpr uint32_t block_size_y = block_size_y_;
+    static constexpr uint32_t remained_size_y = tile_size_y % block_size_y;
+
+    static constexpr reg_layout register_layout = reg_layout_;
+    static constexpr bool reg_transpose
+            = reg_layout_ == reg_layout::transpose_tiled;
+
+    static_assert(
+            tile_size_x >= block_size_x, "tile_size_x should >= block_size_x ");
+    static_assert(
+            tile_size_y >= block_size_y, "tile_size_y should >= block_size_y ");
+    static_assert((tile_size_y == 1) || (block_size_y == 1)
+                    || ((block_size_x & (block_size_x - 1)) == 0),
+            "if tile_size_y/block_size_y > 1, block_size_x should be power of "
+            "2 ");
+    static_assert(tile_size_x % (block_size_x) == 0,
+            "Tile_size_x should be a multiple of block_size_x ");
+
+    static constexpr uint32_t num_block_x = tile_size_x / block_size_x;
+    static constexpr uint32_t num_block_y = tile_size_y / block_size_y;
+    static constexpr uint32_t num_block
+            = num_block_x * (num_block_y + (remained_size_y > 0 ? 1 : 0));
+
+    static constexpr uint32_t block_elems = block_size_x * block_size_y;
+    static constexpr uint32_t tile_elems = tile_size_x * tile_size_y;
+    static constexpr bool col_majored = col_majored_;
+};
+
+/// @brief Is a struct contains some register file.
+/// @tparam dtype_ Is the data type.
+/// @tparam tile_desc_ Is tile_desc_t struct.
+template <typename dtype_, typename tile_desc_, bool dst_ = true>
+struct tile_t : public tile_desc_ {
+    using dtype = dtype_;
+    using tile_desc = tile_desc_;
+    static constexpr bool dst = dst_;
+    xetla_vector<dtype, tile_desc::tile_elems> reg;
+
+    // Cannot init value by constructor
+    inline tile_t(native_type_t<dtype> val) {
+        static_assert(!is_internal_type<dtype>::value,
+                "compiler currently does NOT support using plained BF16 data "
+                "to initialize a BF16 data");
+        this->reg = val;
+    }
+
+    inline tile_t() = default;
+    __XETLA_API void init(native_type_t<dtype> val) { this->reg = val; }
+};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/chained_tile_op.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/chained_tile_op.hpp
new file mode 100644
index 00000000000000..f32539064e480f
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/chained_tile_op.hpp
@@ -0,0 +1,126 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/common.hpp"
+
+namespace gpu::xetla::subgroup {
+
+template <int idx, typename tile_op_args_t>
+struct tile_op_arg_helper_t {
+    tile_op_args_t args;
+    inline tile_op_arg_helper_t(tile_op_args_t args_) : args(args_) {}
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // ~tile_op_arg_helper_t(){}
+    inline tile_op_arg_helper_t(
+            const tile_op_arg_helper_t<idx, tile_op_args_t> &args_helper)
+        : args(args_helper.args) {}
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // inline ~tile_op_arg_helper_t(){}
+    inline tile_op_arg_helper_t &operator=(
+            const tile_op_arg_helper_t<idx, tile_op_args_t> &args_helper) {
+        this->args = args_helper.args;
+        return *this;
+    }
+    inline tile_op_arg_helper_t() = default;
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // ~tile_op_arg_helper_t(){}
+
+    inline tile_op_args_t get_args() const { return args; }
+    inline void set_args(const tile_op_args_t &new_args) { args = new_args; }
+};
+
+template <int idx, typename... tile_op_args_t>
+struct chained_tile_op_arg_t {};
+
+template <int idx, typename curr_args_t, typename... remain_args_t>
+struct chained_tile_op_arg_t<idx, curr_args_t, remain_args_t...>
+    : public tile_op_arg_helper_t<idx, curr_args_t>,
+      public chained_tile_op_arg_t<idx + 1, remain_args_t...> {
+    inline chained_tile_op_arg_t() = default;
+    inline chained_tile_op_arg_t(
+            curr_args_t curr_args, remain_args_t... remain_args)
+        : tile_op_arg_helper_t<idx, curr_args_t>(curr_args)
+        , chained_tile_op_arg_t<idx + 1, remain_args_t...>(remain_args...) {}
+
+    inline chained_tile_op_arg_t(
+            chained_tile_op_arg_t<idx, curr_args_t, remain_args_t...> const
+                    &args)
+            = default;
+
+    template <int idx_, typename T>
+    inline T get() const {
+        return this->tile_op_arg_helper_t<idx_, T>::get_args();
+    }
+    template <int idx_, typename T>
+    inline void set(T new_args) {
+        this->tile_op_arg_helper_t<idx_, T>::set_args(new_args);
+    }
+};
+
+template <typename... tile_op_t>
+struct chained_tile_op_t {
+    using arguments_t
+            = chained_tile_op_arg_t<0, typename tile_op_t::arguments_t...>;
+    static constexpr int list_size = sizeof...(tile_op_t);
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args_helper,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        if constexpr (list_size == 0) {
+            return;
+        } else {
+            chained_tile_op_helper<tile_op_t...> chained_tile_op;
+            chained_tile_op(
+                    matAcc, coord, args_helper, slm_base, nbarrier_base);
+        }
+    }
+
+private:
+    template <typename... total_tile_op_t>
+    struct chained_tile_op_helper {};
+
+    template <typename curr_tile_op_t, typename... remain_tile_op_t>
+    struct chained_tile_op_helper<curr_tile_op_t, remain_tile_op_t...> {
+        using curr_tile_op_args_t = typename curr_tile_op_t::arguments_t;
+        static constexpr int curr_idx
+                = list_size - sizeof...(remain_tile_op_t) - 1;
+        template <typename matAcc_t, typename coord_t>
+        __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+                const coord_t &coord, const arguments_t &args_helper,
+                uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+            curr_tile_op_t curr_tile_op;
+            //call the actual tile op
+            curr_tile_op(matAcc, coord,
+                    args_helper.template get<curr_idx, curr_tile_op_args_t>(),
+                    slm_base, nbarrier_base);
+            if constexpr (sizeof...(remain_tile_op_t) > 0) {
+                chained_tile_op_helper<remain_tile_op_t...> remain_tile_op;
+                remain_tile_op(
+                        matAcc, coord, args_helper, slm_base, nbarrier_base);
+            }
+        }
+    };
+};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/common.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/common.hpp
new file mode 100644
index 00000000000000..364bf6561e1654
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/common.hpp
@@ -0,0 +1,331 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "common/common.hpp"
+
+namespace gpu::xetla::subgroup {
+
+namespace detail {
+
+/// @brief Compute next power of 2 of a constexpr with guaranteed compile-time
+/// evaluation.
+///
+/// @tparam N
+/// @tparam K
+/// @tparam K_gt_eq_N
+template <uint32_t N, uint32_t K, bool K_gt_eq_N>
+struct NextPowerOf2;
+
+/// @brief
+///
+/// @tparam N
+/// @tparam K
+template <uint32_t N, uint32_t K>
+struct NextPowerOf2<N, K, true> {
+    static constexpr uint32_t get() { return K; }
+};
+
+/// @brief
+///
+/// @tparam N
+/// @tparam K
+template <uint32_t N, uint32_t K>
+struct NextPowerOf2<N, K, false> {
+    static constexpr uint32_t get() {
+        return NextPowerOf2<N, K * 2, K * 2 >= N>::get();
+    }
+};
+
+/// @brief Get the Next Power Of2 object
+///
+/// @tparam N
+/// @return constexpr uint32_t
+template <uint32_t N>
+constexpr uint32_t getNextPowerOf2() {
+    return NextPowerOf2<N, 1, (1 >= N)>::get();
+}
+
+/// @brief Get the Next Power Of2<0> object
+///
+/// @tparam
+/// @return constexpr uint32_t
+template <>
+constexpr uint32_t getNextPowerOf2<0>() {
+    return 0;
+}
+
+/// @brief
+///
+/// @tparam a
+/// @tparam b
+template <uint32_t a, uint32_t b>
+struct gcd {
+    static constexpr uint32_t value = gcd<b, a % b>::value;
+};
+
+/// @brief
+///
+/// @tparam a
+template <uint32_t a>
+struct gcd<a, 0> {
+    static constexpr uint32_t value = a;
+};
+
+enum class process_flag : uint8_t { load = 0, store = 1 };
+
+template <uint32_t remained_len, uint32_t base_len, process_flag flag,
+        cache_hint L1, cache_hint L2, typename payload_t, typename tile_t>
+__XETLA_API typename std::enable_if_t<base_len == 0> process_1d_tail(
+        tile_t &tile, payload_t &payload, uint32_t offset) {}
+
+template <uint32_t remained_len, uint32_t base_len, process_flag flag,
+        cache_hint L1, cache_hint L2, typename payload_t, typename tile_t>
+__XETLA_API typename std::enable_if_t<base_len == 0> process_1d_tail(
+        tile_t &tile, payload_t &payload, uint32_t offset,
+        uint32_t address_offset) {}
+
+template <uint32_t remained_len, uint32_t base_len, process_flag flag,
+        cache_hint L1, cache_hint L2, typename payload_t, typename tile_t>
+__XETLA_API typename std::enable_if_t<base_len != 0
+        && payload_t::memory_space == mem_space::global>
+process_1d_tail(tile_t &tile, payload_t &payload, uint32_t offset) {
+    using dtype = typename payload_t::dtype;
+    using mem_dtype = typename payload_t::mem_dtype;
+    if constexpr (remained_len >= base_len) {
+        uint32_t address_offset = offset * sizeof(dtype);
+        auto reg_sub
+                = tile.reg.xetla_select<base_len * payload_t::scale_factor, 1>(
+                        offset);
+        if constexpr (flag == process_flag::load) {
+            reg_sub.xetla_format<mem_dtype>() = xetla_load_global<mem_dtype,
+                    base_len, data_size::default_size, L1, L2>(
+                    payload.base_ptr, payload.base_offset + address_offset);
+        } else {
+            xetla_store_global<mem_dtype, base_len, data_size::default_size, L1,
+                    L2>(payload.base_ptr, payload.base_offset + address_offset,
+                    reg_sub.xetla_format<mem_dtype>());
+        }
+        process_1d_tail<remained_len - base_len, (base_len >> 1), flag, L1, L2>(
+                tile, payload, offset + base_len * payload_t::scale_factor);
+    } else {
+        process_1d_tail<remained_len, (base_len >> 1), flag, L1, L2>(
+                tile, payload, offset);
+    }
+}
+
+template <uint32_t remained_len, uint32_t base_len, process_flag flag,
+        cache_hint L1, cache_hint L2, typename payload_t, typename tile_t>
+__XETLA_API typename std::enable_if_t<base_len != 0
+        && payload_t::memory_space == mem_space::local>
+process_1d_tail(tile_t &tile, payload_t &payload, uint32_t offset,
+        uint32_t address_offset) {
+    using dtype = typename payload_t::dtype;
+    using mem_dtype = typename payload_t::mem_dtype;
+    if constexpr (remained_len >= base_len) {
+        auto reg_sub
+                = tile.reg.xetla_select<base_len * payload_t::scale_factor, 1>(
+                        offset);
+        if constexpr (flag == process_flag::load) {
+            reg_sub.xetla_format<mem_dtype>() = xetla_load_local<mem_dtype,
+                    base_len, data_size::default_size>(
+                    payload.base_address + payload.address + address_offset);
+        } else {
+            xetla_store_local<mem_dtype, base_len>(
+                    payload.base_address + payload.address + address_offset,
+                    reg_sub.xetla_format<mem_dtype>());
+        }
+        process_1d_tail<remained_len - base_len, (base_len >> 1), flag, L1, L2,
+                payload_t, tile_t>(tile, payload,
+                offset + base_len * payload_t::scale_factor,
+                address_offset
+                        + base_len * payload_t::scale_factor
+                                * sizeof(typename tile_t::dtype));
+    } else {
+        process_1d_tail<remained_len, (base_len >> 1), flag, L1, L2, payload_t,
+                tile_t>(tile, payload, offset, address_offset);
+    }
+}
+
+// This will end up with base_len equal to 8 because we had made tile_size_x
+// divisible by 8/16/32, depends on dtype
+// this is for prefetch only and use different func arg compare with load/store
+template <uint32_t remained_len, uint32_t base_len, cache_hint L1,
+        cache_hint L2, typename payload_t>
+__XETLA_API typename std::enable_if_t<(base_len < 8)> process_1d_tail(
+        payload_t &payload, uint32_t offset) {
+    using dtype = typename payload_t::dtype;
+    using prefetch_dtype = typename payload_t::prefetch_dtype;
+    uint32_t address_offset = offset * sizeof(dtype);
+    constexpr uint32_t prefetch_min_size = 64 / sizeof(prefetch_dtype);
+    if constexpr (remained_len > 0) {
+        xetla_prefetch_global<prefetch_dtype, prefetch_min_size,
+                data_size::default_size, L1, L2>(
+                payload.base_ptr, payload.base_offset + address_offset);
+    }
+}
+
+template <uint32_t remained_len, uint32_t base_len, cache_hint L1,
+        cache_hint L2, typename payload_t>
+__XETLA_API typename std::enable_if_t<base_len >= 8> process_1d_tail(
+        payload_t &payload, uint32_t offset) {
+    using dtype = typename payload_t::dtype;
+    using prefetch_dtype = typename payload_t::prefetch_dtype;
+    if constexpr (remained_len >= base_len) {
+        uint32_t address_offset = offset * sizeof(dtype);
+        xetla_prefetch_global<prefetch_dtype, base_len, data_size::default_size,
+                L1, L2>(payload.base_ptr, payload.base_offset + address_offset);
+        process_1d_tail<remained_len - base_len, (base_len >> 1), L1, L2,
+                payload_t>(
+                payload, offset + base_len * payload_t::scale_factor);
+    } else {
+        process_1d_tail<remained_len, (base_len >> 1), L1, L2, payload_t>(
+                payload, offset);
+    }
+}
+
+template <uint32_t num_tdesc, uint32_t size_x, uint32_t size_y,
+        uint32_t scale_factor, uint8_t arr_len, bool trans>
+__XETLA_API static void reset_tile_desc_core(
+        xetla_matrix_ref<uint32_t, num_tdesc, 16> __REF__ payload_row) {
+#pragma unroll
+    for (int j = 0; j < num_tdesc; j++) {
+        constexpr uint8_t block_width
+                = trans ? (size_y / scale_factor) : (size_x / scale_factor);
+        constexpr uint8_t block_height = trans ? size_x : size_y;
+        constexpr uint32_t block_widthx_widthy_arrlen = (block_width - 1)
+                | ((block_height - 1) << 8) | ((arr_len - 1) << 16);
+        gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                payload_row.row(j), block_widthx_widthy_arrlen);
+    }
+}
+
+} // namespace detail
+
+template <typename T_dst, typename T_src>
+struct is_same_layout {
+    static constexpr bool value = (T_src::block_size_y == T_dst::block_size_y)
+            && (T_src::block_size_x == T_dst::block_size_x)
+            && (T_src::tile_size_y == T_dst::tile_size_y)
+            && (T_src::tile_size_x == T_dst::tile_size_x);
+};
+
+template <typename T_dst, typename T_src>
+struct is_1d_src {
+    static constexpr bool value = (T_src::tile_elems == T_dst::tile_elems)
+            && (T_src::block_size_y == 1) && (T_src::tile_size_y == 1);
+};
+
+template <typename T_dst, typename T_src>
+struct is_same_tile {
+    static constexpr bool value = (T_src::tile_size_y == T_dst::tile_size_y)
+            && (T_src::tile_size_x == T_dst::tile_size_x);
+};
+
+template <typename T_dst, typename T_src>
+struct is_same_elements {
+    static constexpr bool value = (T_src::tile_elems == T_dst::tile_elems);
+};
+
+template <typename T_dst, typename T_src>
+struct is_floating_to_integer {
+    static constexpr bool value
+            = is_floating_point<typename T_src::dtype>::value
+            && is_integral<typename T_dst::dtype>::value;
+};
+
+template <typename tile_desc_, mem_space memory_space,
+        mem_layout memory_layout = mem_layout::row_major>
+struct msg_type_query {
+    static constexpr msg_type value = memory_space == mem_space::global
+            ? (((tile_desc_::tile_size_y == 1)
+                       && (memory_layout == mem_layout::row_major))
+                            ? msg_type::block_1d
+                            : msg_type::block_2d)
+            : (((tile_desc_::tile_size_y == 1)
+                       && (memory_layout == mem_layout::row_major))
+                            ? msg_type::block_1d
+                            : msg_type::scatter);
+};
+
+template <typename tile_desc_, mem_space memory_space>
+constexpr msg_type msg_type_v = msg_type_query<tile_desc_, memory_space>::value;
+
+template <typename dtype, uint32_t tile_size_x, uint32_t tile_size_y,
+        gpu_arch arch_tag, mem_layout mem_layout_ = mem_layout::row_major,
+        reg_layout reg_layout_ = reg_layout::tiled>
+struct get_load_block_size_auto {};
+
+template <typename dtype, uint32_t tile_size_x, uint32_t tile_size_y>
+struct get_load_block_size_auto<dtype, tile_size_x, tile_size_y, gpu_arch::Xe,
+        mem_layout::row_major, reg_layout::tiled> {
+private:
+    using load_store_attr = arch_attr_t<gpu_arch::Xe>::template load_store_attr<
+            msg_type::block_2d>;
+    static constexpr uint32_t max_load_height_in_elem
+            = load_store_attr::max_load_height_in_elem;
+    static constexpr uint32_t max_load_width_in_bytes
+            = load_store_attr::max_load_width_in_bytes;
+    static constexpr uint32_t max_load_width_in_elem
+            = max_load_width_in_bytes / sizeof(dtype);
+
+public:
+    // block_size_x should be power of 2 and tile_size_x should be divided by block_size_x
+    static constexpr uint32_t block_size_x
+            = detail::gcd<tile_size_x, max_load_width_in_elem>::value;
+    static constexpr uint32_t block_size_y
+            = max_load_height_in_elem > tile_size_y ? tile_size_y
+                                                    : max_load_height_in_elem;
+};
+
+template <typename dtype, uint32_t tile_size_x, uint32_t tile_size_y,
+        gpu_arch arch_tag, mem_layout mem_layout_ = mem_layout::row_major,
+        reg_layout reg_layout_ = reg_layout::tiled>
+struct get_store_block_size_auto {};
+
+template <typename dtype, uint32_t tile_size_x, uint32_t tile_size_y>
+struct get_store_block_size_auto<dtype, tile_size_x, tile_size_y, gpu_arch::Xe,
+        mem_layout::row_major, reg_layout::tiled> {
+private:
+    using load_store_attr = arch_attr_t<gpu_arch::Xe>::template load_store_attr<
+            msg_type::block_2d>;
+    static constexpr uint32_t max_store_height_in_elem
+            = load_store_attr::max_store_height_in_elem;
+    static constexpr uint32_t max_store_width_in_bytes
+            = load_store_attr::max_store_width_in_bytes;
+    static constexpr uint32_t max_store_width_in_elem
+            = max_store_width_in_bytes / sizeof(dtype);
+
+public:
+    // block_size_x should be power of 2 and tile_size_x should be divided by block_size_x
+    static constexpr uint32_t block_size_x
+            = detail::gcd<tile_size_x, max_store_width_in_elem>::value;
+    static constexpr uint32_t block_size_y
+            = max_store_height_in_elem > tile_size_y ? tile_size_y
+                                                     : max_store_height_in_elem;
+};
+
+// This type tag represents "global atomic oob check on" behavior
+struct global_atomic_oob_check_on_tag : std::true_type {};
+
+// This type tag represents "global atomic oob check off" behavior
+struct global_atomic_oob_check_off_tag : std::false_type {};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/fma_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/fma_xe.hpp
new file mode 100644
index 00000000000000..1726fde47a0e53
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/fma_xe.hpp
@@ -0,0 +1,255 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+
+namespace gpu::xetla::subgroup {
+
+/// @brief Is the tile mma operation functor, specialized for Xe and fpu engine.
+template <typename matAcc_dst_t_, typename matAcc_src_t_, typename matB_t_,
+        typename matA_t_, gpu_arch arch_tag_>
+struct tile_mma_t<matAcc_dst_t_, matAcc_src_t_, matB_t_, matA_t_,
+        mma_engine::fpu, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using matA_t = matA_t_;
+    using matB_t = matB_t_;
+    using matSrc_t = matAcc_src_t_;
+    using matDst_t = matAcc_dst_t_;
+    using dtype_a = typename matA_t::dtype;
+    using dtype_b = typename matB_t::dtype;
+    using dtype_src = typename matSrc_t::dtype;
+    using dtype_dst = typename matDst_t::dtype;
+
+    using register_attr =
+            typename arch_attr_t<arch_tag_>::template register_attr<>;
+
+    static_assert(matA_t::reg_transpose,
+            "For FMAOp GEMM, the register layout of matA should be col-major");
+    static_assert(!matB_t::reg_transpose,
+            "For FMAOp GEMM, the register layout of matB should be row-major");
+
+    static constexpr uint32_t a_tile_size_y = matA_t::tile_size_y;
+    static constexpr uint32_t a_tile_size_x = matA_t::tile_size_x;
+    static constexpr uint32_t a_tile_elems = matA_t::tile_elems;
+    static constexpr uint32_t a_block_size_w = matA_t::block_size_y;
+    static constexpr uint32_t a_block_size_h = matA_t::block_size_x;
+    static constexpr uint32_t a_block_elems = matA_t::block_elems;
+
+    static constexpr uint32_t b_tile_size_x = matB_t::tile_size_x;
+    static constexpr uint32_t b_tile_size_y = matB_t::tile_size_y;
+    static constexpr uint32_t b_tile_elems = matB_t::tile_elems;
+    static constexpr uint32_t b_block_size_x = matB_t::block_size_x;
+    static constexpr uint32_t b_block_size_y = matB_t::block_size_y;
+    static constexpr uint32_t b_block_elems = matB_t::block_elems;
+
+    static constexpr uint32_t tile_size_m = matDst_t::tile_size_y;
+    static constexpr uint32_t tile_size_k = a_tile_size_x;
+    static constexpr uint32_t tile_size_n = matDst_t::tile_size_x;
+    static constexpr uint32_t tile_elems = tile_size_m * tile_size_n;
+    static constexpr uint32_t block_size_n = matDst_t::block_size_x;
+    static constexpr uint32_t block_size_k = a_block_size_h;
+    static constexpr uint32_t block_size_m = matDst_t::block_size_y;
+    static constexpr uint32_t block_elems = block_size_m * block_size_n;
+
+    static_assert(tile_size_m == matA_t::tile_size_y,
+            "matAcc tile m should match with matA tile m");
+    static_assert(a_tile_size_x == b_tile_size_y,
+            "matA tile k should match with matB tile k");
+    static_assert(tile_size_n == matB_t::tile_size_x,
+            "matAcc tile n should match with matB tile n");
+    static_assert(block_size_m == a_block_size_w,
+            "matAcc block m should match with matA block m");
+    static_assert(block_size_n == b_block_size_x,
+            "matAcc block n should match with matB block n");
+    static_assert((tile_size_k % block_size_k) == 0,
+            "matAcc tile_size_k should be a multiple of block_size_k");
+
+    static constexpr int32_t num_block_n = matDst_t::num_block_x;
+    static constexpr int32_t num_block_m = matDst_t::num_block_y;
+    static constexpr int32_t num_block_k = tile_size_k / block_size_k;
+
+    static constexpr int32_t mma_m = register_attr::acc_reg_in_bytes
+            / (block_size_n * sizeof(dtype_dst));
+
+    template <int blk_m, int blk_n, int blk_k>
+    __XETLA_API static void mma_core(
+            xetla_vector_ref<dtype_dst, blk_m * blk_n> __REF__ dst,
+            xetla_vector_ref<dtype_src, blk_m * blk_n> __REF__ src,
+            xetla_vector_ref<dtype_b, blk_k * blk_n> __REF__ b_block,
+            xetla_vector_ref<dtype_a, blk_m * blk_k> __REF__ a_block) {
+        auto dst_blk_2d = dst.xetla_format<dtype_dst, blk_m, blk_n>();
+        auto b_blk_2d = b_block.xetla_format<dtype_dst, blk_k, blk_n>();
+        auto src_blk_2d = src.xetla_format<dtype_src, blk_m, blk_n>();
+#pragma unroll
+        for (int i = 0; i < blk_m / mma_m; i++) {
+            xetla_vector<dtype_dst, mma_m * blk_n> dst_tmp;
+            auto dst_tmp_2d = dst_tmp.xetla_format<dtype_dst, mma_m, blk_n>();
+#pragma unroll
+            for (int i_acc = 0; i_acc < mma_m; i_acc++) {
+                dst_tmp_2d.row(i_acc)
+                        = a_block[i_acc + i * mma_m] * b_blk_2d.row(0)
+                        + src_blk_2d.row(i_acc + i * mma_m);
+            }
+#pragma unroll
+            for (int k = 1; k < blk_k - 1; k++) {
+                for (int i_acc = 0; i_acc < mma_m; i_acc++) {
+                    int a_offset = k * blk_m + i_acc + i * mma_m;
+                    dst_tmp_2d.row(i_acc)
+                            += a_block[a_offset] * b_blk_2d.row(k);
+                }
+            }
+            for (int i_acc = 0; i_acc < mma_m; i_acc++) {
+                int a_offset = (blk_k - 1) * blk_m + i_acc + i * mma_m;
+                dst_blk_2d.row(i_acc + i * mma_m)
+                        = a_block[a_offset] * b_blk_2d.row(blk_k - 1)
+                        + dst_tmp_2d.row(i_acc);
+            }
+            SW_BARRIER();
+        }
+
+        if constexpr ((blk_m % mma_m) != 0) {
+            constexpr uint32_t tail_start_m = blk_m / mma_m * mma_m;
+            constexpr uint32_t tail_m = blk_m % mma_m;
+            xetla_vector<dtype_dst, tail_m * blk_n> dst_tmp;
+            auto dst_tmp_2d = dst_tmp.xetla_format<dtype_dst, tail_m, blk_n>();
+#pragma unroll
+            for (int i_acc = 0; i_acc < tail_m; i_acc++) {
+                dst_tmp_2d.row(i_acc)
+                        = a_block[i_acc + tail_start_m] * b_blk_2d.row(0)
+                        + src_blk_2d.row(i_acc + tail_start_m);
+            }
+#pragma unroll
+            for (int k = 1; k < blk_k - 1; k++) {
+                for (int i_acc = 0; i_acc < tail_m; i_acc++) {
+                    int a_offset = k * blk_m + i_acc + tail_start_m;
+                    dst_tmp_2d.row(i_acc)
+                            += a_block[a_offset] * b_blk_2d.row(k);
+                }
+            }
+            for (int i_acc = 0; i_acc < tail_m; i_acc++) {
+                int a_offset = (blk_k - 1) * blk_m + i_acc + tail_start_m;
+                dst_blk_2d.row(i_acc + tail_start_m)
+                        = a_block[a_offset] * b_blk_2d.row(blk_k - 1)
+                        + dst_tmp_2d.row(i_acc);
+            }
+        }
+    }
+
+    __XETLA_API static void mma(
+            matDst_t &dst, matSrc_t &src, matB_t &b, matA_t &a) {
+        { //k_blk=0
+            auto b_reg
+                    = b.reg.xetla_select<b_block_size_y * b_tile_size_x, 1>(0);
+#pragma unroll
+            for (int i = 0; i < tile_size_m / block_size_m; i++) {
+                auto a_block = a.reg.xetla_select<a_block_elems, 1>(
+                        i * num_block_k * a_block_elems);
+#pragma unroll
+                for (int j = 0; j < num_block_n; j++) {
+                    auto b_block = b_reg.xetla_select<b_block_elems, 1>(
+                            j * b_block_elems);
+                    auto src_block = src.reg.xetla_select<block_elems, 1>(
+                            (i * num_block_n + j) * block_elems);
+                    auto dst_block = dst.reg.xetla_select<block_elems, 1>(
+                            (i * num_block_n + j) * block_elems);
+                    mma_core<block_size_m, block_size_n, block_size_k>(
+                            dst_block, src_block, b_block, a_block);
+                }
+            }
+
+            // process the tail
+            if constexpr ((tile_size_m % block_size_m) != 0) {
+                constexpr uint32_t tail_start_m
+                        = tile_size_m / block_size_m * block_size_m;
+                constexpr uint32_t a_tail_blk_w = a_tile_size_y - tail_start_m;
+                constexpr uint32_t a_tail_blk_elems
+                        = a_block_size_h * a_tail_blk_w;
+                constexpr uint32_t tail_size_m = tile_size_m - tail_start_m;
+                constexpr uint32_t acc_tail_blk_elems
+                        = tail_size_m * block_size_n;
+                auto a_block = a.reg.xetla_select<a_tail_blk_elems, 1>(
+                        a_tile_size_x * tail_start_m);
+#pragma unroll
+                for (int j = 0; j < num_block_n; j++) {
+                    auto b_block = b_reg.xetla_select<b_block_elems, 1>(
+                            j * b_block_elems);
+                    auto src_block
+                            = src.reg.xetla_select<acc_tail_blk_elems, 1>(
+                                    (tail_start_m * tile_size_n)
+                                    + j * acc_tail_blk_elems);
+                    auto dst_block
+                            = dst.reg.xetla_select<acc_tail_blk_elems, 1>(
+                                    (tail_start_m * tile_size_n)
+                                    + j * acc_tail_blk_elems);
+                    mma_core<tail_size_m, block_size_n, block_size_k>(
+                            dst_block, src_block, b_block, a_block);
+                }
+            }
+        }
+        // different K block
+#pragma unroll
+        for (int k_i = 1; k_i < num_block_k; k_i++) {
+
+            auto b_reg = b.reg.xetla_select<b_block_size_y * b_tile_size_x, 1>(
+                    k_i * b_block_size_y * b_tile_size_x);
+#pragma unroll
+            for (int i = 0; i < tile_size_m / block_size_m; i++) {
+                auto a_block = a.reg.xetla_select<a_block_elems, 1>(
+                        (i * num_block_k + k_i) * a_block_elems);
+#pragma unroll
+                for (int j = 0; j < num_block_n; j++) {
+                    auto b_block = b_reg.xetla_select<b_block_elems, 1>(
+                            j * b_block_elems);
+                    auto dst_block = dst.reg.xetla_select<block_elems, 1>(
+                            (i * num_block_n + j) * block_elems);
+                    mma_core<block_size_m, block_size_n, block_size_k>(
+                            dst_block, dst_block, b_block, a_block);
+                }
+            }
+            // process the tail
+            if constexpr ((tile_size_m % block_size_m) != 0) {
+                constexpr uint32_t tail_start_m
+                        = tile_size_m / block_size_m * block_size_m;
+                constexpr uint32_t a_tail_blk_w = a_tile_size_y - tail_start_m;
+                constexpr uint32_t a_tail_blk_elems
+                        = a_block_size_h * a_tail_blk_w;
+                constexpr uint32_t tail_size_m = tile_size_m - tail_start_m;
+                constexpr uint32_t acc_tail_blk_elems
+                        = tail_size_m * block_size_n;
+                auto a_block = a.reg.xetla_select<a_tail_blk_elems, 1>(
+                        a_tile_size_x * tail_start_m + k_i * a_tail_blk_elems);
+#pragma unroll
+                for (int j = 0; j < num_block_n; j++) {
+                    auto b_block = b_reg.xetla_select<b_block_elems, 1>(
+                            j * b_block_elems);
+                    auto dst_block
+                            = dst.reg.xetla_select<acc_tail_blk_elems, 1>(
+                                    (tail_start_m * tile_size_n)
+                                    + j * acc_tail_blk_elems);
+                    mma_core<tail_size_m, block_size_n, block_size_k>(
+                            dst_block, dst_block, b_block, a_block);
+                }
+            }
+        }
+    }
+};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/load_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/load_xe.hpp
new file mode 100644
index 00000000000000..16a0fb62ab09ee
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/load_xe.hpp
@@ -0,0 +1,926 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/impl/op_function.hpp"
+#include "subgroup/tile/impl/payload_xe.hpp"
+
+namespace gpu::xetla::subgroup {
+
+namespace detail {
+template <typename tile_t, typename payload_t>
+struct check_load_type {
+    static constexpr bool is_global_2d_xe
+            = (payload_t::memory_space == mem_space::global
+                    && (payload_t::message_type == msg_type::block_2d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_global_block_1d_xe
+            = ((payload_t::memory_space == mem_space::global)
+                    && (tile_t::tile_size_y == 1) && (tile_t::block_size_y == 1)
+                    && (payload_t::message_type == msg_type::block_1d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_global_unaligned_2d_xe
+            = ((payload_t::memory_space == mem_space::global)
+                    && (payload_t::message_type == msg_type::unaligned_2d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_local_scatter_xe
+            = ((payload_t::memory_space == mem_space::local)
+                    && (payload_t::message_type == msg_type::scatter)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_local_block_1d_xe
+            = ((payload_t::memory_space == mem_space::local)
+                    && (tile_t::block_size_y == 1)
+                    && (payload_t::message_type == msg_type::block_1d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+};
+
+} // namespace detail
+
+/// @brief This function loads data from 2D memory surface.
+/// Loads an array of rectangular regions (X,Y)..(X+W,Y+H) from memory into registers.
+/// Each block will be loaded serially by its corresponding payload.
+/// @tparam tile_t Is the tile_t struct contains registers.
+/// These registers will be the destination of load operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory information
+/// Payload indicates the source of load operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, holds the return data of the loads.
+/// @param payload Is the payload object with type payload_t. Contains all the information for loads.
+/// @return No return, update in place.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename tile_t, typename payload_t>
+__XETLA_API typename std::enable_if_t<tile_t::dst
+        && detail::check_load_type<tile_t, payload_t>::is_global_2d_xe>
+tile_load(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using load_dtype = typename payload_t::mem_dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using check_load = typename subgroup::check_load<gpu_arch::Xe, dtype,
+            load_dtype>::template global_2d<payload_t::mem_transform,
+            tile_desc::block_size_x>;
+
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+
+    static constexpr uint32_t block_elems = tile_desc::block_elems;
+
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+    static constexpr uint32_t num_block_y = tile_desc::num_block_y;
+    static constexpr uint32_t num_block = tile_desc::num_block;
+
+    static constexpr gpu_arch arch_tag = payload_t::arch_tag;
+
+    static constexpr reg_layout reg_layout_ = tile_desc::register_layout;
+    static constexpr bool is_vnni_reverse = payload_t::mem_dword_transpose
+            && ((reg_layout_ == reg_layout::tiled)
+                    || (reg_layout_ == reg_layout::transpose_tiled));
+    static constexpr bool reg_transpose = tile_desc::reg_transpose;
+
+    static constexpr mem_layout mem_layout_ = payload_t::memory_layout;
+    static constexpr bool mem_transpose = payload_t::mem_transpose;
+    static constexpr bool trans = reg_transpose ^ mem_transpose;
+    static constexpr uint32_t scale_factor = payload_t::scale_factor;
+
+    static constexpr bool mem_transform = payload_t::mem_transform;
+
+    using load_store_attr = typename arch_attr_t<
+            arch_tag>::template load_store_attr<msg_type::block_2d>;
+    static constexpr uint32_t elems_per_CL
+            = load_store_attr::cache_line_size_in_bytes / sizeof(dtype);
+    static constexpr uint32_t elems_per_reg
+            = arch_attr_t<arch_tag>::template register_attr<>::reg_in_bytes
+            / sizeof(dtype);
+    static constexpr int32_t max_load_block_height
+            = load_store_attr::max_load_height_in_elem;
+    static constexpr int32_t max_block_width
+            = load_store_attr::max_load_width_in_bytes / sizeof(dtype);
+    static constexpr int32_t max_trans_block_width
+            = load_store_attr::max_trans_load_width_in_bytes / sizeof(dtype);
+    static constexpr int32_t special_trans_block_width
+            = load_store_attr::special_trans_load_width_in_bytes
+            / sizeof(dtype);
+    static constexpr int32_t trans_block_width_limit
+            = (block_size_y % special_trans_block_width) == 0
+            ? special_trans_block_width
+            : max_trans_block_width;
+    static constexpr int32_t max_vnni_block_width
+            = load_store_attr::max_vnni_load_width_in_elems;
+
+    static constexpr uint32_t ld_blk_size_y_limit
+            = mem_transpose ? trans_block_width_limit : max_load_block_height;
+    static constexpr uint32_t ld_blk_size_y = reg_transpose
+            ? block_size_y
+            : (block_size_y > ld_blk_size_y_limit ? ld_blk_size_y_limit
+                                                  : block_size_y);
+
+    // array len is used to make sure memory load is cache line aligned
+    // disabled while register or memory transpose
+    static constexpr uint8_t arr_len_candidate
+            = (reg_transpose
+                      || mem_transpose
+                      // block elements should be integer
+                      // times of register bytes
+                      || ((block_size_y * block_size_x) % elems_per_reg != 0)
+                      // tail blocks also need to meet above condition
+                      || (((tile_size_y % block_size_y) * block_size_x)
+                                      % elems_per_reg
+                              != 0))
+                    || (block_size_y > ld_blk_size_y_limit)
+            ? 1
+            : (((tile_size_x % elems_per_CL) == 0)
+                            ? (((elems_per_CL % block_size_x) == 0)
+                                            ? elems_per_CL / block_size_x
+                                            : 1)
+                            : ((tile_size_x < elems_per_CL)
+                                            ? (tile_size_x / block_size_x)
+                                            : 1));
+    static constexpr bool is_valid_arr_len_candidate = (arr_len_candidate == 1)
+            || (arr_len_candidate == 2) || (arr_len_candidate == 4);
+
+    static constexpr uint8_t arr_len
+            = is_valid_arr_len_candidate ? arr_len_candidate : 1;
+
+    static_assert(reg_transpose || mem_transpose
+                    || (!mem_transpose
+                            && (block_size_x * arr_len) <= max_block_width),
+            "When reg_transpose was disabled, check 2d block width "
+            "restriction");
+    static_assert(!reg_transpose
+                    || (!mem_transpose
+                            && (block_size_x * arr_len)
+                                    <= trans_block_width_limit)
+                    || (mem_transpose
+                            && (block_size_y * arr_len) <= max_block_width),
+            "When reg_transpose was enabled, check 2d block width "
+            "restriction");
+    static_assert(!reg_transpose
+                    || (!mem_transpose
+                            && (block_size_y <= max_load_block_height))
+                    || (mem_transpose
+                            && (block_size_x) <= max_load_block_height),
+            "When reg_transpose was enabled, check 2d block height "
+            "restriction");
+    static_assert(tile_size_x % (block_size_x * arr_len) == 0,
+            "tile_size_x should be a multiple of (block_size_x * arr_len)");
+    static_assert(
+            (reg_transpose
+                    && ((block_size_x * sizeof(dtype)) % sizeof(load_dtype)
+                            == 0))
+                    || ((block_size_y * sizeof(dtype)) % sizeof(load_dtype)
+                            == 0),
+            "check vnni limitation for DW transpose");
+
+    auto payload_2d = payload.payloads.xetla_format<uint32_t, num_block, 16>();
+    uint32_t base_offset_y = 0;
+#pragma unroll
+    for (int i = 0; i < num_block_y; ++i) {
+        constexpr uint32_t load_block_elems = block_elems * arr_len;
+        auto payload_row = payload_2d.xetla_select<num_block_x, 1, 16, 1>(
+                i * num_block_x, 0);
+        detail::reset_tile_desc_core<num_block_x, block_size_x, ld_blk_size_y,
+                scale_factor, arr_len, mem_transpose>(payload_row);
+#pragma unroll
+        for (int j = 0; j < num_block_x; j += arr_len) {
+            xetla_tdescriptor tdesc = payload_row.row(j);
+            auto reg_blk = tile.reg.xetla_select<load_block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            constexpr uint32_t ld_blk_height = (reg_transpose && trans)
+                    ? detail::getNextPowerOf2<ld_blk_size_y>()
+                    : ld_blk_size_y;
+            constexpr uint32_t tmp_size
+                    = ld_blk_height * block_size_x * arr_len;
+            xetla_vector<dtype, tmp_size> reg_tmp;
+#pragma unroll
+            for (int ii = 0; ii < block_size_y / ld_blk_size_y; ++ii) {
+                constexpr uint32_t load_elems
+                        = ld_blk_size_y * block_size_x * arr_len;
+
+                reg_tmp.xetla_format<native_type_t<load_dtype>>()
+                        = xetla_tload_global<load_dtype,
+                                ld_blk_height * block_size_x * arr_len
+                                        / scale_factor,
+                                L1, L2, trans, mem_transform, arch_tag>(tdesc);
+
+                if constexpr (reg_transpose && trans) {
+                    reg_blk.xetla_select<load_elems, 1>(ii * load_elems)
+                            .xetla_format<native_type_t<load_dtype>>()
+                            = reg_tmp.xetla_format<load_dtype,
+                                             block_size_x / scale_factor,
+                                             ld_blk_height>()
+                                      .xetla_select<block_size_x / scale_factor,
+                                              1, ld_blk_size_y, 1>(0, 0);
+                } else {
+                    reg_blk.xetla_select<tmp_size, 1>(ii * tmp_size) = reg_tmp;
+                }
+
+                if constexpr (mem_transpose) {
+                    xetla_update_tdesc_offsetx(tdesc.xetla_format<uint32_t>(),
+                            ld_blk_size_y / scale_factor);
+                } else {
+                    xetla_update_tdesc_offsety(
+                            tdesc.xetla_format<uint32_t>(), ld_blk_size_y);
+                }
+            }
+            // exceed HW limitation
+            if constexpr (block_size_y % ld_blk_size_y != 0) {
+                constexpr uint32_t remained_start_y
+                        = block_size_y / ld_blk_size_y * ld_blk_size_y;
+                constexpr uint32_t remained_start
+                        = remained_start_y * block_size_x * arr_len;
+                constexpr uint32_t remained_blk_size_y
+                        = block_size_y % ld_blk_size_y;
+                constexpr uint32_t load_elems
+                        = remained_blk_size_y * block_size_x * arr_len;
+
+                constexpr uint8_t block_width = mem_transpose
+                        ? (remained_blk_size_y / scale_factor)
+                        : block_size_x;
+                constexpr uint8_t block_height
+                        = trans ? block_size_x : remained_blk_size_y;
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_width - 1) | ((block_height - 1) << 8);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc.xetla_format<uint32_t>(),
+                        block_widthx_widthy_arrlen);
+
+                reg_blk.xetla_select<load_elems, 1>(remained_start)
+                        .xetla_format<native_type_t<load_dtype>>()
+                        = xetla_tload_global<load_dtype,
+                                (load_elems / scale_factor), L1, L2, trans,
+                                mem_transform, arch_tag>(tdesc);
+            }
+        }
+    }
+    // process tail
+    if constexpr (remained_size_y > 0) {
+        constexpr uint32_t remained_block_elems
+                = block_size_x * remained_size_y;
+        constexpr uint32_t processed_elems
+                = num_block_y * num_block_x * block_elems;
+
+        static constexpr int32_t tail_trans_block_width_limit
+                = (remained_size_y % special_trans_block_width) == 0
+                ? special_trans_block_width
+                : max_trans_block_width;
+
+        static constexpr uint32_t tail_ld_blk_size_y_limit = mem_transpose
+                ? tail_trans_block_width_limit
+                : max_load_block_height;
+
+        constexpr uint32_t remained_ld_blk_size_y
+                = (!reg_transpose
+                          && (remained_size_y > tail_ld_blk_size_y_limit))
+                ? tail_ld_blk_size_y_limit
+                : remained_size_y;
+        auto payload_row = payload_2d.xetla_select<num_block_x, 1, 16, 1>(
+                num_block_y * num_block_x, 0);
+        detail::reset_tile_desc_core<num_block_x, block_size_x,
+                remained_ld_blk_size_y, scale_factor, arr_len, mem_transpose>(
+                payload_row);
+#pragma unroll
+        for (int j = 0; j < num_block_x; j += arr_len) {
+            xetla_tdescriptor tdesc = payload_row.row(j);
+            auto reg_blk
+                    = tile.reg.xetla_select<remained_block_elems * arr_len, 1>(
+                            processed_elems + j * remained_block_elems);
+            constexpr uint32_t ld_blk_height = (reg_transpose && trans)
+                    ? detail::getNextPowerOf2<remained_ld_blk_size_y>()
+                    : remained_ld_blk_size_y;
+            constexpr uint32_t tmp_size
+                    = ld_blk_height * block_size_x * arr_len;
+            xetla_vector<dtype, tmp_size> reg_tmp;
+#pragma unroll
+            for (int ii = 0; ii < remained_size_y / remained_ld_blk_size_y;
+                    ++ii) {
+                constexpr uint32_t load_elems
+                        = remained_ld_blk_size_y * block_size_x * arr_len;
+
+                reg_tmp.xetla_format<native_type_t<load_dtype>>()
+                        = xetla_tload_global<load_dtype,
+                                (ld_blk_height * block_size_x * arr_len
+                                        / scale_factor),
+                                L1, L2, trans, mem_transform, arch_tag>(tdesc);
+
+                if constexpr (reg_transpose && trans) {
+                    reg_blk.xetla_select<load_elems, 1>(ii * load_elems)
+                            .xetla_format<native_type_t<load_dtype>>()
+                            = reg_tmp.xetla_format<load_dtype,
+                                             block_size_x / scale_factor,
+                                             ld_blk_height>()
+                                      .xetla_select<block_size_x / scale_factor,
+                                              1, remained_ld_blk_size_y, 1>(
+                                              0, 0);
+                } else {
+                    reg_blk.xetla_select<tmp_size, 1>(ii * tmp_size) = reg_tmp;
+                }
+                if constexpr (mem_transpose) {
+                    xetla_update_tdesc_offsetx(tdesc.xetla_format<uint32_t>(),
+                            remained_ld_blk_size_y / scale_factor);
+                } else {
+                    xetla_update_tdesc_offsety(tdesc.xetla_format<uint32_t>(),
+                            remained_ld_blk_size_y);
+                }
+            }
+            constexpr uint32_t final_ld_blk_size_y
+                    = remained_size_y % remained_ld_blk_size_y;
+            if constexpr (final_ld_blk_size_y != 0) {
+                constexpr uint32_t final_start = remained_size_y
+                        / remained_ld_blk_size_y * remained_ld_blk_size_y
+                        * block_size_x * arr_len;
+                constexpr uint32_t final_load_elems
+                        = final_ld_blk_size_y * block_size_x * arr_len;
+                constexpr uint8_t block_width = mem_transpose
+                        ? (final_ld_blk_size_y / scale_factor)
+                        : block_size_x;
+                constexpr uint8_t block_height
+                        = trans ? block_size_x : final_ld_blk_size_y;
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_width - 1) | ((block_height - 1) << 8);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc.xetla_format<uint32_t>(),
+                        block_widthx_widthy_arrlen);
+                reg_blk.xetla_select<final_load_elems, 1>(final_start)
+                        .xetla_format<native_type_t<load_dtype>>()
+                        = xetla_tload_global<load_dtype,
+                                final_load_elems / scale_factor, L1, L2, trans,
+                                mem_transform, arch_tag>(tdesc);
+            }
+        }
+    }
+
+    if constexpr (is_vnni_reverse) {
+        SW_BARRIER();
+        vnni_reverse(tile);
+    }
+}
+
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename tile_t, typename payload_t>
+__XETLA_API typename std::enable_if_t<!tile_t::dst> tile_load(
+        tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using load_dtype = typename payload_t::mem_dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using check_load = typename subgroup::check_load<gpu_arch::Xe, dtype,
+            load_dtype>::template global_2d<payload_t::mem_transform,
+            tile_desc::block_size_x>;
+
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+
+    static constexpr uint32_t block_elems = tile_desc::block_elems;
+
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+    static constexpr uint32_t num_block_y = tile_desc::num_block_y;
+    static constexpr uint32_t num_block = tile_desc::num_block;
+
+    static constexpr gpu_arch arch_tag = payload_t::arch_tag;
+
+    static constexpr reg_layout reg_layout_ = tile_desc::register_layout;
+    static constexpr bool is_vnni_reverse = payload_t::mem_dword_transpose
+            && ((reg_layout_ == reg_layout::tiled)
+                    || (reg_layout_ == reg_layout::transpose_tiled));
+    static constexpr bool reg_transpose = tile_desc::reg_transpose;
+
+    static constexpr mem_layout mem_layout_ = payload_t::memory_layout;
+    static constexpr bool mem_transpose = payload_t::mem_transpose;
+    static constexpr bool trans = reg_transpose ^ mem_transpose;
+    static constexpr uint32_t scale_factor = payload_t::scale_factor;
+
+    static constexpr bool mem_transform = payload_t::mem_transform;
+
+    using load_store_attr = typename arch_attr_t<
+            arch_tag>::template load_store_attr<msg_type::block_2d>;
+    static constexpr uint32_t elems_per_CL
+            = load_store_attr::cache_line_size_in_bytes / sizeof(dtype);
+    static constexpr uint32_t elems_per_reg
+            = arch_attr_t<arch_tag>::template register_attr<>::reg_in_bytes
+            / sizeof(dtype);
+    static constexpr int32_t max_load_block_height
+            = load_store_attr::max_load_height_in_elem;
+    static constexpr int32_t max_block_width
+            = load_store_attr::max_load_width_in_bytes / sizeof(dtype);
+    static constexpr int32_t max_trans_block_width
+            = load_store_attr::max_trans_load_width_in_bytes / sizeof(dtype);
+    static constexpr int32_t special_trans_block_width
+            = load_store_attr::special_trans_load_width_in_bytes
+            / sizeof(dtype);
+    static constexpr int32_t trans_block_width_limit
+            = (block_size_y % special_trans_block_width) == 0
+            ? special_trans_block_width
+            : max_trans_block_width;
+    static constexpr int32_t max_vnni_block_width
+            = load_store_attr::max_vnni_load_width_in_elems;
+
+    static constexpr uint32_t ld_blk_size_y_limit
+            = mem_transpose ? trans_block_width_limit : max_load_block_height;
+    static constexpr uint32_t ld_blk_size_y = reg_transpose
+            ? block_size_y
+            : (block_size_y > ld_blk_size_y_limit ? ld_blk_size_y_limit
+                                                  : block_size_y);
+
+    // array len is used to make sure memory load is cache line aligned
+    // disabled while register or memory transpose
+    static constexpr uint8_t arr_len_candidate
+            = (reg_transpose
+                      || mem_transpose
+                      // block elements should be integer
+                      // times of register bytes
+                      || ((block_size_y * block_size_x) % elems_per_reg != 0)
+                      // tail blocks also need to meet above condition
+                      || (((tile_size_y % block_size_y) * block_size_x)
+                                      % elems_per_reg
+                              != 0))
+                    || (block_size_y > ld_blk_size_y_limit)
+            ? 1
+            : (((tile_size_x % elems_per_CL) == 0)
+                            ? (((elems_per_CL % block_size_x) == 0)
+                                            ? elems_per_CL / block_size_x
+                                            : 1)
+                            : ((tile_size_x < elems_per_CL)
+                                            ? (tile_size_x / block_size_x)
+                                            : 1));
+    static constexpr bool is_valid_arr_len_candidate = (arr_len_candidate == 1)
+            || (arr_len_candidate == 2) || (arr_len_candidate == 4);
+
+    static constexpr uint8_t arr_len
+            = is_valid_arr_len_candidate ? arr_len_candidate : 1;
+
+    static_assert(reg_transpose || mem_transpose
+                    || (!mem_transpose
+                            && (block_size_x * arr_len) <= max_block_width),
+            "When reg_transpose was disabled, check 2d block width "
+            "restriction");
+    static_assert(!reg_transpose
+                    || (!mem_transpose
+                            && (block_size_x * arr_len)
+                                    <= trans_block_width_limit)
+                    || (mem_transpose
+                            && (block_size_y * arr_len) <= max_block_width),
+            "When reg_transpose was enabled, check 2d block width "
+            "restriction");
+    static_assert(!reg_transpose
+                    || (!mem_transpose
+                            && (block_size_y <= max_load_block_height))
+                    || (mem_transpose
+                            && (block_size_x) <= max_load_block_height),
+            "When reg_transpose was enabled, check 2d block height "
+            "restriction");
+    static_assert(tile_size_x % (block_size_x * arr_len) == 0,
+            "tile_size_x should be a multiple of (block_size_x * arr_len)");
+    static_assert(
+            (reg_transpose
+                    && ((block_size_x * sizeof(dtype)) % sizeof(load_dtype)
+                            == 0))
+                    || ((block_size_y * sizeof(dtype)) % sizeof(load_dtype)
+                            == 0),
+            "check vnni limitation for DW transpose");
+
+    auto payload_2d = payload.payloads.xetla_format<uint32_t, num_block, 16>();
+    uint32_t base_offset_y = 0;
+#pragma unroll
+    for (int i = 0; i < num_block_y; ++i) {
+        constexpr uint32_t load_block_elems = block_elems * arr_len;
+        auto payload_row = payload_2d.xetla_select<num_block_x, 1, 16, 1>(
+                i * num_block_x, 0);
+        detail::reset_tile_desc_core<num_block_x, block_size_x, ld_blk_size_y,
+                scale_factor, arr_len, mem_transpose>(payload_row);
+#pragma unroll
+        for (int j = 0; j < num_block_x; j += arr_len) {
+            xetla_tdescriptor tdesc = payload_row.row(j);
+            constexpr uint32_t ld_blk_height = (reg_transpose && trans)
+                    ? detail::getNextPowerOf2<ld_blk_size_y>()
+                    : ld_blk_size_y;
+#pragma unroll
+            for (int ii = 0; ii < block_size_y / ld_blk_size_y; ++ii) {
+                xetla_tprefetch_global<load_dtype, L1, L2, arch_tag>(tdesc);
+                if constexpr (mem_transpose) {
+                    xetla_update_tdesc_offsetx(tdesc.xetla_format<uint32_t>(),
+                            ld_blk_size_y / scale_factor);
+                } else {
+                    xetla_update_tdesc_offsety(
+                            tdesc.xetla_format<uint32_t>(), ld_blk_size_y);
+                }
+            }
+            // exceed HW limitation
+            if constexpr (block_size_y % ld_blk_size_y != 0) {
+                constexpr uint32_t remained_start_y
+                        = block_size_y / ld_blk_size_y * ld_blk_size_y;
+                constexpr uint32_t remained_start
+                        = remained_start_y * block_size_x * arr_len;
+                constexpr uint32_t remained_blk_size_y
+                        = block_size_y % ld_blk_size_y;
+                constexpr uint32_t load_elems
+                        = remained_blk_size_y * block_size_x * arr_len;
+
+                constexpr uint8_t block_width = mem_transpose
+                        ? (remained_blk_size_y / scale_factor)
+                        : block_size_x;
+                constexpr uint8_t block_height
+                        = trans ? block_size_x : remained_blk_size_y;
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_width - 1) | ((block_height - 1) << 8);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc.xetla_format<uint32_t>(),
+                        block_widthx_widthy_arrlen);
+                xetla_tprefetch_global<load_dtype, L1, L2, arch_tag>(tdesc);
+            }
+        }
+    }
+    // process tail
+    if constexpr (remained_size_y > 0) {
+        constexpr uint32_t remained_block_elems
+                = block_size_x * remained_size_y;
+        constexpr uint32_t processed_elems
+                = num_block_y * num_block_x * block_elems;
+
+        static constexpr int32_t tail_trans_block_width_limit
+                = (remained_size_y % special_trans_block_width) == 0
+                ? special_trans_block_width
+                : max_trans_block_width;
+
+        static constexpr uint32_t tail_ld_blk_size_y_limit = mem_transpose
+                ? tail_trans_block_width_limit
+                : max_load_block_height;
+
+        constexpr uint32_t remained_ld_blk_size_y
+                = (!reg_transpose
+                          && (remained_size_y > tail_ld_blk_size_y_limit))
+                ? tail_ld_blk_size_y_limit
+                : remained_size_y;
+        auto payload_row = payload_2d.xetla_select<num_block_x, 1, 16, 1>(
+                num_block_y * num_block_x, 0);
+        detail::reset_tile_desc_core<num_block_x, block_size_x,
+                remained_ld_blk_size_y, scale_factor, arr_len, mem_transpose>(
+                payload_row);
+#pragma unroll
+        for (int j = 0; j < num_block_x; j += arr_len) {
+            xetla_tdescriptor tdesc = payload_row.row(j);
+            constexpr uint32_t ld_blk_height = (reg_transpose && trans)
+                    ? detail::getNextPowerOf2<remained_ld_blk_size_y>()
+                    : remained_ld_blk_size_y;
+#pragma unroll
+            for (int ii = 0; ii < remained_size_y / remained_ld_blk_size_y;
+                    ++ii) {
+                xetla_tprefetch_global<load_dtype, L1, L2, arch_tag>(tdesc);
+            }
+            constexpr uint32_t final_ld_blk_size_y
+                    = remained_size_y % remained_ld_blk_size_y;
+            if constexpr (final_ld_blk_size_y != 0) {
+                constexpr uint32_t final_start = remained_size_y
+                        / remained_ld_blk_size_y * remained_ld_blk_size_y
+                        * block_size_x * arr_len;
+                constexpr uint32_t final_load_elems
+                        = final_ld_blk_size_y * block_size_x * arr_len;
+                constexpr uint8_t block_width = mem_transpose
+                        ? (final_ld_blk_size_y / scale_factor)
+                        : block_size_x;
+                constexpr uint8_t block_height
+                        = trans ? block_size_x : final_ld_blk_size_y;
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_width - 1) | ((block_height - 1) << 8);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc.xetla_format<uint32_t>(),
+                        block_widthx_widthy_arrlen);
+                xetla_tprefetch_global<load_dtype, L1, L2, arch_tag>(tdesc);
+            }
+        }
+    }
+}
+
+/// @brief This function loads data from memory.
+/// For each enabled SIMT lane, a vector is read from memory into registers.
+/// @tparam tile_t Is the tile_t struct contains registers.
+/// These registers will be the destination of load operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory information.
+/// Payload indicates the source of load operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, holds the return data of the loads.
+/// @param payload Is the payload object with type payload_t. Contains all the information for loads.
+/// @return No return, update in place.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename tile_t, typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_load_type<tile_t, payload_t>::is_global_block_1d_xe>
+tile_load(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using load_dtype = typename payload_t::mem_dtype;
+    using check_load = typename subgroup::check_load<gpu_arch::Xe, dtype,
+            load_dtype>::global_1d;
+
+    static constexpr uint32_t tile_size_x = tile_t::tile_size_x;
+    static constexpr uint32_t scale_factor = payload_t::scale_factor;
+    constexpr uint32_t load_len = tile_size_x / scale_factor;
+
+    if constexpr (load_len >= 64) {
+#pragma unroll
+        for (int i = 0; i < load_len / 64; i++) {
+            uint32_t offset_x = i * 64 * scale_factor;
+            auto reg_sub
+                    = tile.reg.xetla_select<64 * scale_factor, 1>(offset_x);
+            uint32_t address_offset = offset_x * sizeof(dtype);
+            reg_sub.xetla_format<load_dtype>() = xetla_load_global<load_dtype,
+                    64, data_size::default_size, L1, L2>(
+                    payload.base_ptr, payload.base_offset + address_offset);
+        }
+    }
+    constexpr uint32_t tail_len = load_len % 64;
+    uint32_t tail_offset = load_len / 64 * 64 * scale_factor;
+    detail::process_1d_tail<tail_len, 32, detail::process_flag::load, L1, L2>(
+            tile, payload, tail_offset);
+}
+
+/// @brief This function loads data from unaligned-2D memory surface.
+/// Loads an array of rectangular regions (X,Y)..(X+W,Y+H) from memory into registers.
+/// Each block will be loaded serially by its corresponding payload.
+/// @tparam tile_t Is the tile_t struct contains registers.
+/// These registers will be the destination of load operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory information.
+/// Payload indicates the source of load operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L3 Is the cache hint for L3 cache.
+/// @param tile Is the tile object with type tile_t, holds the return data of the loads.
+/// @param payload Is the payload object with type payload_t. Contains all the information for loads.
+/// @return No return, update in place.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L3 = cache_hint::cached, typename tile_t, typename payload_t,
+        typename oob_check_tag = global_atomic_oob_check_on_tag>
+__XETLA_API typename std::enable_if_t<
+        detail::check_load_type<tile_t, payload_t>::is_global_unaligned_2d_xe>
+tile_load(tile_t &tile, payload_t &payload, oob_check_tag tag = {}) {
+    constexpr bool oob_check = std::is_same<oob_check_tag,
+            global_atomic_oob_check_on_tag>::value;
+    using dtype = typename payload_t::dtype;
+    using tile_desc = typename payload_t::tile_desc;
+    using load_dtype = typename payload_t::mem_dtype;
+    using check_load = typename subgroup::check_load<gpu_arch::Xe, dtype,
+            load_dtype>::template unaligned_2d<payload_t::mem_transform,
+            tile_desc::block_size_x>;
+    constexpr uint32_t num_channel_y = payload_t::num_channel_y;
+    constexpr uint32_t load_elems = num_channel_y * payload_t::num_channel_x;
+    constexpr uint32_t scale_factor = payload_t::scale_factor;
+
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y / tile_desc::block_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::block_size_y;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<tile_desc::block_elems, 1>(
+                    (i * tile_desc::num_block_x + j) * tile_desc::block_elems);
+            xetla_mask<load_elems> pred_x = oob_check
+                    ? payload.step_x + payload.base_x + offset_x
+                            < payload.width_in_elems
+                    : 1;
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < tile_desc::block_size_y;
+                    sub_block_y += num_channel_y) {
+                xetla_vector<load_dtype, load_elems> reg_tmp;
+                xetla_mask<load_elems> pred_y = oob_check
+                        ? payload.step_y + payload.base_y + offset_y
+                                        + sub_block_y
+                                < payload.height_in_elems
+                        : 1;
+
+                uint32_t address_offset = payload_t::trans
+                        ? offset_x * payload.pitch_in_bytes
+                                + (offset_y + sub_block_y) * sizeof(dtype)
+                        : offset_x * sizeof(dtype)
+                                + (offset_y + sub_block_y)
+                                        * payload.pitch_in_bytes;
+
+                reg_tmp = xetla_load_global<load_dtype, 1,
+                        data_size::default_size, L1, L3, load_elems>(
+                        payload.base_ptr,
+                        payload.channel_offset + payload.base_offset
+                                + address_offset,
+                        pred_x && pred_y);
+                reg_tmp.xetla_merge(reg_tmp, 0, pred_x && pred_y);
+
+                reg_sub.xetla_select<load_elems * scale_factor, 1>(
+                               sub_block_y * tile_desc::block_size_x)
+                        .xetla_format<load_dtype>()
+                        = reg_tmp;
+            }
+        }
+    }
+    //process the tail
+    if constexpr ((tile_desc::tile_size_y % tile_desc::block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_desc::tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_desc::tile_size_x;
+        constexpr uint32_t remain_block_elems
+                = remained_size_y * tile_desc::block_size_x;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+            xetla_mask<load_elems> pred_x = oob_check
+                    ? payload.step_x + payload.base_x + offset_x
+                            < payload.width_in_elems
+                    : 1;
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < remained_size_y;
+                    sub_block_y += num_channel_y) {
+                xetla_vector<load_dtype, load_elems> reg_tmp;
+                xetla_mask<load_elems> pred_y = oob_check
+                        ? payload.step_y + payload.base_y + offset_y
+                                        + sub_block_y
+                                < payload.height_in_elems
+                        : 1;
+
+                uint32_t address_offset = payload_t::trans
+                        ? offset_x * payload.pitch_in_bytes
+                                + (offset_y + sub_block_y) * sizeof(dtype)
+                        : offset_x * sizeof(dtype)
+                                + (offset_y + sub_block_y)
+                                        * payload.pitch_in_bytes;
+
+                reg_tmp = xetla_load_global<load_dtype, 1,
+                        data_size::default_size, L1, L3, load_elems>(
+                        payload.base_ptr,
+                        payload.channel_offset + payload.base_offset
+                                + address_offset,
+                        pred_x && pred_y);
+
+                reg_tmp.xetla_merge(reg_tmp, 0, pred_x && pred_y);
+
+                reg_sub.xetla_select<load_elems * scale_factor, 1>(
+                               sub_block_y * tile_desc::block_size_x)
+                        .xetla_format<load_dtype>()
+                        = reg_tmp;
+            }
+        }
+    }
+
+    if constexpr (payload_t::mem_transform) {
+        SW_BARRIER();
+        vnni_convert(tile);
+    }
+}
+
+/// @brief Is the data load func from local shared memory to register file, which
+/// supports the memory surface is 1d or 2d scenario. And we always assume data in SLM
+/// is row major.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the destination of load operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory information.
+/// Payload indicates the source of load operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, holds the return data of the loads.
+/// @param payload Is the payload object with type payload_t. Contains all the information for loads.
+/// @return No return, update in place.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename tile_t, typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_load_type<tile_t, payload_t>::is_local_scatter_xe>
+tile_load(tile_t &tile, payload_t &payload) {
+    using dtype = typename payload_t::dtype;
+    using tile_desc = typename payload_t::tile_desc;
+    using load_dtype = typename payload_t::mem_dtype;
+    using check_load = typename subgroup::check_load<gpu_arch::Xe, dtype,
+            load_dtype>::template local_scatter<payload_t::memory_layout,
+            payload_t::tile_desc::block_size_x, payload_t::tile_bytes,
+            payload_t::min_bytes, payload_t::block_bytes,
+            payload_t::num_channel_x, payload_t::num_channel>;
+
+    constexpr uint32_t num_channel_y = payload_t::num_channel_y;
+    constexpr uint32_t load_elems = num_channel_y * tile_desc::block_size_x;
+    static constexpr bool mem_transform = payload_t::mem_transform;
+
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y / tile_desc::block_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::block_size_y;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<tile_desc::block_elems, 1>(
+                    (i * tile_desc::num_block_x + j) * tile_desc::block_elems);
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < tile_desc::block_size_y;
+                    sub_block_y += num_channel_y) {
+                uint32_t address_offset = offset_x * sizeof(dtype)
+                        + (sub_block_y + offset_y) * payload.pitch_in_bytes;
+                reg_sub.xetla_select<load_elems, 1>(
+                               sub_block_y * tile_desc::block_size_x)
+                        .xetla_format<load_dtype>()
+                        = xetla_load_local<load_dtype>(
+                                payload.address + address_offset);
+            }
+        }
+    }
+    //process the tail
+    if constexpr ((tile_desc::tile_size_y % tile_desc::block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_desc::tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_desc::tile_size_x;
+        constexpr uint32_t remain_block_elems
+                = remained_size_y * tile_desc::block_size_x;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < remained_size_y;
+                    sub_block_y += num_channel_y) {
+                uint32_t address_offset = offset_x * sizeof(dtype)
+                        + (sub_block_y + offset_y) * payload.pitch_in_bytes;
+                reg_sub.xetla_select<load_elems, 1>(
+                               sub_block_y * tile_desc::block_size_x)
+                        .xetla_format<load_dtype>()
+                        = xetla_load_local<load_dtype>(
+                                payload.address + address_offset);
+            }
+        }
+    }
+    if constexpr (mem_transform) {
+        SW_BARRIER();
+        vnni_convert(tile);
+    }
+}
+
+/// @brief Is the data load func from shared local memory to register file, which
+/// supports the memory surface is 1d scenario. And the src memory layout is always
+/// row major.
+/// @tparam tile_t Is the tile_t struct contains registers.
+/// These registers will be the destination of load operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory information.
+/// Payload indicates the source of load operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, holds the return data of the loads.
+/// @param payload Is the payload object with type payload_t. Contains all the information for loads.
+/// @return No return, update in place.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename tile_t, typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_load_type<tile_t, payload_t>::is_local_block_1d_xe>
+tile_load(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using load_dtype = typename payload_t::mem_dtype;
+    using check_load = typename subgroup::check_load<gpu_arch::Xe, dtype,
+            load_dtype>::local_1d;
+
+    constexpr uint32_t scale_factor = payload_t::scale_factor;
+    constexpr uint32_t load_len = tile_desc::tile_size_x / scale_factor;
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::tile_size_x;
+        uint32_t address_offset_y = i * payload.pitch_in_bytes;
+        if constexpr (load_len >= 64) {
+#pragma unroll
+            for (int j = 0; j < load_len / 64; j++) {
+                uint32_t offset_x = j * 64 * scale_factor;
+                auto reg_sub = tile.reg.xetla_select<64 * scale_factor, 1>(
+                        offset_x + offset_y);
+                uint32_t address_offset
+                        = address_offset_y + offset_x * sizeof(dtype);
+                reg_sub.xetla_format<load_dtype>()
+                        = xetla_load_local<load_dtype, 64,
+                                data_size::default_size>(payload.base_address
+                                + payload.address + address_offset);
+            }
+        }
+        uint32_t tail_offset = offset_y + load_len / 64 * 64 * scale_factor;
+        uint32_t tail_address_offset = address_offset_y
+                + load_len / 64 * 64 * scale_factor * sizeof(dtype);
+        detail::process_1d_tail<load_len % 64, 32, detail::process_flag::load,
+                L1, L2>(tile, payload, tail_offset, tail_address_offset);
+    }
+}
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/mma_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/mma_xe.hpp
new file mode 100644
index 00000000000000..3e447046e9af10
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/mma_xe.hpp
@@ -0,0 +1,260 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+
+namespace gpu::xetla::subgroup {
+
+/// @brief Is the tile mma operation functor, specialized for Xe and matrix engine.
+template <typename matAcc_dst_t_, typename matAcc_src_t_, typename matB_t_,
+        typename matA_t_, gpu_arch arch_tag_>
+struct tile_mma_t<matAcc_dst_t_, matAcc_src_t_, matB_t_, matA_t_,
+        mma_engine::xmx, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using matA_t = matA_t_;
+    using matB_t = matB_t_;
+    using matSrc_t = matAcc_src_t_;
+    using matDst_t = matAcc_dst_t_;
+    using dtype_a = typename matA_t::dtype;
+    using dtype_b = typename matB_t::dtype;
+    using dtype_src = typename matSrc_t::dtype;
+    using dtype_dst = typename matDst_t::dtype;
+
+    using mma_attr = typename arch_attr_t<arch_tag_>::mma_attr;
+
+    static constexpr uint32_t a_tile_size_y = matA_t::tile_size_y;
+    static constexpr uint32_t a_tile_size_x = matA_t::tile_size_x;
+    static constexpr uint32_t a_tile_elems = matA_t::tile_elems;
+    static constexpr uint32_t a_block_size_y = matA_t::block_size_y;
+    static constexpr uint32_t a_block_size_x = matA_t::block_size_x;
+    static constexpr uint32_t a_block_elems = matA_t::block_elems;
+
+    static constexpr uint32_t b_tile_size_x = matB_t::tile_size_x;
+    static constexpr uint32_t b_tile_size_y = matB_t::tile_size_y;
+    static constexpr uint32_t b_tile_elems = matB_t::tile_elems;
+    static constexpr uint32_t b_block_size_x = matB_t::block_size_x;
+    static constexpr uint32_t b_block_size_y = matB_t::block_size_y;
+    static constexpr uint32_t b_block_elems = matB_t::block_elems;
+
+    static constexpr uint32_t tile_size_m = matDst_t::tile_size_y;
+    static constexpr uint32_t tile_size_k = a_tile_size_x;
+    static constexpr uint32_t tile_size_n = matDst_t::tile_size_x;
+    static constexpr uint32_t tile_elems = tile_size_m * tile_size_n;
+    static constexpr uint32_t block_size_n = matDst_t::block_size_x;
+    static constexpr uint32_t block_size_k
+            = a_block_size_x; //cannot use b_block_size_y
+    static constexpr uint32_t block_size_m = matDst_t::block_size_y;
+    static constexpr uint32_t block_elems = block_size_m * block_size_n;
+
+    static_assert(tile_size_m == matA_t::tile_size_y,
+            "matAcc tile m should match with matA tile m");
+    static_assert(a_tile_size_x == b_tile_size_y,
+            "matA tile k should match with matB tile k");
+    static_assert(tile_size_n == matB_t::tile_size_x,
+            "matAcc tile n should match with matB tile n");
+    static_assert(block_size_m == a_block_size_y,
+            "matAcc block m should match with matA block m");
+    static_assert(block_size_n == b_block_size_x,
+            "matAcc block n should match with matB block n");
+    static_assert(b_block_size_y % a_block_size_x == 0,
+            "matA block k should match with matB block k");
+    static_assert((tile_size_k % block_size_k) == 0,
+            "matAcc tile_size_k should be a multiple of block_size_k");
+    static_assert((block_size_k == 32 / sizeof(dtype_a)),
+            "DPAS depth only support the value of 32 / sizeof(dtype_a). "
+            "Currently we don't support the "
+            "splitting of block when call the DPAS");
+
+    static constexpr int32_t num_block_n = matDst_t::num_block_x;
+    static constexpr int32_t num_block_m = matDst_t::num_block_y;
+    static constexpr int32_t num_block_k = tile_size_k / block_size_k;
+    static constexpr int32_t num_block_mma_b = b_block_size_y / block_size_k;
+    static constexpr uint32_t b_block_mma_elems
+            = b_block_elems / num_block_mma_b;
+
+    static constexpr int32_t mma_m = mma_attr::mma_m_in_elem;
+    static constexpr int32_t mma_k
+            = mma_attr::mma_k_in_bytes / sizeof(uint32_t);
+    static_assert(tile_size_m % mma_m == 0,
+            "tile_size_m shoud be a multiple of mma_m");
+
+    __XETLA_API static void mma(
+            matDst_t &dst, matSrc_t &src, matB_t &b, matA_t &a) {
+        constexpr int32_t a_mma_elems = mma_m * a_block_size_x;
+        constexpr int32_t c_mma_elems = mma_m * block_size_n;
+#pragma unroll
+        for (int j = 0; j < num_block_n; j++) {
+#pragma unroll
+            for (int i = 0; i < tile_size_m / block_size_m; i++) {
+                auto src_block = src.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_n + j) * block_elems);
+                auto dst_block = dst.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_n + j) * block_elems);
+#pragma unroll
+                for (int mma_i = 0; mma_i < block_size_m / mma_m; mma_i++) {
+                    auto src_sub_blk = src_block.xetla_select<c_mma_elems, 1>(
+                            mma_i * c_mma_elems);
+                    auto dst_sub_blk = dst_block.xetla_select<c_mma_elems, 1>(
+                            mma_i * c_mma_elems);
+                    { //k=0
+                        auto a_block = a.reg.xetla_select<a_block_elems, 1>(
+                                (i * num_block_k) * a_block_elems);
+                        auto a_sub_blk = a_block.xetla_select<a_mma_elems, 1>(
+                                mma_i * a_mma_elems);
+                        auto b_blk = b.reg.xetla_select<b_block_elems, 1>(
+                                j * b_block_elems);
+                        auto b_sub_blk
+                                = b_blk.xetla_select<b_block_mma_elems, 1>(0);
+                        dst_sub_blk = xetla_mma<
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_b>(),
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_a>(),
+                                mma_k, mma_m, dtype_src, uint32_t, uint32_t,
+                                c_mma_elems,
+                                b_block_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_b)),
+                                a_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_a))>(
+                                src_sub_blk, b_sub_blk.xetla_format<uint32_t>(),
+                                a_sub_blk.xetla_format<uint32_t>());
+                    }
+
+#pragma unroll
+                    for (int k = 1; k < num_block_k; k++) {
+                        auto a_block = a.reg.xetla_select<a_block_elems, 1>(
+                                (i * num_block_k + k) * a_block_elems);
+                        auto a_sub_blk = a_block.xetla_select<a_mma_elems, 1>(
+                                mma_i * a_mma_elems);
+                        int inter_k_b = k / num_block_mma_b;
+                        int inner_k_b = k % num_block_mma_b;
+                        auto b_blk = b.reg.xetla_select<b_block_elems, 1>(
+                                (j + inter_k_b * num_block_n) * b_block_elems);
+                        auto b_sub_blk
+                                = b_blk.xetla_select<b_block_mma_elems, 1>(
+                                        inner_k_b * b_block_mma_elems);
+                        dst_sub_blk = xetla_mma<
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_b>(),
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_a>(),
+                                mma_k, mma_m, dtype_src, uint32_t, uint32_t,
+                                c_mma_elems,
+                                b_block_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_b)),
+                                a_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_a))>(
+                                dst_sub_blk, b_sub_blk.xetla_format<uint32_t>(),
+                                a_sub_blk.xetla_format<uint32_t>());
+                    }
+                }
+            }
+            if constexpr ((tile_size_m % block_size_m) != 0) {
+                constexpr uint32_t tail_block_size_m
+                        = tile_size_m % block_size_m;
+                constexpr uint32_t tail_block_elems
+                        = block_size_n * tail_block_size_m;
+                constexpr uint32_t a_tail_block_elems
+                        = tail_block_size_m * a_block_size_x;
+                constexpr uint32_t tail_m_start
+                        = tile_size_m / block_size_m * block_size_m;
+                constexpr uint32_t tail_elems_start
+                        = tail_m_start * tile_size_n;
+                constexpr uint32_t a_tail_elems_start
+                        = tail_m_start * a_tile_size_x;
+                auto src_block = src.reg.xetla_select<tail_block_elems, 1>(
+                        tail_elems_start + j * tail_block_elems);
+                auto dst_block = dst.reg.xetla_select<tail_block_elems, 1>(
+                        tail_elems_start + j * tail_block_elems);
+#pragma unroll
+                for (int mma_i = 0; mma_i < tail_block_size_m / mma_m;
+                        mma_i++) {
+                    auto src_sub_blk = src_block.xetla_select<c_mma_elems, 1>(
+                            mma_i * c_mma_elems);
+                    auto dst_sub_blk = dst_block.xetla_select<c_mma_elems, 1>(
+                            mma_i * c_mma_elems);
+                    { //k=0
+                        auto a_block
+                                = a.reg.xetla_select<a_tail_block_elems, 1>(
+                                        a_tail_elems_start);
+                        auto a_sub_blk = a_block.xetla_select<a_mma_elems, 1>(
+                                mma_i * a_mma_elems);
+                        auto b_blk = b.reg.xetla_select<b_block_elems, 1>(
+                                j * b_block_elems);
+                        auto b_sub_blk
+                                = b_blk.xetla_select<b_block_mma_elems, 1>(0);
+
+                        dst_sub_blk = xetla_mma<
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_b>(),
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_a>(),
+                                mma_k, mma_m, dtype_src, uint32_t, uint32_t,
+                                c_mma_elems,
+                                b_block_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_b)),
+                                a_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_a))>(
+                                src_sub_blk, b_sub_blk.xetla_format<uint32_t>(),
+                                a_sub_blk.xetla_format<uint32_t>());
+                    }
+#pragma unroll
+                    for (int k = 1; k < num_block_k; k++) {
+                        auto a_block
+                                = a.reg.xetla_select<a_tail_block_elems, 1>(
+                                        a_tail_elems_start
+                                        + k * a_tail_block_elems);
+                        auto a_sub_blk = a_block.xetla_select<a_mma_elems, 1>(
+                                mma_i * a_mma_elems);
+                        int inter_k_b = k / num_block_mma_b;
+                        int inner_k_b = k % num_block_mma_b;
+                        auto b_blk = b.reg.xetla_select<b_block_elems, 1>(
+                                (j + inter_k_b * num_block_n) * b_block_elems);
+                        auto b_sub_blk
+                                = b_blk.xetla_select<b_block_mma_elems, 1>(
+                                        inner_k_b * b_block_mma_elems);
+
+                        dst_sub_blk = xetla_mma<
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_b>(),
+                                gpu::xetla::detail::mma_argument_type<
+                                        dtype_a>(),
+                                mma_k, mma_m, dtype_src, uint32_t, uint32_t,
+                                c_mma_elems,
+                                b_block_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_b)),
+                                a_mma_elems
+                                        / (sizeof(uint32_t) / sizeof(dtype_a))>(
+                                dst_sub_blk, b_sub_blk.xetla_format<uint32_t>(),
+                                a_sub_blk.xetla_format<uint32_t>());
+                    }
+                }
+            }
+        }
+        if constexpr (num_block_k > 1) {
+            constexpr uint32_t last_uint16_idx
+                    = tile_elems * sizeof(dtype_dst) / sizeof(uint16_t) - 1;
+            xetla_wait(dst.reg.xetla_format<uint16_t>()[0]);
+        }
+    }
+};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/op_function.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/op_function.hpp
new file mode 100644
index 00000000000000..a3585e29bd329b
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/op_function.hpp
@@ -0,0 +1,657 @@
+/*******************************************************************************
+ * Copyright (c) 2022-2023 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/common.hpp"
+
+namespace gpu::xetla::subgroup {
+/// @brief Is the element wise data conversion, the src and dst tile should have the same layout.
+///
+/// @tparam T_dst Is the destination tile data type.
+/// @tparam T_src Is the source tile data type.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API
+        typename std::enable_if_t<(T_src::register_layout != reg_layout::linear)
+                && (T_dst::register_layout != reg_layout::linear)
+                && (is_same_elements<T_dst, T_src>::value)
+                && (!is_floating_to_integer<T_dst, T_src>::value)>
+        elemwise_cvt(T_dst &dst, T_src &src) {
+    constexpr uint32_t block_size_x = T_dst::block_size_x;
+    constexpr uint32_t tile_elems = T_dst::tile_elems;
+    using dtype_src = typename T_src::dtype;
+    using dtype_dst = typename T_dst::dtype;
+    if constexpr (std::is_same<dtype_src, dtype_dst>::value) {
+        dst.reg = xetla_cvt<dtype_dst, dtype_src>(src.reg);
+    } else {
+#pragma unroll
+        for (int i = 0; i < tile_elems; i += block_size_x) {
+            dst.reg.xetla_select<block_size_x, 1>(i)
+                    = xetla_cvt<dtype_dst, dtype_src, block_size_x>(
+                            src.reg.xetla_select<block_size_x, 1>(i));
+        }
+    }
+}
+
+/// @brief Is the element wise data conversion from floating point to integral,
+/// the src and dst tile should have the same layout.
+/// @tparam T_dst Is the destination tile data type.
+/// @tparam T_src Is the source tile data type.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API
+        typename std::enable_if_t<(T_src::register_layout != reg_layout::linear)
+                && (T_dst::register_layout != reg_layout::linear)
+                && is_same_layout<T_dst, T_src>::value
+                && is_floating_to_integer<T_dst, T_src>::value>
+        elemwise_cvt(T_dst &dst, T_src &src) {
+    constexpr uint32_t block_size_x = T_dst::block_size_x;
+    constexpr uint32_t tile_elems = T_dst::tile_elems;
+    using dtype_src = typename T_src::dtype;
+    using dtype_dst = typename T_dst::dtype;
+
+    xetla_vector<dtype_src, tile_elems> rnde_reg;
+    //rnde
+#pragma unroll
+    for (int i = 0; i < tile_elems; i += block_size_x) {
+        rnde_reg.xetla_select<block_size_x, 1>(i)
+                = xetla_rnde<dtype_src, block_size_x>(
+                        src.reg.xetla_select<block_size_x, 1>(i));
+    }
+    //sat
+#pragma unroll
+    for (int i = 0; i < tile_elems; i += block_size_x) {
+        dst.reg.xetla_select<block_size_x, 1>(i)
+                = xetla_sat<dtype_dst, dtype_src, block_size_x>(
+                        rnde_reg.xetla_select<block_size_x, 1>(i));
+    }
+}
+
+/// @brief element wise data conversion with scaling, the src and dst tile should have the same layout.
+/// @tparam T_dst is the destination tile data type.
+/// @tparam T_src is the source tile data type.
+/// @param dst is the reference of the destination tile object.
+/// @param src is the reference of the destination tile object.
+/// @param scale is the scaling value to be applied before the assignment.
+/// @return no return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API
+        typename std::enable_if_t<(T_src::register_layout != reg_layout::linear)
+                && (T_dst::register_layout != reg_layout::linear)
+                && is_same_layout<T_dst, T_src>::value>
+        elemwise_cvt(T_dst &dst, T_src &src, float scale) {
+    dst.reg = xetla_cvt<typename T_dst::dtype, typename T_src::dtype>(
+            src.reg, scale);
+}
+
+/// @brief Converts tiled layout to vnni_tiled layout format.
+///
+/// @tparam T Is the tile data type.
+/// @param mat_Acc Is the reference of the tile object.
+/// @return No return, update the data in-place.
+template <typename T>
+__XETLA_API
+        typename std::enable_if_t<T::register_layout == reg_layout::vnni_tiled>
+        vnni_convert(T &mat_Acc) {
+    constexpr uint32_t tile_size_y = T::tile_size_y;
+    constexpr uint32_t tile_size_x = T::tile_size_x;
+    constexpr uint32_t tile_elems = tile_size_y * tile_size_x;
+    constexpr uint32_t block_size_y = T::block_size_y;
+    constexpr uint32_t block_size_x = T::block_size_x;
+    constexpr uint32_t block_elems = block_size_y * block_size_x;
+    constexpr int32_t num_block_x = tile_size_x / block_size_x;
+    using dtype = typename T::dtype;
+    constexpr int32_t vnni_stride = sizeof(uint32_t) / sizeof(dtype);
+    constexpr int32_t move_cols = block_size_x * vnni_stride;
+    constexpr int32_t move_rows = block_size_y / vnni_stride;
+    xetla_vector<dtype, tile_elems> rdst;
+    static_assert(block_size_y % vnni_stride == 0, "vnni alignement check");
+    if constexpr (tile_size_x == 1) { return; }
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg = (mat_Acc.reg)
+                               .xetla_select<block_elems, 1>(
+                                       (i * num_block_x + j) * block_elems);
+            auto reg_2d = reg.xetla_format<native_type_t<dtype>, block_size_y,
+                    block_size_x>();
+            auto reg_dst = rdst.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            auto reg_dst_2d = reg_dst.xetla_format<native_type_t<dtype>,
+                    move_rows, move_cols>();
+#pragma unroll
+            for (int vnni_i = 0; vnni_i < vnni_stride; vnni_i++) {
+                reg_dst_2d
+                        .xetla_select<move_rows, 1, block_size_x, vnni_stride>(
+                                0, vnni_i)
+                        = reg_2d.xetla_select<move_rows, vnni_stride,
+                                block_size_x, 1>(vnni_i, 0);
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr int i = tile_size_y / block_size_y;
+        constexpr uint32_t remain_elems_start = i * block_size_y * tile_size_x;
+        constexpr uint32_t remain_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t remain_block_elems = remain_size_y * block_size_x;
+        static_assert(
+                remain_size_y % vnni_stride == 0, "vnni alignement check");
+        constexpr int32_t remain_move_cols = block_size_x * vnni_stride;
+        constexpr int32_t remain_move_rows = remain_size_y / vnni_stride;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg = (mat_Acc.reg)
+                               .xetla_select<remain_block_elems, 1>(
+                                       remain_elems_start
+                                       + j * remain_block_elems);
+            auto reg_2d = reg.xetla_format<native_type_t<dtype>, remain_size_y,
+                    block_size_x>();
+            auto reg_dst = rdst.xetla_select<remain_block_elems, 1>(
+                    remain_elems_start + j * remain_block_elems);
+            auto reg_dst_2d = reg_dst.xetla_format<native_type_t<dtype>,
+                    remain_move_rows, remain_move_cols>();
+            for (int vnni_i = 0; vnni_i < vnni_stride; vnni_i++) {
+                reg_dst_2d.xetla_select<remain_move_rows, 1, block_size_x,
+                        vnni_stride>(0, vnni_i)
+                        = reg_2d.xetla_select<remain_move_rows, vnni_stride,
+                                block_size_x, 1>(vnni_i, 0);
+            }
+        }
+    }
+    mat_Acc.reg = rdst;
+}
+
+/// @brief Converts vnni_tiled layout format to tiled layout.
+///
+/// @tparam T Is the tile data type.
+/// @param mat_Acc Is the reference of the tile object.
+/// @return No return, update the data in-place.
+template <typename T>
+__XETLA_API typename std::enable_if_t<T::register_layout == reg_layout::tiled
+        || T::register_layout == reg_layout::vnni_tiled>
+vnni_reverse(T &mat_Acc) {
+    constexpr uint32_t tile_size_y = T::tile_size_y;
+    constexpr uint32_t tile_size_x = T::tile_size_x;
+    constexpr uint32_t tile_elems = tile_size_y * tile_size_x;
+    constexpr uint32_t block_size_y = T::block_size_y;
+    constexpr uint32_t block_size_x = T::block_size_x;
+    constexpr uint32_t block_elems = block_size_y * block_size_x;
+    constexpr int32_t num_block_x = tile_size_x / block_size_x;
+    using dtype = typename T::dtype;
+    constexpr int32_t vnni_stride = sizeof(uint32_t) / sizeof(dtype);
+    constexpr int32_t move_cols = block_size_x * vnni_stride;
+    constexpr int32_t move_rows = block_size_y / vnni_stride;
+    xetla_vector<dtype, tile_elems> rdst;
+    static_assert(block_size_y % vnni_stride == 0, "vnni alignement check");
+    if constexpr (tile_size_x == 1) { return; }
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg = (mat_Acc.reg)
+                               .xetla_select<block_elems, 1>(
+                                       (i * num_block_x + j) * block_elems);
+            auto reg_2d = reg.xetla_format<native_type_t<dtype>, move_rows,
+                    move_cols>();
+            auto reg_dst = rdst.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            auto reg_dst_2d = reg_dst.xetla_format<native_type_t<dtype>,
+                    block_size_y, block_size_x>();
+#pragma unroll
+            for (int vnni_i = 0; vnni_i < vnni_stride; vnni_i++) {
+                reg_dst_2d
+                        .xetla_select<move_rows, vnni_stride, block_size_x, 1>(
+                                vnni_i, 0)
+                        = reg_2d.xetla_select<move_rows, 1, block_size_x,
+                                vnni_stride>(0, vnni_i);
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr int i = tile_size_y / block_size_y;
+        constexpr uint32_t remain_elems_start = i * block_size_y * tile_size_x;
+        constexpr uint32_t remain_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t remain_block_elems = remain_size_y * block_size_x;
+        static_assert(
+                remain_size_y % vnni_stride == 0, "vnni alignement check");
+        constexpr int32_t remain_move_cols = block_size_x * vnni_stride;
+        constexpr int32_t remain_move_rows = remain_size_y / vnni_stride;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg = (mat_Acc.reg)
+                               .xetla_select<remain_block_elems, 1>(
+                                       remain_elems_start
+                                       + j * remain_block_elems);
+            auto reg_2d = reg.xetla_format<native_type_t<dtype>,
+                    remain_move_rows, remain_move_cols>();
+            auto reg_dst = rdst.xetla_select<remain_block_elems, 1>(
+                    remain_elems_start + j * remain_block_elems);
+            auto reg_dst_2d = reg_dst.xetla_format<native_type_t<dtype>,
+                    remain_size_y, block_size_x>();
+            for (int vnni_i = 0; vnni_i < vnni_stride; vnni_i++) {
+                reg_dst_2d.xetla_select<remain_move_rows, vnni_stride,
+                        block_size_x, 1>(vnni_i, 0)
+                        = reg_2d.xetla_select<remain_move_rows, 1, block_size_x,
+                                vnni_stride>(0, vnni_i);
+            }
+        }
+    }
+    mat_Acc.reg = rdst;
+}
+
+/// @brief Converts vnni_tiled layout format to transpose_tiled layout.
+///
+/// @tparam T Is the tile data type.
+/// @param mat_Acc Is the reference of the tile object.
+/// @return No return, update the data in-place.
+template <typename T>
+__XETLA_API typename std::enable_if_t<T::register_layout
+        == reg_layout::transpose_tiled>
+vnni_reverse(T &mat_Acc) {
+    constexpr uint32_t tile_size_y = T::tile_size_y;
+    constexpr uint32_t tile_size_x = T::tile_size_x;
+    constexpr uint32_t tile_elems = tile_size_y * tile_size_x;
+    constexpr uint32_t block_size_y = T::block_size_y;
+    constexpr uint32_t block_size_x = T::block_size_x;
+    constexpr uint32_t block_elems = block_size_y * block_size_x;
+    constexpr int32_t num_block_x = tile_size_x / block_size_x;
+    using dtype = typename T::dtype;
+    constexpr int32_t vnni_stride = sizeof(uint32_t) / sizeof(dtype);
+    constexpr int32_t move_cols = block_size_y * vnni_stride;
+    constexpr int32_t move_rows = block_size_x / vnni_stride;
+    xetla_vector<dtype, tile_elems> rdst;
+    static_assert(block_size_x % vnni_stride == 0, "vnni alignement check");
+    if constexpr (tile_size_y == 1) { return; }
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg = (mat_Acc.reg)
+                               .xetla_select<block_elems, 1>(
+                                       (i * num_block_x + j) * block_elems);
+            auto reg_2d = reg.xetla_format<native_type_t<dtype>, move_rows,
+                    move_cols>();
+            auto reg_dst = rdst.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            //transpose
+            auto reg_dst_2d = reg_dst.xetla_format<native_type_t<dtype>,
+                    block_size_x, block_size_y>();
+            for (int vnni_i = 0; vnni_i < vnni_stride; vnni_i++) {
+                reg_dst_2d
+                        .xetla_select<move_rows, vnni_stride, block_size_y, 1>(
+                                vnni_i, 0)
+                        = reg_2d.xetla_select<move_rows, 1, block_size_y,
+                                vnni_stride>(0, vnni_i);
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr int i = tile_size_y / block_size_y;
+        constexpr uint32_t remain_elems_start = i * block_size_y * tile_size_x;
+        constexpr uint32_t remain_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t remain_block_elems = remain_size_y * block_size_x;
+        constexpr int32_t remain_move_cols = remain_size_y * vnni_stride;
+        constexpr int32_t remain_move_rows = block_size_x / vnni_stride;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg = (mat_Acc.reg)
+                               .xetla_select<remain_block_elems, 1>(
+                                       remain_elems_start
+                                       + j * remain_block_elems);
+            auto reg_2d = reg.xetla_format<native_type_t<dtype>,
+                    remain_move_rows, remain_move_cols>();
+            auto reg_dst = rdst.xetla_select<remain_block_elems, 1>(
+                    remain_elems_start + j * remain_block_elems);
+            //transpose
+            auto reg_dst_2d = reg_dst.xetla_format<native_type_t<dtype>,
+                    block_size_x, remain_size_y>();
+
+            for (int vnni_i = 0; vnni_i < vnni_stride; vnni_i++) {
+                reg_dst_2d.xetla_select<remain_move_rows, vnni_stride,
+                        remain_size_y, 1>(vnni_i, 0)
+                        = reg_2d.xetla_select<remain_move_rows, 1,
+                                remain_size_y, vnni_stride>(0, vnni_i);
+            }
+        }
+    }
+    mat_Acc.reg = rdst;
+}
+
+/// @brief Changes vnni layout.
+///
+/// @tparam T_dst Is the destination tile data type.
+/// @tparam T_src Is the source tile data type.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API typename std::enable_if_t<is_same_layout<T_dst, T_src>::value>
+vnni_transform(T_dst &dst, T_src &src) {
+    constexpr uint32_t tile_size_y = T_dst::tile_size_y;
+    constexpr uint32_t tile_size_x = T_dst::tile_size_x;
+    constexpr uint32_t tile_elems = tile_size_y * tile_size_x;
+    constexpr uint32_t block_size_y = T_dst::block_size_y;
+    constexpr uint32_t block_size_x = T_dst::block_size_x;
+    constexpr uint32_t block_elems = block_size_y * block_size_x;
+    constexpr int32_t num_block_x = tile_size_x / block_size_x;
+    using dtype_dst = typename T_dst::dtype;
+    using dtype_src = typename T_src::dtype;
+    constexpr uint32_t vnni_row_src = sizeof(uint32_t) / sizeof(dtype_src);
+    constexpr uint32_t vnni_row_dst = sizeof(uint32_t) / sizeof(dtype_dst);
+    constexpr int32_t vnni_row
+            = vnni_row_src > vnni_row_dst ? vnni_row_src : vnni_row_dst;
+    static_assert(block_size_y % vnni_row == 0);
+    static_assert(tile_size_y % vnni_row == 0);
+    constexpr int32_t move_elems = vnni_row * block_size_x;
+    xetla_vector<dtype_dst, tile_elems> reg_src
+            = xetla_cvt<dtype_dst, dtype_src, tile_elems>(src.reg);
+    if constexpr (sizeof(dtype_src) == sizeof(dtype_dst)) {
+        dst.reg = reg_src;
+        return;
+    }
+    xetla_vector<dtype_dst, tile_elems> reg_dst;
+    constexpr uint32_t scale_factor
+            = detail::gcd<vnni_row_src, vnni_row_dst>::value;
+    using move_dtype = get_uint_type_t<sizeof(dtype_dst) * scale_factor>;
+    constexpr uint32_t select_stride = vnni_row / scale_factor;
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg_src_blk = reg_src.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            auto reg_dst_blk = reg_dst.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            for (int row_i = 0; row_i < block_size_y; row_i += vnni_row) {
+                auto reg_src_move
+                        = reg_src_blk
+                                  .xetla_select<move_elems, 1>(
+                                          row_i * block_size_x)
+                                  .xetla_format<native_type_t<move_dtype>>();
+                auto reg_dst_move
+                        = reg_dst_blk
+                                  .xetla_select<move_elems, 1>(
+                                          row_i * block_size_x)
+                                  .xetla_format<native_type_t<move_dtype>>();
+#pragma unroll
+                for (int move_i = 0; move_i < select_stride; move_i++) {
+                    if constexpr (sizeof(dtype_dst) > sizeof(dtype_src)) {
+                        reg_dst_move.xetla_select<block_size_x, 1>(
+                                move_i * block_size_x)
+                                = reg_src_move.xetla_select<block_size_x,
+                                        select_stride>(move_i);
+                    } else {
+                        reg_dst_move.xetla_select<block_size_x, select_stride>(
+                                move_i)
+                                = reg_src_move.xetla_select<block_size_x, 1>(
+                                        move_i * block_size_x);
+                    }
+                }
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr int i = tile_size_y / block_size_y;
+        constexpr uint32_t remain_elems_start = i * block_size_y * tile_size_x;
+        constexpr uint32_t remain_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t remain_block_elems = remain_size_y * block_size_x;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg_src_blk = reg_src.xetla_select<remain_block_elems, 1>(
+                    remain_elems_start + j * remain_block_elems);
+            auto reg_dst_blk = reg_dst.xetla_select<remain_block_elems, 1>(
+                    remain_elems_start + j * remain_block_elems);
+            // for mma, here we can guarantee that the remaining is a multiple of
+            // vnni_row
+            for (int row_i = 0; row_i < remain_size_y; row_i += vnni_row) {
+                auto reg_src_move
+                        = reg_src_blk
+                                  .xetla_select<move_elems, 1>(
+                                          row_i * block_size_x)
+                                  .xetla_format<native_type_t<move_dtype>>();
+                auto reg_dst_move
+                        = reg_dst_blk
+                                  .xetla_select<move_elems, 1>(
+                                          row_i * block_size_x)
+                                  .xetla_format<native_type_t<move_dtype>>();
+#pragma unroll
+                for (int move_i = 0; move_i < select_stride; move_i++) {
+                    if constexpr (sizeof(dtype_dst) > sizeof(dtype_src)) {
+                        reg_dst_move.xetla_select<block_size_x, 1>(
+                                move_i * block_size_x)
+                                = reg_src_move.xetla_select<block_size_x,
+                                        select_stride>(move_i);
+                    } else {
+                        reg_dst_move.xetla_select<block_size_x, select_stride>(
+                                move_i)
+                                = reg_src_move.xetla_select<block_size_x, 1>(
+                                        move_i * block_size_x);
+                    }
+                }
+            }
+        }
+    }
+    dst.reg = reg_dst;
+}
+
+/// @brief Broadcasts 1d src tile to the entire 2d tile, as well as do the data conversion.
+///
+/// @tparam T_dst Is the destination tile data type.
+/// @tparam T_src Is the source tile data type, interpreted as 1D data.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API
+        typename std::enable_if_t<(T_dst::register_layout == reg_layout::tiled)
+                && (T_src::register_layout == reg_layout::tiled)
+                && (T_src::tile_size_x == T_dst::tile_size_x)
+                && (T_src::tile_size_y == 1)>
+        row_broadcast(T_dst &dst, T_src &src) {
+    static constexpr uint32_t dst_tile_size_y = T_dst::tile_size_y;
+    static constexpr uint32_t dst_tile_size_x = T_dst::tile_size_x;
+    static constexpr uint32_t dst_tile_elems = T_dst::tile_elems;
+    static constexpr uint32_t dst_block_size_y = T_dst::block_size_y;
+    static constexpr uint32_t dst_block_size_x = T_dst::block_size_x;
+    static constexpr uint32_t dst_block_elems = T_dst::block_elems;
+    static constexpr int32_t dst_num_block_y = T_dst::num_block_y;
+    static constexpr int32_t dst_num_block_x = T_dst::num_block_x;
+    using dst_dtype = typename T_dst::dtype;
+    using src_dtype = typename T_src::dtype;
+
+#pragma unroll
+    for (int i = 0; i < dst_tile_size_y / dst_block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < dst_num_block_x; j++) {
+            auto dst_reg
+                    = (dst.reg)
+                              .xetla_select<dst_block_elems, 1>(
+                                      (i * dst_num_block_x + j)
+                                      * dst_block_elems)
+                              .xetla_format<native_type_t<dst_dtype>,
+                                      dst_block_size_y, dst_block_size_x>();
+#pragma unroll
+            for (int row_i = 0; row_i < dst_block_size_y; row_i++) {
+                auto src_reg = src.reg.xetla_select<dst_block_size_x, 1>(
+                        j * dst_block_size_x);
+                dst_reg.row(row_i)
+                        = xetla_cvt<dst_dtype, src_dtype, dst_block_size_x>(
+                                src_reg);
+            }
+        }
+    }
+
+    // process the tail
+    if constexpr ((dst_tile_size_y % dst_block_size_y) != 0) {
+        constexpr uint32_t tail_start_y
+                = dst_tile_size_y / dst_block_size_y * dst_block_size_y;
+        constexpr int32_t dst_tail_size_y = dst_tile_size_y % dst_block_size_y;
+        constexpr int32_t dst_tail_block_elems
+                = dst_tail_size_y * dst_block_size_x;
+#pragma unroll
+        for (int j = 0; j < dst_num_block_x; j++) {
+            auto dst_reg = (dst.reg)
+                                   .xetla_select<dst_tail_block_elems, 1>(
+                                           tail_start_y * dst_tile_size_x
+                                           + j * dst_tail_block_elems)
+                                   .xetla_format<native_type_t<dst_dtype>,
+                                           dst_tail_size_y, dst_block_size_x>();
+#pragma unroll
+            for (int row_i = 0; row_i < dst_tail_size_y; row_i++) {
+                auto src_reg = src.reg.xetla_select<dst_block_size_x, 1>(
+                        j * dst_block_size_x);
+                dst_reg.row(row_i)
+                        = xetla_cvt<dst_dtype, src_dtype, dst_block_size_x>(
+                                src_reg);
+            }
+        }
+    }
+}
+
+/// @brief convert 2d tile in a tiled register layout to a 2d tile in a linear register layout
+///
+/// @tparam T_dst Is the destination tile data type.
+/// @tparam T_src Is the source tile data type.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API typename std::enable_if_t<(T_dst::register_layout
+                                              == reg_layout::linear)
+        && (T_src::register_layout == reg_layout::tiled)
+        && (T_src::tile_size_x == T_dst::tile_size_x)
+        && (T_src::tile_size_y == T_dst::tile_size_y)
+        && (T_dst::tile_size_x == T_dst::block_size_x)
+        && (T_dst::tile_size_y == T_dst::block_size_y)
+        && (std::is_same<typename T_dst::dtype, typename T_src::dtype>::value)>
+layout_convert(T_dst &dst, T_src &src) {
+    using tile_desc = typename T_src::tile_desc;
+    using dtype = typename T_dst::dtype;
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+    static constexpr uint32_t num_block_y = tile_desc::num_block_y;
+    static constexpr uint32_t block_elems = tile_desc::block_elems;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+
+    auto dst_reg = dst.reg.xetla_format<native_type_t<dtype>, tile_size_y,
+            tile_size_x>();
+#pragma unroll
+    for (int i = 0; i < num_block_y; ++i) {
+        uint32_t offset_y = i * block_size_y;
+#pragma unroll
+        for (int j = 0; j < num_block_x; ++j) {
+            uint32_t offset_x = j * block_size_x;
+            auto src_reg = src.reg.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            dst_reg.xetla_select<block_size_y, 1, block_size_x, 1>(
+                    offset_y, offset_x)
+                    = src_reg;
+        }
+    }
+    // process the tail
+    if constexpr (tile_desc::remained_size_y > 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_size_x;
+        constexpr uint32_t remained_block_elems
+                = remained_size_y * block_size_x;
+#pragma unroll
+        for (int j = 0; j < num_block_x; ++j) {
+            uint32_t offset_x = j * block_size_x;
+            auto src_reg = src.reg.xetla_select<remained_block_elems, 1>(
+                    processed_elems + j * remained_block_elems);
+            dst_reg.xetla_select<remained_size_y, 1, block_size_x, 1>(
+                    offset_y, offset_x)
+                    = src_reg;
+        }
+    }
+}
+
+/// @brief convert 2d tile in a linear register layout to a 2d tile in a tiled register layout
+///
+/// @tparam T_dst Is the destination tile data type.
+/// @tparam T_src Is the source tile data type.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+template <typename T_dst, typename T_src>
+__XETLA_API typename std::enable_if_t<(T_dst::register_layout
+                                              == reg_layout::tiled)
+        && (T_src::register_layout == reg_layout::linear)
+        && (T_dst::tile_size_x == T_src::tile_size_x)
+        && (T_dst::tile_size_y == T_src::tile_size_y)
+        && (T_src::tile_size_x == T_src::block_size_x)
+        && (T_src::tile_size_y == T_src::block_size_y)
+        && (std::is_same<typename T_dst::dtype, typename T_src::dtype>::value)>
+layout_convert(T_dst &dst, T_src &src) {
+    using tile_desc = typename T_dst::tile_desc;
+    using dtype = typename T_dst::dtype;
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+    static constexpr uint32_t num_block_y = tile_desc::num_block_y;
+    static constexpr uint32_t block_elems = tile_desc::block_elems;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+
+    auto src_reg = src.reg.xetla_format<native_type_t<dtype>, tile_size_y,
+            tile_size_x>();
+#pragma unroll
+    for (int i = 0; i < num_block_y; ++i) {
+        uint32_t offset_y = i * block_size_y;
+#pragma unroll
+        for (int j = 0; j < num_block_x; ++j) {
+            uint32_t offset_x = j * block_size_x;
+            auto dst_reg = dst.reg.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            dst_reg = src_reg.xetla_select<block_size_y, 1, block_size_x, 1>(
+                    offset_y, offset_x);
+        }
+    }
+    // process the tail
+    if constexpr (tile_desc::remained_size_y > 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_size_x;
+        constexpr uint32_t remained_block_elems
+                = remained_size_y * block_size_x;
+#pragma unroll
+        for (int j = 0; j < num_block_x; ++j) {
+            uint32_t offset_x = j * block_size_x;
+            auto dst_reg = dst.reg.xetla_select<remained_block_elems, 1>(
+                    processed_elems + j * remained_block_elems);
+            dst_reg = src_reg.xetla_select<remained_size_y, 1, block_size_x, 1>(
+                    offset_y, offset_x);
+        }
+    }
+}
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/payload_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/payload_xe.hpp
new file mode 100644
index 00000000000000..c718962a8fd232
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/payload_xe.hpp
@@ -0,0 +1,1615 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/impl/op_function.hpp"
+
+namespace gpu::xetla::subgroup {
+
+/// @brief Is to describe the global memory surface for block-2d load/store
+/// for each block in one tile, a payload message is prepared here.
+/// in tile_load case, memory transpose, register transpose, memory transform
+/// and dword transpose can be enable.
+/// While in tile store case, we only support row major store, no register
+/// operations can be applied.
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+template <typename dtype_, typename tile_desc_, mem_layout mem_layout_,
+        gpu_arch arch_tag_, uint32_t alignment_, uint32_t dim_>
+struct mem_payload_t<
+        mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_, dim_>,
+        tile_desc_, msg_type::block_2d, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using tile_desc = tile_desc_;
+    using mem_desc_t = mem_desc_t<dtype_, mem_layout_, mem_space::global,
+            alignment_, dim_>;
+    using dtype = dtype_;
+    static constexpr msg_type message_type = msg_type::block_2d;
+    static constexpr mem_space memory_space = mem_space::global;
+    static constexpr mem_layout memory_layout = mem_layout_;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+private:
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+    static constexpr uint32_t num_block_y = tile_desc::num_block_y;
+    static constexpr uint32_t num_block = tile_desc::num_block;
+    static constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+    using this_payload_t = mem_payload_t<mem_desc_t, tile_desc,
+            msg_type::block_2d, arch_tag>;
+
+public:
+    static constexpr bool mem_transpose
+            = memory_layout == mem_layout::col_major;
+
+    static constexpr reg_layout register_layout = tile_desc::register_layout;
+    static constexpr bool reg_transpose
+            = register_layout == reg_layout::transpose_tiled;
+    static constexpr bool trans = mem_transpose ^ reg_transpose;
+
+    static constexpr bool mem_transform = (sizeof(dtype) < 4) && !mem_transpose
+            && (register_layout == reg_layout::vnni_tiled
+                    || register_layout == reg_layout::vnni_tiled_col_major);
+    static constexpr bool mem_dword_transpose = (sizeof(dtype) < 4) && trans;
+
+    using mem_dtype = typename std::conditional<mem_dword_transpose, uint32_t,
+            dtype>::type;
+    static constexpr uint32_t scale_factor = sizeof(mem_dtype) / sizeof(dtype);
+
+    xetla_vector<uint32_t, 16 * num_block> payloads;
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->payloads = rhs.payloads;
+    }
+
+    inline mem_payload_t(mem_desc_t &mem_desc) {
+        xetla_tdescriptor base_tdesc = mem_desc.get_tdesc();
+        int32_t offset
+                = gpu::xetla::detail::xetla_get_tensor_offset_x(base_tdesc)
+                / int32_t(scale_factor);
+        gpu::xetla::detail::xetla_set_tensor_offset_x(
+                base_tdesc.xetla_format<uint32_t>(), offset);
+        prepare_tdesc(base_tdesc);
+    }
+
+    inline mem_payload_t(dtype *p, uint32_t surface_width,
+            uint32_t surface_height, uint32_t surface_pitch,
+            int32_t surface_offset_x = 0, int32_t surface_offset_y = 0) {
+        xetla_tdescriptor base_tdesc;
+        xetla_fill_tdesc(base_tdesc.xetla_format<uint32_t>(), p, surface_width,
+                surface_height, surface_pitch,
+                surface_offset_x / int32_t(scale_factor), surface_offset_y);
+        prepare_tdesc(base_tdesc);
+    }
+
+    __XETLA_API void init(mem_desc_t &mem_desc) {
+        xetla_tdescriptor base_tdesc = mem_desc.get_tdesc();
+        int32_t offset
+                = gpu::xetla::detail::xetla_get_tensor_offset_x(base_tdesc)
+                / int32_t(scale_factor);
+        gpu::xetla::detail::xetla_set_tensor_offset_x(
+                base_tdesc.xetla_format<uint32_t>(), offset);
+        prepare_tdesc(base_tdesc);
+    }
+
+    __XETLA_API void init(xetla_tdescriptor base_tdesc) {
+        int32_t offset
+                = gpu::xetla::detail::xetla_get_tensor_offset_x(base_tdesc)
+                / int32_t(scale_factor);
+        gpu::xetla::detail::xetla_set_tensor_offset_x(
+                base_tdesc.xetla_format<uint32_t>(), offset);
+        prepare_tdesc(base_tdesc);
+    }
+
+    __XETLA_API void init(dtype *p, uint32_t surface_width,
+            uint32_t surface_height, uint32_t surface_pitch,
+            int32_t surface_offset_x = 0, int32_t surface_offset_y = 0) {
+        xetla_tdescriptor base_tdesc;
+        xetla_fill_tdesc(base_tdesc.xetla_format<uint32_t>(), p, surface_width,
+                surface_height, surface_pitch,
+                surface_offset_x / int32_t(scale_factor), surface_offset_y);
+        prepare_tdesc(base_tdesc);
+    }
+
+    inline mem_payload_t() = default;
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // ~mem_payload_t(){}
+
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->payloads = rhs.payloads;
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+#pragma unroll
+            for (int i = 0; i < num_block; i++) {
+                xetla_update_tdesc_offsetx(
+                        payloads_2d.row(i), offset / int32_t(scale_factor));
+            }
+        } else {
+#pragma unroll
+            for (int i = 0; i < num_block; i++) {
+                xetla_update_tdesc_offsety(payloads_2d.row(i), offset);
+            }
+        }
+    }
+
+    __XETLA_API void update_tdesc_base_address(int offset) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_update_tdesc_base_address(payloads_2d.row(i), offset);
+        }
+    }
+
+    __XETLA_API void set_tdesc_width(uint32_t size) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_set_tdesc_width<dtype>(payloads_2d.row(i), size);
+        }
+    }
+
+    __XETLA_API void set_tdesc_pitch(uint32_t size) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_set_tdesc_pitch<dtype>(payloads_2d.row(i), size);
+        }
+    }
+
+    __XETLA_API void set_tdesc_height(uint32_t size) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_set_tdesc_height(payloads_2d.row(i), size);
+        }
+    }
+
+    __XETLA_API void update_tdesc_base_address_masked(
+            int offset, uint16_t mask = 1) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_update_tdesc_base_address(payloads_2d.row(i), offset);
+        }
+
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_tdesc_mask_op(payloads_2d.row(i), mask);
+        }
+    }
+    __XETLA_API void set_tdesc_base_address_masked(
+            uint64_t offset, uint16_t mask = 1) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            gpu::xetla::detail::xetla_set_tensor_base_address(
+                    payloads_2d.row(i), offset);
+        }
+
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            xetla_tdesc_mask_op(payloads_2d.row(i), mask);
+        }
+    }
+
+    __XETLA_API void set_tdesc_base_address(uint64_t addr) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+#pragma unroll
+        for (int i = 0; i < num_block; i++) {
+            gpu::xetla::detail::xetla_set_tensor_base_address(
+                    payloads_2d.row(i), addr);
+        }
+    }
+
+    __XETLA_API void set_offset(int32_t offset_x, int32_t offset_y) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+        constexpr uint32_t arr_len = 1;
+        int32_t base_offset_y = offset_y;
+#pragma unroll
+        for (int i = 0; i < num_block_y; i++) {
+            auto tdesc_row_2d = payloads_2d.xetla_select<num_block_x, 1, 16, 1>(
+                    i * num_block_x, 0);
+
+            int32_t base_offset_x = offset_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                // To mimic dw transpose for word/byte data type with transpose and pack
+                constexpr uint8_t block_width = mem_transpose
+                        ? (block_size_y / scale_factor)
+                        : (block_size_x / scale_factor);
+                constexpr uint8_t block_height
+                        = mem_transpose ? block_size_x : block_size_y;
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_width - 1) | ((block_height - 1) << 8)
+                        | ((arr_len - 1) << 16);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc_row_2d.row(j), block_widthx_widthy_arrlen);
+
+                int32_t offset_width = mem_transpose
+                        ? (base_offset_y / int32_t(scale_factor))
+                        : (base_offset_x / int32_t(scale_factor));
+                int32_t offset_height
+                        = mem_transpose ? base_offset_x : base_offset_y;
+
+                gpu::xetla::detail::xetla_set_tensor_offset_x(
+                        tdesc_row_2d.row(j), offset_width);
+                gpu::xetla::detail::xetla_set_tensor_offset_y(
+                        tdesc_row_2d.row(j), offset_height);
+
+                base_offset_x += block_size_x * arr_len;
+            }
+            base_offset_y += block_size_y;
+        }
+        // process the tail
+        if constexpr (remained_size_y > 0) {
+            auto tdesc_row_2d = payloads_2d.xetla_select<num_block_x, 1, 16, 1>(
+                    num_block_y * num_block_x, 0);
+            // this is exactly copy paste from above. so maybe worth createing some function
+            int32_t base_offset_x = offset_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                // To mimic dw transpose for word/byte data type with transpose and pack
+                constexpr uint8_t block_width = mem_transpose
+                        ? (block_size_y / scale_factor)
+                        : (block_size_x / scale_factor);
+                constexpr uint8_t block_height
+                        = mem_transpose ? block_size_x : block_size_y;
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_width - 1) | ((block_height - 1) << 8)
+                        | ((arr_len - 1) << 16);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc_row_2d.row(j), block_widthx_widthy_arrlen);
+
+                int32_t offset_width = mem_transpose
+                        ? (base_offset_y / int32_t(scale_factor))
+                        : (base_offset_x / int32_t(scale_factor));
+                int32_t offset_height
+                        = mem_transpose ? base_offset_x : base_offset_y;
+
+                gpu::xetla::detail::xetla_set_tensor_offset_x(
+                        tdesc_row_2d.row(j), offset_width);
+                gpu::xetla::detail::xetla_set_tensor_offset_y(
+                        tdesc_row_2d.row(j), offset_height);
+
+                base_offset_x += block_size_x;
+            }
+        }
+    }
+
+private:
+    __XETLA_API void prepare_tdesc(xetla_tdescriptor base_tdesc) {
+        auto payloads_2d = payloads.xetla_format<uint32_t, num_block, 16>();
+        uint32_t base_offset_y = 0;
+#pragma unroll
+        for (int i = 0; i < num_block_y; i++) {
+            auto tdesc_row_2d = payloads_2d.xetla_select<num_block_x, 1, 16, 1>(
+                    i * num_block_x, 0);
+            prepare_tile_desc_core<num_block_x, block_size_x, block_size_y, 1,
+                    mem_transpose>(tdesc_row_2d, base_tdesc, base_offset_y);
+            base_offset_y += block_size_y;
+        }
+        // process the tail
+        if constexpr (remained_size_y > 0) {
+            auto tdesc_row_2d = payloads_2d.xetla_select<num_block_x, 1, 16, 1>(
+                    num_block_y * num_block_x, 0);
+            prepare_tile_desc_core<num_block_x, block_size_x, remained_size_y,
+                    1, mem_transpose>(tdesc_row_2d, base_tdesc, base_offset_y);
+        }
+    }
+
+    template <uint32_t num_tdesc, uint32_t size_x, uint32_t size_y,
+            uint8_t arr_len, bool trans>
+    __XETLA_API static void prepare_tile_desc_core(
+            xetla_matrix_ref<uint32_t, num_tdesc, 16> __REF__ payloads_row_2d,
+            xetla_tdescriptor base_tdesc, uint32_t base_offset_y) {
+        uint32_t base_offset_x = 0;
+#pragma unroll
+        for (int j = 0; j < num_tdesc; j++) {
+            payloads_row_2d.row(j) = base_tdesc;
+            // To mimic dw transpose for word/byte data type with transpose and pack
+            constexpr uint8_t block_width
+                    = trans ? (size_y / scale_factor) : (size_x / scale_factor);
+            constexpr uint8_t block_height = trans ? size_x : size_y;
+            constexpr uint32_t block_widthx_widthy_arrlen = (block_width - 1)
+                    | ((block_height - 1) << 8) | ((arr_len - 1) << 16);
+            gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                    payloads_row_2d.row(j), block_widthx_widthy_arrlen);
+
+            // To mimic dw transpose for word/byte data type with transpose and pack
+            uint32_t offset_width = trans
+                    ? (base_offset_y / int32_t(scale_factor))
+                    : (base_offset_x / int32_t(scale_factor));
+            uint32_t offset_height = trans ? base_offset_x : base_offset_y;
+
+            xetla_update_tdesc_offsetx(payloads_row_2d.row(j), offset_width);
+            xetla_update_tdesc_offsety(payloads_row_2d.row(j), offset_height);
+            base_offset_x += size_x * arr_len;
+        }
+    }
+};
+
+/// @brief Is to describe the global memory surface for block-1d load/store
+/// For a block-1d payload message we need to set the base address and
+/// offset of surface.
+/// memory transpose and register operations can not be applied here.
+/// 2d and 1d surface both can be accepted here
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+template <typename dtype_, typename tile_desc_, gpu_arch arch_tag_,
+        uint32_t alignment_>
+struct mem_payload_t<mem_desc_t<dtype_, mem_layout::row_major,
+                             mem_space::global, alignment_>,
+        tile_desc_, msg_type::block_1d, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using mem_desc_t = mem_desc_t<dtype_, mem_layout::row_major,
+            mem_space::global, alignment_>;
+    using dtype = dtype_;
+    using tile_desc = tile_desc_;
+    static constexpr mem_space memory_space = mem_space::global;
+    static constexpr mem_layout memory_layout = mem_layout::row_major;
+    static constexpr msg_type message_type = msg_type::block_1d;
+    static constexpr uint32_t alignment_in_bytes
+            = mem_desc_t::alignment_in_bytes;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    static_assert((alignment_in_bytes % sizeof(uint32_t)) == 0,
+            "alignment should at least DW aligned");
+
+private:
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static_assert(tile_size_y == 1,
+            "For tile_size_y > 1 case, please use 2d block message! ");
+    using this_payload_t = mem_payload_t<mem_desc_t, tile_desc,
+            msg_type::block_1d, arch_tag>;
+
+public:
+    static constexpr uint32_t bytes_per_row = tile_size_x * sizeof(dtype);
+    using mem_dtype = typename std::conditional<
+            (bytes_per_row % sizeof(uint64_t) == 0)
+                    && (alignment_in_bytes % sizeof(uint64_t) == 0),
+            uint64_t,
+            typename std::conditional<(bytes_per_row % sizeof(uint32_t) == 0),
+                    uint32_t, dtype>::type>::type;
+    static constexpr uint32_t scale_factor = sizeof(mem_dtype) / sizeof(dtype);
+
+    uint64_t base_offset;
+    mem_dtype *base_ptr;
+    uint32_t pitch_in_bytes;
+
+    inline mem_payload_t(mem_desc_t &mem_tdesc) {
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        uint32_t offset_x = mem_tdesc.coord.x;
+        uint32_t offset_y = mem_tdesc.coord.y;
+        base_offset = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)mem_tdesc.base.base;
+    }
+
+    inline mem_payload_t(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        base_offset = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)p;
+    }
+
+    __XETLA_API void init(mem_desc_t &mem_tdesc) {
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        uint32_t offset_x = mem_tdesc.coord.x;
+        uint32_t offset_y = mem_tdesc.coord.y;
+        base_offset = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)mem_tdesc.base.base;
+    }
+
+    __XETLA_API void init(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        base_offset = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)p;
+    }
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->base_offset = rhs.base_offset;
+        this->base_ptr = rhs.base_ptr;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+    }
+
+    inline mem_payload_t() = default;
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->base_offset = rhs.base_offset;
+        this->base_ptr = rhs.base_ptr;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            base_offset += int64_t(offset) * sizeof(dtype);
+        } else {
+            base_offset += int64_t(offset) * pitch_in_bytes;
+        }
+    }
+};
+
+/// @brief Is to describe the global memory surface for atomic store
+/// For atomic store, we need to prepare necessary information for
+/// each simd channel.
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+template <typename dtype_, typename tile_desc_, mem_layout mem_layout_,
+        gpu_arch arch_tag_, uint32_t alignment_, uint32_t dim_>
+struct mem_payload_t<
+        mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_, dim_>,
+        tile_desc_, msg_type::atomic_add, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using mem_desc_t = mem_desc_t<dtype_, mem_layout_, mem_space::global,
+            alignment_, dim_>;
+
+    using dtype = dtype_;
+    using tile_desc = tile_desc_;
+    static constexpr mem_space memory_space = mem_space::global;
+    static constexpr mem_layout memory_layout = mem_layout_;
+    static constexpr msg_type message_type = msg_type::atomic_add;
+    static constexpr uint32_t alignment_in_bytes
+            = mem_desc_t::alignment_in_bytes;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+    static_assert(
+            sizeof(dtype) >= 2, "for atomic add, we only support W, DW or QW");
+
+private:
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    using this_payload_t = mem_payload_t<mem_desc_t, tile_desc,
+            msg_type::atomic_add, arch_tag>;
+
+public:
+    static constexpr uint32_t tile_bytes
+            = tile_size_x * tile_size_y * sizeof(dtype);
+    static constexpr uint32_t block_bytes
+            = block_size_x * block_size_y * sizeof(dtype);
+
+    // for pvc, we can use simd16 or simd32
+    static constexpr uint32_t min_store_bytes = 16 * sizeof(dtype);
+    static constexpr uint32_t max_store_bytes = 32 * sizeof(dtype);
+    static constexpr uint32_t num_channel
+            = ((tile_bytes % max_store_bytes) == 0
+                      && (block_bytes % max_store_bytes) == 0)
+            ? 32
+            : 16;
+
+    static constexpr uint32_t num_channel_x = block_size_x;
+    static constexpr uint32_t num_channel_y = num_channel / num_channel_x;
+    static constexpr uint32_t store_elems = num_channel_y * block_size_x;
+
+    //may need to set it to be configurable later
+    using Toffset = uint32_t;
+
+    xetla_vector<Toffset, num_channel> channel_offset;
+    xetla_vector<uint32_t, num_channel> step_x;
+    xetla_vector<uint32_t, num_channel> step_y;
+    uint32_t pitch_in_bytes;
+    uint32_t width_in_elems;
+    uint32_t height_in_elems;
+    uint32_t base_x;
+    uint32_t base_y;
+    uint64_t base_pointer;
+
+    inline mem_payload_t(mem_desc_t &mem_tdesc) {
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        base_x = mem_tdesc.coord.x;
+        base_y = mem_tdesc.coord.y;
+        width_in_elems = mem_tdesc.shape.x;
+        height_in_elems = mem_tdesc.shape.y;
+        base_pointer = (uint64_t)mem_tdesc.base.base;
+        base_pointer += base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = step_x * sizeof(dtype) + step_y * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        base_x = surface_offset_x;
+        base_y = surface_offset_y;
+        width_in_elems = surface_width;
+        height_in_elems = surface_height;
+        base_pointer = (uint64_t)p;
+        base_pointer += base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = step_x * sizeof(dtype) + step_y * pitch_in_bytes;
+    }
+
+    __XETLA_API void init(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        base_x = surface_offset_x;
+        base_y = surface_offset_y;
+        width_in_elems = surface_width;
+        height_in_elems = surface_height;
+        base_pointer = (uint64_t)p;
+        base_pointer += base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = step_x * sizeof(dtype) + step_y * pitch_in_bytes;
+    }
+
+    __XETLA_API void init(mem_desc_t &mem_tdesc) {
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        base_x = mem_tdesc.coord.x;
+        base_y = mem_tdesc.coord.y;
+        width_in_elems = mem_tdesc.shape.x;
+        height_in_elems = mem_tdesc.shape.y;
+        base_pointer = (uint64_t)mem_tdesc.base.base;
+        base_pointer += base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = step_x * sizeof(dtype) + step_y * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->width_in_elems = rhs.width_in_elems;
+        this->height_in_elems = rhs.height_in_elems;
+        this->base_x = rhs.base_x;
+        this->base_y = rhs.base_y;
+        this->base_pointer = rhs.base_pointer;
+        this->channel_offset = rhs.channel_offset;
+        this->step_x = rhs.step_x;
+        this->step_y = rhs.step_y;
+    }
+
+    inline mem_payload_t() = default;
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->width_in_elems = rhs.width_in_elems;
+        this->height_in_elems = rhs.height_in_elems;
+        this->base_x = rhs.base_x;
+        this->base_y = rhs.base_y;
+        this->base_pointer = rhs.base_pointer;
+        this->channel_offset = rhs.channel_offset;
+        this->step_x = rhs.step_x;
+        this->step_y = rhs.step_y;
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            base_pointer += int64_t(offset) * sizeof(dtype);
+            base_x += offset;
+        } else {
+            base_pointer += int64_t(offset) * pitch_in_bytes;
+            base_y += offset;
+        }
+    }
+
+    __XETLA_API void set_tdesc_base_address_masked(
+            uint64_t offset, uint16_t mask = 1) {
+        base_pointer = offset;
+        base_pointer += base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        base_x += width_in_elems & (uint32_t)(mask - 1);
+    }
+};
+
+/// @brief Is to describe the shared local memory surface for block-1d load/store
+/// 1. data located in shared local memory 2. tile will be loaded / stored in 1d mode.
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+template <typename dtype_, typename tile_desc_, gpu_arch arch_tag_,
+        uint32_t alignment_>
+struct mem_payload_t<
+        mem_desc_t<dtype_, mem_layout::row_major, mem_space::local, alignment_>,
+        tile_desc_, msg_type::block_1d, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using mem_desc_t = mem_desc_t<dtype_, mem_layout::row_major,
+            mem_space::local, alignment_>;
+    using dtype = dtype_;
+    using tile_desc = tile_desc_;
+    static constexpr mem_space memory_space = mem_space::local;
+    static constexpr mem_layout memory_layout = mem_layout::row_major;
+    static constexpr msg_type message_type = msg_type::block_1d;
+    static constexpr uint32_t alignment_in_bytes
+            = mem_desc_t::alignment_in_bytes;
+    static_assert((alignment_in_bytes % sizeof(uint32_t)) == 0,
+            "alignment should at least DW aligned");
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+private:
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    using this_payload_t = mem_payload_t<mem_desc_t, tile_desc,
+            msg_type::block_1d, arch_tag>;
+
+public:
+    static constexpr uint32_t tile_bytes
+            = tile_size_x * tile_size_y * sizeof(dtype);
+    static constexpr uint32_t block_bytes
+            = block_size_x * block_size_y * sizeof(dtype);
+    static constexpr uint32_t bytes_per_row = block_size_x * sizeof(dtype);
+    using mem_dtype = typename std::conditional<
+            (bytes_per_row % sizeof(uint64_t) == 0)
+                    && (alignment_in_bytes % sizeof(uint64_t) == 0),
+            uint64_t,
+            typename std::conditional<(bytes_per_row % sizeof(uint32_t) == 0),
+                    uint32_t, dtype>::type>::type;
+    static constexpr uint32_t scale_factor = sizeof(mem_dtype) / sizeof(dtype);
+
+    uint32_t base_address;
+    uint32_t address;
+    uint32_t pitch_in_bytes;
+
+    __XETLA_API void init(mem_desc_t &mem_tdesc) {
+        base_address = mem_tdesc.base.base;
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        uint32_t offset_x = mem_tdesc.coord.x;
+        uint32_t offset_y = mem_tdesc.coord.y;
+        address = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+    }
+
+    __XETLA_API void init(uint32_t base, uint32_t surface_width,
+            uint32_t surface_height, uint32_t surface_pitch,
+            int32_t surface_offset_x, int32_t surface_offset_y) {
+        base_address = base;
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        address = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+    }
+
+    inline mem_payload_t(mem_desc_t &mem_tdesc) { init(mem_tdesc); }
+    inline mem_payload_t(uint32_t base, uint32_t surface_width,
+            uint32_t surface_height, uint32_t surface_pitch,
+            int32_t surface_offset_x, int32_t surface_offset_y) {
+        init(base, surface_width, surface_height, surface_pitch,
+                surface_offset_x, surface_offset_y);
+    }
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->base_address = rhs.base_address;
+        this->address = rhs.address;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+    }
+
+    inline mem_payload_t() = default;
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->base_address = rhs.base_address;
+        this->address = rhs.address;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int32_t offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            address += offset * sizeof(dtype);
+        } else {
+            address += offset * pitch_in_bytes;
+        }
+    }
+
+    __XETLA_API void set_base_address(uint32_t base) {
+        this->base_address = base;
+    }
+};
+
+/// @brief Is to describe the global memory surface for unaligned-2d load/store
+/// for each block in one tile, a payload message is prepared here.
+/// in tile_load case, memory transpose, register transpose, memory transform
+/// and dword transpose can be enable.
+/// While in tile store case, we only support row major store, no register
+/// operations can be applied.
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+template <typename dtype_, typename tile_desc_, mem_layout mem_layout_,
+        uint32_t alignment_, gpu_arch arch_tag_>
+struct mem_payload_t<
+        mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_>,
+        tile_desc_, msg_type::unaligned_2d, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using dtype = dtype_;
+    using mem_desc_t
+            = mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_>;
+    using tile_desc = tile_desc_;
+    static constexpr mem_space memory_space = mem_space::global;
+    static constexpr mem_layout memory_layout = mem_layout_;
+    static constexpr msg_type message_type = msg_type::unaligned_2d;
+    static constexpr uint32_t alignment_in_bytes
+            = mem_desc_t::alignment_in_bytes;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+private:
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+
+    using this_payload_t = mem_payload_t<mem_desc_t, tile_desc,
+            msg_type::unaligned_2d, arch_tag_>;
+
+public:
+    static constexpr bool mem_transpose
+            = memory_layout == mem_layout::col_major;
+
+    static constexpr reg_layout register_layout = tile_desc::register_layout;
+    static constexpr bool reg_transpose
+            = register_layout == reg_layout::transpose_tiled;
+    static constexpr bool trans = mem_transpose ^ reg_transpose;
+
+    static constexpr bool mem_transform = (sizeof(dtype) < 4)
+            && (register_layout == reg_layout::vnni_tiled
+                    || register_layout == reg_layout::vnni_tiled_col_major);
+
+    static constexpr uint32_t tile_bytes
+            = tile_size_x * tile_size_y * sizeof(dtype);
+    static constexpr uint32_t block_bytes
+            = block_size_x * block_size_y * sizeof(dtype);
+
+    using mem_dtype = typename std::conditional<
+            (alignment_in_bytes % sizeof(uint64_t) == 0), uint64_t,
+            typename std::conditional<(alignment_in_bytes % sizeof(uint32_t)
+                                              == 0),
+                    uint32_t, dtype>::type>::type;
+    static constexpr uint32_t scale_factor = sizeof(mem_dtype) / sizeof(dtype);
+
+    // for pvc, we can use simd16 or simd32
+    static constexpr uint32_t min_store_bytes = 16 * sizeof(dtype);
+    static constexpr uint32_t max_store_bytes = 32 * sizeof(dtype);
+    static constexpr uint32_t num_channel
+            = ((tile_bytes % max_store_bytes) == 0
+                      && (block_bytes % max_store_bytes) == 0)
+            ? 32
+            : 16;
+
+    static constexpr uint32_t num_channel_x
+            = block_size_x * sizeof(dtype) / sizeof(mem_dtype);
+    static constexpr uint32_t num_channel_y = num_channel / num_channel_x;
+
+    xetla_vector<uint32_t, num_channel> channel_offset;
+    xetla_vector<uint32_t, num_channel> step_x;
+    xetla_vector<uint32_t, num_channel> step_y;
+
+    uint64_t base_offset;
+    uint32_t base_x;
+    uint32_t base_y;
+    uint32_t width_in_elems;
+    uint32_t height_in_elems;
+
+    mem_dtype *base_ptr;
+    uint32_t pitch_in_bytes;
+
+    inline mem_payload_t(mem_desc_t &mem_tdesc) {
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        base_x = mem_tdesc.coord.x;
+        base_y = mem_tdesc.coord.y;
+        width_in_elems = mem_tdesc.shape.x;
+        height_in_elems = mem_tdesc.shape.y;
+        base_offset = trans ? base_x * pitch_in_bytes + base_y * sizeof(dtype)
+                            : base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)mem_tdesc.base.base;
+
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = trans
+                ? step_y * sizeof(mem_dtype) + step_x * pitch_in_bytes
+                : step_x * sizeof(mem_dtype) + step_y * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        base_x = surface_offset_x;
+        base_y = surface_offset_y;
+        width_in_elems = surface_width;
+        height_in_elems = surface_height;
+        base_offset = trans ? base_x * pitch_in_bytes + base_y * sizeof(dtype)
+                            : base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)p;
+
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = trans
+                ? step_y * sizeof(mem_dtype) + step_x * pitch_in_bytes
+                : step_x * sizeof(mem_dtype) + step_y * pitch_in_bytes;
+    }
+
+    __XETLA_API void init(mem_desc_t &mem_tdesc) {
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        base_x = mem_tdesc.coord.x;
+        base_y = mem_tdesc.coord.y;
+        width_in_elems = mem_tdesc.shape.x;
+        height_in_elems = mem_tdesc.shape.y;
+        base_offset = trans ? base_x * pitch_in_bytes + base_y * sizeof(dtype)
+                            : base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)mem_tdesc.base.base;
+
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = trans
+                ? step_y * sizeof(mem_dtype) + step_x * pitch_in_bytes
+                : step_x * sizeof(mem_dtype) + step_y * pitch_in_bytes;
+    }
+
+    __XETLA_API void init(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        base_x = surface_offset_x;
+        base_y = surface_offset_y;
+        width_in_elems = surface_width;
+        height_in_elems = surface_height;
+        base_offset = trans ? base_x * pitch_in_bytes + base_y * sizeof(dtype)
+                            : base_y * pitch_in_bytes + base_x * sizeof(dtype);
+        base_ptr = (mem_dtype *)p;
+
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        step_x = channel_index % num_channel_x;
+        step_y = channel_index / num_channel_x;
+        channel_offset = trans
+                ? step_y * sizeof(mem_dtype) + step_x * pitch_in_bytes
+                : step_x * sizeof(mem_dtype) + step_y * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->base_offset = rhs.base_offset;
+        this->base_ptr = rhs.base_ptr;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->base_x = rhs.base_x;
+        this->base_y = rhs.base_y;
+        this->width_in_elems = rhs.width_in_elems;
+        this->height_in_elems = rhs.height_in_elems;
+
+        this->step_x = rhs.step_x;
+        this->step_y = rhs.step_y;
+
+        this->channel_offset = rhs.channel_offset;
+    }
+
+    inline mem_payload_t() = default;
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->base_offset = rhs.base_offset;
+        this->base_ptr = rhs.base_ptr;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->base_x = rhs.base_x;
+        this->base_y = rhs.base_y;
+        this->width_in_elems = rhs.width_in_elems;
+        this->height_in_elems = rhs.height_in_elems;
+
+        this->step_x = rhs.step_x;
+        this->step_y = rhs.step_y;
+        this->channel_offset = rhs.channel_offset;
+
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            base_offset += int64_t(offset) * sizeof(dtype);
+            trans ? base_y += offset : base_x += offset;
+        } else {
+            base_offset += int64_t(offset) * pitch_in_bytes;
+            trans ? base_x += offset : base_y += offset;
+        }
+    }
+};
+
+/// @brief Is to describe the shared local memory surface for scatter load/store
+/// 1. data located in shared local memory 2. tile will be loaded / stored in scatter mode
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+template <typename dtype_, typename tile_desc_, gpu_arch arch_tag_,
+        uint32_t alignment_>
+struct mem_payload_t<
+        mem_desc_t<dtype_, mem_layout::row_major, mem_space::local, alignment_>,
+        tile_desc_, msg_type::scatter, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using mem_desc_t = mem_desc_t<dtype_, mem_layout::row_major,
+            mem_space::local, alignment_>;
+    using dtype = dtype_;
+    using tile_desc = tile_desc_;
+    static constexpr mem_space memory_space = mem_space::local;
+    static constexpr mem_layout memory_layout = mem_layout::row_major;
+    static constexpr msg_type message_type = msg_type::scatter;
+    static constexpr uint32_t alignment_in_bytes
+            = mem_desc_t::alignment_in_bytes;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+private:
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    using this_payload_t
+            = mem_payload_t<mem_desc_t, tile_desc, msg_type::scatter, arch_tag>;
+
+public:
+    static constexpr reg_layout register_layout = tile_desc::register_layout;
+    static constexpr bool mem_transform
+            = (sizeof(dtype) < 4) && register_layout == reg_layout::vnni_tiled;
+
+    static constexpr uint32_t tile_bytes
+            = tile_size_x * tile_size_y * sizeof(dtype);
+    static constexpr uint32_t block_bytes
+            = block_size_x * block_size_y * sizeof(dtype);
+    using mem_dtype = typename std::conditional<
+            (block_bytes % (16 * sizeof(uint64_t)) == 0), uint64_t,
+            typename std::conditional<(block_bytes % (16 * sizeof(uint32_t))
+                                              == 0),
+                    uint32_t, dtype>::type>::type;
+    // we can use simd16 or simd32
+    static constexpr uint32_t min_bytes = 16 * sizeof(mem_dtype);
+    static constexpr uint32_t max_bytes = 32 * sizeof(mem_dtype);
+
+    static constexpr uint32_t num_channel
+            = ((tile_bytes % max_bytes) == 0 && (block_bytes % max_bytes) == 0)
+            ? 32
+            : 16;
+    static constexpr uint32_t num_channel_x
+            = block_size_x * sizeof(dtype) / sizeof(mem_dtype);
+    static constexpr uint32_t num_channel_y = num_channel / num_channel_x;
+    xetla_vector<uint32_t, num_channel> address;
+    uint32_t pitch_in_bytes;
+    uint32_t wg_width_in_bytes;
+    uint32_t wg_height_in_elems;
+
+    inline mem_payload_t(mem_desc_t &mem_tdesc) {
+        xetla_tdescriptor base_tdesc = mem_tdesc.get_tdesc();
+        pitch_in_bytes = base_tdesc[4];
+        wg_width_in_bytes = base_tdesc[2];
+        wg_height_in_elems = base_tdesc[3];
+        uint32_t offset_x = base_tdesc[5];
+        uint32_t offset_y = base_tdesc[6];
+        uint32_t start_address = base_tdesc[0];
+        start_address += offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        address = start_address
+                + (channel_index % num_channel_x) * sizeof(mem_dtype)
+                + (channel_index / num_channel_x) * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(uint32_t base, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        wg_width_in_bytes = surface_width * sizeof(dtype);
+        wg_height_in_elems = surface_height;
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        uint32_t start_address = base;
+        start_address += offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        address = start_address
+                + (channel_index % num_channel_x) * sizeof(mem_dtype)
+                + (channel_index / num_channel_x) * pitch_in_bytes;
+    }
+
+    __XETLA_API void init(uint32_t base, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        wg_width_in_bytes = surface_width * sizeof(dtype);
+        wg_height_in_elems = surface_height;
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        uint32_t start_address = base;
+        start_address += offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        address = start_address
+                + (channel_index % num_channel_x) * sizeof(mem_dtype)
+                + (channel_index / num_channel_x) * pitch_in_bytes;
+    }
+
+    __XETLA_API void init(mem_desc_t &mem_tdesc) {
+        xetla_tdescriptor base_tdesc = mem_tdesc.get_tdesc();
+        pitch_in_bytes = base_tdesc[4];
+        wg_width_in_bytes = base_tdesc[2];
+        wg_height_in_elems = base_tdesc[3];
+        uint32_t offset_x = base_tdesc[5];
+        uint32_t offset_y = base_tdesc[6];
+        uint32_t start_address = base_tdesc[0];
+        start_address += offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        address = start_address
+                + (channel_index % num_channel_x) * sizeof(mem_dtype)
+                + (channel_index / num_channel_x) * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->address = rhs.address;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->wg_width_in_bytes = rhs.wg_width_in_bytes;
+        this->wg_height_in_elems = rhs.wg_height_in_elems;
+    }
+
+    inline mem_payload_t() = default;
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->address = rhs.address;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->wg_width_in_bytes = rhs.wg_width_in_bytes;
+        this->wg_height_in_elems = rhs.wg_height_in_elems;
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            address += offset * sizeof(dtype);
+        } else {
+            address += offset * pitch_in_bytes;
+        }
+    }
+};
+
+/// @brief Is to describe the shared local memory surface for scattering store
+/// 1. data located in shared local memory 2. tile will be stored in scatter mode
+/// 3. data in register file is vnni packed and col majored.
+/// @tparam dtype Is the data type
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam mem_layout_ Is the memory layout
+/// @note this is used for Atrans SLM path, so, we can add more limitation for best performance.
+template <typename dtype_, uint32_t tile_size_x_, uint32_t tile_size_y_,
+        uint32_t block_size_x_, uint32_t block_size_y_, gpu_arch arch_tag_,
+        uint32_t alignment_>
+struct mem_payload_t<
+        mem_desc_t<dtype_, mem_layout::row_major, mem_space::local, alignment_>,
+        tile_desc_t<tile_size_x_, tile_size_y_, block_size_x_, block_size_y_,
+                reg_layout::vnni_tiled_col_major>,
+        msg_type::scatter, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using mem_desc_t = mem_desc_t<dtype_, mem_layout::row_major,
+            mem_space::local, alignment_>;
+    using dtype = dtype_;
+    using tile_desc = tile_desc_t<tile_size_x_, tile_size_y_, block_size_x_,
+            block_size_y_, reg_layout::vnni_tiled_col_major>;
+    static constexpr mem_space memory_space = mem_space::local;
+    static constexpr mem_layout memory_layout = mem_layout::row_major;
+    static constexpr msg_type message_type = msg_type::scatter;
+    static constexpr uint32_t alignment_in_bytes
+            = mem_desc_t::alignment_in_bytes;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+private:
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    using this_payload_t
+            = mem_payload_t<mem_desc_t, tile_desc, msg_type::scatter, arch_tag>;
+
+public:
+    static constexpr uint32_t tile_bytes
+            = tile_size_x * tile_size_y * sizeof(dtype);
+    static constexpr uint32_t block_bytes
+            = block_size_x * block_size_y * sizeof(dtype);
+    using store_dtype = uint32_t;
+    static constexpr uint32_t vnni_scale_factor
+            = sizeof(store_dtype) / sizeof(dtype);
+    static_assert(block_size_x % 16 == 0,
+            "block size x at least need to be 16 channel aligned");
+    static constexpr uint32_t num_channel = block_size_x;
+    static constexpr uint32_t max_vector_size = (block_size_x == 16) ? 8 : 4;
+    static constexpr uint32_t num_vector_size
+            = detail::gcd<tile_size_y / vnni_scale_factor,
+                    max_vector_size>::value;
+    static constexpr uint32_t store_elems
+            = num_channel * num_vector_size * vnni_scale_factor;
+
+    uint32_t base_address;
+    uint32_t pitch_in_bytes;
+    xetla_vector<uint32_t, num_channel> channel_address;
+
+    __XETLA_API void init(mem_desc_t &mem_tdesc) {
+        base_address = mem_tdesc.base.base;
+        pitch_in_bytes = mem_tdesc.shape.stride_x * sizeof(dtype);
+        uint32_t offset_x = mem_tdesc.coord.x; //because this is row-major
+        uint32_t offset_y = mem_tdesc.coord.y;
+        uint32_t offset_address
+                = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        channel_address = offset_address + channel_index * pitch_in_bytes;
+    }
+    __XETLA_API void init(uint32_t base, uint32_t surface_width,
+            uint32_t surface_height, uint32_t surface_pitch,
+            int32_t surface_offset_x, int32_t surface_offset_y) {
+        base_address = base;
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        uint32_t offset_address
+                = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        xetla_vector<uint32_t, num_channel> channel_index
+                = xetla_vector_gen<uint32_t, num_channel>(0, 1);
+        channel_address = offset_address + channel_index * pitch_in_bytes;
+    }
+
+    inline mem_payload_t(uint32_t base, uint32_t surface_width,
+            uint32_t surface_height, uint32_t surface_pitch,
+            int32_t surface_offset_x, int32_t surface_offset_y) {
+        init(base, surface_width, surface_height, surface_pitch,
+                surface_offset_x, surface_offset_y);
+    }
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // ~mem_payload_t(){}
+    inline mem_payload_t(mem_desc_t &mem_tdesc) { init(mem_tdesc); }
+
+    inline mem_payload_t(const this_payload_t &rhs) {
+        this->base_address = rhs.base_address;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->channel_address = rhs.channel_address;
+    }
+
+    inline mem_payload_t() = default;
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->base_address = rhs.base_address;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        this->channel_address = rhs.channel_address;
+        return *this;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            channel_address += offset * sizeof(dtype);
+        } else {
+            channel_address += offset * pitch_in_bytes;
+        }
+    }
+
+    __XETLA_API void set_base_address(uint32_t base) {
+        this->base_address = base;
+    }
+};
+
+/// @brief Is to describe the global memory surface to prefetch data to cache
+/// data in global memory will be prefetched into 2d tile
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam dtype Is the data type
+/// @tparam mem_layout Is the data layout
+/// @tparam num_coop_sg_ Is the thread nums to prefetch data
+template <typename dtype_, uint32_t tile_size_x_, uint32_t tile_size_y_,
+        uint32_t block_size_x_, uint32_t block_size_y_, mem_layout mem_layout_,
+        uint32_t alignment_, uint32_t num_coop_sg_, reg_layout reg_layout_,
+        gpu_arch arch_tag_>
+struct prefetch_payload_t<
+        mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_>,
+        tile_desc_t<tile_size_x_, tile_size_y_, block_size_x_, block_size_y_,
+                reg_layout_>,
+        num_coop_sg_, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using dtype = dtype_;
+    using mem_desc_t
+            = mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_>;
+    using tile_desc = tile_desc_t<tile_size_x_, tile_size_y_, block_size_x_,
+            block_size_y_, reg_layout_>;
+    static constexpr mem_space memory_space = mem_space::global;
+    static constexpr mem_layout memory_layout = mem_layout_;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+
+    // private:
+    static constexpr bool is_col_major = mem_layout_ == mem_layout::col_major;
+    static constexpr uint32_t mem_tile_size_w
+            = is_col_major ? tile_size_y : tile_size_x;
+    static constexpr uint32_t mem_tile_size_h
+            = is_col_major ? tile_size_x : tile_size_y;
+    using load_store_attr = typename arch_attr_t<
+            arch_tag>::template load_store_attr<msg_type::block_2d>;
+    static constexpr uint32_t special_prefetch_width
+            = load_store_attr::special_prefetch_width_in_bytes / sizeof(dtype);
+    static constexpr uint32_t normal_prefetch_width
+            = load_store_attr::max_load_width_in_bytes / sizeof(dtype);
+    static constexpr bool is_special_prefetch
+            = (mem_tile_size_w % special_prefetch_width) == 0;
+
+    static constexpr uint32_t block_size_w = is_special_prefetch
+            ? special_prefetch_width
+            : (normal_prefetch_width > mem_tile_size_w ? mem_tile_size_w
+                                                       : normal_prefetch_width);
+    static constexpr uint32_t block_size_h
+            = load_store_attr::max_load_height_in_elem;
+    //could have over-prefetch, but that's should be fine
+    static constexpr uint32_t max_num_block_w
+            = (mem_tile_size_w + block_size_w - 1) / block_size_w;
+    static constexpr uint32_t num_coop_sg = num_coop_sg_;
+    static constexpr uint32_t num_coop_sg_w
+            = detail::gcd<num_coop_sg, max_num_block_w>::value;
+    static constexpr uint32_t num_coop_sg_h = num_coop_sg / num_coop_sg_w;
+
+    static constexpr uint32_t num_block_w = max_num_block_w / num_coop_sg_w;
+    static constexpr uint32_t tile_size_w = block_size_w * num_block_w;
+    static constexpr uint32_t tile_size_h
+            = (mem_tile_size_h + num_coop_sg_h - 1) / num_coop_sg_h;
+    static constexpr uint32_t num_block_h
+            = (tile_size_h + block_size_h - 1) / block_size_h;
+    using this_payload_t
+            = prefetch_payload_t<mem_desc_t, tile_desc, num_coop_sg_, arch_tag>;
+
+public:
+    static constexpr uint32_t num_tdesc = num_block_w * num_block_h;
+    xetla_vector<uint32_t, num_tdesc * 16> tdesc_prefetch;
+
+    inline prefetch_payload_t(const this_payload_t &rhs) {
+        this->tdesc_prefetch = rhs.tdesc_prefetch;
+    }
+
+    inline prefetch_payload_t() = default;
+
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->tdesc_prefetch = rhs.tdesc_prefetch;
+        return *this;
+    }
+
+    inline prefetch_payload_t(mem_desc_t &mem_desc, uint32_t coop_id = 0) {
+        xetla_tdescriptor base_tdesc = mem_desc.get_tdesc();
+        uint32_t coop_id_x = coop_id % num_coop_sg_w;
+        uint32_t coop_id_y = coop_id / num_coop_sg_w;
+        xetla_update_tdesc_offsetx(
+                base_tdesc.xetla_format<uint32_t>(), coop_id_x * tile_size_w);
+        xetla_update_tdesc_offsety(
+                base_tdesc.xetla_format<uint32_t>(), coop_id_y * tile_size_h);
+        prepare_tdesc(base_tdesc);
+    }
+
+    inline prefetch_payload_t(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y,
+            uint32_t coop_id = 0) {
+        uint32_t coop_id_x = coop_id % num_coop_sg_w;
+        uint32_t coop_id_y = coop_id / num_coop_sg_w;
+        xetla_tdescriptor base_tdesc;
+        xetla_fill_tdesc(base_tdesc.xetla_format<uint32_t>(), p, surface_width,
+                surface_height, surface_pitch,
+                surface_offset_x + coop_id_x * tile_size_w,
+                surface_offset_y + coop_id_y * tile_size_h);
+        prepare_tdesc(base_tdesc);
+    }
+
+    inline void init(xetla_tdescriptor base_tdesc, uint32_t coop_id = 0) {
+        uint32_t coop_id_x = coop_id % num_coop_sg_w;
+        uint32_t coop_id_y = coop_id / num_coop_sg_w;
+        xetla_update_tdesc_offsetx(
+                base_tdesc.xetla_format<uint32_t>(), coop_id_x * tile_size_w);
+        xetla_update_tdesc_offsety(
+                base_tdesc.xetla_format<uint32_t>(), coop_id_y * tile_size_h);
+        prepare_tdesc(base_tdesc);
+    }
+    // Be aware of the risks: Rule of three (copy constructor, copy assignment, destructor)
+    // Please check if you need to add self-define destructor
+    // ~prefetch_payload_t(){}
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+#pragma unroll
+            for (int i = 0; i < num_tdesc; i++) {
+                xetla_update_tdesc_offsetx(tdesc_2d.row(i), offset);
+            }
+        } else {
+#pragma unroll
+            for (int i = 0; i < num_tdesc; i++) {
+                xetla_update_tdesc_offsety(tdesc_2d.row(i), offset);
+            }
+        }
+    }
+    __XETLA_API void set_tdesc_width(uint32_t size) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            xetla_set_tdesc_width<dtype>(tdesc_2d.row(i), size);
+        }
+    }
+
+    __XETLA_API void set_tdesc_pitch(uint32_t size) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            xetla_set_tdesc_pitch<dtype>(tdesc_2d.row(i), size);
+        }
+    }
+
+    __XETLA_API void set_tdesc_height(uint32_t size) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            xetla_set_tdesc_height(tdesc_2d.row(i), size);
+        }
+    }
+
+    __XETLA_API void update_tdesc_base_address(int offset) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            xetla_update_tdesc_base_address(tdesc_2d.row(i), offset);
+        }
+    }
+
+    __XETLA_API void set_tdesc_base_address(uint64_t addr) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            gpu::xetla::detail::xetla_set_tensor_base_address(
+                    tdesc_2d.row(i), addr);
+        }
+    }
+
+    __XETLA_API void update_tdesc_base_address_masked(
+            int offset, uint16_t mask = 1) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            xetla_update_tdesc_base_address(tdesc_2d.row(i), offset);
+        }
+
+#pragma unroll
+        for (int i = 0; i < num_tdesc; i++) {
+            xetla_tdesc_mask_op(tdesc_2d.row(i), mask);
+        }
+    }
+
+    __XETLA_API void set_offset(
+            int32_t offset_x, int32_t offset_y, uint32_t coop_id = 0) {
+        uint32_t coop_id_x = coop_id % num_coop_sg_w;
+        uint32_t coop_id_y = coop_id / num_coop_sg_w;
+
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+        int32_t base_offset_y = offset_y
+                + (is_col_major ? coop_id_x * tile_size_w
+                                : coop_id_y * tile_size_h);
+#pragma unroll
+        for (int i = 0; i < num_block_h; i++) {
+            auto tdesc_row_2d = tdesc_2d.xetla_select<num_block_w, 1, 16, 1>(
+                    i * num_block_w, 0);
+
+            int32_t base_offset_x = offset_x
+                    + (is_col_major ? coop_id_y * tile_size_h
+                                    : coop_id_x * tile_size_w);
+#pragma unroll
+            for (int j = 0; j < num_block_w; j++) {
+                int32_t offset_width
+                        = is_col_major ? base_offset_y : base_offset_x;
+                int32_t offset_height
+                        = is_col_major ? base_offset_x : base_offset_y;
+                gpu::xetla::detail::xetla_set_tensor_offset_x(
+                        tdesc_row_2d.row(j), offset_width);
+                gpu::xetla::detail::xetla_set_tensor_offset_y(
+                        tdesc_row_2d.row(j), offset_height);
+
+                base_offset_x += block_size_w;
+            }
+            base_offset_y += block_size_h;
+        }
+    }
+
+private:
+    __XETLA_API void prepare_tdesc(xetla_tdescriptor base_tdesc) {
+        auto tdesc_2d = tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+        uint32_t base_offset_y = 0;
+#pragma unroll
+        for (int i = 0; i < tile_size_h / block_size_h; i++) {
+            auto tdesc_row_2d = tdesc_2d.xetla_select<num_block_w, 1, 16, 1>(
+                    i * num_block_w, 0);
+            prepare_tile_desc_core<num_block_w, block_size_w, block_size_h>(
+                    tdesc_row_2d, base_tdesc, base_offset_y);
+            base_offset_y += block_size_h;
+        }
+        if constexpr ((tile_size_h % block_size_h) != 0) {
+            constexpr int i = tile_size_h / block_size_h;
+            auto tdesc_row_2d = tdesc_2d.xetla_select<num_block_w, 1, 16, 1>(
+                    i * num_block_w, 0);
+            constexpr uint32_t remain_size_y = tile_size_h % block_size_h;
+            prepare_tile_desc_core<num_block_w, block_size_w, remain_size_y>(
+                    tdesc_row_2d, base_tdesc, base_offset_y);
+        }
+    }
+
+    template <int32_t num_tdesc, uint32_t size_x, uint32_t size_y>
+    __XETLA_API static void prepare_tile_desc_core(
+            xetla_matrix_ref<uint32_t, num_tdesc, 16> __REF__ tdesc_2d,
+            xetla_tdescriptor base_tdesc, uint32_t base_offset_y) {
+        uint32_t base_offset_x = 0;
+#pragma unroll
+        for (int j = 0; j < num_tdesc; j++) {
+            tdesc_2d.row(j) = base_tdesc;
+
+            constexpr uint32_t block_widthx_widthy_arrlen
+                    = (size_x - 1) | ((size_y - 1) << 8);
+            gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                    tdesc_2d.row(j), block_widthx_widthy_arrlen);
+
+            xetla_update_tdesc_offsetx(tdesc_2d.row(j), base_offset_x);
+            xetla_update_tdesc_offsety(tdesc_2d.row(j), base_offset_y);
+            base_offset_x += size_x;
+        }
+    }
+};
+
+/// @brief Is to describe the memory memory to prefetch data to cache
+/// data in global memory will be prefetched into 1d tile
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam dtype Is the data type
+/// @tparam mem_layout Is the data layout
+/// @tparam num_coop_sg_ Is the thread nums to prefetch data
+template <typename dtype_, uint32_t tile_size_x_, uint32_t block_size_x_,
+        mem_layout mem_layout_, uint32_t alignment_, uint32_t num_coop_sg_,
+        reg_layout reg_layout_, gpu_arch arch_tag_>
+struct prefetch_payload_t<
+        mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_>,
+        tile_desc_t<tile_size_x_, 1, block_size_x_, 1, reg_layout_>,
+        num_coop_sg_, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using dtype = dtype_;
+    using mem_desc_t
+            = mem_desc_t<dtype_, mem_layout_, mem_space::global, alignment_>;
+    // CL aligned, so we can use uint64_t
+    using prefetch_dtype = uint64_t;
+    using tile_desc
+            = tile_desc_t<tile_size_x_, 1, block_size_x_, 1, reg_layout_>;
+    static constexpr mem_space memory_space = mem_space::global;
+    static constexpr mem_layout memory_layout = mem_layout_;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+private:
+    // Fetches the entire CL.
+    static constexpr uint32_t cacheline_elems = 64 / sizeof(dtype);
+    static constexpr uint32_t mem_block_nums
+            = (tile_desc::tile_size_x + cacheline_elems - 1) / cacheline_elems;
+    static constexpr uint32_t num_coop_sg = num_coop_sg_;
+
+    // For mem_tile_nums < num_coop_sg cases, mem_tile_size_x will be CL length
+    // which might lead to illegal read.
+    // there are num_coop_sg threads to prefetch mem_block_nums
+    // each thread will prefetch mem_tile_size_x elements
+    static constexpr uint32_t mem_tile_size_x = mem_block_nums > num_coop_sg
+            ? (mem_block_nums + num_coop_sg - 1) / num_coop_sg *cacheline_elems
+            : 0;
+    using this_payload_t
+            = prefetch_payload_t<mem_desc_t, tile_desc, num_coop_sg_, arch_tag>;
+
+    // Fixed prefetch_dtype, close this assertion
+    // static_assert(sizeof(prefetch_dtype) >= 4,
+    //         "prefetch dtype size should at least DW aligned");
+
+public:
+    static constexpr uint32_t scale_factor
+            = sizeof(prefetch_dtype) / sizeof(dtype);
+    uint32_t base_offset;
+    prefetch_dtype *base_ptr;
+    uint32_t pitch_in_bytes;
+
+    inline prefetch_payload_t(const this_payload_t &rhs) {
+        this->base_offset = rhs.base_offset;
+        this->base_ptr = rhs.base_ptr;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+    }
+
+    inline prefetch_payload_t() = default;
+
+    inline this_payload_t &operator=(const this_payload_t &rhs) {
+        this->base_offset = rhs.base_offset;
+        this->base_ptr = rhs.base_ptr;
+        this->pitch_in_bytes = rhs.pitch_in_bytes;
+        return *this;
+    }
+
+    inline prefetch_payload_t(mem_desc_t &mem_desc, uint32_t coop_id = 0) {
+        pitch_in_bytes = mem_desc.shape.stride_x * sizeof(dtype);
+        uint32_t offset_x = mem_desc.coord.x;
+        uint32_t offset_y = mem_desc.coord.y;
+        base_offset = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        uint64_t ptr_temp = (uint64_t)mem_desc.base.base;
+        base_ptr = (prefetch_dtype *)ptr_temp
+                + (coop_id % num_coop_sg) * mem_tile_size_x;
+    }
+
+    inline prefetch_payload_t(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y,
+            uint32_t coop_id = 0) {
+        pitch_in_bytes = surface_pitch * sizeof(dtype);
+        uint32_t offset_x = surface_offset_x;
+        uint32_t offset_y = surface_offset_y;
+        base_offset = offset_y * pitch_in_bytes + offset_x * sizeof(dtype);
+        base_ptr = (prefetch_dtype *)p
+                + (coop_id % num_coop_sg) * mem_tile_size_x;
+    }
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {
+        if constexpr (update_dir == tdesc_update_dir::x_dir) {
+            base_offset += offset * sizeof(dtype);
+        } else {
+            base_offset += offset * pitch_in_bytes;
+        }
+    }
+};
+
+/// @brief Is to describe the memory infomation to prefetch data to cache
+/// data located in shared local memory, nothing will do.
+/// @tparam tile_desc_ Is the tile descriptor
+/// @tparam dtype Is the data type
+/// @tparam mem_layout Is the data layout
+/// @tparam num_coop_sg_ Is the thread nums to prefetch data
+template <typename dtype_, typename tile_desc_, mem_layout mem_layout_,
+        uint32_t alignment_, uint32_t num_coop_sg_, gpu_arch arch_tag_>
+struct prefetch_payload_t<
+        mem_desc_t<dtype_, mem_layout_, mem_space::local, alignment_>,
+        tile_desc_, num_coop_sg_, arch_tag_,
+        std::enable_if_t<(arch_tag_ == gpu_arch::Xe)>> {
+    using dtype = dtype_;
+    using mem_desc_t
+            = mem_desc_t<dtype_, mem_layout_, mem_space::local, alignment_>;
+    using tile_desc = tile_desc_;
+    static constexpr mem_space memory_space = mem_space::local;
+    static constexpr mem_layout memory_layout = mem_layout_;
+    static constexpr gpu_arch arch_tag = arch_tag_;
+
+    inline prefetch_payload_t(mem_desc_t &mem_desc, uint32_t coop_id = 0) {}
+
+    inline prefetch_payload_t(dtype *p, int surface_width, int surface_height,
+            int surface_pitch, int surface_offset_x, int surface_offset_y,
+            uint32_t coop_id = 0) {}
+
+    template <tdesc_update_dir update_dir = tdesc_update_dir::x_dir>
+    __XETLA_API void update_tdesc(int offset) {}
+};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/prefetch_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/prefetch_xe.hpp
new file mode 100644
index 00000000000000..52822cfb1ee0e4
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/prefetch_xe.hpp
@@ -0,0 +1,119 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/impl/op_function.hpp"
+#include "subgroup/tile/impl/payload_xe.hpp"
+
+namespace gpu::xetla::subgroup {
+namespace detail {
+template <typename payload_t>
+struct check_prefetch_type {
+    static constexpr bool is_global_2d_xe
+            = ((payload_t::memory_space == mem_space::global)
+                    && (payload_t::tile_desc::tile_size_y != 1)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_global_block_1d_xe
+            = ((payload_t::memory_space == mem_space::global)
+                    && (payload_t::tile_desc::tile_size_y == 1)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_local_xe
+            = ((payload_t::memory_space == mem_space::local)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+};
+
+} // namespace detail
+
+/// @brief Is prefetch data func, which data located in global memory is prefetched to
+/// cache, where has higher bandwidth. e.g. In gemm, prefetch next iteration data for mma
+/// consumption. This func is specicalized for block 2d scenario.
+/// @tparam payload_t Is the mem_payload_t struct illustrating memory info
+/// payload indicates the source of prefetch operation.
+/// @tparam L1 Is cache hint for L1 cache.
+/// @tparam L2 Is cache hint for L2 cache.
+/// @param payload Is the payload object with type payload_t. Contains all the information for prefetches.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_prefetch_type<payload_t>::is_global_2d_xe>
+tile_prefetch(payload_t &payload, uint16_t pred = 1) {
+    using dtype = typename payload_t::dtype;
+    static constexpr uint32_t num_tdesc = payload_t::num_tdesc;
+    auto tdesc_2d
+            = payload.tdesc_prefetch.xetla_format<uint32_t, num_tdesc, 16>();
+
+#pragma unroll
+    for (int i = 0; i < num_tdesc; i++) {
+        xetla_mask<16> mask = pred;
+        xetla_tprefetch_global<dtype, L1, L2, payload_t::arch_tag>(
+                tdesc_2d.row(i), pred);
+    }
+}
+
+/// @brief Is prefetch data func, which data located in global memory is prefetched to
+/// cache, where has higher bandwidth. e.g. In gemm, prefetch next iteration data for mma
+/// consumption. This func is specicalized for block 1d scenario.
+/// @tparam payload_t Is the mem_payload_t struct illustrating memory info
+/// payload indicates the source of prefetch operation
+/// @tparam L1 Is cache hint for L1 cache.
+/// @tparam L2 Is cache hint for L2 cache.
+/// @param payload Is the payload object with type payload_t. Contains all the information for prefetches.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_prefetch_type<payload_t>::is_global_block_1d_xe>
+tile_prefetch(payload_t &payload) {
+    using dtype = typename payload_t::dtype;
+    using tile_desc = typename payload_t::tile_desc;
+    using prefetch_dtype = typename payload_t::prefetch_dtype;
+    constexpr uint32_t prefetch_len
+            = tile_desc::tile_size_x / payload_t::scale_factor;
+    if constexpr (prefetch_len >= 64) {
+#pragma unroll
+        for (int j = 0; j < prefetch_len / 64; j++) {
+            uint32_t offset_x = j * 64 * payload_t::scale_factor;
+            uint32_t address_offset = offset_x * sizeof(dtype);
+            xetla_prefetch_global<prefetch_dtype, 64, data_size::default_size,
+                    L1, L2>(
+                    payload.base_ptr, payload.base_offset + address_offset);
+        }
+    }
+    constexpr uint32_t tail_len = prefetch_len % 64;
+    uint32_t tail_offset = prefetch_len / 64 * 64 * payload_t::scale_factor;
+    detail::process_1d_tail<tail_len, 32, L1, L2, payload_t>(
+            payload, tail_offset);
+}
+
+/// @brief Is prefetch data func.
+/// Current shared local memory prefetch is not supported yet. Only used to keep the consistency with global prefetch.
+/// @tparam payload_t Is the mem_payload_t struct illustrating memory info.
+/// @tparam L1 Is cache hint for L1 cache.
+/// @tparam L2 Is cache hint for L2 cache.
+/// @param payload Is the payload object with type payload_t. Contains all the information for prefetches.
+template <cache_hint L1 = cache_hint::cached,
+        cache_hint L2 = cache_hint::cached, typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_prefetch_type<payload_t>::is_local_xe>
+tile_prefetch(payload_t &payload) {}
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/reduction.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/reduction.hpp
new file mode 100644
index 00000000000000..9bdd0140990083
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/reduction.hpp
@@ -0,0 +1,375 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/common.hpp"
+
+namespace gpu::xetla::subgroup {
+
+// dim=0 : reduce along y dir;
+// dim=1 : reduce along x dir;
+template <reduce_op reduce_kind, typename dtype_out, typename dtype_acc,
+        int dim, typename mat_t>
+__XETLA_API typename std::enable_if_t<(dim == 1),
+        xetla_vector<dtype_out, mat_t::tile_size_y>>
+tile_reduce(mat_t &src) {
+    static constexpr uint32_t tile_size_y = mat_t::tile_size_y;
+    static constexpr uint32_t tile_size_x = mat_t::tile_size_x;
+    static constexpr uint32_t tile_elems = mat_t::tile_elems;
+    static constexpr uint32_t block_size_y = mat_t::block_size_y;
+    static constexpr uint32_t block_size_x = mat_t::block_size_x;
+    static constexpr uint32_t block_elems = mat_t::block_elems;
+    static constexpr int32_t num_block_y = mat_t::num_block_y;
+    static constexpr int32_t num_block_x = mat_t::num_block_x;
+    using dtype = typename mat_t::dtype;
+    /// The idea is
+    /// 1) allocate a temp buffer;
+    /// 2) reduce the entire tile into temp buffer;
+    /// 3) reduce within temp buffer
+    xetla_vector<dtype_acc, tile_size_y * block_size_x> acc;
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+        //j=0, initial the buffer
+        {
+            auto src_reg = (src.reg).xetla_select<block_elems, 1>(
+                    (i * num_block_x) * block_elems);
+            auto src_reg_acc
+                    = xetla_cvt<dtype_acc, dtype, block_elems>(src_reg);
+            auto dst_reg_acc
+                    = acc.xetla_select<block_elems, 1>(i * block_elems);
+            dst_reg_acc = src_reg_acc;
+        }
+#pragma unroll
+        for (int j = 1; j < num_block_x; j++) {
+            auto src_reg = (src.reg).xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            auto src_reg_acc
+                    = xetla_cvt<dtype_acc, dtype, block_elems>(src_reg);
+            auto dst_reg_acc
+                    = acc.xetla_select<block_elems, 1>(i * block_elems);
+            dst_reg_acc = reduce_helper<reduce_kind, dtype_acc, block_elems>(
+                    dst_reg_acc, src_reg_acc);
+        }
+    }
+
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr uint32_t tail_start_y
+                = tile_size_y / block_size_y * block_size_y;
+        constexpr uint32_t tail_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t tail_block_elems = tail_size_y * block_size_x;
+        //j=0, initial the buffer
+        {
+            auto src_reg = (src.reg).xetla_select<tail_block_elems, 1>(
+                    tail_start_y * tile_size_x);
+            auto src_reg_acc
+                    = xetla_cvt<dtype_acc, dtype, tail_block_elems>(src_reg);
+            auto dst_reg_acc = acc.xetla_select<tail_block_elems, 1>(
+                    tail_start_y * block_size_x);
+            dst_reg_acc = src_reg_acc;
+        }
+#pragma unroll
+        for (int j = 1; j < num_block_x; j++) {
+            auto src_reg = (src.reg).xetla_select<tail_block_elems, 1>(
+                    tail_start_y * tile_size_x + j * tail_block_elems);
+            auto src_reg_acc
+                    = xetla_cvt<dtype_acc, dtype, tail_block_elems>(src_reg);
+            auto dst_reg_acc = acc.xetla_select<tail_block_elems, 1>(
+                    tail_start_y * block_size_x);
+            dst_reg_acc
+                    = reduce_helper<reduce_kind, dtype_acc, tail_block_elems>(
+                            dst_reg_acc, src_reg_acc);
+        }
+    }
+
+    xetla_vector<dtype_acc, tile_size_y> out = recur_col_reduce<reduce_kind,
+            dtype_acc, block_size_x, tile_size_y>(acc);
+
+    return xetla_cvt<dtype_out, dtype_acc, tile_size_y>(out);
+}
+
+template <reduce_op reduce_kind, typename dtype_out, typename dtype_acc,
+        int dim, typename mat_t>
+__XETLA_API typename std::enable_if_t<(dim == 0),
+        xetla_vector<dtype_out, mat_t::tile_size_x>>
+tile_reduce(mat_t &src) {
+    static constexpr uint32_t tile_size_y = mat_t::tile_size_y;
+    static constexpr uint32_t tile_size_x = mat_t::tile_size_x;
+    static constexpr uint32_t tile_elems = mat_t::tile_elems;
+    static constexpr uint32_t block_size_y = mat_t::block_size_y;
+    static constexpr uint32_t block_size_x = mat_t::block_size_x;
+    static constexpr uint32_t block_elems = mat_t::block_elems;
+    static constexpr int32_t num_block_y = mat_t::num_block_y;
+    static constexpr int32_t num_block_x = mat_t::num_block_x;
+    using dtype = typename mat_t::dtype;
+    static constexpr uint32_t num_acc = 8;
+    static constexpr uint32_t first_block_size_y
+            = (tile_size_y / block_size_y == 0) ? (tile_size_y % block_size_y)
+                                                : block_size_y;
+    static constexpr uint32_t acc_size_y
+            = (num_acc > first_block_size_y) ? first_block_size_y : num_acc;
+    /// The idea is
+    /// 1) allocate a temp buffer;
+    /// 2) reduce the entire tile into temp buffer;
+    /// 3) reduce within temp buffer
+    /// This will introduce additional instructions to initialize the temp
+    /// buffer, but will have more parallelism
+    static constexpr uint32_t first_block_elems
+            = first_block_size_y * block_size_x;
+    static constexpr uint32_t acc_block_elems = acc_size_y * block_size_x;
+    xetla_vector<dtype_acc, acc_size_y * tile_size_x> acc;
+#pragma unroll
+    for (int j = 0; j < num_block_x; j++) {
+        auto src_reg = (src.reg).xetla_select<first_block_elems, 1>(
+                j * first_block_elems);
+        auto src_reg_acc
+                = xetla_cvt<dtype_acc, dtype, first_block_elems>(src_reg);
+        acc.xetla_select<acc_block_elems, 1>(j * acc_block_elems)
+                = src_reg_acc.xetla_select<acc_block_elems, 1>(0);
+    }
+
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto src_reg = (src.reg).xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            auto src_reg_acc
+                    = xetla_cvt<dtype_acc, dtype, block_elems>(src_reg);
+            auto dst_reg_acc
+                    = acc.xetla_select<acc_block_elems, 1>(j * acc_block_elems);
+#pragma unroll
+            for (int row_i = 0; row_i < block_size_y / acc_size_y; row_i++) {
+                if (i == 0 && row_i == 0) continue;
+                dst_reg_acc = reduce_helper<reduce_kind, dtype_acc,
+                        acc_block_elems>(dst_reg_acc,
+                        src_reg_acc.xetla_select<acc_block_elems, 1>(
+                                row_i * acc_block_elems));
+            }
+            // process the tail
+            if constexpr ((block_size_y % acc_size_y) != 0) {
+                constexpr uint32_t acc_tail_start_y
+                        = block_size_y / acc_size_y * acc_size_y;
+                constexpr uint32_t acc_tail_size_y = block_size_y % acc_size_y;
+                constexpr uint32_t acc_tail_block_elems
+                        = acc_tail_size_y * block_size_x;
+                auto dst_reg_acc_tail
+                        = dst_reg_acc.xetla_select<acc_tail_block_elems>(0);
+                dst_reg_acc_tail = reduce_helper<reduce_kind, dtype_acc,
+                        acc_tail_block_elems>(dst_reg_acc_tail,
+                        src_reg_acc.xetla_select<acc_tail_block_elems, 1>(
+                                acc_tail_start_y * block_size_x));
+            }
+        }
+    }
+
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr uint32_t tail_start_y
+                = tile_size_y / block_size_y * block_size_y;
+        constexpr uint32_t tail_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t tail_block_elems = tail_size_y * block_size_x;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto src_reg = (src.reg).xetla_select<tail_block_elems, 1>(
+                    tail_start_y * tile_size_x + j * tail_block_elems);
+            auto src_reg_acc
+                    = xetla_cvt<dtype_acc, dtype, tail_block_elems>(src_reg);
+            auto dst_reg_acc
+                    = acc.xetla_select<acc_block_elems, 1>(j * acc_block_elems);
+#pragma unroll
+            for (int row_i = 0; row_i < tail_size_y / acc_size_y; row_i++) {
+                if ((tile_size_y / block_size_y == 0) && row_i == 0) continue;
+                dst_reg_acc = reduce_helper<reduce_kind, dtype_acc,
+                        acc_block_elems>(dst_reg_acc,
+                        src_reg_acc.xetla_select<acc_block_elems, 1>(
+                                row_i * acc_block_elems));
+            }
+            // process the tail
+            if constexpr ((tail_size_y % acc_size_y) != 0) {
+                constexpr uint32_t acc_tail_start_y
+                        = tail_size_y / acc_size_y * acc_size_y;
+                constexpr uint32_t acc_tail_size_y = tail_size_y % acc_size_y;
+                constexpr uint32_t acc_tail_block_elems
+                        = acc_tail_size_y * block_size_x;
+                auto dst_reg_acc_tail
+                        = dst_reg_acc.xetla_select<acc_tail_block_elems>(0);
+                dst_reg_acc_tail = reduce_helper<reduce_kind, dtype_acc,
+                        acc_tail_block_elems>(dst_reg_acc_tail,
+                        src_reg_acc.xetla_select<acc_tail_block_elems, 1>(
+                                acc_tail_start_y * block_size_x));
+            }
+        }
+    }
+
+    xetla_vector<dtype_acc, tile_size_x> out;
+#pragma unroll
+    for (int i = 0; i < acc_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto reg_acc
+                    = acc.xetla_select<acc_block_elems, 1>(j * acc_block_elems);
+            auto reg_acc_2d = reg_acc.xetla_format<dtype_acc, acc_size_y,
+                    block_size_x>();
+            if (i == 0) {
+                out.xetla_select<block_size_x, 1>(j * block_size_x)
+                        = reg_acc_2d.row(i);
+            } else {
+                out.xetla_select<block_size_x, 1>(j * block_size_x)
+                        = reduce_helper<reduce_kind, dtype_acc, block_size_x>(
+                                out.xetla_select<block_size_x, 1>(
+                                        j * block_size_x),
+                                reg_acc_2d.row(i));
+            }
+        }
+    }
+
+    return xetla_cvt<dtype_out, dtype_acc, tile_size_x>(out);
+}
+
+/// @brief Reduce 2d src tile to the 1d tile, and output to 1d dst.
+///
+/// @tparam T_dst Is the destination tile data type, interpreted as 1d data.
+/// @tparam T_src Is the source tile data type, interpreted as 2d data.
+/// @tparam accumulate is to accumulate the old value or not.
+/// @tparam dtype_acc Is the accumulation data type, src ==> convert to
+/// dtype_acc ==> reduction + accumulation ==>  convert to dtype_dst.
+/// @param dst Is the reference of the destination tile object.
+/// @param src Is the reference of the destination tile object.
+/// @return No return, in-place update in the destination tile.
+/// @note This is only for reduce add, and will be deprecated in future. Please use tile_reduce instead.
+template <typename T_dst, typename T_src, bool accumulate = true,
+        typename dtype_acc = float, uint32_t num_acc = 4>
+XETLA_MARKER(
+        "This is only for reduce add, and will be deprecated in future. "
+        "Please use tile_reduce instead.")
+__XETLA_API
+        typename std::enable_if_t<(T_dst::register_layout == reg_layout::tiled)
+                && (T_src::register_layout == reg_layout::tiled)
+                && (T_dst::tile_size_x == T_src::tile_size_x)
+                && (T_dst::tile_size_y == 1)> tile_row_reduce(T_dst &dst,
+                T_src &src) {
+    static constexpr uint32_t tile_size_y = T_src::tile_size_y;
+    static constexpr uint32_t tile_size_x = T_src::tile_size_x;
+    static constexpr uint32_t tile_elems = T_src::tile_elems;
+    static constexpr uint32_t block_size_y = T_src::block_size_y;
+    static constexpr uint32_t block_size_x = T_src::block_size_x;
+    static constexpr uint32_t block_elems = T_src::block_elems;
+    static constexpr int32_t num_block_y = T_src::num_block_y;
+    static constexpr int32_t num_block_x = T_src::num_block_x;
+    using dtype_dst = typename T_dst::dtype;
+    using dtype_src = typename T_src::dtype;
+    /// Here we rely on compiler to generate mixed mode for bf16
+    static constexpr uint32_t SIMD = 64 / sizeof(dtype_acc);
+    static constexpr uint32_t accum_len
+            = ((block_size_x % SIMD) && (sizeof(dtype_src) < 4)) == 0
+            ? SIMD
+            : block_size_x;
+    static constexpr uint32_t accum_elems = accum_len * block_size_y;
+    /// The idea is
+    /// 1) allocate a temp buffer;
+    /// 2) accumulate the entire tile into temp buffer;
+    /// 3) reduce within temp buffer
+    /// This will introduce additional instructions to initialize the temp
+    /// buffer, but will have more parallelism
+    xetla_vector<dtype_acc, tile_size_x * num_acc> acc(0);
+    auto acc_2d = acc.xetla_format<dtype_acc, num_acc, tile_size_x>();
+    if constexpr (accumulate) {
+        acc_2d.row(0) = xetla_cvt<dtype_acc, dtype_dst, tile_size_x>(dst.reg);
+    }
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto src_reg = (src.reg).xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            auto src_reg_dtype_acc
+                    = xetla_cvt<dtype_acc, dtype_src, block_elems>(src_reg);
+            auto src_reg_2d = src_reg_dtype_acc.xetla_format<dtype_acc,
+                    block_size_y, block_size_x>();
+#pragma unroll
+            for (int row_i = 0; row_i < block_size_y; row_i += num_acc) {
+#pragma unroll
+                for (int acc_i = 0;
+                        (acc_i < num_acc) && (row_i + acc_i < block_size_y);
+                        acc_i++) {
+                    auto acc_sub = acc.xetla_select<block_size_x, 1>(
+                            acc_i * tile_size_x + j * block_size_x);
+#pragma unroll
+                    for (int k = 0; k < block_size_x / accum_len; k++) {
+                        acc_sub.xetla_select<accum_len, 1>(k * accum_len)
+                                = acc_sub.xetla_select<accum_len, 1>(
+                                          k * accum_len)
+                                + src_reg_2d.row(row_i + acc_i)
+                                          .xetla_select<accum_len, 1>(
+                                                  k * accum_len);
+                    }
+                }
+            }
+        }
+    }
+
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr uint32_t tail_start_y
+                = tile_size_y / block_size_y * block_size_y;
+        constexpr uint32_t tail_size_y = tile_size_y % block_size_y;
+        constexpr uint32_t tail_block_elems = tail_size_y * block_size_x;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            auto src_reg = (src.reg).xetla_select<tail_block_elems, 1>(
+                    tail_start_y * tile_size_x + j * tail_block_elems);
+            auto src_reg_dtype_acc
+                    = xetla_cvt<dtype_acc, dtype_src, tail_block_elems>(
+                            src_reg);
+            auto src_reg_2d = src_reg_dtype_acc.xetla_format<dtype_acc,
+                    tail_size_y, block_size_x>();
+#pragma unroll
+            for (int row_i = 0; row_i < tail_size_y; row_i += num_acc) {
+#pragma unroll
+                for (int acc_i = 0;
+                        (acc_i < num_acc) && (row_i + acc_i < tail_size_y);
+                        acc_i++) {
+                    auto acc_sub = acc.xetla_select<block_size_x, 1>(
+                            acc_i * tile_size_x + j * block_size_x);
+#pragma unroll
+                    for (int k = 0; k < block_size_x / accum_len; k++) {
+                        acc_sub.xetla_select<accum_len, 1>(k * accum_len)
+                                = acc_sub.xetla_select<accum_len, 1>(
+                                          k * accum_len)
+                                + src_reg_2d.row(row_i + acc_i)
+                                          .xetla_select<accum_len, 1>(
+                                                  k * accum_len);
+                    }
+                }
+            }
+        }
+    }
+
+#pragma unroll
+    for (int i = 1; i < num_acc; i++) {
+        acc_2d.row(0) += acc_2d.row(i);
+    }
+
+    dst.reg = xetla_cvt<dtype_dst, dtype_acc, tile_size_x>(acc_2d.row(0));
+}
+
+} // namespace gpu::xetla::subgroup
\ No newline at end of file
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/store_xe.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/store_xe.hpp
new file mode 100644
index 00000000000000..084f17b59c1b7a
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/store_xe.hpp
@@ -0,0 +1,790 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/impl/op_function.hpp"
+#include "subgroup/tile/impl/payload_xe.hpp"
+
+namespace gpu::xetla::subgroup {
+
+namespace detail {
+template <typename tile_t, typename payload_t>
+struct check_store_type {
+    static constexpr bool is_global_2d_xe
+            = (payload_t::memory_space == mem_space::global
+                    && (payload_t::message_type == msg_type::block_2d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_global_block_1d_xe
+            = ((payload_t::memory_space == mem_space::global)
+                    && (tile_t::tile_size_y == 1) && (tile_t::block_size_y == 1)
+                    && (payload_t::message_type == msg_type::block_1d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_global_unaligned_2d_xe
+            = (payload_t::memory_space == mem_space::global
+                    && (payload_t::message_type == msg_type::unaligned_2d)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_global_atomic_xe
+            = ((payload_t::memory_space == mem_space::global)
+                    && (payload_t::message_type == msg_type::atomic_add)
+                    && (payload_t::arch_tag == gpu_arch::Xe));
+
+    static constexpr bool is_local_scatter_xe = ((payload_t::memory_space
+                                                         == mem_space::local)
+            && (payload_t::message_type == msg_type::scatter)
+            && (payload_t::arch_tag == gpu_arch::Xe)
+            && (payload_t::tile_desc::register_layout == reg_layout::tiled
+                    || payload_t::tile_desc::register_layout
+                            == reg_layout::vnni_tiled));
+
+    static constexpr bool is_local_scatter_vnni_col_xe
+            = ((payload_t::memory_space == mem_space::local)
+                    && (payload_t::message_type == msg_type::scatter)
+                    && (payload_t::arch_tag == gpu_arch::Xe)
+                    && (payload_t::tile_desc::register_layout
+                            == reg_layout::vnni_tiled_col_major));
+
+    static constexpr bool is_local_block_1d_xe = ((payload_t::memory_space
+                                                          == mem_space::local)
+            && (payload_t::message_type == msg_type::block_1d)
+            && (payload_t::arch_tag == gpu_arch::Xe)
+            && (payload_t::tile_desc::register_layout == reg_layout::tiled));
+};
+
+} // namespace detail
+
+/// @brief Is the func storing data from register file to global memory.
+/// store a rectangular region (X,Y)..(X+W,Y+H) into memory from registers.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_global_2d_xe>
+tile_store(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using store_dtype = typename payload_t::mem_dtype;
+    using check_store =
+            typename subgroup::check_store<gpu_arch::Xe, dtype, store_dtype>::
+                    template global_2d<payload_t::tile_desc::block_size_x>;
+
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+
+    static constexpr uint32_t block_elems = tile_desc::block_elems;
+
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+    static constexpr uint32_t num_block_y = tile_desc::num_block_y;
+    static constexpr uint32_t num_block = tile_desc::num_block;
+
+    using load_store_attr = typename arch_attr_t<
+            payload_t::arch_tag>::template load_store_attr<msg_type::block_2d>;
+
+    static constexpr int32_t max_block_width
+            = load_store_attr::max_load_width_in_bytes / sizeof(dtype);
+    static constexpr int32_t max_store_block_height
+            = load_store_attr::max_store_height_in_elem;
+    static_assert((max_block_width % block_size_x) == 0,
+            "max_block_width should be a multiply of block size x.");
+    static constexpr uint32_t elems_per_CL
+            = load_store_attr::cache_line_size_in_bytes / sizeof(dtype);
+    static constexpr uint32_t st_blk_size_y
+            = block_size_y > max_store_block_height ? max_store_block_height
+                                                    : block_size_y;
+    // to make sure full CL store
+    static constexpr uint32_t st_block_x = ((tile_size_x % elems_per_CL) == 0)
+            ? elems_per_CL
+            : (((elems_per_CL % tile_size_x) == 0) ? tile_size_x
+                                                   : block_size_x);
+
+    static constexpr uint8_t arr_len_candidate = st_block_x / block_size_x;
+    static constexpr bool is_valid_arr_len_candidate = (arr_len_candidate == 1)
+            || (arr_len_candidate == 2) || (arr_len_candidate == 4);
+
+    static constexpr uint8_t arr_len
+            = is_valid_arr_len_candidate ? arr_len_candidate : 1;
+
+    auto payload_2d = payload.payloads.xetla_format<uint32_t, num_block, 16>();
+    uint32_t base_offset_y = 0;
+#pragma unroll
+    for (int i = 0; i < num_block_y; ++i) {
+        constexpr uint32_t store_block_elems = block_elems * arr_len;
+        auto payload_row = payload_2d.xetla_select<num_block_x, 1, 16, 1>(
+                i * num_block_x, 0);
+        detail::reset_tile_desc_core<num_block_x, block_size_x * arr_len,
+                st_blk_size_y, 1, 1, false>(payload_row);
+        base_offset_y += block_size_y;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j += arr_len) {
+            xetla_tdescriptor tdesc = payload_row.row(j);
+            auto reg_blk = tile.reg.xetla_select<store_block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            xetla_vector<dtype, store_block_elems> combine_blk;
+            auto combine_blk_2d = combine_blk.xetla_format<native_type_t<dtype>,
+                    block_size_y, block_size_x * arr_len>();
+#pragma unroll
+            for (int combine_i = 0; combine_i < arr_len; ++combine_i) {
+                combine_blk_2d.xetla_select<block_size_y, 1, block_size_x, 1>(
+                        0, combine_i * block_size_x)
+                        = reg_blk.xetla_select<block_elems, 1>(
+                                combine_i * block_elems);
+            }
+#pragma unroll
+            for (int ii = 0; ii < block_size_y / st_blk_size_y; ++ii) {
+                constexpr uint32_t store_elems
+                        = st_blk_size_y * block_size_x * arr_len;
+                auto st_blk = combine_blk.xetla_select<store_elems, 1>(
+                        ii * store_elems);
+                xetla_tstore_global<dtype, store_elems, L1, L2,
+                        payload_t::arch_tag>(tdesc, st_blk);
+                xetla_update_tdesc_offsety(
+                        tdesc.xetla_format<uint32_t>(), st_blk_size_y);
+            }
+            // exceed hardware limitation
+            if constexpr ((block_size_y % st_blk_size_y) != 0) {
+                constexpr uint32_t blk_remained_start = block_size_y
+                        / st_blk_size_y * st_blk_size_y * block_size_x
+                        * arr_len;
+                constexpr uint8_t blk_remained_y = block_size_y % st_blk_size_y;
+                constexpr uint8_t blk_remained_elems
+                        = blk_remained_y * block_size_x * arr_len;
+                auto st_blk = combine_blk.xetla_select<blk_remained_elems, 1>(
+                        blk_remained_start);
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_size_x * arr_len - 1)
+                        | ((blk_remained_y - 1) << 8);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc.xetla_format<uint32_t>(),
+                        block_widthx_widthy_arrlen);
+                xetla_tstore_global<dtype, blk_remained_elems, L1, L2,
+                        payload_t::arch_tag>(tdesc, st_blk);
+            }
+        }
+    }
+    // process tail
+    if constexpr (remained_size_y > 0) {
+        constexpr uint32_t remained_block_elems
+                = block_size_x * remained_size_y;
+        constexpr uint32_t processed_elems
+                = num_block_y * num_block_x * block_elems;
+        constexpr uint32_t remained_st_blk_size_y
+                = st_blk_size_y > remained_size_y ? remained_size_y
+                                                  : st_blk_size_y;
+        auto payload_row = payload_2d.xetla_select<num_block_x, 1, 16, 1>(
+                num_block_y * num_block_x, 0);
+        detail::reset_tile_desc_core<num_block_x, block_size_x * arr_len,
+                remained_st_blk_size_y, 1, 1, false>(payload_row);
+#pragma unroll
+        for (int j = 0; j < num_block_x; j += arr_len) {
+            xetla_tdescriptor tdesc = payload_row.row(j);
+            auto reg_blk
+                    = tile.reg.xetla_select<remained_block_elems * arr_len, 1>(
+                            processed_elems + j * remained_block_elems);
+            // Do combination
+            xetla_vector<dtype, remained_block_elems * arr_len> combine_blk;
+            auto combine_blk_2d = combine_blk.xetla_format<native_type_t<dtype>,
+                    remained_size_y, block_size_x * arr_len>();
+#pragma unroll
+            for (int combine_i = 0; combine_i < arr_len; ++combine_i) {
+                combine_blk_2d
+                        .xetla_select<remained_size_y, 1, block_size_x, 1>(
+                                0, combine_i * block_size_x)
+                        = reg_blk.xetla_select<remained_block_elems, 1>(
+                                combine_i * remained_block_elems);
+            }
+#pragma unroll
+            for (int ii = 0; ii < remained_size_y / remained_st_blk_size_y;
+                    ++ii) {
+                constexpr uint32_t store_elems
+                        = remained_st_blk_size_y * block_size_x * arr_len;
+                auto st_blk = combine_blk.xetla_select<store_elems, 1>(
+                        ii * store_elems);
+                xetla_tstore_global<dtype, store_elems, L1, L2,
+                        payload_t::arch_tag>(tdesc, st_blk);
+                xetla_update_tdesc_offsety(
+                        tdesc.xetla_format<uint32_t>(), remained_st_blk_size_y);
+            }
+            constexpr uint32_t final_st_blk_size_y
+                    = remained_size_y % remained_st_blk_size_y;
+            if constexpr (final_st_blk_size_y != 0) {
+                constexpr uint32_t final_start = remained_size_y
+                        / remained_st_blk_size_y * remained_st_blk_size_y
+                        * block_size_x * arr_len;
+                constexpr uint32_t final_store_elems
+                        = final_st_blk_size_y * block_size_x * arr_len;
+                auto st_blk = combine_blk.xetla_select<final_store_elems, 1>(
+                        final_start);
+                constexpr uint32_t block_widthx_widthy_arrlen
+                        = (block_size_x * arr_len - 1)
+                        | ((final_st_blk_size_y - 1) << 8);
+                gpu::xetla::detail::xetla_set_block_widthx_widthy_arrlen(
+                        tdesc.xetla_format<uint32_t>(),
+                        block_widthx_widthy_arrlen);
+                xetla_tstore_global<dtype, final_store_elems, L1, L2,
+                        payload_t::arch_tag>(tdesc, st_blk);
+            }
+        }
+    }
+}
+
+/// @brief Is the func storing data from register file to global memory.
+/// For each enabled SIMT lane, a vector is written into memory from registers.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_global_block_1d_xe>
+tile_store(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using store_dtype = typename payload_t::mem_dtype;
+    using check_store = typename subgroup::check_store<gpu_arch::Xe, dtype,
+            store_dtype>::global_1d;
+
+    static constexpr uint32_t tile_size_x = tile_t::tile_size_x;
+    static constexpr uint32_t scale_factor = payload_t::scale_factor;
+
+    constexpr uint32_t store_len = tile_size_x / scale_factor;
+    if constexpr (store_len >= 64) {
+#pragma unroll
+        for (int i = 0; i < store_len / 64; i++) {
+            uint32_t offset_x = i * 64 * scale_factor;
+            auto reg_sub
+                    = tile.reg.xetla_select<64 * scale_factor, 1>(offset_x);
+            uint32_t address_offset = offset_x * sizeof(dtype);
+
+            xetla_store_global<store_dtype, 64, data_size::default_size, L1,
+                    L2>(payload.base_ptr, payload.base_offset + address_offset,
+                    reg_sub.xetla_format<store_dtype>());
+        }
+    }
+    constexpr uint32_t tail_len = store_len % 64;
+    uint32_t tail_offset = store_len / 64 * 64 * scale_factor;
+    detail::process_1d_tail<tail_len, 32, detail::process_flag::store, L1, L2>(
+            tile, payload, tail_offset);
+}
+
+/// @brief Is the func storing data from register file to unaligned global memory surface.
+/// store a rectangular region (X,Y)..(X+W,Y+H) into memory from registers.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation.
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L3 Is the cache hint for L3 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+/// @return No return, update in place.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L3 = cache_hint::write_back, typename tile_t,
+        typename payload_t,
+        typename oob_check_tag = global_atomic_oob_check_on_tag>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_global_unaligned_2d_xe>
+tile_store(tile_t &tile, payload_t &payload, oob_check_tag tag = {}) {
+    constexpr bool oob_check = std::is_same<oob_check_tag,
+            global_atomic_oob_check_on_tag>::value;
+    using dtype = typename payload_t::dtype;
+    using tile_desc = typename payload_t::tile_desc;
+    using store_dtype = typename payload_t::mem_dtype;
+    using check_store =
+            typename subgroup::check_store<gpu_arch::Xe, dtype, store_dtype>::
+                    template unaligned_2d<payload_t::tile_desc::block_size_x>;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    // using num_block_x = tile_desc::num_block_x;
+    constexpr uint32_t num_channel_y = payload_t::num_channel_y;
+    constexpr uint32_t load_elems = num_channel_y * payload_t::num_channel_x;
+    constexpr uint32_t scale_factor = payload_t::scale_factor;
+
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y / tile_desc::block_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::block_size_y;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<tile_desc::block_elems, 1>(
+                    (i * tile_desc::num_block_x + j) * tile_desc::block_elems);
+            xetla_mask<load_elems> pred_x = oob_check
+                    ? payload.step_x + payload.base_x + offset_x
+                            < payload.width_in_elems
+                    : 1;
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < tile_desc::block_size_y;
+                    sub_block_y += num_channel_y) {
+                xetla_mask<load_elems> pred_y = oob_check
+                        ? payload.step_y + payload.base_y + offset_y
+                                        + sub_block_y
+                                < payload.height_in_elems
+                        : 1;
+
+                uint32_t address_offset = offset_x * sizeof(dtype)
+                        + (offset_y + sub_block_y) * payload.pitch_in_bytes;
+                xetla_store_global<store_dtype, 1, data_size::default_size, L1,
+                        L3, load_elems>(payload.base_ptr,
+                        (payload.base_offset + address_offset
+                                + payload.channel_offset),
+                        reg_sub.xetla_select<load_elems * scale_factor, 1>(
+                                       sub_block_y * tile_desc::block_size_x)
+                                .xetla_format<store_dtype>(),
+                        (pred_x && pred_y));
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_desc::tile_size_y % tile_desc::block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_desc::tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_desc::tile_size_x;
+        constexpr uint32_t remain_block_elems
+                = remained_size_y * tile_desc::block_size_x;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+            xetla_mask<load_elems> pred_x = oob_check
+                    ? payload.step_x + payload.base_x + offset_x
+                            < payload.width_in_elems
+                    : 1;
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < remained_size_y;
+                    sub_block_y += num_channel_y) {
+                xetla_mask<load_elems> pred_y = oob_check
+                        ? payload.step_y + payload.base_y + offset_y
+                                        + sub_block_y
+                                < payload.height_in_elems
+                        : 1;
+
+                uint32_t address_offset = offset_x * sizeof(dtype)
+                        + (offset_y + sub_block_y) * payload.pitch_in_bytes;
+                xetla_store_global<store_dtype, 1, data_size::default_size, L1,
+                        L3, load_elems>(payload.base_ptr,
+                        (payload.base_offset + address_offset
+                                + payload.channel_offset),
+                        reg_sub.xetla_select<load_elems * scale_factor, 1>(
+                                       sub_block_y * tile_desc::block_size_x)
+                                .xetla_format<store_dtype>(),
+                        (pred_x && pred_y));
+            }
+        }
+    }
+}
+
+/// @brief Is the func storing data from register file to global memory
+/// enable atomic adding data into the same buffer, but support float32, float64, uint32_t,
+/// uint64_t and int type
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::uncached,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t,
+        typename oob_check_tag = global_atomic_oob_check_on_tag>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_global_atomic_xe>
+tile_store(tile_t &tile, payload_t &payload, oob_check_tag tag = {}) {
+    constexpr bool oob_check = std::is_same<oob_check_tag,
+            global_atomic_oob_check_on_tag>::value;
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using check_store = typename subgroup::check_store<gpu_arch::Xe,
+            dtype>::template global_atomic<payload_t::tile_bytes,
+            payload_t::min_store_bytes, payload_t::block_bytes,
+            payload_t::num_channel_x, payload_t::num_channel>;
+
+    static constexpr uint32_t tile_size_x = tile_desc::tile_size_x;
+    static constexpr uint32_t tile_size_y = tile_desc::tile_size_y;
+    static constexpr uint32_t block_size_x = tile_desc::block_size_x;
+    static constexpr uint32_t block_size_y = tile_desc::block_size_y;
+    static constexpr uint32_t block_elems = tile_desc::block_elems;
+    static constexpr uint32_t num_block_x = tile_desc::num_block_x;
+
+    static constexpr atomic_op op_kind
+            = (std::is_same<remove_const_t<dtype>, float>::value
+                      || std::is_same<remove_const_t<dtype>, double>::value)
+            ? atomic_op::fadd
+            : atomic_op::iadd;
+
+#pragma unroll
+    for (int i = 0; i < tile_size_y / block_size_y; i++) {
+        uint32_t offset_y = i * block_size_y;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            uint32_t offset_x = j * block_size_x;
+            auto reg_sub = tile.reg.xetla_select<block_elems, 1>(
+                    (i * num_block_x + j) * block_elems);
+            xetla_mask<payload_t::num_channel> pred_x = oob_check
+                    ? (payload.step_x + offset_x + payload.base_x)
+                            < payload.width_in_elems
+                    : 1;
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < block_size_y;
+                    sub_block_y += payload_t::num_channel_y) {
+                xetla_mask<payload_t::num_channel> pred_y = oob_check
+                        ? (payload.step_y + offset_y + payload.base_y
+                                  + sub_block_y)
+                                < payload.height_in_elems
+                        : 1;
+                uint64_t address_offset = offset_x * sizeof(dtype)
+                        + (sub_block_y + offset_y) * payload.pitch_in_bytes;
+
+                xetla_tatomic_store_global<dtype, payload_t::num_channel, L1,
+                        L2, op_kind, payload_t::arch_tag,
+                        typename payload_t::Toffset>(
+                        payload.base_pointer + address_offset,
+                        payload.channel_offset,
+                        reg_sub.xetla_select<payload_t::store_elems, 1>(
+                                sub_block_y * block_size_x),
+                        pred_x & pred_y);
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_size_y % block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_size_x;
+        constexpr uint32_t remain_block_elems = remained_size_y * block_size_x;
+#pragma unroll
+        for (int j = 0; j < num_block_x; j++) {
+            uint32_t offset_x = j * block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+            xetla_mask<payload_t::num_channel> pred_x = oob_check
+                    ? (payload.step_x + offset_x + payload.base_x)
+                            < payload.width_in_elems
+                    : 1;
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < remained_size_y;
+                    sub_block_y += payload_t::num_channel_y) {
+                xetla_mask<payload_t::num_channel> pred_y = oob_check
+                        ? (payload.step_y + offset_y + payload.base_y
+                                  + sub_block_y)
+                                < payload.height_in_elems
+                        : 1;
+                uint64_t address_offset = offset_x * sizeof(dtype)
+                        + (sub_block_y + offset_y) * payload.pitch_in_bytes;
+
+                xetla_tatomic_store_global<dtype, payload_t::num_channel, L1,
+                        L2, op_kind, payload_t::arch_tag,
+                        typename payload_t::Toffset>(
+                        (uint64_t)payload.base_pointer + address_offset,
+                        payload.channel_offset,
+                        reg_sub.xetla_select<payload_t::store_elems, 1>(
+                                sub_block_y * block_size_x),
+                        pred_x & pred_y);
+            }
+        }
+    }
+}
+
+/// @brief Is the func storing data from register file to shared local memory,
+/// which supports the memory surface 2d scenario. And the dst memory layout is
+/// is always row major.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_local_scatter_xe>
+tile_store(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using store_dtype = typename payload_t::mem_dtype;
+    using check_store = typename subgroup::check_store<gpu_arch::Xe, dtype,
+            store_dtype>::template local_scatter<payload_t::tile_bytes,
+            payload_t::min_bytes, payload_t::block_bytes,
+            payload_t::num_channel_x, payload_t::num_channel>;
+
+    constexpr uint32_t num_channel_y = payload_t::num_channel_y;
+    constexpr uint32_t store_elems = num_channel_y * tile_desc::block_size_x;
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y / tile_desc::block_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::block_size_y;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<tile_desc::block_elems, 1>(
+                    (i * tile_desc::num_block_x + j) * tile_desc::block_elems);
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < tile_desc::block_size_y;
+                    sub_block_y += num_channel_y) {
+                uint32_t address_offset = offset_x * sizeof(dtype)
+                        + (sub_block_y + offset_y) * payload.pitch_in_bytes;
+                xetla_store_local<store_dtype>(payload.address + address_offset,
+                        reg_sub.xetla_select<store_elems, 1>(
+                                       sub_block_y * tile_desc::block_size_x)
+                                .xetla_format<store_dtype>());
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_desc::tile_size_y % tile_desc::block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_desc::block_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_desc::tile_size_x;
+        constexpr uint32_t remain_block_elems
+                = remained_size_y * tile_desc::block_size_x;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < remained_size_y;
+                    sub_block_y += num_channel_y) {
+                uint32_t address_offset = offset_x * sizeof(dtype)
+                        + (sub_block_y + offset_y) * payload.pitch_in_bytes;
+                xetla_store_local<store_dtype>(payload.address + address_offset,
+                        reg_sub.xetla_select<store_elems, 1>(
+                                       sub_block_y * tile_desc::block_size_x)
+                                .xetla_format<store_dtype>());
+            }
+        }
+    }
+}
+
+/// @brief Is the data store func from register file to local shared memory,
+/// where the data in register is vnni packed and col major. And we always assume
+/// the dst memory layout is row major.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t>
+__XETLA_API typename std::enable_if_t<detail::check_store_type<tile_t,
+        payload_t>::is_local_scatter_vnni_col_xe>
+tile_store(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using store_dtype = typename payload_t::store_dtype;
+
+    constexpr uint32_t vnni_scale_factor = payload_t::vnni_scale_factor;
+    constexpr uint32_t num_vector_size = payload_t::num_vector_size;
+    constexpr uint32_t store_elems = payload_t::store_elems;
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y / tile_desc::block_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::block_size_y;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<tile_desc::block_elems, 1>(
+                    (i * tile_desc::num_block_x + j) * tile_desc::block_elems);
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < tile_desc::block_size_y;
+                    sub_block_y += num_vector_size * vnni_scale_factor) {
+                uint32_t address_offset = payload.base_address
+                        + offset_x * payload.pitch_in_bytes
+                        + (sub_block_y + offset_y) * sizeof(dtype);
+                xetla_store_local<store_dtype, num_vector_size>(
+                        payload.channel_address + address_offset,
+                        reg_sub.xetla_select<store_elems, 1>(
+                                       sub_block_y * tile_desc::block_size_x)
+                                .xetla_format<store_dtype>());
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_desc::tile_size_y % tile_desc::block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_desc::tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_desc::tile_size_x;
+        constexpr uint32_t remain_block_elems
+                = remained_size_y * tile_desc::block_size_x;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+#pragma unroll
+            for (int sub_block_y = 0; sub_block_y < remained_size_y;
+                    sub_block_y += num_vector_size * vnni_scale_factor) {
+                uint32_t address_offset = payload.base_address
+                        + offset_x * payload.pitch_in_bytes
+                        + (sub_block_y + offset_y) * sizeof(dtype);
+                xetla_store_local<store_dtype, num_vector_size>(
+                        payload.channel_address + address_offset,
+                        reg_sub.xetla_select<store_elems, 1>(
+                                       sub_block_y * tile_desc::block_size_x)
+                                .xetla_format<store_dtype>());
+            }
+        }
+    }
+}
+
+/// @brief Is the data store func from register file to shared local memory,
+/// where supports memory surface 1d or 2d scenario, and we always assume dst memory
+/// layout is row major.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_local_block_1d_xe
+        && tile_t::block_size_y != 1>
+tile_store(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename tile_t::tile_desc;
+    using store_dtype = typename payload_t::mem_dtype;
+    using check_store = typename subgroup::check_store<gpu_arch::Xe, dtype,
+            store_dtype>::local_1d;
+
+    constexpr uint32_t vector_size
+            = payload_t::bytes_per_row / sizeof(store_dtype);
+
+#pragma unroll
+    for (int i = 0; i < tile_desc::tile_size_y / tile_desc::block_size_y; i++) {
+        uint32_t offset_y = i * tile_desc::block_size_y;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<tile_desc::block_elems, 1>(
+                    (i * tile_desc::num_block_x + j) * tile_desc::block_elems);
+            auto reg_sub_2d = reg_sub.xetla_format<dtype,
+                    tile_desc::block_size_y, tile_desc::block_size_x>();
+            uint32_t address_offset = offset_x * sizeof(dtype)
+                    + offset_y * payload.pitch_in_bytes;
+#pragma unroll
+            for (int row_i = 0; row_i < tile_desc::block_size_y; row_i++) {
+                xetla_store_local<store_dtype, vector_size>(payload.base_address
+                                + payload.address + address_offset
+                                + row_i * payload.pitch_in_bytes,
+                        reg_sub_2d.row(row_i).xetla_format<store_dtype>());
+            }
+        }
+    }
+    // process the tail
+    if constexpr ((tile_desc::tile_size_y % tile_desc::block_size_y) != 0) {
+        constexpr uint32_t remained_size_y = tile_desc::remained_size_y;
+        constexpr uint32_t offset_y = tile_desc::tile_size_y - remained_size_y;
+        constexpr uint32_t processed_elems = offset_y * tile_desc::tile_size_x;
+        constexpr uint32_t remain_block_elems
+                = remained_size_y * tile_desc::block_size_x;
+#pragma unroll
+        for (int j = 0; j < tile_desc::num_block_x; j++) {
+            uint32_t offset_x = j * tile_desc::block_size_x;
+            auto reg_sub = tile.reg.xetla_select<remain_block_elems, 1>(
+                    processed_elems + j * remain_block_elems);
+            auto reg_sub_2d = reg_sub.xetla_format<dtype, remained_size_y,
+                    tile_desc::block_size_x>();
+            uint32_t address_offset = offset_x * sizeof(dtype)
+                    + offset_y * payload.pitch_in_bytes;
+#pragma unroll
+            for (int row_i = 0; row_i < remained_size_y; row_i++) {
+                xetla_store_local<store_dtype, vector_size>(payload.base_address
+                                + payload.address + address_offset
+                                + row_i * payload.pitch_in_bytes,
+                        reg_sub_2d.row(row_i).xetla_format<store_dtype>());
+            }
+        }
+    }
+}
+
+/// @brief Is the func storing data from register file to shared local memory,
+/// the data in registers will be stored to SLM in 1d mode, and we always assume dst memory
+/// layout is row major.
+/// @tparam tile_t Is the tile_t struct contains registers
+/// These registers will be the source of store operation.
+/// @tparam payload_t Is the mem_payload_t struct describing the memory info
+/// payload indicates the destination of store operation
+/// @tparam L1 Is the cache hint for L1 cache.
+/// @tparam L2 Is the cache hint for L2 cache.
+/// @param tile Is the tile object with type tile_t, contains the data to be stored.
+/// @param payload Is the payload object with type payload_t. Contains all the information for stores.
+template <cache_hint L1 = cache_hint::write_back,
+        cache_hint L2 = cache_hint::write_back, typename tile_t,
+        typename payload_t>
+__XETLA_API typename std::enable_if_t<
+        detail::check_store_type<tile_t, payload_t>::is_local_block_1d_xe
+        && tile_t::tile_size_y == 1 && tile_t::block_size_y == 1>
+tile_store(tile_t &tile, payload_t &payload) {
+    using dtype = typename tile_t::dtype;
+    using tile_desc = typename payload_t::tile_desc;
+    using store_dtype = typename payload_t::mem_dtype;
+    using check_store = typename subgroup::check_store<gpu_arch::Xe, dtype,
+            store_dtype>::local_1d;
+
+    constexpr uint32_t scale_factor = payload_t::scale_factor;
+    constexpr uint32_t store_len = tile_desc::tile_size_x / scale_factor;
+    if constexpr (store_len >= 64) {
+#pragma unroll
+        for (int j = 0; j < store_len / 64; j++) {
+            uint32_t offset_x = j * 64 * scale_factor;
+            auto reg_sub
+                    = tile.reg.xetla_select<64 * scale_factor, 1>(offset_x);
+            uint32_t address_offset = offset_x * sizeof(dtype);
+            xetla_store_local<store_dtype, 64>(
+                    payload.base_address + payload.address + address_offset,
+                    reg_sub.xetla_format<store_dtype>());
+        }
+    }
+    uint32_t tail_offset = store_len / 64 * 64 * scale_factor;
+    detail::process_1d_tail<store_len % 64, 32, detail::process_flag::store, L1,
+            L2>(tile, payload, tail_offset, tail_offset * sizeof(dtype));
+}
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/tile_op_functor.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/tile_op_functor.hpp
new file mode 100644
index 00000000000000..4b5445a6c924c5
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/impl/tile_op_functor.hpp
@@ -0,0 +1,1506 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/common.hpp"
+#include "subgroup/tile/impl/load_xe.hpp"
+#include "subgroup/tile/impl/payload_xe.hpp"
+#include "subgroup/tile/impl/prefetch_xe.hpp"
+#include "subgroup/tile/impl/reduction.hpp"
+#include "subgroup/tile/impl/store_xe.hpp"
+
+namespace gpu::xetla::subgroup {
+
+/// @brief Is none op functor, for placeholder purpose.
+/// Used in epilogue::tile_op or chained_tile_op.
+struct none_op_t {
+    struct arguments_t {};
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {}
+    //none_op_t functor for dequant_op
+    template <typename mat_out_t, typename mat_in_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(mat_out_t &mat_out,
+            mat_in_t &mat_in, const coord_t &coord, const arguments_t &args) {
+        mat_out = mat_in;
+    }
+};
+
+/// @brief Is the element-wise relu op functor.
+/// Get the relu input from matAcc, update the relu output in place,
+/// Used in epilogue::tile_op or chained_tile_op.
+struct relu_op_t {
+    struct arguments_t {};
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        xetla_mask<matAcc_t::tile_elems> mask = matAcc.reg < 0;
+        matAcc.reg.xetla_merge(0, mask);
+    }
+};
+
+/// @brief Is the element-wise relu op functor with relu mask collection.
+/// Get the relu input from matAcc, update the relu output in place, store the mask in memory.
+/// The mask has the same layout as the relu output.
+/// Used in epilogue::tile_op or chained_tile_op.
+template <typename dtype_mask, gpu_arch arch_tag, class enable = void>
+struct relu_pack_mask_op_t {};
+
+template <typename dtype_mask_, gpu_arch arch_tag>
+struct relu_pack_mask_op_t<dtype_mask_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_mask = dtype_mask_;
+    using mem_desc_mask_t
+            = mem_desc_t<dtype_mask, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_mask_t::shape_t;
+    using coord_t = typename mem_desc_mask_t::coord_t;
+    using base_t = typename mem_desc_mask_t::base_t;
+
+    static constexpr uint32_t simd_len = 16;
+    static constexpr uint32_t out_elems_per_step = 4 * simd_len;
+
+    struct arguments_t {
+        shape_t mask_shape;
+        base_t mask_base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t mask_base_, shape_t mask_shape_)
+            : mask_base(mask_base_), mask_shape(mask_shape_) {}
+    };
+
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using mask_out_tile_desc_t = tile_desc_t<tile_size_x, tile_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mask_out_tile_t = tile_t<dtype_mask, mask_out_tile_desc_t>;
+        using mask_out_payload_t = mem_payload_t<mem_desc_mask_t,
+                mask_out_tile_desc_t,
+                msg_type_v<mask_out_tile_desc_t, mem_desc_mask_t::space>,
+                arch_tag>;
+
+        mem_desc_mask_t mem_desc_mask(args.mask_base, args.mask_shape, coord);
+        mask_out_tile_t mask_out;
+        mask_out_payload_t mask_out_payload(mem_desc_mask);
+
+        if constexpr (tile_elems / out_elems_per_step != 0) {
+#pragma unroll
+            for (int i = 0; i < tile_elems / out_elems_per_step; ++i) {
+                auto out_sub = matAcc.reg.xetla_select<out_elems_per_step, 1>(
+                        i * out_elems_per_step);
+                auto mask_sub
+                        = mask_out.reg.xetla_select<out_elems_per_step, 1>(
+                                i * out_elems_per_step);
+                xetla_mask<out_elems_per_step> mask_flag = out_sub < 0;
+                out_sub.xetla_merge(0, mask_flag);
+                mask_sub.xetla_merge(1, 0, mask_flag);
+            }
+        }
+
+        if constexpr (tile_elems % out_elems_per_step != 0) {
+            constexpr uint32_t remain_len = tile_elems % out_elems_per_step;
+            constexpr uint32_t remain_start
+                    = tile_elems / out_elems_per_step * out_elems_per_step;
+            auto out_sub = matAcc.reg.xetla_select<remain_len, 1>(remain_start);
+            auto mask_sub
+                    = mask_out.reg.xetla_select<remain_len, 1>(remain_start);
+            xetla_mask<remain_len> mask_flag = out_sub < 0;
+            out_sub.xetla_merge(0, mask_flag.xetla_select<remain_len, 1>(0));
+            mask_sub.xetla_merge(
+                    1, 0, mask_flag.xetla_select<remain_len, 1>(0));
+        }
+
+        tile_store<cache_hint::streaming>(mask_out, mask_out_payload);
+    }
+};
+
+/// @brief Is the relu-mask-based element-wise relu op functor.
+/// Get the relu input from matAcc, update the relu output in place using the mask stored in memory.
+/// The mask has the same layout as the relu output.
+/// Used in epilogue::tile_op or chained_tile_op.
+template <typename dtype_mask, gpu_arch arch_tag, class enable = void>
+struct relu_unpack_mask_op_t {};
+
+template <typename dtype_mask_, gpu_arch arch_tag>
+struct relu_unpack_mask_op_t<dtype_mask_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_mask = dtype_mask_;
+    using mem_desc_mask_t
+            = mem_desc_t<dtype_mask, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_mask_t::shape_t;
+    using coord_t = typename mem_desc_mask_t::coord_t;
+    using base_t = typename mem_desc_mask_t::base_t;
+
+    static constexpr uint32_t simd_len = 16;
+    static constexpr uint32_t out_elems_per_step = 4 * simd_len;
+
+    struct arguments_t {
+        shape_t mask_shape;
+        base_t mask_base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t mask_base_, shape_t mask_shape_)
+            : mask_base(mask_base_), mask_shape(mask_shape_) {}
+    };
+
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using mask_in_tile_desc_t = tile_desc_t<tile_size_x, tile_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mask_in_tile_t = tile_t<dtype_mask, mask_in_tile_desc_t>;
+        using mask_in_payload_t
+                = mem_payload_t<mem_desc_mask_t, mask_in_tile_desc_t,
+                        msg_type_v<mask_in_tile_desc_t, mem_desc_mask_t::space>,
+                        arch_tag>;
+
+        mem_desc_mask_t mem_desc_mask(args.mask_base, args.mask_shape, coord);
+        mask_in_tile_t mask_in;
+        mask_in_payload_t mask_in_payload(mem_desc_mask);
+
+        tile_load<cache_hint::cached, cache_hint::cached>(
+                mask_in, mask_in_payload);
+
+        if constexpr (tile_elems / out_elems_per_step != 0) {
+#pragma unroll
+            for (int i = 0; i < tile_elems / out_elems_per_step; ++i) {
+                xetla_mask<out_elems_per_step> mask_flag
+                        = mask_in.reg.xetla_select<out_elems_per_step, 1>(
+                                  i * out_elems_per_step)
+                        > 0;
+                auto dst_reg = matAcc.reg.xetla_select<out_elems_per_step, 1>(
+                        i * out_elems_per_step);
+                dst_reg.xetla_merge(0, mask_flag);
+            }
+        }
+
+        if constexpr (tile_elems % out_elems_per_step != 0) {
+            constexpr uint32_t remain_len = tile_elems % out_elems_per_step;
+            constexpr uint32_t remain_start
+                    = tile_elems / out_elems_per_step * out_elems_per_step;
+            xetla_mask<remain_len> mask_flag
+                    = mask_in.reg.xetla_select<remain_len, 1>(remain_start) > 0;
+            auto dst_reg = matAcc.reg.xetla_select<remain_len, 1>(remain_start);
+            dst_reg.xetla_merge(0, mask_flag);
+        }
+    }
+};
+
+/// @brief Is the element-wise tanh op functor.
+/// Get the tanh input from matAcc, update the the tanh output in place,
+/// Used in epilogue::tile_op or chained_tile_op.
+struct tanh_op_t {
+    struct arguments_t {};
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        constexpr int elems = matAcc_t::tile_desc::block_elems;
+        constexpr int rounds = matAcc_t::tile_desc::tile_elems / elems;
+        using dtype = typename matAcc_t::dtype;
+#pragma unroll
+        for (int i = 0; i < rounds; ++i) {
+            auto sub_vec = matAcc.reg.xetla_select<elems, 1>(elems * i);
+            sub_vec = xetla_tanh<dtype, elems>(sub_vec);
+        }
+        constexpr int remaining_elems = matAcc_t::tile_desc::tile_elems % elems;
+        if constexpr (remaining_elems != 0) {
+            auto sub_vec = matAcc.reg.xetla_select<remaining_elems, 1>(
+                    elems * (matAcc_t::tile_elems / elems));
+            sub_vec = xetla_tanh<dtype, remaining_elems>(sub_vec);
+        }
+    }
+};
+
+/// @brief Is the element-wise sigmoid op functor.
+/// Get the sigmoid input from matAcc, update the the sigmoid output in place,
+/// Used in epilogue::tile_op or chained_tile_op.
+struct sigmoid_op_t {
+    struct arguments_t {};
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        constexpr int elems = matAcc_t::tile_desc::block_elems;
+        constexpr int rounds = matAcc_t::tile_desc::tile_elems / elems;
+#pragma unroll
+        for (int i = 0; i < rounds; ++i) {
+            auto sub_vec = matAcc.reg.xetla_select<elems, 1>(elems * i);
+            sub_vec = xetla_sigmoid<typename matAcc_t::dtype, elems>(sub_vec);
+        }
+        constexpr int remaining_elems = matAcc_t::tile_desc::tile_elems % elems;
+        if constexpr (remaining_elems != 0) {
+            auto sub_vec = matAcc.reg.xetla_select<remaining_elems, 1>(
+                    elems * (matAcc_t::tile_elems / elems));
+            sub_vec = xetla_sigmoid<typename matAcc_t::dtype, remaining_elems>(
+                    sub_vec);
+        }
+    }
+};
+
+/// @brief Is the element-wise silu op functor.
+/// Get the silu input from matAcc, update the the silu output in place,
+/// Used in epilogue::tile_op or chained_tile_op.
+struct silu_op_t {
+    struct arguments_t {};
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        constexpr int elems = matAcc_t::tile_desc::block_elems;
+        constexpr int rounds = matAcc_t::tile_desc::tile_elems / elems;
+#pragma unroll
+        for (int i = 0; i < rounds; ++i) {
+            auto sub_vec = matAcc.reg.xetla_select<elems, 1>(elems * i);
+            xetla_vector<typename matAcc_t::dtype, elems> sigmoid_value
+                    = xetla_sigmoid<typename matAcc_t::dtype, elems>(sub_vec);
+            sub_vec = sub_vec * sigmoid_value;
+        }
+        constexpr int remaining_elems = matAcc_t::tile_desc::tile_elems % elems;
+        if constexpr (remaining_elems != 0) {
+            auto sub_vec = matAcc.reg.xetla_select<remaining_elems, 1>(
+                    elems * (matAcc_t::tile_elems / elems));
+            xetla_vector<typename matAcc_t::dtype, remaining_elems>
+                    sigmoid_value
+                    = xetla_sigmoid<typename matAcc_t::dtype, remaining_elems>(
+                            sub_vec);
+            sub_vec = sub_vec * sigmoid_value;
+        }
+    }
+};
+
+/// @brief Is the element-wise gelu inference forward op functor.
+/// Get the gelu input from matAcc, update the the gelu output in place,
+/// Used in epilogue::tile_op or chained_tile_op.
+struct gelu_fwd_op_t {
+    struct arguments_t {};
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype = typename matAcc_t::dtype;
+        constexpr dtype C0 = 0.044715f;
+        constexpr dtype sqrt_two_over_pi = 0.79788458347320556640625f;
+        // total flag register
+        constexpr int elems = 8 * 16;
+        constexpr int rounds = matAcc_t::tile_elems / elems;
+        if constexpr (rounds != 0) {
+#pragma unroll
+            for (int i = 0; i < rounds; ++i) {
+                auto sub_vec = matAcc.reg.xetla_select<elems, 1>(elems * i);
+                xetla_vector<dtype, elems> sub_vec_x = (sqrt_two_over_pi
+                        * sub_vec * (1.f + C0 * sub_vec * sub_vec));
+                xetla_vector<dtype, elems> tanh_value
+                        = xetla_tanh<dtype, elems>(sub_vec_x);
+                sub_vec = 0.5f * sub_vec * (1.f + tanh_value);
+            }
+        }
+
+        constexpr int remaining_elems = matAcc_t::tile_elems % elems;
+        if constexpr (remaining_elems != 0) {
+            auto sub_vec = matAcc.reg.xetla_select<remaining_elems, 1>(
+                    elems * (matAcc_t::tile_elems / elems));
+            xetla_vector<dtype, remaining_elems> sub_vec_x = (sqrt_two_over_pi
+                    * sub_vec * (1.f + C0 * sub_vec * sub_vec));
+            xetla_vector<dtype, remaining_elems> tanh_value
+                    = xetla_tanh<dtype, remaining_elems>(sub_vec_x);
+            sub_vec = 0.5f * sub_vec * (1.f + tanh_value);
+        }
+    }
+};
+
+/// @brief Is the element-wise gelu training forward op functor.
+/// Get the gelu input from matAcc, update the the gelu output in place,
+/// and dump the intermediate buffer_w to memory for backward purpose.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_out Is the data type of the intermediate buffer_w.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_out, gpu_arch arch_tag, class enable = void>
+struct gelu_fwd_w_op_t {};
+/// @brief Is the element-wise gelu training forward op functor, specialized for Xe architecture.
+template <typename dtype_out_, gpu_arch arch_tag>
+struct gelu_fwd_w_op_t<dtype_out_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_out = dtype_out_;
+    using mem_desc_w_t
+            = mem_desc_t<dtype_out, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_w_t::shape_t;
+    using coord_t = typename mem_desc_w_t::coord_t;
+    using base_t = typename mem_desc_w_t::base_t;
+
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t base_, shape_t shape_)
+            : base(base_), shape(shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+
+        mem_desc_w_t mem_desc_w(args.base, args.shape, coord);
+        using bwd_w_tile_desc_t = tile_desc_t<block_size_x, block_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using bwd_w_tile_t = tile_t<dtype_out, bwd_w_tile_desc_t>;
+        using bwd_w_payload_t = mem_payload_t<mem_desc_w_t, bwd_w_tile_desc_t,
+                msg_type::block_2d, arch_tag>;
+        bwd_w_tile_t bwd_w;
+        bwd_w_payload_t bwd_w_payload(mem_desc_w);
+        // start compute
+        constexpr dtype_acc c0 = 0.044715f;
+        constexpr dtype_acc d0 = 0.134145f;
+        constexpr dtype_acc sqrt_two_over_pi = 0.79788458347320556640625f;
+        constexpr uint32_t block_elems = matAcc_t::block_elems;
+        constexpr uint32_t num_block_x = matAcc_t::num_block_x;
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; ++i) {
+#pragma unroll
+            for (int j = 0; j < num_block_x; ++j) {
+                auto x = matAcc.reg.xetla_select<block_elems, 1>(
+                        block_elems * (i * num_block_x + j));
+                xetla_vector<dtype_acc, block_elems> z
+                        = xetla_tanh<dtype_acc, block_elems>(
+                                sqrt_two_over_pi * (x + c0 * x * x * x));
+                xetla_vector<dtype_acc, block_elems> w = (0.5f * (1.f + z)
+                        + 0.5f * x * (1.f - z * z)
+                                * (sqrt_two_over_pi * (1.f + d0 * x * x)));
+                x = 0.5f * x * (1.f + z);
+                bwd_w.reg = xetla_cvt<dtype_out, dtype_acc, block_elems>(w);
+                tile_store<cache_hint::uncached>(bwd_w, bwd_w_payload);
+                bwd_w_payload.template update_tdesc<tdesc_update_dir::x_dir>(
+                        block_size_x);
+            }
+            bwd_w_payload.template update_tdesc<tdesc_update_dir::x_dir>(
+                    -1 * tile_size_x);
+            bwd_w_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                    block_size_y);
+        }
+        if constexpr (tile_size_y % block_size_y != 0) {
+            constexpr uint32_t remain_size_y = tile_size_y % block_size_y;
+            constexpr uint32_t remain_y_start
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr uint32_t remain_elems_start
+                    = remain_y_start * tile_size_x;
+            constexpr uint32_t remain_block_elems
+                    = remain_size_y * block_size_x;
+
+            using remain_bwd_w_tile_desc_t
+                    = tile_desc_t<block_size_x, remain_size_y, block_size_x,
+                            remain_size_y, reg_layout::tiled>;
+            using remain_bwd_w_tile_t
+                    = tile_t<dtype_out, remain_bwd_w_tile_desc_t>;
+            using remain_bwd_w_payload_t = mem_payload_t<mem_desc_w_t,
+                    remain_bwd_w_tile_desc_t, msg_type::block_2d, arch_tag>;
+
+            mem_desc_w.update_coord_y(remain_y_start);
+            remain_bwd_w_payload_t remain_bwd_w_payload(mem_desc_w);
+            remain_bwd_w_tile_t remain_bwd_w;
+#pragma unroll
+            for (int j = 0; j < num_block_x; ++j) {
+                auto x = matAcc.reg.xetla_select<remain_block_elems, 1>(
+                        remain_elems_start + remain_block_elems * j);
+                xetla_vector<dtype_acc, remain_block_elems> z
+                        = xetla_tanh<dtype_acc, remain_block_elems>(
+                                sqrt_two_over_pi * (x + c0 * x * x * x));
+                xetla_vector<dtype_acc, remain_block_elems> w = (0.5f
+                                * (1.f + z)
+                        + 0.5f * x * (1.f - z * z)
+                                * (sqrt_two_over_pi * (1.f + d0 * x * x)));
+                x = 0.5f * x * (1.f + z);
+                remain_bwd_w.reg
+                        = xetla_cvt<dtype_out, dtype_acc, remain_block_elems>(
+                                w);
+                tile_store<cache_hint::uncached>(
+                        remain_bwd_w, remain_bwd_w_payload);
+                remain_bwd_w_payload
+                        .template update_tdesc<tdesc_update_dir::x_dir>(
+                                block_size_x);
+            }
+        }
+    }
+};
+
+/// @brief Is the element-wise gelu backward op functor.
+/// Load the gelu forward input buffer from memory and get the gradient data from matAcc, update the output in place.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_in Is the data type of the gelu forward input buffer.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_in, gpu_arch arch_tag, class enable = void>
+struct gelu_bwd_op_t {};
+/// @brief Is the element-wise gelu backward op functor, specialized for Xe architecture.
+template <typename dtype_in_, gpu_arch arch_tag>
+struct gelu_bwd_op_t<dtype_in_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_in = dtype_in_;
+    using mem_desc_x_t
+            = mem_desc_t<dtype_in, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_x_t::shape_t;
+    using coord_t = typename mem_desc_x_t::coord_t;
+    using base_t = typename mem_desc_x_t::base_t;
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t base_, shape_t shape_)
+            : base(base_), shape(shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+
+        using bwd_x_tile_desc_t = tile_desc_t<tile_size_x, tile_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using bwd_x_tile_t = tile_t<dtype_in, bwd_x_tile_desc_t>;
+        using bwd_x_payload_t = mem_payload_t<mem_desc_x_t, bwd_x_tile_desc_t,
+                msg_type::block_2d, arch_tag>;
+        bwd_x_tile_t bwd_x;
+        // init tdesc
+        mem_desc_x_t mem_desc_x(args.base, args.shape, coord);
+        bwd_x_payload_t bwd_x_payload(mem_desc_x);
+        tile_load<cache_hint::cached, cache_hint::cached>(bwd_x, bwd_x_payload);
+        // start compute
+        constexpr dtype_acc c0 = 0.044715f;
+        constexpr dtype_acc d0 = 0.134145f;
+        constexpr dtype_acc sqrt_two_over_pi = 0.79788458347320556640625f;
+        constexpr uint32_t block_elems = matAcc_t::block_elems;
+        constexpr uint32_t num_block_x = matAcc_t::num_block_x;
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; ++i) {
+#pragma unroll
+            for (int j = 0; j < num_block_x; ++j) {
+                auto x_in = bwd_x.reg.xetla_select<block_elems, 1>(
+                        block_elems * (i * num_block_x + j));
+                auto x = xetla_cvt<dtype_acc, dtype_in, block_elems>(x_in);
+                auto dy = matAcc.reg.xetla_select<block_elems, 1>(
+                        block_elems * (i * num_block_x + j));
+                xetla_vector<dtype_acc, block_elems> z
+                        = xetla_tanh<dtype_acc, block_elems>(
+                                sqrt_two_over_pi * (x + c0 * x * x * x));
+                xetla_vector<dtype_acc, block_elems> w = (0.5f * (1.f + z)
+                        + 0.5f * x * (1.f - z * z)
+                                * (sqrt_two_over_pi * (1.f + d0 * x * x)));
+                dy = w * dy;
+            }
+        }
+        if constexpr (tile_size_y % block_size_y != 0) {
+            constexpr uint32_t remain_size_y = tile_size_y % block_size_y;
+            constexpr uint32_t remain_y_start
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr uint32_t remain_elems_start
+                    = remain_y_start * tile_size_x;
+            constexpr uint32_t remain_block_elems
+                    = remain_size_y * block_size_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; ++j) {
+                auto x_in = bwd_x.reg.xetla_select<remain_block_elems, 1>(
+                        remain_elems_start + remain_block_elems * j);
+                auto x = xetla_cvt<dtype_acc, dtype_in, remain_block_elems>(
+                        x_in);
+                auto dy = matAcc.reg.xetla_select<remain_block_elems, 1>(
+                        remain_elems_start + remain_block_elems * j);
+                xetla_vector<dtype_acc, remain_block_elems> z
+                        = xetla_tanh<dtype_acc, remain_block_elems>(
+                                sqrt_two_over_pi * (x + c0 * x * x * x));
+                xetla_vector<dtype_acc, remain_block_elems> w = (0.5f
+                                * (1.f + z)
+                        + 0.5f * x * (1.f - z * z)
+                                * (sqrt_two_over_pi * (1.f + d0 * x * x)));
+                dy = w * dy;
+            }
+        }
+    }
+};
+
+/// @brief Is the bias_add op functor.
+/// Load the 1d bias data from memory and get the input from matAcc, update the output in place.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_bias Is the data type of bias buffer.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_bias, gpu_arch arch_tag, class enable = void>
+struct bias_add_op_t {};
+/// @brief Is the bias_add op functor, specialized for Xe architecture.
+template <typename dtype_bias_, gpu_arch arch_tag>
+struct bias_add_op_t<dtype_bias_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_bias = dtype_bias_;
+    using mem_desc_bias_t
+            = mem_desc_t<dtype_bias, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_bias_t::shape_t;
+    using coord_t = typename mem_desc_bias_t::coord_t;
+    using base_t = typename mem_desc_bias_t::base_t;
+
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t base_, shape_t shape_)
+            : base(base_), shape(shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using bias_tile_desc_t = tile_desc_t<tile_size_x, 1, block_size_x, 1,
+                reg_layout::tiled>;
+        using bias_t = tile_t<dtype_bias, bias_tile_desc_t>;
+        using bias_payload_t = mem_payload_t<mem_desc_bias_t, bias_tile_desc_t,
+                msg_type_v<bias_tile_desc_t, mem_desc_bias_t::space>, arch_tag>;
+        coord_t bias_coord(coord.x, 0);
+        mem_desc_bias_t mem_desc_bias(args.base, args.shape, bias_coord);
+        bias_t bias;
+        bias_payload_t bias_payload(mem_desc_bias);
+        tile_load<cache_hint::cached, cache_hint::cached>(bias, bias_payload);
+
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto dst_reg
+                        = matAcc.reg
+                                  .xetla_select<block_elems, 1>(
+                                          (i * num_block_x + j) * block_elems)
+                                  .xetla_format<dtype_acc, block_size_y,
+                                          block_size_x>();
+#pragma unroll
+                for (int row_i = 0; row_i < block_size_y; row_i++) {
+                    auto src_reg = bias.reg.xetla_select<block_size_x, 1>(
+                            j * block_size_x);
+                    dst_reg.row(row_i)
+                            = xetla_cvt<dtype_acc, dtype_bias, block_size_x>(
+                                      src_reg)
+                            + dst_reg.row(row_i);
+                }
+            }
+        }
+        // process the tail
+        if constexpr ((tile_size_y % block_size_y) != 0) {
+            constexpr uint32_t tail_start_y
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr int32_t tail_size_y = tile_size_y % block_size_y;
+            constexpr int32_t tail_block_elems = tail_size_y * block_size_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto dst_reg = matAcc.reg
+                                       .xetla_select<tail_block_elems, 1>(
+                                               tail_start_y * tile_size_x
+                                               + j * tail_block_elems)
+                                       .xetla_format<dtype_acc, tail_size_y,
+                                               block_size_x>();
+#pragma unroll
+                for (int row_i = 0; row_i < tail_size_y; row_i++) {
+                    auto src_reg = bias.reg.xetla_select<block_size_x, 1>(
+                            j * block_size_x);
+                    dst_reg.row(row_i)
+                            = xetla_cvt<dtype_acc, dtype_bias, block_size_x>(
+                                      src_reg)
+                            + dst_reg.row(row_i);
+                }
+            }
+        }
+    }
+};
+
+/// @brief Is the element-wise along-height summing reduction op functor.
+/// Get the input from matAcc, reduce it along height by summing, add the computed output to data in memory.
+/// Used in epilogue::tile_op or chained_tile_op.
+template <typename dtype_sum, gpu_arch arch_tag, class enable = void>
+struct height_reduce_outer_sum_op_t {};
+
+template <typename dtype_sum_, gpu_arch arch_tag>
+struct height_reduce_outer_sum_op_t<dtype_sum_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_sum = dtype_sum_;
+    using base_t = typename mem_desc_t<dtype_sum, mem_layout::row_major,
+            mem_space::global>::base_t;
+
+    static constexpr uint32_t simd_len = 16;
+
+    struct arguments_t {
+        base_t sum_base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t sum_base_) : sum_base(sum_base_) {}
+    };
+    template <typename matAcc_t, typename coord_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static_assert(std::is_same<dtype_sum, dtype_acc>::value,
+                "dtype_sum shall match matAcc_t::dtype");
+
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+
+        xetla_vector<dtype_sum, tile_size_x> row_reg
+                = tile_reduce<reduce_op::sum, dtype_sum, dtype_acc, 0>(matAcc);
+        xetla_vector<uint32_t, simd_len> offsets
+                = xetla_vector_gen<uint32_t, simd_len>(coord.x, 1);
+        xetla_mask<simd_len> pred(1);
+
+#pragma unroll
+        for (uint32_t pos_x = 0; pos_x < tile_size_x; pos_x += simd_len) {
+            xetla_atomic_global<is_integral<dtype_sum>::value ? atomic_op::iadd
+                                                              : atomic_op::fadd,
+                    dtype_sum, simd_len, data_size::default_size,
+                    cache_hint::uncached, cache_hint::write_back>(
+                    args.sum_base.base, (offsets + pos_x) * sizeof(dtype_sum),
+                    row_reg.xetla_select<simd_len, 1>(pos_x), pred);
+        }
+    }
+};
+
+/// @brief Is MatAcc * vector scale + vector offset.
+/// @tparam scale_dtype Is the scale data type.
+/// @tparam offset_dtype Is the offset data type.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename scale_dtype, typename offset_dtype, gpu_arch arch_tag,
+        class enable = void>
+struct scale_v_offset_v_op_t {};
+/// @brief Is the scale_v_offset_v op functor, specialized for Xe architecture.
+template <typename scale_dtype_, typename offset_dtype_, gpu_arch arch_tag>
+struct scale_v_offset_v_op_t<scale_dtype_, offset_dtype_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using scale_dtype = scale_dtype_;
+    using offset_dtype = offset_dtype_;
+
+    using scale_mem_desc_t
+            = mem_desc_t<scale_dtype, mem_layout::row_major, mem_space::global>;
+    using offset_mem_desc_t = mem_desc_t<offset_dtype, mem_layout::row_major,
+            mem_space::global>;
+
+    using scale_shape_t = typename scale_mem_desc_t::shape_t;
+    using scale_base_t = typename scale_mem_desc_t::base_t;
+
+    using offset_shape_t = typename offset_mem_desc_t::shape_t;
+    using offset_base_t = typename offset_mem_desc_t::base_t;
+
+    using coord_t = typename scale_mem_desc_t::coord_t;
+
+    struct arguments_t {
+        scale_base_t scale_base;
+        scale_shape_t scale_shape;
+        offset_base_t offset_base;
+        offset_shape_t offset_shape;
+        inline arguments_t() = default;
+        inline arguments_t(scale_base_t scale_base_, scale_shape_t scale_shape_,
+                offset_base_t offset_base_, offset_shape_t offset_shape_)
+            : scale_base(scale_base_)
+            , scale_shape(scale_shape_)
+            , offset_base(offset_base_)
+            , offset_shape(offset_shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using scale_tile_desc_t = tile_desc_t<tile_size_x, 1, block_size_x, 1,
+                reg_layout::tiled>;
+        using scale_tile_t = tile_t<scale_dtype, scale_tile_desc_t>;
+        using scale_payload_t
+                = mem_payload_t<scale_mem_desc_t, scale_tile_desc_t,
+                        msg_type_v<scale_tile_desc_t, scale_mem_desc_t::space>,
+                        arch_tag>;
+        coord_t scale_coord(coord.x, 0);
+        scale_mem_desc_t scale_mem_desc(
+                args.scale_base, args.scale_shape, scale_coord);
+        scale_tile_t scale_tile;
+        scale_payload_t scale_payload(scale_mem_desc);
+        tile_load<cache_hint::cached, cache_hint::cached>(
+                scale_tile, scale_payload);
+
+        using offset_tile_desc_t = tile_desc_t<tile_size_x, 1, block_size_x, 1,
+                reg_layout::tiled>;
+        using offset_tile_t = tile_t<offset_dtype, offset_tile_desc_t>;
+        using offset_payload_t = mem_payload_t<offset_mem_desc_t,
+                offset_tile_desc_t,
+                msg_type_v<offset_tile_desc_t, offset_mem_desc_t::space>,
+                arch_tag>;
+        coord_t offset_coord(coord.x, 0);
+        offset_mem_desc_t offset_mem_desc(
+                args.offset_base, args.offset_shape, offset_coord);
+        offset_tile_t offset_tile;
+        offset_payload_t offset_payload(offset_mem_desc);
+        tile_load<cache_hint::cached, cache_hint::cached>(
+                offset_tile, offset_payload);
+
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto acc_reg = matAcc.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_x + j) * block_elems);
+                auto offset_reg = offset_tile.reg.xetla_select<block_size_x, 1>(
+                        j * block_size_x);
+                auto scale_reg = scale_tile.reg.xetla_select<block_size_x, 1>(
+                        j * block_size_x);
+#pragma unroll
+                for (int row_i = 0; row_i < block_size_y; row_i++) {
+                    acc_reg.xetla_select<block_size_x, 1>(row_i * block_size_x)
+                            = scale_reg
+                                    * acc_reg.xetla_select<block_size_x, 1>(
+                                            row_i * block_size_x)
+
+                            + offset_reg;
+                }
+            }
+        }
+        // process the tail
+        if constexpr ((tile_size_y % block_size_y) != 0) {
+            constexpr uint32_t tail_start_y
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr int32_t tail_size_y = tile_size_y % block_size_y;
+            constexpr int32_t tail_block_elems = tail_size_y * block_size_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto acc_reg = matAcc.reg.xetla_select<tail_block_elems, 1>(
+                        tail_start_y * tile_size_x + j * tail_block_elems);
+                auto offset_reg = offset_tile.reg.xetla_select<block_size_x, 1>(
+                        j * block_size_x);
+                auto scale_reg = scale_tile.reg.xetla_select<block_size_x, 1>(
+                        j * block_size_x);
+#pragma unroll
+                for (int row_i = 0; row_i < tail_size_y; row_i++) {
+                    acc_reg.xetla_select<block_size_x, 1>(row_i * block_size_x)
+                            = scale_reg
+                                    * acc_reg.xetla_select<block_size_x, 1>(
+                                            row_i * block_size_x)
+                            + offset_reg;
+                }
+            }
+        }
+    }
+};
+
+/// @brief Is MatAcc * vector scale.
+/// @tparam scale_dtype Is the scale data type.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename scale_dtype, gpu_arch arch_tag, class enable = void>
+struct scale_v_op_t {};
+/// @brief Is the scale_v op functor, specialized for Xe architecture.
+template <typename scale_dtype_, gpu_arch arch_tag>
+struct scale_v_op_t<scale_dtype_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using scale_dtype = scale_dtype_;
+
+    using scale_mem_desc_t
+            = mem_desc_t<scale_dtype, mem_layout::row_major, mem_space::global>;
+
+    using scale_shape_t = typename scale_mem_desc_t::shape_t;
+    using scale_base_t = typename scale_mem_desc_t::base_t;
+    using coord_t = typename scale_mem_desc_t::coord_t;
+
+    struct arguments_t {
+        scale_base_t scale_base;
+        scale_shape_t scale_shape;
+
+        inline arguments_t() = default;
+        inline arguments_t(scale_base_t scale_base_, scale_shape_t scale_shape_)
+            : scale_base(scale_base_), scale_shape(scale_shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using scale_tile_desc_t = tile_desc_t<tile_size_x, 1, block_size_x, 1,
+                reg_layout::tiled>;
+        using scale_tile_t = tile_t<scale_dtype, scale_tile_desc_t>;
+        using scale_payload_t
+                = mem_payload_t<scale_mem_desc_t, scale_tile_desc_t,
+                        msg_type_v<scale_tile_desc_t, scale_mem_desc_t::space>,
+                        arch_tag>;
+        coord_t scale_coord(coord.x, 0);
+        scale_mem_desc_t scale_mem_desc(
+                args.scale_base, args.scale_shape, scale_coord);
+        scale_tile_t scale_tile;
+        scale_payload_t scale_payload(scale_mem_desc);
+        tile_load<cache_hint::cached, cache_hint::cached>(
+                scale_tile, scale_payload);
+
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto acc_reg = matAcc.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_x + j) * block_elems);
+                auto scale_reg = scale_tile.reg.xetla_select<block_size_x, 1>(
+                        j * block_size_x);
+#pragma unroll
+                for (int row_i = 0; row_i < block_size_y; row_i++) {
+                    acc_reg.xetla_select<block_size_x, 1>(row_i * block_size_x)
+                            = scale_reg
+                            * acc_reg.xetla_select<block_size_x, 1>(
+                                    row_i * block_size_x);
+                }
+            }
+        }
+        // process the tail
+        if constexpr ((tile_size_y % block_size_y) != 0) {
+            constexpr uint32_t tail_start_y
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr int32_t tail_size_y = tile_size_y % block_size_y;
+            constexpr int32_t tail_block_elems = tail_size_y * block_size_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto acc_reg = matAcc.reg.xetla_select<tail_block_elems, 1>(
+                        tail_start_y * tile_size_x + j * tail_block_elems);
+                auto scale_reg = scale_tile.reg.xetla_select<block_size_x, 1>(
+                        j * block_size_x);
+#pragma unroll
+                for (int row_i = 0; row_i < tail_size_y; row_i++) {
+                    acc_reg.xetla_select<block_size_x, 1>(row_i * block_size_x)
+                            = scale_reg
+                            * acc_reg.xetla_select<block_size_x, 1>(
+                                    row_i * block_size_x);
+                }
+            }
+        }
+    }
+};
+
+/// @brief Is the element-wise reduce op functor.
+/// Load one buffer from memory and get another from matAcc,
+/// element-wise reduce and update the output in place.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam reduce_kind Is the reduce type, can be sum, prod, min and max.
+/// @tparam dtype_in Is the memory side buffer data type.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <reduce_op reduce_kind, typename dtype_in, gpu_arch arch_tag,
+        class enable = void>
+struct elemwise_reduce_op_t {};
+/// @brief Is the element-wise reduce op functor, specialized for Xe architecture.
+template <reduce_op reduce_kind_, typename dtype_in_, gpu_arch arch_tag>
+struct elemwise_reduce_op_t<reduce_kind_, dtype_in_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_in = dtype_in_;
+    using mem_desc_in_t
+            = mem_desc_t<dtype_in, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_in_t::shape_t;
+    using coord_t = typename mem_desc_in_t::coord_t;
+    using base_t = typename mem_desc_in_t::base_t;
+    static constexpr reduce_op reduce_kind = reduce_kind_;
+
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t base_, shape_t shape_)
+            : base(base_), shape(shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using mat_in_tile_desc_t = tile_desc_t<tile_size_x, block_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mat_in_tile_t = tile_t<dtype_in, mat_in_tile_desc_t>;
+        using mat_in_payload_t = mem_payload_t<mem_desc_in_t,
+                mat_in_tile_desc_t,
+                msg_type_v<mat_in_tile_desc_t, mem_desc_in_t::space>, arch_tag>;
+        using mat_in_tile_acc_t = tile_t<dtype_acc, mat_in_tile_desc_t>;
+        mem_desc_in_t mem_desc_in(args.base, args.shape, coord);
+        mat_in_tile_t mat_in;
+        mat_in_payload_t mat_in_payload(mem_desc_in);
+        mat_in_tile_acc_t mat_in_acc;
+
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; i++) {
+            tile_load<cache_hint::cached, cache_hint::cached>(
+                    mat_in, mat_in_payload);
+            elemwise_cvt(mat_in_acc, mat_in);
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto dst_reg = matAcc.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_x + j) * block_elems);
+                auto src_reg = mat_in_acc.reg.xetla_select<block_elems, 1>(
+                        j * block_elems);
+                dst_reg = reduce_helper<reduce_kind, dtype_acc, block_elems>(
+                        src_reg, dst_reg);
+            }
+            mat_in_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                    block_size_y);
+        }
+        // process the tail
+        if constexpr ((tile_size_y % block_size_y) != 0) {
+            constexpr uint32_t tail_start_y
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr int32_t tail_size_y = tile_size_y % block_size_y;
+            constexpr int32_t tail_block_elems = tail_size_y * block_size_x;
+
+            using mat_tail_in_tile_desc_t = tile_desc_t<tile_size_x,
+                    tail_size_y, block_size_x, tail_size_y, reg_layout::tiled>;
+            using mat_tail_in_tile_t
+                    = tile_t<dtype_in, mat_tail_in_tile_desc_t>;
+            using mat_tail_in_payload_t = mem_payload_t<mem_desc_in_t,
+                    mat_tail_in_tile_desc_t,
+                    msg_type_v<mat_tail_in_tile_desc_t, mem_desc_in_t::space>,
+                    arch_tag>;
+            using mat_tail_in_tile_acc_t
+                    = tile_t<dtype_acc, mat_tail_in_tile_desc_t>;
+            mat_tail_in_tile_t mat_tail_in;
+            mat_tail_in_payload_t mat_tail_in_payload(mem_desc_in);
+            mat_tail_in_tile_acc_t mat_tail_in_acc;
+            mat_tail_in_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                    tail_start_y);
+            tile_load<cache_hint::cached, cache_hint::cached>(
+                    mat_tail_in, mat_tail_in_payload);
+            elemwise_cvt(mat_tail_in_acc, mat_tail_in);
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+                auto dst_reg = matAcc.reg.xetla_select<tail_block_elems, 1>(
+                        tail_start_y * tile_size_x + j * tail_block_elems);
+                auto src_reg
+                        = mat_tail_in_acc.reg.xetla_select<tail_block_elems, 1>(
+                                j * tail_block_elems);
+                dst_reg = reduce_helper<reduce_kind, dtype_acc,
+                        tail_block_elems>(src_reg, dst_reg);
+            }
+        }
+    }
+};
+
+/// @brief Is the element-wise reduce op functor, specialized for stream_k dispatch
+///Load partial sum from scratchspace
+///Reduce in GRF
+///Store zero to scratchspace
+///Do these steps with smaller tiles to minimize GRF pressure
+/// @tparam reduce_kind Is the reduce type, can be sum, prod, min and max.
+/// @tparam dtype_in Is the memory side buffer data type.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <reduce_op reduce_kind, typename dtype_in,
+        gpu_arch arch_tag = gpu_arch::Xe, class enable = void>
+struct elemwise_reduce_op_stream_k_t {};
+/// @brief Is the element-wise reduce op functor, specialized for Xe architecture.
+template <reduce_op reduce_kind_, typename dtype_in_, gpu_arch arch_tag>
+struct elemwise_reduce_op_stream_k_t<reduce_kind_, dtype_in_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_in = dtype_in_;
+    using mem_desc_in_t
+            = mem_desc_t<dtype_in, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_in_t::shape_t;
+    using coord_t = typename mem_desc_in_t::coord_t;
+    using base_t = typename mem_desc_in_t::base_t;
+    static constexpr reduce_op reduce_kind = reduce_kind_;
+
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        inline arguments_t() = default;
+        inline arguments_t(base_t base_, shape_t shape_)
+            : base(base_), shape(shape_) {}
+    };
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using mat_in_tile_desc_t = tile_desc_t<block_size_x, block_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mat_in_tile_t = tile_t<dtype_in, mat_in_tile_desc_t>;
+        using mat_in_payload_t = mem_payload_t<mem_desc_in_t,
+                mat_in_tile_desc_t,
+                msg_type_v<mat_in_tile_desc_t, mem_desc_in_t::space>, arch_tag>;
+        mem_desc_in_t mem_desc_in(args.base, args.shape, coord);
+        mat_in_tile_t mat_in;
+        mat_in_tile_t mat_zero(0);
+        mat_in_payload_t mat_in_payload(mem_desc_in);
+
+#pragma unroll
+        for (int i = 0; i < tile_size_y / block_size_y; i++) {
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+
+                tile_load<cache_hint::cached, cache_hint::cached>(
+                        mat_in, mat_in_payload);
+                auto dst_reg = matAcc.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_x + j) * block_elems);
+
+                auto src_reg = mat_in.reg;
+                dst_reg = reduce_helper<reduce_kind, dtype_acc, block_elems>(
+                        src_reg, dst_reg);
+
+                subgroup::tile_store<cache_hint::uncached,
+                        cache_hint::write_back>(mat_zero, mat_in_payload);
+                mat_in_payload.template update_tdesc<tdesc_update_dir::x_dir>(
+                        block_size_x);
+            }
+            mat_in_payload.template update_tdesc<tdesc_update_dir::x_dir>(
+                    -num_block_x * block_size_x);
+            mat_in_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                    block_size_y);
+        }
+        // process the tail
+        if constexpr ((tile_size_y % block_size_y) != 0) {
+            constexpr uint32_t tail_start_y
+                    = tile_size_y / block_size_y * block_size_y;
+            constexpr int32_t tail_size_y = tile_size_y % block_size_y;
+            constexpr int32_t tail_block_elems = tail_size_y * block_size_x;
+#pragma unroll
+            for (int j = 0; j < num_block_x; j++) {
+
+                tile_load<cache_hint::cached, cache_hint::cached>(
+                        mat_in, mat_in_payload);
+                auto dst_reg = matAcc.reg.xetla_select<tail_block_elems, 1>(
+                        tail_start_y * tile_size_x + j * tail_block_elems);
+                auto src_reg = mat_in.reg.xetla_select<tail_block_elems, 1>(
+                        tail_start_y * tile_size_x + j * tail_block_elems);
+                dst_reg = reduce_helper<reduce_kind, dtype_acc,
+                        tail_block_elems>(src_reg, dst_reg);
+
+                subgroup::tile_store<cache_hint::uncached,
+                        cache_hint::write_back>(mat_zero, mat_in_payload);
+
+                mat_in_payload.template update_tdesc<tdesc_update_dir::x_dir>(
+                        block_size_x);
+            }
+        }
+    }
+};
+
+/// @brief Is the dropout op functor.
+/// Load the mask from memory and get input from matAcc,
+/// do the scaling and zero out, update the output in place.
+/// The mask has the same layout as the output.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_mask Is the mask data type.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_mask, gpu_arch arch_tag, class enable = void>
+struct dropout_op_t {};
+/// @brief Is the dropout op functor, specialized for Xe architecture.
+template <typename dtype_mask_, gpu_arch arch_tag>
+struct dropout_op_t<dtype_mask_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_mask = dtype_mask_;
+    using mem_desc_mask_t
+            = mem_desc_t<dtype_mask, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_mask_t::shape_t;
+    using coord_t = typename mem_desc_mask_t::coord_t;
+    using base_t = typename mem_desc_mask_t::base_t;
+    static constexpr uint32_t num_flag = 4;
+    static constexpr uint32_t unroll_size = num_flag * 16;
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        float prob;
+        float scale;
+        inline arguments_t() = default;
+        inline arguments_t(
+                base_t base_, shape_t shape_, float prob_, float scale_)
+            : base(base_), shape(shape_), prob(prob_), scale(scale_) {}
+    };
+
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+        if (args.prob == 0) { return; }
+        using mask_in_tile_desc_t = tile_desc_t<tile_size_x, tile_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mask_in_tile_t = tile_t<dtype_mask, mask_in_tile_desc_t>;
+        using mask_in_payload_t
+                = mem_payload_t<mem_desc_mask_t, mask_in_tile_desc_t,
+                        msg_type_v<mask_in_tile_desc_t, mem_desc_mask_t::space>,
+                        arch_tag>;
+        mem_desc_mask_t mem_desc_mask(args.base, args.shape, coord);
+        mask_in_tile_t mask_in;
+        mask_in_payload_t mask_in_payload(mem_desc_mask);
+        tile_load<cache_hint::cached, cache_hint::cached>(
+                mask_in, mask_in_payload);
+        if constexpr (tile_elems / unroll_size != 0) {
+#pragma unroll
+            for (int i = 0; i < tile_elems / unroll_size; i++) {
+                xetla_mask<unroll_size> mask_flag
+                        = mask_in.reg.xetla_select<unroll_size, 1>(
+                                  i * unroll_size)
+                        > 0;
+                auto dst_reg = matAcc.reg.xetla_select<unroll_size, 1>(
+                        i * unroll_size);
+                dst_reg *= args.scale;
+                dst_reg.xetla_merge(0, mask_flag);
+            }
+        }
+        if constexpr (tile_elems % unroll_size != 0) {
+            constexpr uint32_t remain_len = tile_elems % unroll_size;
+            constexpr uint32_t remain_start
+                    = tile_elems / unroll_size * unroll_size;
+            xetla_mask<remain_len> mask_flag
+                    = mask_in.reg.xetla_select<remain_len, 1>(remain_start) > 0;
+            auto dst_reg = matAcc.reg.xetla_select<remain_len, 1>(remain_start);
+            dst_reg *= args.scale;
+            dst_reg.xetla_merge(0, mask_flag);
+        }
+    }
+};
+
+/// @brief Is the random number generator and dropout op functor.
+/// Generate the mask data and get input from matAcc, do the scaling and zero out,
+/// update the output in place, dump the mask buffer to memory.
+/// The mask has the same layout as the output.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_mask Is the mask data type.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_mask, gpu_arch arch_tag, class enable = void>
+struct rng_dropout_op_t {};
+/// @brief Is the random number generator and dropout op functor, specialized for Xe architecture.
+template <typename dtype_mask_, gpu_arch arch_tag>
+struct rng_dropout_op_t<dtype_mask_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_mask = dtype_mask_;
+    using mem_desc_mask_t
+            = mem_desc_t<dtype_mask, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_mask_t::shape_t;
+    using coord_t = typename mem_desc_mask_t::coord_t;
+    using base_t = typename mem_desc_mask_t::base_t;
+    static constexpr uint32_t random_simd = 16;
+    static constexpr uint32_t random_len = 4 * random_simd;
+    xetla_rand_t<random_simd> rand_gen;
+
+    struct arguments_t {
+        shape_t mask_shape;
+        base_t mask_base;
+        uint64_t *rand_offset_ptr;
+        float prob;
+        uint64_t rand_seed;
+
+        inline arguments_t() = default;
+        inline arguments_t(base_t mask_base_, shape_t mask_shape_, float prob_,
+                uint64_t *rand_offset_ptr_,
+                uint64_t rand_seed_ = 67280421310721)
+            : mask_base(mask_base_)
+            , mask_shape(mask_shape_)
+            , prob(prob_)
+            , rand_offset_ptr(rand_offset_ptr_)
+            , rand_seed(rand_seed_) {}
+    };
+
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr int32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr int32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+
+        using mask_out_tile_desc_t = tile_desc_t<tile_size_x, tile_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mask_out_tile_t = tile_t<dtype_mask, mask_out_tile_desc_t>;
+        using mask_out_payload_t = mem_payload_t<mem_desc_mask_t,
+                mask_out_tile_desc_t,
+                msg_type_v<mask_out_tile_desc_t, mem_desc_mask_t::space>,
+                arch_tag>;
+        if (args.prob == 0) { return; }
+        //calculate the scale internally
+        float scale = 1.f / (1.f - args.prob);
+        uint32_t threshold = uint32_t(args.prob * float(4294967296));
+        xetla_vector<uint64_t, 1> rand_offset_v
+                = xetla_load_global<uint64_t, 1, data_size::default_size,
+                        cache_hint::cached, cache_hint::cached>(
+                        args.rand_offset_ptr, 0);
+        uint64_t rand_offset = rand_offset_v[0];
+        uint64_t rand_subseq = uint64_t(coord.y) << 32 | uint64_t(coord.x);
+        rand_gen.init(args.rand_seed, rand_subseq, rand_offset);
+
+        mem_desc_mask_t mem_desc_mask(args.mask_base, args.mask_shape, coord);
+        mask_out_tile_t mask_out;
+        mask_out_payload_t mask_out_payload(mem_desc_mask);
+        if constexpr (tile_elems / random_len != 0) {
+#pragma unroll
+            for (int i = 0; i < tile_elems / random_len; i++) {
+                auto out_sub = matAcc.reg.xetla_select<random_len, 1>(
+                        i * random_len);
+                auto mask_sub = mask_out.reg.xetla_select<random_len, 1>(
+                        i * random_len);
+                xetla_vector<uint32_t, random_len> rand_val = rand_gen.rand();
+                xetla_mask<random_len> mask_flag = rand_val < threshold;
+                out_sub *= scale;
+                out_sub.xetla_merge(0, mask_flag);
+                mask_sub.xetla_merge(1, 0, mask_flag);
+            }
+        }
+        if constexpr (tile_elems % random_len != 0) {
+            constexpr uint32_t remain_len = tile_elems % random_len;
+            constexpr uint32_t remain_start
+                    = tile_elems / random_len * random_len;
+            auto out_sub = matAcc.reg.xetla_select<remain_len, 1>(remain_start);
+            auto mask_sub
+                    = mask_out.reg.xetla_select<remain_len, 1>(remain_start);
+            // dropout, still generate random_len
+            xetla_vector<uint32_t, random_len> rand_val = rand_gen.rand();
+            xetla_mask<random_len> mask_flag = rand_val < threshold;
+            out_sub *= scale;
+            out_sub.xetla_merge(0, mask_flag.xetla_select<remain_len, 1>(0));
+            mask_sub.xetla_merge(
+                    1, 0, mask_flag.xetla_select<remain_len, 1>(0));
+        }
+        tile_store<cache_hint::streaming>(mask_out, mask_out_payload);
+    }
+};
+
+/// @brief Is the scalar_multiply op functor.
+/// Get the input from matAcc, multiply with a scalar, update the output in place.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_in Is the data type of multiplier buffer.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_in, gpu_arch arch_tag, class enable = void>
+struct scalar_mul_op_t {};
+/// @brief Is the scalar_multiply op functor, specialized for Xe architecture.
+template <typename dtype_in_, gpu_arch arch_tag>
+struct scalar_mul_op_t<dtype_in_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_in = dtype_in_;
+    using mem_desc_in_t
+            = mem_desc_t<dtype_in, mem_layout::row_major, mem_space::global>;
+    using coord_t = typename mem_desc_in_t::coord_t;
+
+    struct arguments_t {
+        dtype_in multiplier;
+        inline arguments_t() = default;
+        inline arguments_t(dtype_in multiplier_) : multiplier(multiplier_) {}
+    };
+
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc, coord_t coord,
+            arguments_t args, uint32_t slm_base = 0,
+            uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static_assert(std::is_same<dtype_in, dtype_acc>::value,
+                "Given multiplier must have same type as matAcc!");
+        matAcc.reg *= args.multiplier;
+    }
+};
+
+/// @brief Is the linear_op functor.
+/// Multiply matAcc with a scalar, then add a bias, update the output in place.
+/// Used in epilogue::tile_op or chained_tile_op.
+/// @tparam dtype_in Is the data type of multiplier buffer.
+/// @tparam arch_tag Is the hardware architecture tag.
+template <typename dtype_in, gpu_arch arch_tag, class enable = void>
+struct linear_op_t {};
+/// @brief Is the linear_op functor, specialized for Xe architecture.
+template <typename dtype_in_, gpu_arch arch_tag>
+struct linear_op_t<dtype_in_, arch_tag,
+        std::enable_if_t<(arch_tag == gpu_arch::Xe)>> {
+    using dtype_in = dtype_in_;
+    using mem_desc_in_t
+            = mem_desc_t<dtype_in, mem_layout::row_major, mem_space::global>;
+    using shape_t = typename mem_desc_in_t::shape_t;
+    using coord_t = typename mem_desc_in_t::coord_t;
+    using base_t = typename mem_desc_in_t::base_t;
+
+    struct arguments_t {
+        shape_t shape;
+        base_t base;
+        dtype_in alpha;
+        dtype_in beta;
+        inline arguments_t() = default;
+        inline arguments_t(
+                base_t base_, shape_t shape_, dtype_in alpha_, dtype_in beta_)
+            : base(base_), shape(shape_), alpha(alpha_), beta(beta_) {}
+    };
+
+    template <typename matAcc_t>
+    __XETLA_API KERNEL_FUNC void operator()(matAcc_t &matAcc,
+            const coord_t &coord, const arguments_t &args,
+            uint32_t slm_base = 0, uint32_t nbarrier_base = 0) {
+        using dtype_acc = typename matAcc_t::dtype;
+        static constexpr uint32_t tile_size_x = matAcc_t::tile_size_x;
+        static constexpr uint32_t tile_size_y = matAcc_t::tile_size_y;
+        static constexpr uint32_t block_size_x = matAcc_t::block_size_x;
+        static constexpr uint32_t block_size_y = matAcc_t::block_size_y;
+        static constexpr uint32_t num_block_x = matAcc_t::num_block_x;
+        static constexpr uint32_t num_block_y = matAcc_t::num_block_y;
+        static constexpr uint32_t tile_elems = matAcc_t::tile_elems;
+        static constexpr uint32_t block_elems = matAcc_t::block_elems;
+        static constexpr uint32_t remained_size_y = tile_size_y % block_size_y;
+
+        using mat_in_tile_desc_t = tile_desc_t<tile_size_x, block_size_y,
+                block_size_x, block_size_y, reg_layout::tiled>;
+        using mat_in_tile_t = tile_t<dtype_in, mat_in_tile_desc_t>;
+        using mat_in_payload_t = mem_payload_t<mem_desc_in_t,
+                mat_in_tile_desc_t,
+                msg_type_v<mat_in_tile_desc_t, mem_desc_in_t::space>, arch_tag>;
+        using mat_in_tile_acc_t = tile_t<dtype_acc, mat_in_tile_desc_t>;
+        mem_desc_in_t mem_desc_in(args.base, args.shape, coord);
+        mat_in_tile_t mat_in;
+        mat_in_payload_t mat_in_payload(mem_desc_in);
+        mat_in_tile_acc_t mat_in_acc;
+
+        dtype_acc alpha = dtype_acc(args.alpha);
+        dtype_acc beta = dtype_acc(args.beta);
+        matAcc.reg *= alpha;
+
+#pragma unroll
+        for (uint32_t i = 0; i < num_block_y; ++i) {
+            tile_load<cache_hint::cached, cache_hint::cached>(
+                    mat_in, mat_in_payload);
+            elemwise_cvt(mat_in_acc, mat_in);
+            mat_in_acc.reg *= beta;
+#pragma unroll
+            for (uint32_t j = 0; j < num_block_x; ++j) {
+                auto dst_reg = matAcc.reg.xetla_select<block_elems, 1>(
+                        (i * num_block_x + j) * block_elems);
+                auto src_reg = mat_in_acc.reg.xetla_select<block_elems, 1>(
+                        j * block_elems);
+                dst_reg = reduce_helper<reduce_op::sum, dtype_acc, block_elems>(
+                        src_reg, dst_reg);
+            }
+            mat_in_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                    block_size_y);
+        }
+        // process the tail
+        if constexpr (remained_size_y > 0) {
+            constexpr uint32_t tail_start_y = num_block_y * block_size_y;
+            constexpr uint32_t tail_block_elems
+                    = remained_size_y * block_size_x;
+
+            using mat_tail_in_tile_desc_t
+                    = tile_desc_t<tile_size_x, remained_size_y, block_size_x,
+                            remained_size_y, reg_layout::tiled>;
+            using mat_tail_in_tile_t
+                    = tile_t<dtype_in, mat_tail_in_tile_desc_t>;
+            using mat_tail_in_payload_t = mem_payload_t<mem_desc_in_t,
+                    mat_tail_in_tile_desc_t,
+                    msg_type_v<mat_tail_in_tile_desc_t, mem_desc_in_t::space>,
+                    arch_tag>;
+            using mat_tail_in_tile_acc_t
+                    = tile_t<dtype_acc, mat_tail_in_tile_desc_t>;
+
+            mat_tail_in_tile_t mat_tail_in;
+            mat_tail_in_payload_t mat_tail_in_payload(mem_desc_in);
+            mat_tail_in_tile_acc_t mat_tail_in_acc;
+            mat_tail_in_payload.template update_tdesc<tdesc_update_dir::y_dir>(
+                    tail_start_y);
+            tile_load<cache_hint::cached, cache_hint::cached>(
+                    mat_tail_in, mat_tail_in_payload);
+            elemwise_cvt(mat_tail_in_acc, mat_tail_in);
+            mat_tail_in_acc.reg *= beta;
+#pragma unroll
+            for (int j = 0; j < num_block_x; ++j) {
+                auto dst_reg = matAcc.reg.xetla_select<tail_block_elems, 1>(
+                        tail_start_y * tile_size_x + j * tail_block_elems);
+                auto src_reg
+                        = mat_tail_in_acc.reg.xetla_select<tail_block_elems, 1>(
+                                j * tail_block_elems);
+                dst_reg = reduce_helper<reduce_op::sum, dtype_acc,
+                        tail_block_elems>(src_reg, dst_reg);
+            }
+        }
+    }
+};
+
+} // namespace gpu::xetla::subgroup
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/tile.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/tile.hpp
new file mode 100644
index 00000000000000..3cc22c3e938355
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/subgroup/tile/tile.hpp
@@ -0,0 +1,33 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+
+#include "subgroup/tile/api.hpp"
+#include "subgroup/tile/chained_tile_op.hpp"
+#include "subgroup/tile/common.hpp"
+#include "subgroup/tile/impl/fma_xe.hpp"
+#include "subgroup/tile/impl/load_xe.hpp"
+#include "subgroup/tile/impl/mma_xe.hpp"
+#include "subgroup/tile/impl/op_function.hpp"
+#include "subgroup/tile/impl/payload_xe.hpp"
+#include "subgroup/tile/impl/prefetch_xe.hpp"
+#include "subgroup/tile/impl/reduction.hpp"
+#include "subgroup/tile/impl/store_xe.hpp"
+#include "subgroup/tile/impl/tile_op_functor.hpp"
diff --git a/src/plugins/intel_gpu/thirdparty/xetla/include/xetla.hpp b/src/plugins/intel_gpu/thirdparty/xetla/include/xetla.hpp
new file mode 100644
index 00000000000000..86bf1ee00bb3f3
--- /dev/null
+++ b/src/plugins/intel_gpu/thirdparty/xetla/include/xetla.hpp
@@ -0,0 +1,28 @@
+/*******************************************************************************
+* Copyright (c) 2022-2023 Intel Corporation
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/// @file
+/// C++ API
+
+#pragma once
+//Order of includes changed for windows build, otherwise file paths are resolved incorrectly
+
+// clang-format off
+#include "common/common.hpp"
+#include "group/group.hpp"
+#include "kernel/kernel.hpp"
+#include "subgroup/subgroup.hpp"
+// clang-format on

From 64e76e862898b27ac2c389843036db837479706a Mon Sep 17 00:00:00 2001
From: Vatsala Shanubhag <vatsala.shanubhag@intel.com>
Date: Tue, 18 Feb 2025 11:53:14 +0530
Subject: [PATCH 03/20] [ONNX] Added BiasAdd from com.microsoft domain (#28713)

Details:
Microsoft Contrib Operator "BiasAdd" for ONNX RT

Tickets:
N/A
---
 .../src/op/com.microsoft/bias_add.cpp         | 80 +++++++++++++++++
 .../models/com.microsoft/bias_add.prototxt    | 86 +++++++++++++++++++
 .../tests/onnx_import_com_microsoft.in.cpp    | 21 +++++
 3 files changed, 187 insertions(+)
 create mode 100644 src/frontends/onnx/frontend/src/op/com.microsoft/bias_add.cpp
 create mode 100644 src/frontends/onnx/tests/models/com.microsoft/bias_add.prototxt

diff --git a/src/frontends/onnx/frontend/src/op/com.microsoft/bias_add.cpp b/src/frontends/onnx/frontend/src/op/com.microsoft/bias_add.cpp
new file mode 100644
index 00000000000000..fd69b1a51a30de
--- /dev/null
+++ b/src/frontends/onnx/frontend/src/op/com.microsoft/bias_add.cpp
@@ -0,0 +1,80 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "core/operator_set.hpp"
+#include "exceptions.hpp"
+#include "openvino/frontend/exception.hpp"
+#include "openvino/op/add.hpp"
+#include "openvino/op/constant.hpp"
+#include "utils/common.hpp"
+
+using namespace ov::op;
+
+namespace ov {
+namespace frontend {
+namespace onnx {
+namespace com_microsoft {
+namespace opset_1 {
+
+ov::OutputVector bias_add(const ov::frontend::onnx::Node& node) {
+    // Documentation: BiasAdd computes Y = X + bias + skip
+    // https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#commicrosoftbiasadd
+
+    common::default_op_checks(node, 3);
+
+    const auto inputs = node.get_ov_inputs();
+    const auto& X = inputs[0];
+    const auto& bias = inputs[1];
+    const auto& skip = inputs[2];
+
+    auto element_type = X.get_element_type();
+    CHECK_VALID_NODE(node,
+                     element_type == ov::element::f16 || element_type == ov::element::f32,
+                     "Unsupported input data type for X, expected FP16 or FP32 but got: ",
+                     element_type);
+
+    const auto& X_shape = X.get_partial_shape();
+    const auto& bias_shape = bias.get_partial_shape();
+    const auto& skip_shape = skip.get_partial_shape();
+
+    CHECK_VALID_NODE(node,
+                     X_shape.rank().is_static() && X_shape.rank().get_length() == 3,
+                     "Input X must have rank 3 (N, S, C), but got: ",
+                     X_shape);
+    CHECK_VALID_NODE(node,
+                     skip_shape.rank().is_static() && skip_shape.rank().get_length() == 3,
+                     "Input skip must have rank 3 (N, S, C), but got: ",
+                     skip_shape);
+
+    CHECK_VALID_NODE(node,
+                     X_shape.compatible(skip_shape),
+                     "Input X and skip must have the same shape, but got: X=",
+                     X_shape,
+                     ", skip=",
+                     skip_shape);
+
+    CHECK_VALID_NODE(node,
+                     bias_shape.rank().is_static() && bias_shape.rank().get_length() == 1,
+                     "Input bias must have rank 1 (C), but got: ",
+                     bias_shape);
+
+    CHECK_VALID_NODE(node,
+                     X_shape[2].compatible(bias_shape[0]),
+                     "Input bias shape must match the channel dimension (C) of X and skip, but got: bias=",
+                     bias_shape,
+                     ", X=",
+                     X_shape);
+
+    auto X_plus_bias = std::make_shared<v1::Add>(X, bias);
+
+    return {std::make_shared<v1::Add>(X_plus_bias, skip)};
+}
+
+ONNX_OP("BiasAdd", OPSET_SINCE(1), com_microsoft::opset_1::bias_add, MICROSOFT_DOMAIN);
+
+}  // namespace opset_1
+}  // namespace com_microsoft
+}  // namespace onnx
+}  // namespace frontend
+}  // namespace ov
diff --git a/src/frontends/onnx/tests/models/com.microsoft/bias_add.prototxt b/src/frontends/onnx/tests/models/com.microsoft/bias_add.prototxt
new file mode 100644
index 00000000000000..62d32ecdcc65c0
--- /dev/null
+++ b/src/frontends/onnx/tests/models/com.microsoft/bias_add.prototxt
@@ -0,0 +1,86 @@
+ir_version: 7
+producer_name: "OpenVINO ONNX Frontend"
+graph {
+  node {
+    input: "X"
+    input: "bias"
+    input: "skip"
+    output: "Y"
+    op_type: "BiasAdd"
+    domain: "com.microsoft"
+  }
+  name: "test_bias_add_float"
+  input {
+    name: "X"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 2
+          }
+          dim {
+            dim_value: 4
+          }
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+  input {
+    name: "bias"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+  input {
+    name: "skip"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 2
+          }
+          dim {
+            dim_value: 4
+          }
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+  output {
+    name: "Y"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 2
+          }
+          dim {
+            dim_value: 4
+          }
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+}
+opset_import {
+  version: 1
+}
diff --git a/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp b/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
index 47a336f1749417..1324c116804140 100644
--- a/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
+++ b/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
@@ -1682,3 +1682,24 @@ OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_qlinear_mul) {
     test_case.add_expected_output<int8_t>(Shape{2, 2}, expected_output);
     test_case.run();
 }
+
+OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_bias_add) {
+    const auto model = convert_model("com.microsoft/bias_add.onnx");
+    auto test_case = ov::test::TestCase(model, s_device);
+
+    const std::vector<float> X = {1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12,
+                                  13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24};
+    const std::vector<float> bias = {2, 0, -1};
+    const std::vector<float> skip = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7};
+
+    const std::vector<float> expected_output = {3,  2,  2,  7,  6,  6,  11, 10, 10, 15, 14, 14,
+                                                19, 18, 18, 23, 22, 22, 27, 26, 26, 31, 30, 30};
+
+    test_case.add_input<float>(Shape{2, 4, 3}, X);
+    test_case.add_input<float>(Shape{3}, bias);
+    test_case.add_input<float>(Shape{2, 4, 3}, skip);
+
+    test_case.add_expected_output<float>(Shape{2, 4, 3}, expected_output);
+
+    test_case.run();
+}

From 06b5ad8a64fbb3a31d36428461e0a85a991ef9b8 Mon Sep 17 00:00:00 2001
From: Bogdan Pereanu <bogdan.pereanu@intel.com>
Date: Tue, 18 Feb 2025 08:33:20 +0200
Subject: [PATCH 04/20] Update Level Zero to v1.20.5 (#29034)

### Details:
 - *Update level zero to v1.20.5*

Signed-off-by: Bogdan Pereanu <bogdan.pereanu@intel.com>
---
 thirdparty/level_zero/level-zero | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/thirdparty/level_zero/level-zero b/thirdparty/level_zero/level-zero
index 3969f34c16a843..c0c23ad24e06a6 160000
--- a/thirdparty/level_zero/level-zero
+++ b/thirdparty/level_zero/level-zero
@@ -1 +1 @@
-Subproject commit 3969f34c16a843b943b948f8fe7081ef87deb369
+Subproject commit c0c23ad24e06a6109550381f9997b0b74fba90d7

From 37775f6bf4d1eb69c95df68dcde39fbafce1a1d1 Mon Sep 17 00:00:00 2001
From: Xiuchuan Zhai <xiuchuan.zhai@intel.com>
Date: Tue, 18 Feb 2025 15:09:46 +0800
Subject: [PATCH 05/20] [CPU][oneDNN] disable avx512 gemm in onednn (#28844)

### Details:
 - *disable building avx512 gemm binary*
 - *skip bf16 rnn test on ICX platforms*

### Tickets:
 - *118244*
---
 .../functional/shared_tests_instances/skip_tests_config.cpp  | 5 +++++
 src/plugins/intel_cpu/thirdparty/CMakeLists.txt              | 1 +
 2 files changed, 6 insertions(+)

diff --git a/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp b/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
index a25fba30ec73ca..fa400a51ad2639 100644
--- a/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
+++ b/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
@@ -574,6 +574,11 @@ std::vector<std::string> disabledTestPatterns() {
         retVector.emplace_back(R"(.*smoke_Snippets_MHAWOTransposeEnforceBF16.*)");
         retVector.emplace_back(R"(.*smoke_Snippets_MHA.*EnforceBF16.*)");
         retVector.emplace_back(R"(.*ConcatSDPTest.*bf16.*)");
+    }
+        // RNN/LSTM/GRU/AUGRU BF16 tests on avx512 core ISA
+    if (ov::with_cpu_x86_avx512_core() && !ov::with_cpu_x86_avx512_core_amx_bf16()) {
+        retVector.emplace_back(R"(smoke.*(AUGRUCellCPUTest|GRUCellCPUTest|RNNCellCPUTest|LSTMCellLayerCPUTest).CompareWithRefs.*INFERENCE_PRECISION_HINT=bf16.*)");
+        retVector.emplace_back(R"(nightly.*bf16.*(AUGRUSequenceCPUTest|GRUSequenceCPUTest|LSTMSequenceCPUTest).CompareWithRefs.*INFERENCE_PRECISION_HINT=bf16.*)");
     }
     // MHA FP16 precision is only supported on amx_fp16 platform
     if (!ov::with_cpu_x86_avx512_core_amx_fp16()) {
diff --git a/src/plugins/intel_cpu/thirdparty/CMakeLists.txt b/src/plugins/intel_cpu/thirdparty/CMakeLists.txt
index d172e4579862d6..709afa62cb86af 100644
--- a/src/plugins/intel_cpu/thirdparty/CMakeLists.txt
+++ b/src/plugins/intel_cpu/thirdparty/CMakeLists.txt
@@ -50,6 +50,7 @@ function(ov_add_onednn)
     set(DNNL_CPU_RUNTIME "${THREADING}" CACHE STRING "" FORCE)
     set(DNNL_GPU_RUNTIME "NONE" CACHE STRING "" FORCE)
     set(DNNL_BLAS_VENDOR "NONE" CACHE STRING "" FORCE)
+    set(ONEDNN_ENABLE_GEMM_KERNELS_ISA "AVX2" CACHE STRING "" FORCE)
     # plugin does not use onednn graph
     set(ONEDNN_BUILD_GRAPH OFF CACHE BOOL "" FORCE)
     # select needed primitives

From 54c2792f72b713a8317a279b3911020759557e48 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <gooddoog@student.su>
Date: Tue, 18 Feb 2025 08:41:00 +0100
Subject: [PATCH 06/20] Fix clang-tidy executable path (#29041)

### Details:
 - Fix clang-tidy executable detection

### Tickets:
 - N/A

Co-authored-by: Alina Kladieva <alina.kladieva@intel.com>
---
 cmake/developer_package/plugins/plugins.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmake/developer_package/plugins/plugins.cmake b/cmake/developer_package/plugins/plugins.cmake
index 0cf7606f7e7f12..3fabab67d8618d 100644
--- a/cmake/developer_package/plugins/plugins.cmake
+++ b/cmake/developer_package/plugins/plugins.cmake
@@ -109,7 +109,7 @@ function(ov_add_plugin)
         if (OV_PLUGIN_ADD_CLANG_TIDY)
             if (ENABLE_CLANG_TIDY)
                 set_target_properties(${OV_PLUGIN_NAME} PROPERTIES
-                    CXX_CLANG_TIDY "clang-tidy-${CLANG_TIDY_REQUIRED_VERSION};--extra-arg=-Wno-unused-command-line-argument")
+                    CXX_CLANG_TIDY "${CLANG_TIDY};--extra-arg=-Wno-unused-command-line-argument")
             endif()
         endif()
 

From b3a32cb62a07cf9b8dbfd3f7f06176af4c0738f7 Mon Sep 17 00:00:00 2001
From: Stefania Hergane <stefania-persida.hergane@intel.com>
Date: Tue, 18 Feb 2025 09:59:53 +0200
Subject: [PATCH 07/20] [NPU] Update NF4 precision conversions in NPU plugin
 (#29026)

### Details:
 - Fix for https://github.com/openvinotoolkit/openvino/pull/27903
 - Update NF4 precision conversions in NPU plugin
 - *...*
---
 samples/cpp/benchmark_app/inputs_filling.cpp                  | 2 ++
 .../src/compiler_adapter/src/ze_graph_ext_wrappers.cpp        | 2 ++
 .../src/utils/include/intel_npu/utils/zero/zero_utils.hpp     | 4 ++++
 3 files changed, 8 insertions(+)

diff --git a/samples/cpp/benchmark_app/inputs_filling.cpp b/samples/cpp/benchmark_app/inputs_filling.cpp
index 2a9ce2242b0825..4fd294555e9ea2 100644
--- a/samples/cpp/benchmark_app/inputs_filling.cpp
+++ b/samples/cpp/benchmark_app/inputs_filling.cpp
@@ -610,6 +610,8 @@ ov::Tensor get_random_tensor(const std::pair<std::string, benchmark_app::InputIn
         return create_tensor_random_4bit(inputInfo.second, 0, 15);
     } else if (type == ov::element::i4) {
         return create_tensor_random_4bit(inputInfo.second, 0, 15);
+    } else if (type == ov::element::nf4) {
+        return create_tensor_random_4bit(inputInfo.second, 0, 15);
     } else if (type == ov::element::string) {
         const auto& in_info = inputInfo.second;
         const auto tensor_size = ov::shape_size(in_info.dataShape);
diff --git a/src/plugins/intel_npu/src/compiler_adapter/src/ze_graph_ext_wrappers.cpp b/src/plugins/intel_npu/src/compiler_adapter/src/ze_graph_ext_wrappers.cpp
index a083eaa8582005..45ab0ff57bcd10 100644
--- a/src/plugins/intel_npu/src/compiler_adapter/src/ze_graph_ext_wrappers.cpp
+++ b/src/plugins/intel_npu/src/compiler_adapter/src/ze_graph_ext_wrappers.cpp
@@ -45,6 +45,8 @@ ov::element::Type_t toOVElementType(const ze_graph_argument_precision_t zeElemen
         return ov::element::Type_t::dynamic;
     case ZE_GRAPH_ARGUMENT_PRECISION_BOOLEAN:
         return ov::element::Type_t::boolean;
+    case ZE_GRAPH_ARGUMENT_PRECISION_NF4:
+        return ov::element::Type_t::nf4;
     case ZE_GRAPH_ARGUMENT_PRECISION_BF16:
         return ov::element::Type_t::bf16;
     case ZE_GRAPH_ARGUMENT_PRECISION_FP16:
diff --git a/src/plugins/intel_npu/src/utils/include/intel_npu/utils/zero/zero_utils.hpp b/src/plugins/intel_npu/src/utils/include/intel_npu/utils/zero/zero_utils.hpp
index e68eb0200a09ce..29bb50b12dd2b3 100644
--- a/src/plugins/intel_npu/src/utils/include/intel_npu/utils/zero/zero_utils.hpp
+++ b/src/plugins/intel_npu/src/utils/include/intel_npu/utils/zero/zero_utils.hpp
@@ -85,6 +85,8 @@ static inline std::size_t precisionToSize(const ze_graph_argument_precision_t va
         return 64;
     case ZE_GRAPH_ARGUMENT_PRECISION_UINT64:
         return 64;
+    case ZE_GRAPH_ARGUMENT_PRECISION_NF4:
+        return 4;
     case ZE_GRAPH_ARGUMENT_PRECISION_BF16:
         return 16;
     case ZE_GRAPH_ARGUMENT_PRECISION_FP16:
@@ -122,6 +124,8 @@ static inline ze_graph_argument_precision_t getZePrecision(const ov::element::Ty
         return ZE_GRAPH_ARGUMENT_PRECISION_INT64;
     case ov::element::Type_t::u64:
         return ZE_GRAPH_ARGUMENT_PRECISION_UINT64;
+    case ov::element::Type_t::nf4:
+        return ZE_GRAPH_ARGUMENT_PRECISION_NF4;
     case ov::element::Type_t::bf16:
         return ZE_GRAPH_ARGUMENT_PRECISION_BF16;
     case ov::element::Type_t::f16:

From 398842a719f2dd92a486fe3f2238ab6ca58ce61c Mon Sep 17 00:00:00 2001
From: Kelvin Choi <kelvin.choi@intel.com>
Date: Tue, 18 Feb 2025 17:24:05 +0900
Subject: [PATCH 08/20] [GPU] static strided_sliced crop to use tensor (#28507)

### Details:
 - *static strided_sliced crop to use tensor*

### Tickets:
 - *160254*
---
 .../src/plugin/ops/strided_slice.cpp          |  4 +-
 .../subgraph_tests/stridedslice_eltwise.cpp   | 30 +++++++
 .../unit/test_cases/eltwise_gpu_test.cpp      |  2 +
 .../subgraph_tests/stridedslice_eltwise.hpp   | 15 ++++
 .../subgraph/stridedslice_eltwise.hpp         | 42 ++++++++++
 .../src/subgraph/stridedslice_eltwise.cpp     | 83 +++++++++++++++++++
 6 files changed, 175 insertions(+), 1 deletion(-)
 create mode 100644 src/plugins/intel_gpu/tests/functional/shared_tests_instances/subgraph_tests/stridedslice_eltwise.cpp
 create mode 100644 src/tests/functional/plugin/shared/include/subgraph_tests/stridedslice_eltwise.hpp
 create mode 100644 src/tests/functional/shared_test_classes/include/shared_test_classes/subgraph/stridedslice_eltwise.hpp
 create mode 100644 src/tests/functional/shared_test_classes/src/subgraph/stridedslice_eltwise.cpp

diff --git a/src/plugins/intel_gpu/src/plugin/ops/strided_slice.cpp b/src/plugins/intel_gpu/src/plugin/ops/strided_slice.cpp
index 9f21b72114c24a..16700f1145d3d3 100644
--- a/src/plugins/intel_gpu/src/plugin/ops/strided_slice.cpp
+++ b/src/plugins/intel_gpu/src/plugin/ops/strided_slice.cpp
@@ -252,7 +252,9 @@ static void CreateStridedSliceOp(ProgramBuilder& p, const std::shared_ptr<ov::op
             }
 
             auto reshapeOutName = op->get_friendly_name() + "/Crop";
-            auto reshapePrim = cldnn::reshape(reshapeOutName, layerName, false, output_pattern, output_pshape);
+            auto output_ts = tensor_from_dims(output_shape);
+            auto reshapePrim = cldnn::reshape(reshapeOutName, layerName, output_ts);
+
             p.add_primitive(*op, reshapePrim);
             last_layer_primitive = reshapeOutName;
         }
diff --git a/src/plugins/intel_gpu/tests/functional/shared_tests_instances/subgraph_tests/stridedslice_eltwise.cpp b/src/plugins/intel_gpu/tests/functional/shared_tests_instances/subgraph_tests/stridedslice_eltwise.cpp
new file mode 100644
index 00000000000000..ddec2a4208f3fa
--- /dev/null
+++ b/src/plugins/intel_gpu/tests/functional/shared_tests_instances/subgraph_tests/stridedslice_eltwise.cpp
@@ -0,0 +1,30 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include <vector>
+
+#include "subgraph_tests/stridedslice_eltwise.hpp"
+
+namespace {
+using ov::test::StridedSliceEltwiseTest;
+
+std::vector<ov::test::StridedSliceEltwiseSpecificParams> ss_spec = {
+        ov::test::StridedSliceEltwiseSpecificParams{ ov::test::static_shapes_to_test_representation(std::vector<ov::Shape>({
+                                { 1, 2, 2, 3}, { 1, 1, 3}})),
+                                { 0 }, { 2 }, { 1 },
+                                { 0 }, { 0 }, { 0 }, { 1 }, { 0 } },
+        ov::test::StridedSliceEltwiseSpecificParams{ ov::test::static_shapes_to_test_representation(std::vector<ov::Shape>({
+                                { 2, 3, 4, 5}, { 3, 1, 1}})),
+                                { 0 }, { 2 }, { 1 },
+                                { 0 }, { 0 }, { 0 }, { 1 }, { 0 } },
+};
+
+INSTANTIATE_TEST_SUITE_P(smoke_StridedSliceEltwise, StridedSliceEltwiseTest,
+                        testing::Combine(
+                                testing::ValuesIn(ss_spec),
+                                testing::Values(ov::element::f32),
+                                testing::Values(ov::test::utils::DEVICE_GPU)),
+                        StridedSliceEltwiseTest::getTestCaseName);
+
+}  // namespace
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp
index 47d1af9667c67c..74ba0f7379f7a8 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/eltwise_gpu_test.cpp
@@ -10,9 +10,11 @@
 #include <intel_gpu/primitives/eltwise.hpp>
 #include <intel_gpu/primitives/gather.hpp>
 #include <intel_gpu/primitives/reorder.hpp>
+#include <intel_gpu/primitives/reshape.hpp>
 #include <intel_gpu/primitives/data.hpp>
 
 #include "eltwise_inst.h"
+#include "reshape_inst.h"
 
 using namespace cldnn;
 using namespace ::tests;
diff --git a/src/tests/functional/plugin/shared/include/subgraph_tests/stridedslice_eltwise.hpp b/src/tests/functional/plugin/shared/include/subgraph_tests/stridedslice_eltwise.hpp
new file mode 100644
index 00000000000000..bb7b6805109d32
--- /dev/null
+++ b/src/tests/functional/plugin/shared/include/subgraph_tests/stridedslice_eltwise.hpp
@@ -0,0 +1,15 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include "shared_test_classes/subgraph/stridedslice_eltwise.hpp"
+
+namespace ov {
+namespace test {
+TEST_P(StridedSliceEltwiseTest, Inference) {
+    run();
+};
+}  // namespace test
+}  // namespace ov
diff --git a/src/tests/functional/shared_test_classes/include/shared_test_classes/subgraph/stridedslice_eltwise.hpp b/src/tests/functional/shared_test_classes/include/shared_test_classes/subgraph/stridedslice_eltwise.hpp
new file mode 100644
index 00000000000000..df4dc519c09cf8
--- /dev/null
+++ b/src/tests/functional/shared_test_classes/include/shared_test_classes/subgraph/stridedslice_eltwise.hpp
@@ -0,0 +1,42 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include <tuple>
+#include <string>
+#include <vector>
+#include <memory>
+
+#include "shared_test_classes/base/ov_subgraph.hpp"
+
+namespace ov {
+namespace test {
+
+struct StridedSliceEltwiseSpecificParams {
+    std::vector<InputShape> input_shape;
+    std::vector<int64_t> begin;
+    std::vector<int64_t> end;
+    std::vector<int64_t> strides;
+    std::vector<int64_t> begin_mask;
+    std::vector<int64_t> end_mask;
+    std::vector<int64_t> new_axis_mask;
+    std::vector<int64_t> shrink_axis_mask;
+    std::vector<int64_t> ellipsis_axis_mask;
+};
+
+using StridedSliceEltwiseParamsTuple = typename std::tuple<
+        StridedSliceEltwiseSpecificParams, // strided_slice params
+        ov::element::Type,          // Network precision
+        std::string>;               // Device name
+
+class StridedSliceEltwiseTest: public testing::WithParamInterface<StridedSliceEltwiseParamsTuple>,
+                         virtual public ov::test::SubgraphBaseStaticTest{
+public:
+    static std::string getTestCaseName(const testing::TestParamInfo<StridedSliceEltwiseParamsTuple> &obj);
+protected:
+    void SetUp() override;
+};
+}  // namespace test
+}  // namespace ov
diff --git a/src/tests/functional/shared_test_classes/src/subgraph/stridedslice_eltwise.cpp b/src/tests/functional/shared_test_classes/src/subgraph/stridedslice_eltwise.cpp
new file mode 100644
index 00000000000000..5ee17cd1f6c75f
--- /dev/null
+++ b/src/tests/functional/shared_test_classes/src/subgraph/stridedslice_eltwise.cpp
@@ -0,0 +1,83 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "shared_test_classes/subgraph/stridedslice_eltwise.hpp"
+
+#include "common_test_utils/node_builders/constant.hpp"
+#include "common_test_utils/node_builders/eltwise.hpp"
+#include "common_test_utils/test_enums.hpp"
+#include "common_test_utils/ov_tensor_utils.hpp"
+
+#include "openvino/op/parameter.hpp"
+#include "openvino/op/constant.hpp"
+#include "openvino/op/result.hpp"
+#include "openvino/op/reduce_sum.hpp"
+
+namespace ov {
+namespace test {
+std::string StridedSliceEltwiseTest::getTestCaseName(const testing::TestParamInfo<StridedSliceEltwiseParamsTuple> &obj) {
+    StridedSliceEltwiseSpecificParams params;
+    ov::element::Type model_type;
+    std::string target_device;
+    std::tie(params, model_type, target_device) = obj.param;
+    std::ostringstream result;
+    result << "IS=(";
+    for (size_t i = 0lu; i < params.input_shape.size(); i++) {
+        result << ov::test::utils::partialShape2str({params.input_shape[i].first})
+               << (i < params.input_shape.size() - 1lu ? "_" : "");
+    }
+    result << ")_TS=";
+    for (size_t i = 0lu; i < params.input_shape.front().second.size(); i++) {
+        result << "{";
+        for (size_t j = 0lu; j < params.input_shape.size(); j++) {
+            result << ov::test::utils::vec2str(params.input_shape[j].second[i]) << (j < params.input_shape.size() - 1lu ? "_" : "");
+        }
+        result << "}_";
+    }
+    result << "modelType=" << model_type.to_string() << "_";
+    result << "begin=" << ov::test::utils::vec2str(params.begin) << "_";
+    result << "end=" << ov::test::utils::vec2str(params.end) << "_";
+    result << "stride=" << ov::test::utils::vec2str(params.strides) << "_";
+    result << "begin_m=" << ov::test::utils::vec2str(params.begin_mask) << "_";
+    result << "end_m=" << ov::test::utils::vec2str(params.end_mask) << "_";
+    result << "new_axis_m=" << (params.new_axis_mask.empty() ? "def" : ov::test::utils::vec2str(params.new_axis_mask)) << "_";
+    result << "shrink_m=" << (params.shrink_axis_mask.empty() ? "def" : ov::test::utils::vec2str(params.shrink_axis_mask)) << "_";
+    result << "ellipsis_m=" << (params.ellipsis_axis_mask.empty() ? "def" : ov::test::utils::vec2str(params.ellipsis_axis_mask)) << "_";
+    result << "trgDev=" << target_device;
+    return result.str();
+}
+
+void StridedSliceEltwiseTest::SetUp() {
+    StridedSliceEltwiseSpecificParams ssParams;
+    ov::element::Type type;
+    std::tie(ssParams, type, targetDevice) = this->GetParam();
+
+    init_input_shapes(ssParams.input_shape);
+
+    ASSERT_EQ(ssParams.begin.size(), ssParams.end.size());
+    ASSERT_EQ(ssParams.begin.size(), ssParams.strides.size());
+
+    auto param = std::make_shared<ov::op::v0::Parameter>(type, inputDynamicShapes.front());
+    ov::Shape const_shape = {ssParams.begin.size()};
+    auto begin_node = std::make_shared<ov::op::v0::Constant>(ov::element::i64, const_shape, ssParams.begin.data());
+    auto end_node = std::make_shared<ov::op::v0::Constant>(ov::element::i64, const_shape, ssParams.end.data());
+    auto stride_node = std::make_shared<ov::op::v0::Constant>(ov::element::i64, const_shape, ssParams.strides.data());
+    auto stridedSlice = std::make_shared<ov::op::v1::StridedSlice>(param,
+                                                                   begin_node,
+                                                                   end_node,
+                                                                   stride_node,
+                                                                   ssParams.begin_mask,
+                                                                   ssParams.end_mask,
+                                                                   ssParams.new_axis_mask,
+                                                                   ssParams.shrink_axis_mask,
+                                                                   ssParams.ellipsis_axis_mask);
+
+    auto constant_input1_tensor = ov::test::utils::create_and_fill_tensor(type, targetStaticShapes.front()[1]);
+    auto constant_input1 = std::make_shared<ov::op::v0::Constant>(constant_input1_tensor);
+    auto eltw = ov::test::utils::make_eltwise(stridedSlice, constant_input1, ov::test::utils::EltwiseTypes::ADD);
+    ov::ResultVector results{std::make_shared<ov::op::v0::Result>(eltw)};
+    function = std::make_shared<ov::Model>(results, ov::ParameterVector{param}, "StridedSliceEltwise");
+}
+} // namespace test
+} // namespace ov

From ecc3477990ca16c5fee56fe49bf710260ebe5905 Mon Sep 17 00:00:00 2001
From: Vladimir Paramuzov <vladimir.paramuzov@intel.com>
Date: Tue, 18 Feb 2025 15:54:14 +0400
Subject: [PATCH 09/20] [GPU] POC for shared plugin config (#28667)

### Details:
- Added common base class for plugin configuration and migration in GPU
plugin.
- New config defines options as typed members of config class which
shall provide more efficient access to the value than AnyMap
- Property setting is possible before finalization only which shall
localize the point when config become immutable.
- All config options may be read from environment as well as from json
config file when OV is built w/ debug caps.
 - Debug and release options are defined and handled similarly now

---------

Signed-off-by: Vladimir Paramuzov <vladimir.paramuzov@intel.com>
---
 src/core/src/any.cpp                          |  13 +-
 src/inference/CMakeLists.txt                  |  10 +-
 .../openvino/runtime/internal_properties.hpp  |   6 +
 .../openvino/runtime/plugin_config.hpp        | 416 ++++++++++++
 src/inference/src/dev/plugin_config.cpp       | 319 ++++++++++
 src/inference/tests/unit/config_test.cpp      | 383 +++++++++++
 src/plugins/intel_cpu/src/config.cpp          |   2 +-
 .../intel_cpu/src/internal_properties.hpp     |   5 -
 .../behavior/ov_plugin/properties_tests.cpp   |   2 +-
 src/plugins/intel_gpu/CMakeLists.txt          |   1 +
 src/plugins/intel_gpu/docs/gpu_debug_utils.md | 133 ++--
 .../include/intel_gpu/graph/network.hpp       |   3 +-
 .../include/intel_gpu/graph/program.hpp       |   5 +-
 .../include/intel_gpu/plugin/common_utils.hpp |   5 +-
 .../include/intel_gpu/plugin/plugin.hpp       |   1 -
 .../intel_gpu/plugin/program_builder.hpp      |  10 +-
 .../intel_gpu/plugin/remote_context.hpp       |   2 +-
 .../intel_gpu/runtime/debug_configuration.hpp | 164 ++---
 .../intel_gpu/runtime/execution_config.hpp    | 171 +----
 .../intel_gpu/runtime/internal_properties.hpp | 121 +++-
 .../include/intel_gpu/runtime/memory_pool.hpp |   6 +-
 .../include/intel_gpu/runtime/options.inl     |  82 +++
 .../include/intel_gpu/runtime/profiling.hpp   |   3 +-
 .../intel_gpu/runtime/shape_predictor.hpp     |  35 +-
 src/plugins/intel_gpu/src/graph/broadcast.cpp |   2 +-
 src/plugins/intel_gpu/src/graph/crop.cpp      |   2 +-
 .../intel_gpu/src/graph/debug_helper.cpp      | 241 ++++---
 .../intel_gpu/src/graph/debug_helper.hpp      |   4 -
 src/plugins/intel_gpu/src/graph/eltwise.cpp   |   2 +-
 .../intel_gpu/src/graph/fully_connected.cpp   |   3 +-
 src/plugins/intel_gpu/src/graph/gather.cpp    |   2 +-
 .../graph_optimizer/add_required_reorders.cpp |   2 +-
 .../graph_optimizer/build_implementations.cpp |   2 +-
 .../graph_optimizer/graph_initializations.cpp |   4 +-
 .../graph_optimizer/post_optimize_weights.cpp |   4 -
 .../graph_optimizer/prepare_buffer_fusing.cpp |   6 +-
 .../prepare_primitive_fusing.cpp              |   8 +-
 .../prepare_primitive_fusing_through.cpp      |   3 +
 .../graph_optimizer/propagate_constants.cpp   |   4 +-
 .../graph/graph_optimizer/reorder_inputs.cpp  |   4 +-
 .../select_preferred_formats.cpp              |   4 +-
 .../src/graph/impls/ocl/fully_connected.cpp   |   2 +-
 .../impls/ocl/kernel_selector_helper.cpp      |   4 +-
 .../src/graph/impls/ocl/kernels_cache.cpp     |  32 +-
 .../src/graph/impls/ocl/kernels_cache.hpp     |   1 -
 .../impls/onednn/concatenation_onednn.hpp     |   3 +-
 .../graph/impls/onednn/convolution_onednn.cpp |   2 -
 .../graph/impls/onednn/convolution_onednn.hpp |   3 +-
 .../impls/onednn/deconvolution_onednn.hpp     |   3 +-
 .../impls/onednn/fully_connected_onednn.hpp   |   3 +-
 .../src/graph/impls/onednn/gemm_onednn.hpp    |   3 +-
 .../graph/impls/onednn/lstm_seq_onednn.hpp    |   4 +-
 .../src/graph/impls/onednn/pooling_onednn.hpp |   3 +-
 .../impls/onednn/primitive_onednn_base.h      |  14 +-
 .../src/graph/impls/onednn/reduce_onednn.hpp  |   3 +-
 .../src/graph/impls/onednn/reorder_onednn.hpp |   3 +-
 .../impls/registry/implementation_manager.cpp |   2 +-
 .../registry/non_max_suppression_impls.cpp    |   2 +-
 .../src/graph/include/primitive_inst.h        |   2 +
 .../src/graph/include/program_node.h          |   1 +
 .../intel_gpu/src/graph/layout_optimizer.cpp  |  68 +-
 src/plugins/intel_gpu/src/graph/network.cpp   |  44 +-
 .../src/graph/non_max_suppression.cpp         |   2 +-
 src/plugins/intel_gpu/src/graph/permute.cpp   |   2 +-
 .../intel_gpu/src/graph/primitive_inst.cpp    |  83 +--
 src/plugins/intel_gpu/src/graph/program.cpp   |  92 +--
 .../src/graph/program_dump_graph.cpp          |   4 +-
 .../intel_gpu/src/graph/program_node.cpp      |   3 +-
 src/plugins/intel_gpu/src/graph/reorder.cpp   |   2 +-
 src/plugins/intel_gpu/src/graph/reshape.cpp   |   2 +-
 .../src/graph/scatter_elements_update.cpp     |   2 +-
 .../intel_gpu/src/graph/scatter_nd_update.cpp |   2 +-
 .../intel_gpu/src/graph/scatter_update.cpp    |   2 +-
 src/plugins/intel_gpu/src/graph/select.cpp    |   2 +-
 .../intel_gpu/src/graph/strided_slice.cpp     |   2 +-
 .../dynamic_quantize_kernel_ref.cpp           |   1 -
 .../fully_connected_kernel_bf_tiled.cpp       |  20 -
 .../intel_gpu/src/plugin/compiled_model.cpp   |  31 +-
 src/plugins/intel_gpu/src/plugin/graph.cpp    |  46 +-
 .../intel_gpu/src/plugin/ops/condition.cpp    |  14 +-
 src/plugins/intel_gpu/src/plugin/ops/loop.cpp |   7 +-
 src/plugins/intel_gpu/src/plugin/plugin.cpp   | 137 ++--
 .../intel_gpu/src/plugin/program_builder.cpp  |  87 +--
 .../src/plugin/sync_infer_request.cpp         |  28 +-
 .../dynamic_quantize_fully_connected.cpp      |   7 +-
 .../dynamic_quantize_fully_connected.hpp      |   2 +-
 .../transformations/fc_horizontal_fusion.cpp  |   1 -
 .../src/plugin/transformations_pipeline.cpp   |  37 +-
 .../src/runtime/debug_configuration.cpp       | 601 +-----------------
 src/plugins/intel_gpu/src/runtime/device.cpp  |   3 +-
 src/plugins/intel_gpu/src/runtime/engine.cpp  |   3 +-
 .../src/runtime/execution_config.cpp          | 457 +++++++------
 .../intel_gpu/src/runtime/memory_pool.cpp     |  38 +-
 .../intel_gpu/src/runtime/ocl/ocl_device.cpp  |   3 -
 .../intel_gpu/src/runtime/ocl/ocl_engine.cpp  |   2 +-
 .../intel_gpu/src/runtime/ocl/ocl_event.cpp   |  10 -
 .../intel_gpu/src/runtime/ocl/ocl_stream.cpp  |   8 +-
 .../intel_gpu/src/runtime/shape_predictor.cpp |  10 +-
 src/plugins/intel_gpu/src/runtime/stream.cpp  |   4 +-
 .../concurrency/gpu_reservation_test.cpp      |   6 +-
 .../unit/fusions/convolution_fusion_test.cpp  |   2 +-
 .../fusions/fully_connected_fusion_test.cpp   |   8 +-
 .../tests/unit/fusions/gemm_fusion_test.cpp   |   2 -
 .../tests/unit/fusions/loop_fusion_test.cpp   |   1 -
 .../graph_manipulation_gpu_test.cpp           |   2 +-
 .../module_tests/shape_predictor_test.cpp     |  14 +-
 .../passes/prepare_primitive_fusing_test.cpp  |   2 +-
 .../remove_redundant_reorders_tests.cpp       |  12 +-
 .../test_cases/concatenation_gpu_test.cpp     |   8 +-
 .../tests/unit/test_cases/crop_gpu_test.cpp   |   1 -
 .../unit/test_cases/debug_config_gpu_test.cpp |   2 +-
 .../tests/unit/test_cases/loop_gpu_test.cpp   |   4 +-
 .../unit/test_cases/reorder_gpu_test.cpp      |   2 +-
 .../tests/unit/test_utils/program_wrapper.h   |   4 +-
 .../tests/unit/test_utils/test_utils.cpp      |   6 +-
 115 files changed, 2216 insertions(+), 2014 deletions(-)
 create mode 100644 src/inference/dev_api/openvino/runtime/plugin_config.hpp
 create mode 100644 src/inference/src/dev/plugin_config.cpp
 create mode 100644 src/inference/tests/unit/config_test.cpp
 create mode 100644 src/plugins/intel_gpu/include/intel_gpu/runtime/options.inl

diff --git a/src/core/src/any.cpp b/src/core/src/any.cpp
index 54c6b4f9d868f5..d99eb64199797c 100644
--- a/src/core/src/any.cpp
+++ b/src/core/src/any.cpp
@@ -4,8 +4,12 @@
 
 #include "openvino/core/any.hpp"
 
+#include <array>
 #include <limits>
 #include <string>
+#include <string_view>
+
+#include "openvino/util/common_util.hpp"
 namespace {
 template <class Container>
 bool contains_type_index(Container&& types, const std::type_info& user_type) {
@@ -202,9 +206,14 @@ namespace util {
 void Read<bool>::operator()(std::istream& is, bool& value) const {
     std::string str;
     is >> str;
-    if (str == "YES") {
+
+    constexpr std::array<std::string_view, 4> off = {"0", "false", "off", "no"};
+    constexpr std::array<std::string_view, 4> on = {"1", "true", "on", "yes"};
+    str = util::to_lower(str);
+
+    if (std::find(on.begin(), on.end(), str) != on.end()) {
         value = true;
-    } else if (str == "NO") {
+    } else if (std::find(off.begin(), off.end(), str) != off.end()) {
         value = false;
     } else {
         OPENVINO_THROW("Could not convert to bool from string " + str);
diff --git a/src/inference/CMakeLists.txt b/src/inference/CMakeLists.txt
index 22c28c2acde6e6..40528735f80071 100644
--- a/src/inference/CMakeLists.txt
+++ b/src/inference/CMakeLists.txt
@@ -76,6 +76,10 @@ target_compile_definitions(${TARGET_NAME}_obj PRIVATE
     IMPLEMENT_OPENVINO_RUNTIME_API
     $<$<TARGET_EXISTS:openvino_proxy_plugin_obj>:PROXY_PLUGIN_ENABLED>)
 
+if(ENABLE_DEBUG_CAPS)
+    target_compile_definitions(${TARGET_NAME}_obj PUBLIC ENABLE_DEBUG_CAPS)
+endif()
+
 target_include_directories(${TARGET_NAME}_obj SYSTEM PRIVATE
     $<TARGET_PROPERTY:openvino::pugixml,INTERFACE_INCLUDE_DIRECTORIES>
     $<$<TARGET_EXISTS:xbyak::xbyak>:$<TARGET_PROPERTY:xbyak::xbyak,INTERFACE_INCLUDE_DIRECTORIES>>)
@@ -87,7 +91,7 @@ target_include_directories(${TARGET_NAME}_obj PRIVATE
     # for ov_plugins.hpp
     $<IF:$<AND:$<BOOL:${OV_GENERATOR_MULTI_CONFIG}>,$<VERSION_GREATER_EQUAL:${CMAKE_VERSION},3.20>>,${CMAKE_CURRENT_BINARY_DIR}/$<CONFIG>,${CMAKE_CURRENT_BINARY_DIR}>)
 
-target_link_libraries(${TARGET_NAME}_obj PRIVATE openvino::itt openvino::util openvino::core::dev)
+target_link_libraries(${TARGET_NAME}_obj PRIVATE openvino::itt openvino::util openvino::core::dev nlohmann_json::nlohmann_json)
 ov_mark_target_as_cc(${TARGET_NAME}_obj)
 
 # OpenVINO Runtime is public API => need to mark this library as important for ABI free
@@ -133,6 +137,10 @@ target_link_libraries(${TARGET_NAME}_s PRIVATE openvino::itt ${CMAKE_DL_LIBS}
 
 target_compile_definitions(${TARGET_NAME}_s PUBLIC USE_STATIC_IE)
 
+if(ENABLE_DEBUG_CAPS)
+    target_compile_definitions(${TARGET_NAME}_s PUBLIC ENABLE_DEBUG_CAPS)
+endif()
+
 set_target_properties(${TARGET_NAME}_s PROPERTIES INTERPROCEDURAL_OPTIMIZATION_RELEASE ${ENABLE_LTO})
 
 # LTO
diff --git a/src/inference/dev_api/openvino/runtime/internal_properties.hpp b/src/inference/dev_api/openvino/runtime/internal_properties.hpp
index 9b2f08c17a7fe0..e26024622580e7 100644
--- a/src/inference/dev_api/openvino/runtime/internal_properties.hpp
+++ b/src/inference/dev_api/openvino/runtime/internal_properties.hpp
@@ -90,5 +90,11 @@ static constexpr Property<bool, PropertyMutability::RO> compiled_model_runtime_p
  */
 static constexpr Property<float, PropertyMutability::RW> query_model_ratio{"QUERY_MODEL_RATIO"};
 
+/**
+ * @brief Allow execution of low precision transformations in plugin's pipelines
+ * @ingroup ov_dev_api_plugin_api
+ */
+static constexpr Property<bool, PropertyMutability::RW> enable_lp_transformations{"LP_TRANSFORMS_MODE"};
+
 }  // namespace internal
 }  // namespace ov
diff --git a/src/inference/dev_api/openvino/runtime/plugin_config.hpp b/src/inference/dev_api/openvino/runtime/plugin_config.hpp
new file mode 100644
index 00000000000000..109165b1cd01c6
--- /dev/null
+++ b/src/inference/dev_api/openvino/runtime/plugin_config.hpp
@@ -0,0 +1,416 @@
+// Copyright (C) 2024-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include <filesystem>
+#include <map>
+#include <string_view>
+
+#include "openvino/core/attribute_visitor.hpp"
+#include "openvino/core/except.hpp"
+#include "openvino/runtime/iremote_context.hpp"
+#include "openvino/runtime/properties.hpp"
+
+#define OV_CONFIG_DECLARE_OPTION(PropertyNamespace, PropertyVar, Visibility, ...)                           \
+public:                                                                                                     \
+    const decltype(PropertyNamespace::PropertyVar)::value_type& get_##PropertyVar() const {                 \
+        if (m_is_finalized) {                                                                               \
+            return m_##PropertyVar.value;                                                                   \
+        } else {                                                                                            \
+            if (m_user_properties.find(PropertyNamespace::PropertyVar.name()) != m_user_properties.end()) { \
+                return m_user_properties.at(PropertyNamespace::PropertyVar.name())                          \
+                    .as<decltype(PropertyNamespace::PropertyVar)::value_type>();                            \
+            } else {                                                                                        \
+                return m_##PropertyVar.value;                                                               \
+            }                                                                                               \
+        }                                                                                                   \
+    }                                                                                                       \
+                                                                                                            \
+private:                                                                                                    \
+    ConfigOption<decltype(PropertyNamespace::PropertyVar)::value_type, Visibility> m_##PropertyVar{         \
+        this,                                                                                               \
+        PropertyNamespace::PropertyVar.name(),                                                              \
+        #PropertyNamespace "::" #PropertyVar,                                                               \
+        __VA_ARGS__};
+
+#define OV_CONFIG_RELEASE_OPTION(PropertyNamespace, PropertyVar, ...) \
+    OV_CONFIG_DECLARE_OPTION(PropertyNamespace, PropertyVar, OptionVisibility::RELEASE, __VA_ARGS__)
+
+#define OV_CONFIG_RELEASE_INTERNAL_OPTION(PropertyNamespace, PropertyVar, ...) \
+    OV_CONFIG_DECLARE_OPTION(PropertyNamespace, PropertyVar, OptionVisibility::RELEASE_INTERNAL, __VA_ARGS__)
+
+#ifdef ENABLE_DEBUG_CAPS
+#    define OV_CONFIG_DEBUG_GLOBAL_OPTION(PropertyNamespace, PropertyVar, ...)                              \
+    public:                                                                                                 \
+        static const decltype(PropertyNamespace::PropertyVar)::value_type& get_##PropertyVar() {            \
+            static PluginConfig::GlobalOptionInitializer init_helper(PropertyNamespace::PropertyVar.name(), \
+                                                                     m_allowed_env_prefix,                  \
+                                                                     m_##PropertyVar);                      \
+            return init_helper.m_option.value;                                                              \
+        }                                                                                                   \
+                                                                                                            \
+    private:                                                                                                \
+        static inline ConfigOption<decltype(PropertyNamespace::PropertyVar)::value_type,                    \
+                                   OptionVisibility::DEBUG_GLOBAL>                                          \
+            m_##PropertyVar{nullptr,                                                                        \
+                            PropertyNamespace::PropertyVar.name(),                                          \
+                            #PropertyNamespace "::" #PropertyVar,                                           \
+                            __VA_ARGS__};                                                                   \
+        OptionRegistrationHelper m_##PropertyVar##_rh{this, PropertyNamespace::PropertyVar.name(), &m_##PropertyVar};
+
+#    define OV_CONFIG_DEBUG_OPTION(PropertyNamespace, PropertyVar, ...) \
+        OV_CONFIG_DECLARE_OPTION(PropertyNamespace, PropertyVar, OptionVisibility::DEBUG, __VA_ARGS__)
+#else
+#    define OV_CONFIG_DEBUG_GLOBAL_OPTION(...)
+#    define OV_CONFIG_DEBUG_OPTION(...)
+#endif
+
+namespace ov {
+enum class OptionVisibility : uint8_t {
+    RELEASE = 1 << 0,  // Option can be set for any build type via public interface, environment and config file
+    RELEASE_INTERNAL = 1 << 1,  // Option can be set for any build type via environment and config file only
+    DEBUG = 1 << 2,             // Option can be set for debug builds only via environment and config file
+    DEBUG_GLOBAL = 1 << 3,      // Global option can be set for debug builds only via environment and config file
+    ANY = 0xFF,                 // Any visibility is valid
+};
+
+inline OptionVisibility operator&(OptionVisibility a, OptionVisibility b) {
+    using T = std::underlying_type_t<OptionVisibility>;
+    return static_cast<OptionVisibility>(static_cast<T>(a) & static_cast<T>(b));
+}
+
+inline OptionVisibility operator|(OptionVisibility a, OptionVisibility b) {
+    using T = std::underlying_type_t<OptionVisibility>;
+    return static_cast<OptionVisibility>(static_cast<T>(a) | static_cast<T>(b));
+}
+
+inline OptionVisibility operator~(OptionVisibility a) {
+    using T = std::underlying_type_t<OptionVisibility>;
+    return static_cast<OptionVisibility>(~static_cast<T>(a));
+}
+
+inline std::ostream& operator<<(std::ostream& os, const OptionVisibility& visibility) {
+    switch (visibility) {
+    case OptionVisibility::RELEASE:
+        os << "RELEASE";
+        break;
+    case OptionVisibility::RELEASE_INTERNAL:
+        os << "RELEASE_INTERNAL";
+        break;
+    case OptionVisibility::DEBUG:
+        os << "DEBUG";
+        break;
+    case OptionVisibility::DEBUG_GLOBAL:
+        os << "DEBUG_GLOBAL";
+        break;
+    case OptionVisibility::ANY:
+        os << "ANY";
+        break;
+    default:
+        os << "UNKNOWN";
+        break;
+    }
+
+    return os;
+}
+
+struct ConfigOptionBase {
+    ConfigOptionBase(std::string_view prop_name, std::string_view desc) : property_name(prop_name), description(desc) {}
+    virtual ~ConfigOptionBase() = default;
+
+    virtual void set_any(const ov::Any& any) = 0;
+    virtual ov::Any get_any() const = 0;
+    virtual bool is_valid_value(const ov::Any& val) const = 0;
+    virtual OptionVisibility get_visibility() const = 0;
+
+    std::string_view property_name;
+    std::string_view description;
+};
+
+// Base class for configuration of plugins
+// Implementation should provide a list of properties with default values and validators (optional)
+// and prepare a map string property name -> ConfigOptionBase pointer
+// For the sake of efficiency, we expect that plugin properties are defined as class members of the derived class
+// and accessed directly in the plugin's code (i.e. w/o get_property()/set_property() calls)
+// get/set property members are provided to handle external property access
+// The class provides a helpers to read the properties from configuration file and from environment variables
+//
+// Expected order of properties resolution:
+// 1. Assign default value for each property per device
+// 2. Save user properties passed via Core::set_property() call to user_properties
+// 3. Save user properties passed via Core::compile_model() call to user_properties
+// 4. Apply RT info properties to user_properties if they were not set by user
+// 5. Read and apply properties from the config file as user_properties
+// 6. Read and apply properties from the the environment variables as user_properties
+// 7. Apply user_properties to actual plugin properties
+// 8. Update dependant properties if they were not set by user either way
+class OPENVINO_RUNTIME_API PluginConfig {
+public:
+    PluginConfig() {}
+    virtual ~PluginConfig() = default;
+
+    // Disable copy and move as we need to setup m_options_map properly and ensure that
+    // values are a part of current config object
+    PluginConfig(const PluginConfig& other) = delete;
+    PluginConfig& operator=(const PluginConfig& other) = delete;
+    PluginConfig(PluginConfig&& other) = delete;
+    PluginConfig& operator=(PluginConfig&& other) = delete;
+
+    void set_property(const ov::AnyMap& properties);
+    void set_user_property(const ov::AnyMap& properties, OptionVisibility allowed_visibility = OptionVisibility::ANY);
+    Any get_property(const std::string& name, OptionVisibility allowed_visibility = OptionVisibility::ANY) const;
+
+    template <typename... Properties>
+    util::EnableIfAllStringAny<void, Properties...> set_property(Properties&&... properties) {
+        set_property(ov::AnyMap{std::forward<Properties>(properties)...});
+    }
+    template <typename... Properties>
+    util::EnableIfAllStringAny<void, Properties...> set_user_property(Properties&&... properties) {
+        set_user_property(ov::AnyMap{std::forward<Properties>(properties)...});
+    }
+
+    std::string to_string() const;
+
+    void finalize(const IRemoteContext* context, const ov::Model* model);
+
+    bool visit_attributes(ov::AttributeVisitor& visitor);
+
+    void register_option(const std::string& name, ConfigOptionBase* ptr) {
+        m_options_map.emplace(name, ptr);
+    }
+
+protected:
+    template <typename OptionType>
+    class GlobalOptionInitializer {
+    public:
+        GlobalOptionInitializer(const std::string& name, std::string_view prefix, OptionType& option)
+            : m_option(option) {
+            auto val = PluginConfig::read_env(name, prefix, &option);
+            if (!val.empty()) {
+                std::cout << "Non default global config value for " << name << " = " << val.template as<std::string>()
+                          << std::endl;
+                option.set_any(val);
+            }
+        }
+
+        OptionType& m_option;
+    };
+
+    virtual void apply_model_specific_options(const IRemoteContext* context, const ov::Model& model) {}
+    void apply_env_options();
+    void apply_config_options(std::string_view device_name, std::filesystem::path config_path = "");
+    virtual void finalize_impl(const IRemoteContext* context) {}
+
+    template <typename T, PropertyMutability mutability>
+    bool is_set_by_user(const ov::Property<T, mutability>& property) const {
+        return m_user_properties.find(property.name()) != m_user_properties.end();
+    }
+
+    ConfigOptionBase* get_option_ptr(const std::string& name) const {
+        auto it = m_options_map.find(name);
+        OPENVINO_ASSERT(it != m_options_map.end(), "Option not found: ", name);
+        OPENVINO_ASSERT(it->second != nullptr, "Option is invalid: ", name);
+
+        return it->second;
+    }
+
+    template <typename T, PropertyMutability mutability>
+    void apply_rt_info_property(const ov::Property<T, mutability>& property, const ov::RTMap& rt_info) {
+        if (!is_set_by_user(property)) {
+            auto rt_info_val = rt_info.find(property.name());
+            if (rt_info_val != rt_info.end()) {
+                set_user_property({property(rt_info_val->second.template as<T>())}, OptionVisibility::RELEASE);
+            }
+        }
+    }
+
+    ov::AnyMap read_config_file(std::filesystem::path filename, std::string_view target_device_name) const;
+    ov::AnyMap read_env() const;
+    static ov::Any read_env(const std::string& option_name, std::string_view prefix, const ConfigOptionBase* option);
+    void cleanup_unsupported(ov::AnyMap& config) const;
+
+    std::map<std::string, ConfigOptionBase*> m_options_map;
+    using OptionMapEntry = decltype(m_options_map)::value_type;
+
+    // List of properties explicitly set by user via Core::set_property() or Core::compile_model() or ov::Model's
+    // runtime info
+    ov::AnyMap m_user_properties;
+
+    std::string_view get_help_message(const std::string& name = "") const;
+    void print_help() const;
+
+    bool m_is_finalized = false;
+
+    inline static const std::string_view m_allowed_env_prefix = "OV_";
+};
+
+class OptionRegistrationHelper {
+public:
+    OptionRegistrationHelper(PluginConfig* config, std::string_view name, ConfigOptionBase* option) {
+        if (config)
+            config->register_option(std::string{name}, option);
+    }
+};
+
+template <typename T>
+struct TypedOption : public ConfigOptionBase {
+    TypedOption(const T& default_val, std::string_view prop_name, std::string_view desc)
+        : ConfigOptionBase(prop_name, desc),
+          value(default_val) {}
+    T value;
+};
+
+template <typename T, OptionVisibility visibility_>
+struct ConfigOption : public TypedOption<T> {
+    ConfigOption(PluginConfig* config,
+                 std::string_view name,
+                 std::string_view prop_name,
+                 const T& default_val,
+                 std::string_view desc,
+                 std::function<bool(T)> validator = nullptr)
+        : TypedOption<T>(default_val, prop_name, desc),
+          validator(validator) {
+        OptionRegistrationHelper option(config, name, this);
+    }
+    constexpr static const auto visibility = visibility_;
+
+    void set_any(const ov::Any& any) override {
+        if (validator)
+            OPENVINO_ASSERT(validator(any.as<T>()), "Invalid value: ", any.as<std::string>());
+        this->value = any.as<T>();
+    }
+
+    ov::Any get_any() const override {
+        return ov::Any(this->value);
+    }
+
+    bool is_valid_value(const ov::Any& val) const override {
+        try {
+            auto v = val.as<T>();
+            return validator ? validator(v) : true;
+        } catch (std::exception&) {
+            return false;
+        }
+    }
+
+    OptionVisibility get_visibility() const override {
+        return visibility;
+    }
+
+    operator T() const {
+        return this->value;
+    }
+
+    ConfigOption& operator=(const T& val) {
+        this->value = val;
+        return *this;
+    }
+
+    template <typename U, typename = std::enable_if_t<std::is_convertible_v<U, T>>>
+    bool operator==(const U& val) const {
+        return this->value == static_cast<T>(val);
+    }
+
+    template <typename U, typename = std::enable_if_t<std::is_convertible_v<U, T>>>
+    bool operator!=(const U& val) const {
+        return !(*this == val);
+    }
+
+private:
+    std::function<bool(T)> validator;
+};
+
+template <>
+class OPENVINO_RUNTIME_API AttributeAdapter<ConfigOptionBase*> : public DirectValueAccessor<ConfigOptionBase*> {
+public:
+    AttributeAdapter(ConfigOptionBase*& value) : DirectValueAccessor<ConfigOptionBase*>(value) {}
+
+    OPENVINO_RTTI("AttributeAdapter<ConfigOptionBase*>");
+};
+
+template <>
+class OPENVINO_RUNTIME_API AttributeAdapter<ov::AnyMap> : public DirectValueAccessor<ov::AnyMap> {
+public:
+    AttributeAdapter(ov::AnyMap& value) : DirectValueAccessor<ov::AnyMap>(value) {}
+
+    OPENVINO_RTTI("AttributeAdapter<ov::AnyMap>");
+};
+
+template <typename OStreamType>
+class OstreamAttributeVisitor : public ov::AttributeVisitor {
+    OStreamType& os;
+
+public:
+    OstreamAttributeVisitor(OStreamType& os) : os(os) {}
+
+    void on_adapter(const std::string& name, ov::ValueAccessor<bool>& adapter) override {
+        os << adapter.get();
+    }
+
+    void on_adapter(const std::string& name, ov::ValueAccessor<void>& adapter) override {
+        if (auto a = ov::as_type<ov::AttributeAdapter<ConfigOptionBase*>>(&adapter)) {
+            return handle_option(a->get());
+        } else if (auto a = ov::as_type<ov::AttributeAdapter<ov::AnyMap>>(&adapter)) {
+            const auto& props = a->get();
+            os << props.size();
+            for (auto& kv : props) {
+                os << kv.first << kv.second.as<std::string>();
+            }
+        } else {
+            OPENVINO_THROW("Attribute ", name, " can't be processed\n");
+        }
+    }
+
+    void handle_option(ConfigOptionBase* option) {
+        if (option->get_visibility() == OptionVisibility::RELEASE ||
+            option->get_visibility() == OptionVisibility::RELEASE_INTERNAL)
+            os << option->get_any().as<std::string>();
+    }
+};
+
+template <typename IStreamType>
+class IstreamAttributeVisitor : public ov::AttributeVisitor {
+    IStreamType& is;
+
+public:
+    IstreamAttributeVisitor(IStreamType& is) : is(is) {}
+
+    void on_adapter(const std::string& name, ov::ValueAccessor<void>& adapter) override {
+        if (auto a = ov::as_type<ov::AttributeAdapter<ConfigOptionBase*>>(&adapter)) {
+            return handle_option(a->get());
+        } else if (auto a = ov::as_type<ov::AttributeAdapter<ov::AnyMap>>(&adapter)) {
+            size_t size;
+            is >> size;
+            ov::AnyMap props;
+            for (size_t i = 0; i < size; i++) {
+                std::string name, val;
+                is >> name;
+                is >> val;
+                props[name] = val;
+            }
+            a->set(props);
+        } else {
+            OPENVINO_THROW("Attribute ", name, " can't be processed\n");
+        }
+    }
+
+    void on_adapter(const std::string& name, ov::ValueAccessor<bool>& adapter) override {
+        bool val;
+        is >> val;
+        adapter.set(val);
+    }
+
+    void handle_option(ConfigOptionBase* option) {
+        if (option->get_visibility() == OptionVisibility::RELEASE ||
+            option->get_visibility() == OptionVisibility::RELEASE_INTERNAL) {
+            std::string s;
+            is >> s;
+            if (option->is_valid_value(s))
+                option->set_any(s);
+        }
+    }
+};
+
+}  // namespace ov
diff --git a/src/inference/src/dev/plugin_config.cpp b/src/inference/src/dev/plugin_config.cpp
new file mode 100644
index 00000000000000..d4268da8d827ec
--- /dev/null
+++ b/src/inference/src/dev/plugin_config.cpp
@@ -0,0 +1,319 @@
+// Copyright (C) 2024-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "openvino/runtime/plugin_config.hpp"
+
+#include <array>
+#include <cmath>
+#include <fstream>
+#include <iomanip>
+#include <string_view>
+
+#include "openvino/core/any.hpp"
+#include "openvino/core/except.hpp"
+#include "openvino/runtime/device_id_parser.hpp"
+#include "openvino/util/common_util.hpp"
+#include "openvino/util/env_util.hpp"
+
+#ifdef JSON_HEADER
+#    include <json.hpp>
+#else
+#    include <nlohmann/json.hpp>
+#endif
+
+#ifdef _WIN32
+#    ifndef NOMINMAX
+#        define NOMINMAX
+#    endif
+#    include <windows.h>
+#else
+#    include <sys/ioctl.h>
+#    include <unistd.h>
+#endif
+
+namespace {
+size_t get_terminal_width() {
+    const size_t default_width = 120;
+#ifdef _WIN32
+    CONSOLE_SCREEN_BUFFER_INFO csbi;
+    if (GetConsoleScreenBufferInfo(GetStdHandle(STD_OUTPUT_HANDLE), &csbi)) {
+        return csbi.srWindow.Right - csbi.srWindow.Left + 1;
+    } else {
+        return default_width;
+    }
+#elif defined(__linux__)
+    struct winsize w;
+    if (ioctl(STDOUT_FILENO, TIOCGWINSZ, &w) == 0) {
+        return w.ws_col;
+    } else {
+        return default_width;
+    }
+#else
+    return default_width;
+#endif
+}
+}  // namespace
+
+namespace ov {
+
+ov::Any PluginConfig::get_property(const std::string& name, OptionVisibility allowed_visibility) const {
+    if (m_user_properties.find(name) != m_user_properties.end()) {
+        return m_user_properties.at(name);
+    }
+
+    auto option = get_option_ptr(name);
+    OPENVINO_ASSERT((allowed_visibility & option->get_visibility()) == option->get_visibility(),
+                    "Couldn't get unknown property: ",
+                    name);
+
+    return option->get_any();
+}
+
+void PluginConfig::set_property(const ov::AnyMap& config) {
+    OPENVINO_ASSERT(!m_is_finalized, "Setting property after config finalization is prohibited");
+
+    for (auto& [name, val] : config) {
+        get_option_ptr(name)->set_any(val);
+    }
+}
+
+void PluginConfig::set_user_property(const ov::AnyMap& config, OptionVisibility allowed_visibility) {
+    OPENVINO_ASSERT(!m_is_finalized, "Setting property after config finalization is prohibited");
+
+    for (auto& [name, val] : config) {
+        auto option = get_option_ptr(name);
+        if ((allowed_visibility & option->get_visibility()) != option->get_visibility()) {
+            OPENVINO_THROW("Couldn't set unknown property: ", name);
+        }
+        if (!option->is_valid_value(val)) {
+            OPENVINO_THROW("Invalid value: ",
+                           val.as<std::string>(),
+                           " for property: ",
+                           name,
+                           "\nProperty description: ",
+                           get_help_message(name));
+        }
+
+        m_user_properties[name] = val;
+    }
+}
+
+void PluginConfig::finalize(const IRemoteContext* context, const ov::Model* model) {
+    if (m_is_finalized)
+        return;
+
+    if (model)
+        apply_model_specific_options(context, *model);
+
+    // Copy internal properties before applying hints to ensure that
+    // a property set by hint won't be overriden by a value in user config.
+    // E.g num_streams=AUTO && hint=THROUGHPUT
+    // If we apply hints first and then copy all values from user config to internal one,
+    // then we'll get num_streams=AUTO in final config while some integer number is expected.
+    for (const auto& [name, value] : m_user_properties) {
+        auto& option = m_options_map.at(name);
+        option->set_any(value);
+    }
+
+    finalize_impl(context);
+
+#ifdef ENABLE_DEBUG_CAPS
+    apply_env_options();
+#endif
+
+    // Clear properties after finalize_impl to be able to check if a property was set by user during plugin-side
+    // finalization
+    m_user_properties.clear();
+
+    m_is_finalized = true;
+}
+
+bool PluginConfig::visit_attributes(ov::AttributeVisitor& visitor) {
+    visitor.on_attribute("m_user_properties", m_user_properties);
+    for (auto& [name, option] : m_options_map) {
+        visitor.on_attribute(name + "__internal", option);
+    }
+
+    return true;
+}
+
+void PluginConfig::apply_env_options() {
+    ov::AnyMap env_properties = read_env();
+    cleanup_unsupported(env_properties);
+    for (auto& [name, val] : env_properties) {
+        std::cout << "Non default env value for " << name << " = " << val.as<std::string>() << std::endl;
+    }
+    set_property(env_properties);
+}
+
+void PluginConfig::apply_config_options(std::string_view device_name, std::filesystem::path config_path) {
+    if (!config_path.empty()) {
+        ov::AnyMap config_properties = read_config_file(config_path, device_name);
+        cleanup_unsupported(config_properties);
+        for (auto& [name, val] : config_properties) {
+            std::cout << "Non default config value for " << name << " = " << val.as<std::string>() << std::endl;
+        }
+        set_property(config_properties);
+    }
+}
+
+ov::AnyMap PluginConfig::read_config_file(std::filesystem::path filename, std::string_view target_device_name) const {
+    if (filename.empty())
+        return {};
+
+    ov::AnyMap config;
+
+    std::ifstream ifs(filename);
+    if (!ifs.is_open()) {
+        return config;
+    }
+
+    nlohmann::json json_config;
+    try {
+        ifs >> json_config;
+    } catch (const std::exception&) {
+        return config;
+    }
+
+    DeviceIDParser parser(std::string{target_device_name});
+    for (auto item = json_config.cbegin(), end = json_config.cend(); item != end; ++item) {
+        const std::string& device_name = item.key();
+        if (DeviceIDParser(device_name).get_device_name() != parser.get_device_name())
+            continue;
+
+        const auto& item_value = item.value();
+        for (auto option = item_value.cbegin(), item_value_end = item_value.cend(); option != item_value_end;
+             ++option) {
+            config[option.key()] = option.value().get<std::string>();
+        }
+    }
+
+    return config;
+}
+
+ov::Any PluginConfig::read_env(const std::string& option_name,
+                               std::string_view prefix,
+                               const ConfigOptionBase* option) {
+    auto var_name = std::string(prefix) + option_name;
+    const auto& val = ov::util::getenv_string(var_name.c_str());
+
+    if (!val.empty()) {
+        return val;
+    } else {
+        return ov::Any();
+    }
+}
+
+ov::AnyMap PluginConfig::read_env() const {
+    ov::AnyMap config;
+
+    for (auto& [name, option] : m_options_map) {
+        if (auto val = read_env(name, m_allowed_env_prefix, option); !val.empty()) {
+            config[name] = val;
+        }
+    }
+
+    return config;
+}
+
+void PluginConfig::cleanup_unsupported(ov::AnyMap& config) const {
+    for (auto it = config.begin(); it != config.end();) {
+        auto& name = it->first;
+        auto opt_it = std::find_if(m_options_map.begin(), m_options_map.end(), [&](const OptionMapEntry& o) {
+            return o.first == name;
+        });
+        if (opt_it == m_options_map.end() || opt_it->second->get_visibility() == OptionVisibility::DEBUG_GLOBAL) {
+            it = config.erase(it);
+        } else {
+            ++it;
+        }
+    }
+}
+
+std::string PluginConfig::to_string() const {
+    std::stringstream ss;
+
+    ss << "-----------------------------------------\n";
+    ss << "PROPERTIES:\n";
+
+    for (const auto& [name, option] : m_options_map) {
+        ss << "\t" << name << ": " << option->get_any().as<std::string>() << std::endl;
+    }
+    ss << "USER PROPERTIES:\n";
+    for (const auto& [name, val] : m_user_properties) {
+        ss << "\t" << name << ": " << val.as<std::string>() << std::endl;
+    }
+
+    return ss.str();
+}
+
+void PluginConfig::print_help() const {
+    auto format_text = [](const std::string& cpp_name,
+                          std::string_view str_name,
+                          std::string_view desc,
+                          size_t max_name_width,
+                          size_t max_width) {
+        std::istringstream words(std::string{desc});
+        std::ostringstream formatted_text;
+        std::string word;
+        std::vector<std::string> words_vec;
+
+        while (words >> word) {
+            words_vec.push_back(word);
+        }
+
+        size_t j = 0;
+        size_t count_of_desc_lines = (desc.length() + max_width - 1) / max_width;
+        for (size_t i = 0; i < std::max<size_t>(2, count_of_desc_lines); i++) {
+            if (i == 0) {
+                formatted_text << std::left << std::setw(max_name_width) << cpp_name;
+            } else if (i == 1) {
+                formatted_text << std::left << std::setw(max_name_width) << str_name;
+            } else {
+                formatted_text << std::left << std::setw(max_name_width) << "";
+            }
+
+            formatted_text << " | ";
+
+            size_t line_length = max_name_width + 3;
+            for (; j < words_vec.size();) {
+                line_length += words_vec[j].size() + 1;
+                if (line_length > max_width) {
+                    break;
+                } else {
+                    formatted_text << words_vec[j] << " ";
+                }
+                j++;
+            }
+            formatted_text << "\n";
+        }
+        return formatted_text.str();
+    };
+
+    std::stringstream ss;
+    auto max_name_length_item = std::max_element(m_options_map.begin(),
+                                                 m_options_map.end(),
+                                                 [](const OptionMapEntry& a, const OptionMapEntry& b) {
+                                                     return std::get<0>(a).size() < std::get<0>(b).size();
+                                                 });
+
+    const size_t max_name_width =
+        std::max(max_name_length_item->first.size(), max_name_length_item->second->property_name.size()) + 4;
+    const size_t terminal_width = get_terminal_width();
+    // clang-format off
+    ss << std::left << std::setw(max_name_width) << "Option name" << " | Description\n";
+    ss << std::left << std::setw(terminal_width) << std::setfill('-') << "" << "\n";
+    // clang-format on
+    for (auto& [name, option] : m_options_map) {
+        ss << format_text(name, option->property_name, option->description, max_name_width, terminal_width) << "\n";
+    }
+
+    std::cout << ss.str();
+}
+
+std::string_view PluginConfig::get_help_message(const std::string& name) const {
+    return get_option_ptr(name)->description;
+}
+
+}  // namespace ov
diff --git a/src/inference/tests/unit/config_test.cpp b/src/inference/tests/unit/config_test.cpp
new file mode 100644
index 00000000000000..8e6fe94343a04f
--- /dev/null
+++ b/src/inference/tests/unit/config_test.cpp
@@ -0,0 +1,383 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include <gtest/gtest.h>
+
+#include <cstdlib>
+#include <filesystem>
+#include <fstream>
+#include <string>
+
+#include "openvino/core/any.hpp"
+#include "openvino/core/except.hpp"
+#include "openvino/core/model.hpp"
+#include "openvino/core/node_vector.hpp"
+#include "openvino/op/parameter.hpp"
+#include "openvino/runtime/iremote_context.hpp"
+#include "openvino/runtime/plugin_config.hpp"
+
+#ifdef OV_CONFIG_DECLARE_OPTION
+#    undef OV_CONFIG_DECLARE_OPTION
+#endif
+
+#ifdef OV_CONFIG_DEBUG_GLOBAL_OPTION
+#    undef OV_CONFIG_DEBUG_GLOBAL_OPTION
+#endif
+
+// Same as defined in header, just make members public
+#define OV_CONFIG_DECLARE_OPTION(PropertyNamespace, PropertyVar, Visibility, ...)                           \
+public:                                                                                                     \
+    const decltype(PropertyNamespace::PropertyVar)::value_type& get_##PropertyVar() const {                 \
+        if (m_is_finalized) {                                                                               \
+            return m_##PropertyVar.value;                                                                   \
+        } else {                                                                                            \
+            if (m_user_properties.find(PropertyNamespace::PropertyVar.name()) != m_user_properties.end()) { \
+                return m_user_properties.at(PropertyNamespace::PropertyVar.name())                          \
+                    .as<decltype(PropertyNamespace::PropertyVar)::value_type>();                            \
+            } else {                                                                                        \
+                return m_##PropertyVar.value;                                                               \
+            }                                                                                               \
+        }                                                                                                   \
+    }                                                                                                       \
+    ConfigOption<decltype(PropertyNamespace::PropertyVar)::value_type, Visibility> m_##PropertyVar{         \
+        this,                                                                                               \
+        PropertyNamespace::PropertyVar.name(),                                                              \
+        #PropertyNamespace "::" #PropertyVar,                                                               \
+        __VA_ARGS__};
+
+#ifdef ENABLE_DEBUG_CAPS
+#    define OV_CONFIG_DEBUG_GLOBAL_OPTION(PropertyNamespace, PropertyVar, ...)                              \
+    public:                                                                                                 \
+        static const decltype(PropertyNamespace::PropertyVar)::value_type& get_##PropertyVar() {            \
+            static PluginConfig::GlobalOptionInitializer init_helper(PropertyNamespace::PropertyVar.name(), \
+                                                                     m_allowed_env_prefix,                  \
+                                                                     m_##PropertyVar);                      \
+            return init_helper.m_option.value;                                                              \
+        }                                                                                                   \
+        static inline ConfigOption<decltype(PropertyNamespace::PropertyVar)::value_type,                    \
+                                   OptionVisibility::DEBUG_GLOBAL>                                          \
+            m_##PropertyVar{nullptr,                                                                        \
+                            PropertyNamespace::PropertyVar.name(),                                          \
+                            #PropertyNamespace "::" #PropertyVar,                                           \
+                            __VA_ARGS__};                                                                   \
+        OptionRegistrationHelper m_##PropertyVar##_rh{this, PropertyNamespace::PropertyVar.name(), &m_##PropertyVar};
+#else
+#    define OV_CONFIG_DEBUG_GLOBAL_OPTION(...)
+#endif
+
+using namespace ::testing;
+using namespace ov;
+
+static constexpr Property<float, PropertyMutability::RW> unsupported_property{"UNSUPPORTED_PROPERTY"};
+static constexpr Property<bool, PropertyMutability::RW> bool_property{"BOOL_PROPERTY"};
+static constexpr Property<int32_t, PropertyMutability::RW> int_property{"INT_PROPERTY"};
+static constexpr Property<std::string, PropertyMutability::RW> high_level_property{"HIGH_LEVEL_PROPERTY"};
+static constexpr Property<std::string, PropertyMutability::RW> low_level_property{"LOW_LEVEL_PROPERTY"};
+static constexpr Property<int64_t, PropertyMutability::RW> release_internal_property{"RELEASE_INTERNAL_PROPERTY"};
+
+#ifdef ENABLE_DEBUG_CAPS
+static constexpr Property<int64_t, PropertyMutability::RW> debug_property{"DEBUG_PROPERTY"};
+static constexpr Property<int32_t, PropertyMutability::RW> debug_global_property{"DEBUG_GLOBAL_PROPERTY"};
+#endif
+
+namespace {
+const std::string test_config_path = "test_debug_config_path.json";
+const std::string device_name = "SOME_DEVICE";
+
+void dump_config(const std::string& filename, const std::string& config_content) {
+    std::ofstream ofs(filename);
+    if (!ofs.is_open()) {
+        throw std::runtime_error("Can't save config file \"" + filename + "\".");
+    }
+
+    ofs << config_content;
+}
+
+void set_env(const std::string& name, const std::string& value) {
+#ifdef _WIN32
+    _putenv_s(name.c_str(), value.c_str());
+#else
+    ::setenv(name.c_str(), value.c_str(), 1);
+#endif
+}
+
+void unset_env(const std::string& name) {
+#ifdef _WIN32
+    _putenv_s(name.c_str(), "");
+#else
+    ::unsetenv(name.c_str());
+#endif
+}
+
+}  // namespace
+
+struct EmptyTestConfig : public ov::PluginConfig {
+    std::vector<std::string> get_supported_properties() const {
+        std::vector<std::string> supported_properties;
+        for (const auto& [name, option] : m_options_map) {
+            supported_properties.push_back(name);
+        }
+        return supported_properties;
+    }
+};
+
+struct NotEmptyTestConfig;
+struct NotEmptyTestConfig : public ov::PluginConfig {
+    NotEmptyTestConfig() {}
+
+    NotEmptyTestConfig(const NotEmptyTestConfig& other) : NotEmptyTestConfig() {
+        m_user_properties = other.m_user_properties;
+        for (const auto& [name, option] : other.m_options_map) {
+            m_options_map.at(name)->set_any(option->get_any());
+        }
+    }
+
+    std::vector<std::string> get_supported_properties() const {
+        std::vector<std::string> supported_properties;
+        for (const auto& [name, option] : m_options_map) {
+            supported_properties.push_back(name);
+        }
+        return supported_properties;
+    }
+
+    void finalize_impl(const IRemoteContext* context) override {
+        if (!is_set_by_user(low_level_property)) {
+            m_low_level_property.value = m_high_level_property.value;
+        }
+#ifdef ENABLE_DEBUG_CAPS
+        apply_config_options(device_name, test_config_path);
+#endif
+    }
+
+    void apply_model_specific_options(const IRemoteContext* context, const ov::Model& model) override {
+        apply_rt_info_property(high_level_property, model.get_rt_info<ov::AnyMap>("runtime_options"));
+    }
+
+    using ov::PluginConfig::get_option_ptr;
+    using ov::PluginConfig::is_set_by_user;
+
+    OV_CONFIG_RELEASE_OPTION(, bool_property, true, "")
+    OV_CONFIG_RELEASE_OPTION(, int_property, -1, "")
+    OV_CONFIG_RELEASE_OPTION(, high_level_property, "", "")
+    OV_CONFIG_RELEASE_OPTION(, low_level_property, "", "")
+    OV_CONFIG_RELEASE_INTERNAL_OPTION(, release_internal_property, 1, "")
+    OV_CONFIG_DEBUG_OPTION(, debug_property, 2, "")
+    OV_CONFIG_DEBUG_GLOBAL_OPTION(, debug_global_property, 4, "")
+};
+
+TEST(plugin_config, can_create_empty_config) {
+    ASSERT_NO_THROW(EmptyTestConfig cfg; ASSERT_EQ(cfg.get_supported_properties().size(), 0););
+}
+
+TEST(plugin_config, can_create_not_empty_config) {
+#ifdef ENABLE_DEBUG_CAPS
+    size_t expected_options_num = 7;
+#else
+    size_t expected_options_num = 5;
+#endif
+    ASSERT_NO_THROW(NotEmptyTestConfig cfg; ASSERT_EQ(cfg.get_supported_properties().size(), expected_options_num););
+}
+
+TEST(plugin_config, can_set_get_property) {
+    NotEmptyTestConfig cfg;
+    ASSERT_NO_THROW(cfg.get_bool_property());
+    ASSERT_EQ(cfg.get_bool_property(), true);
+    ASSERT_NO_THROW(cfg.set_property(bool_property(false)));
+    ASSERT_EQ(cfg.get_bool_property(), false);
+}
+
+TEST(plugin_config, throw_for_unsupported_property) {
+    NotEmptyTestConfig cfg;
+    ASSERT_ANY_THROW(cfg.get_property(unsupported_property.name()));
+    ASSERT_ANY_THROW(cfg.set_property(unsupported_property(10.0f)));
+}
+
+TEST(plugin_config, can_direct_access_to_properties) {
+    NotEmptyTestConfig cfg;
+    ASSERT_EQ(cfg.m_int_property.value, cfg.get_int_property());
+    ASSERT_NO_THROW(cfg.set_user_property(int_property(1)));
+    ASSERT_EQ(cfg.m_int_property.value, -1);  // user property doesn't impact member value until finalize() is called
+
+    cfg.m_int_property.value = 2;
+    ASSERT_EQ(cfg.get_int_property(), 1);  // stil 1 as user property was set previously
+}
+
+TEST(plugin_config, finalization_updates_member) {
+    NotEmptyTestConfig cfg;
+    ASSERT_NO_THROW(cfg.set_user_property(bool_property(false)));
+    ASSERT_EQ(cfg.m_bool_property.value, true);  // user property doesn't impact member value until finalize() is called
+
+    cfg.finalize(nullptr, {});
+
+    ASSERT_EQ(cfg.m_bool_property.value, false);  // now the value has changed
+}
+
+TEST(plugin_config, get_property_before_finalization_returns_user_property_if_set) {
+    NotEmptyTestConfig cfg;
+
+    ASSERT_EQ(cfg.get_bool_property(), true);    // default value
+    ASSERT_EQ(cfg.m_bool_property.value, true);  // default value
+
+    cfg.m_bool_property.value = false;          // update member directly
+    ASSERT_EQ(cfg.get_bool_property(), false);  // OK, return the class member value as no user property was set
+
+    ASSERT_NO_THROW(cfg.set_user_property(bool_property(true)));
+    ASSERT_TRUE(cfg.is_set_by_user(bool_property));
+    ASSERT_EQ(cfg.get_bool_property(), true);     // now user property value is returned
+    ASSERT_EQ(cfg.m_bool_property.value, false);  // but class member is not updated
+
+    cfg.finalize(nullptr, {});
+    ASSERT_EQ(cfg.get_bool_property(), cfg.m_bool_property.value);  // equal after finalization
+    ASSERT_FALSE(cfg.is_set_by_user(bool_property));                // and user property is cleared
+}
+
+TEST(plugin_config, finalization_updates_dependant_properties) {
+    NotEmptyTestConfig cfg;
+
+    cfg.set_user_property(high_level_property("value1"));
+    ASSERT_TRUE(cfg.is_set_by_user(high_level_property));
+    ASSERT_FALSE(cfg.is_set_by_user(low_level_property));
+
+    cfg.finalize(nullptr, {});
+    ASSERT_EQ(cfg.m_high_level_property.value, "value1");
+    ASSERT_EQ(cfg.m_low_level_property.value, "value1");
+    ASSERT_FALSE(cfg.is_set_by_user(high_level_property));
+    ASSERT_FALSE(cfg.is_set_by_user(low_level_property));
+}
+
+TEST(plugin_config, can_set_property_from_rt_info) {
+    NotEmptyTestConfig cfg;
+
+    RTMap rt_info = {
+        {high_level_property.name(), "value1"},
+        {int_property.name(), 10}  // int_property is not applied from rt info
+    };
+
+    auto p1 = std::make_shared<ov::op::v0::Parameter>();
+    auto r1 = std::make_shared<ov::op::v0::Result>(p1);
+    ov::Model m(ov::OutputVector{r1}, ov::ParameterVector{p1});
+    m.set_rt_info(rt_info, {"runtime_options"});
+
+    // default values
+    ASSERT_EQ(cfg.m_high_level_property.value, "");
+    ASSERT_EQ(cfg.m_low_level_property.value, "");
+    ASSERT_EQ(cfg.m_int_property.value, -1);
+
+    cfg.finalize(nullptr, &m);
+
+    ASSERT_EQ(cfg.m_high_level_property.value, "value1");
+    ASSERT_EQ(cfg.m_low_level_property.value, "value1");  // dependant is updated too
+    ASSERT_EQ(cfg.m_int_property.value, -1);              // still default
+}
+
+TEST(plugin_config, can_copy_config) {
+    NotEmptyTestConfig cfg1;
+
+    cfg1.m_high_level_property.value = "value1";
+    cfg1.m_low_level_property.value = "value2";
+    cfg1.m_int_property.value = 1;
+    cfg1.set_property(bool_property(false));
+
+    NotEmptyTestConfig cfg2 = cfg1;
+    ASSERT_EQ(cfg2.m_high_level_property.value, "value1");
+    ASSERT_EQ(cfg2.m_low_level_property.value, "value2");
+    ASSERT_EQ(cfg2.m_int_property.value, 1);
+    ASSERT_EQ(cfg2.get_bool_property(), false);  // ensure user properties are copied too
+
+    // check that cfg1 modification doesn't impact a copy
+    cfg1.set_property(high_level_property("value3"));
+    cfg1.m_int_property.value = 3;
+    ASSERT_EQ(cfg2.m_high_level_property.value, "value1");
+    ASSERT_EQ(cfg2.m_int_property.value, 1);
+}
+
+TEST(plugin_config, set_property_throw_for_non_release_options) {
+    NotEmptyTestConfig cfg;
+    ASSERT_ANY_THROW(cfg.set_user_property({release_internal_property(10)}, OptionVisibility::RELEASE));
+#ifdef ENABLE_DEBUG_CAPS
+    ASSERT_ANY_THROW(cfg.set_user_property({debug_property(10)}, OptionVisibility::RELEASE));
+#endif
+}
+
+TEST(plugin_config, visibility_is_correct) {
+    NotEmptyTestConfig cfg;
+    ASSERT_EQ(cfg.get_option_ptr(release_internal_property.name())->get_visibility(),
+              OptionVisibility::RELEASE_INTERNAL);
+    ASSERT_EQ(cfg.get_option_ptr(int_property.name())->get_visibility(), OptionVisibility::RELEASE);
+
+#ifdef ENABLE_DEBUG_CAPS
+    ASSERT_EQ(cfg.get_option_ptr(debug_property.name())->get_visibility(), OptionVisibility::DEBUG);
+#endif
+}
+
+TEST(plugin_config, can_read_from_env_with_debug_caps) {
+    try {
+        NotEmptyTestConfig cfg;
+        ASSERT_EQ(cfg.get_int_property(), -1);
+        set_env("OV_INT_PROPERTY", "10");
+        ASSERT_EQ(cfg.get_int_property(), -1);  // env is applied after finalization only for build with debug caps
+
+#ifdef ENABLE_DEBUG_CAPS
+        set_env("OV_DEBUG_PROPERTY", "20");
+        ASSERT_EQ(cfg.get_debug_property(), 2);  // same for debug option
+#endif
+
+        cfg.finalize(nullptr, nullptr);
+
+#ifdef ENABLE_DEBUG_CAPS
+        ASSERT_EQ(cfg.get_int_property(), 10);
+        ASSERT_EQ(cfg.get_debug_property(), 20);
+#else
+        ASSERT_EQ(cfg.get_int_property(), -1);  // no effect
+#endif
+    } catch (std::exception&) {
+    }
+
+    unset_env("OV_INT_PROPERTY");
+#ifdef ENABLE_DEBUG_CAPS
+    unset_env("OV_DEBUG_PROPERTY");
+#endif
+}
+
+TEST(plugin_config, can_read_from_config) {
+    const std::filesystem::path filepath = test_config_path;
+    try {
+        NotEmptyTestConfig cfg;
+        std::string config = "{\"SOME_DEVICE\":{\"DEBUG_PROPERTY\":\"20\",\"INT_PROPERTY\":\"10\"}}";
+
+        dump_config(filepath.generic_string(), config);
+
+        ASSERT_EQ(cfg.get_int_property(), -1);  // config is applied after finalization only for build with debug caps
+#ifdef ENABLE_DEBUG_CAPS
+        ASSERT_EQ(cfg.get_debug_property(), 2);  // same for debug option
+#endif
+
+        cfg.finalize(nullptr, nullptr);
+#ifdef ENABLE_DEBUG_CAPS
+        ASSERT_EQ(cfg.get_int_property(), 10);
+        ASSERT_EQ(cfg.get_debug_property(), 20);
+#else
+        ASSERT_EQ(cfg.get_int_property(), -1);  // no effect
+#endif
+    } catch (std::exception&) {
+    }
+
+    std::filesystem::remove(filepath);
+}
+
+#ifdef ENABLE_DEBUG_CAPS
+
+TEST(plugin_config, global_property_read_env_on_first_call) {
+    try {
+        set_env("OV_DEBUG_GLOBAL_PROPERTY", "10");
+        ASSERT_EQ(NotEmptyTestConfig::get_debug_global_property(), 10);
+
+        set_env("OV_DEBUG_GLOBAL_PROPERTY", "20");
+        ASSERT_EQ(NotEmptyTestConfig::get_debug_global_property(), 10);
+    } catch (std::exception&) {
+    }
+
+    unset_env("OV_DEBUG_GLOBAL_PROPERTY");
+}
+#endif
diff --git a/src/plugins/intel_cpu/src/config.cpp b/src/plugins/intel_cpu/src/config.cpp
index ef656322ef3288..b0a71005c6a16c 100644
--- a/src/plugins/intel_cpu/src/config.cpp
+++ b/src/plugins/intel_cpu/src/config.cpp
@@ -210,7 +210,7 @@ void Config::readProperties(const ov::AnyMap& prop, const ModelType modelType) {
                                ov::internal::exclusive_async_requests.name(),
                                ". Expected only true/false");
             }
-        } else if (key == ov::intel_cpu::lp_transforms_mode.name()) {
+        } else if (key == ov::internal::enable_lp_transformations.name()) {
             try {
                 lpTransformsMode = val.as<bool>() ? LPTransformsMode::On : LPTransformsMode::Off;
             } catch (ov::Exception&) {
diff --git a/src/plugins/intel_cpu/src/internal_properties.hpp b/src/plugins/intel_cpu/src/internal_properties.hpp
index 35f7729d1453d3..bfa584eb27bbf4 100644
--- a/src/plugins/intel_cpu/src/internal_properties.hpp
+++ b/src/plugins/intel_cpu/src/internal_properties.hpp
@@ -15,11 +15,6 @@ namespace ov::intel_cpu {
  */
 static constexpr Property<int32_t, PropertyMutability::RW> cpu_runtime_cache_capacity{"CPU_RUNTIME_CACHE_CAPACITY"};
 
-/**
- * @brief Allow low precision transform.
- */
-static constexpr Property<bool, PropertyMutability::RW> lp_transforms_mode{"LP_TRANSFORMS_MODE"};
-
 /**
  * @brief Enum to define possible snippets mode hints.
  */
diff --git a/src/plugins/intel_cpu/tests/functional/shared_tests_instances/behavior/ov_plugin/properties_tests.cpp b/src/plugins/intel_cpu/tests/functional/shared_tests_instances/behavior/ov_plugin/properties_tests.cpp
index 6d288d9f5ede8b..fc98a2659f9127 100644
--- a/src/plugins/intel_cpu/tests/functional/shared_tests_instances/behavior/ov_plugin/properties_tests.cpp
+++ b/src/plugins/intel_cpu/tests/functional/shared_tests_instances/behavior/ov_plugin/properties_tests.cpp
@@ -52,7 +52,7 @@ const std::vector<ov::AnyMap> cpu_inproperties = {
     {ov::hint::performance_mode(ov::hint::PerformanceMode::THROUGHPUT),
      {ov::hint::num_requests.name(), "should be int"}},
     {{ov::num_streams.name(), "OFF"}},
-    {{ov::hint::enable_cpu_pinning.name(), "OFF"}},
+    {{ov::hint::enable_cpu_pinning.name(), "NOT_BOOL"}},
 };
 
 INSTANTIATE_TEST_SUITE_P(smoke_BehaviorTests,
diff --git a/src/plugins/intel_gpu/CMakeLists.txt b/src/plugins/intel_gpu/CMakeLists.txt
index 3a847c292c30ba..3322f2f3f1a875 100644
--- a/src/plugins/intel_gpu/CMakeLists.txt
+++ b/src/plugins/intel_gpu/CMakeLists.txt
@@ -51,6 +51,7 @@ endif()
 
 if(ENABLE_GPU_DEBUG_CAPS)
     add_definitions(-DGPU_DEBUG_CONFIG=1)
+    add_definitions(-DENABLE_DEBUG_CAPS=1)
 endif()
 
 set(INTEL_GPU_TARGET_OCL_VERSION "200" CACHE STRING "Target version of OpenCL which should be used by GPU plugin")
diff --git a/src/plugins/intel_gpu/docs/gpu_debug_utils.md b/src/plugins/intel_gpu/docs/gpu_debug_utils.md
index 0708d9dd3557b7..de0d51ba0a8ba0 100644
--- a/src/plugins/intel_gpu/docs/gpu_debug_utils.md
+++ b/src/plugins/intel_gpu/docs/gpu_debug_utils.md
@@ -3,113 +3,65 @@
 This document is a list of useful debug features / tricks that might be used to find root cause of performance / functional issues. Some of them
 are available by default, but some others might require plugin recompilation.
 
-## Debug Config
-
-`Debug_config` is an infrastructure that contains several easy-to-use debugging features. It has various control parameters, which you can check from the source code `cldnn::debug_configuration`.
-
 ### How to use it
 
-First, this feature should be enabled from cmake configuration `ENABLE_DEBUG_CAPS`. When OpenVINO is released, it is turned off by default.
+First, debug features should be enabled from cmake configuration `ENABLE_DEBUG_CAPS`. When OpenVINO is released, it is turned off by default.
 
 The parameters can be set from an environment variable when calling inference engine API.
+The environment variable name is concatenation of `OV_` prefix and string identifier of corresponding ov property (for instance, one of the properties here `src/plugins/intel_gpu/include/intel_gpu/runtime/internal_properties.hpp`)
+
 
 ```
-$ OV_GPU_Verbose=1 ./benchmark_app ...      # Run benchmark_app with OV_GPU_Verbose option
-$ OV_GPU_DumpLayersPath="dump/" ./benchmark_app ...   # Run benchmark_app and store intermediate buffers into dump/ directory.
+$ OV_VERBOSE=1 ./benchmark_app ...                       # Run benchmark_app with OV_VERBOSE option
+$ OV_GPU_DUMP_TENSORS_PATH="dump/" ./benchmark_app ...   # Run benchmark_app and store intermediate buffers into dump/ directory.
 ```
 
 For Windows OS, use the following syntax:
 
 ```
 Windows Power Shell:
-> $env:OV_GPU_Verbose=1
-> .\benchmark_app.exe ...      # Run benchmark_app with OV_GPU_Verbose option
+> $env:OV_VERBOSE=1
+> .\benchmark_app.exe ...      # Run benchmark_app with OV_VERBOSE option
 
 Windows cmd.exe:
-> set "OV_GPU_Verbose=1"
-> benchmark_app.exe ...      # Run benchmark_app with OV_GPU_Verbose option
+> set "OV_VERBOSE=1"
+> benchmark_app.exe ...      # Run benchmark_app with OV_VERBOSE option
 ```
 
-### Options syntax
+Alternative approach, is to prepate config file in json format and set path to it via `OV_DEBUG_CONFIG=path` option.
+NOTE:
+    1. Options set via environment has higher priority than options from the config file.
+    2. Global options can't be activated via config to avoid mess when the finalize() call changes the value of globally visible variable which may lead to some weird behavior.
+Config example:
+```json
+{"GPU.1":{"OV_VERBOSE":"ON","PERF_COUNT":"ON"}}
+```
 
-Plugin is able to parse different naming styles for debug options:
-1. `OV_GPU_SOME_OPTION`
-2. `OV_GPU_SomeOption`
+### Option types
+Plugin config supports 4 option types:
+1. `OV_CONFIG_RELEASE_OPTION` - options that are available via public API for any kind of builds
+1. `OV_CONFIG_RELEASE_INTERNAL_OPTION` - available for any build type, but can't be set via public API.
+1. `OV_CONFIG_DEBUG_OPTION` - these options are available for the builds with `ENABLE_DEBUG_CAPS` only.
+1. `OV_CONFIG_DEBUG_GLOBAL_OPTION` - same as above, but a little bit different behavior (see below).
 
-Behavior when both versions are specified is not defined.
+The difference between "local" and "global" options is that value for local option is resolved during "finalize" call for the config class which typically happens somewhere after `Core::{compile,import,query}_model()` call. That means that the local options can be set per-model basis for the multi model pipelines if env is modified from the code for each model.
 
-Some options also allow multiple prefixes: `OV` and `OV_GPU`. `OV` prefix is intended to be used for options common for all OpenVINO components. When an option is set twice with different prefixes, then `OV_GPU` has higher priority.
+Value of the global options is read from env on the first access to the option, or set as default value if not present in environment. Global option variables are static members of the config which is needed to activate some basic debug capabilities (such as logging) in the arbitrary part of the project w/o need to pass `ExecutionConfig` object to all the places where we need to log something.
 
 ### List of parameters
 
-This is a part of the full list. To get all parameters, see OV_GPU_Help result.
-
-* `OV_GPU_Help`: Shows help message of debug config.
-* `OV_GPU_Verbose`: Verbose execution. Currently, `Verbose=1` and `2` are supported.
-* `OV_GPU_PrintMultiKernelPerf`: Prints kernel latency for multi-kernel primitives. This is turned on by setting `1`. Execution time is printed.
-* `OV_GPU_DisableUsm`: Disables the usage of usm (unified shared memory). This is turned on by setting `1`.
-* `OV_GPU_DisableOnednn`: Disables oneDNN for the hardware with XMX (If GPU does not have XMX, it does not have any effect)
-* `OV_GPU_DumpGraphs`: Dumps optimized graphs into the path that this variable points. This is turned on by setting the destination path into this variable.
-* `OV_GPU_DumpSources`: Dumps openCL sources
-* `OV_GPU_DumpLayersPath`: Enables intermediate buffer dump and store the tensors. This is turned on by setting the destination path into this variable. You can check the exact layer name from `OV_GPU_ListLayers=1`.
-* `OV_GPU_DumpLayers`: Dumps intermediate buffers only for the layers that this variable specifies. Multiple layers can be specified with a space delimiter. Dump feature should be enabled through `OV_GPU_DumpLayersPath`.
-* `OV_GPU_DumpLayersResult`: Dumps output buffers of result layers only.
-* `OV_GPU_DumpLayersDstOnly`: When dumping intermediate buffer, dumps destination buffer only. This is turned on by setting `1`.
-* `OV_GPU_DumpLayersLimitBatch`:        Limits the size of a batch to dump.
-* `OV_GPU_DryRunPath`:                  Dry runs and serializes the execution graph into the specified path.
-* `OV_GPU_BaseBatchForMemEstimation`:   Base batch size to be used in memory estimation.
-* `OV_GPU_AfterProc`:                   Runs inference after the specified process PIDs are finished, separated by space. Supported only on Linux.
-* `OV_GPU_SerialCompile`:               Serializes creating primitives and compiling kernels.
-* `OV_GPU_ForceImplType`:               Forces implementation type of a target primitive or a layer. [primitive or layout_name]:[impl_type] For primitives, `fc:onednn`, `fc:ocl`, `do:cpu`, `do:ocl`, `reduce:ocl` and `reduce:oneDNN` are supported
-* `OV_GPU_MaxKernelsPerBatch`:          Maximum number of kernels in a batch during compiling kernels.
+Full options list is defined in `src/plugins/intel_gpu/include/intel_gpu/runtime/options.inl` file. This can also be printed to console by setting `OV_HELP=1` option
 
-### How to check debug-config works
-If you are uncertain whether debug-config is working or not, you can confirm that with OV_GPU_Help. OV_GPU_Help will just show the help message and terminate the current application. If the help message is properly printed, you can basically believe that this debug config is working correctly. Please note that it requires full execution of inference because the help message is printed from GPU plugin. If you just run `benchmark_app` without any option, it will not show the benchmark_app help message, not the debug-config help message.
 
+### How to check debug-config works
+All options that are found in environment or config file are printed to stdout:
 ```
-$ OV_GPU_Help=1 ./benchmark_app -m resnet_v1.5_50.xml -d GPU
-[Step 1/11] Parsing and validating input arguments
-[ INFO ] Parsing input parameters
-[Step 2/11] Loading OpenVINO Runtime
-[ INFO ] OpenVINO:
-[ INFO ] Build ................................. 2024.2.0
-[ INFO ]
-[ INFO ] Device info:
-GPU_Debug: Config Help = 1
-GPU_Debug: Supported environment variables for debugging
-GPU_Debug:  - OV_GPU_Help                                          Print help messages
-GPU_Debug:  - OV_GPU_Verbose                                       Verbose execution
-GPU_Debug:  - OV_GPU_VerboseColor                                  Print verbose color
-GPU_Debug:  - OV_GPU_ListLayers                                    Print layers names
-GPU_Debug:  - OV_GPU_PrintMultiKernelPerf                          Print execution time of each kernel in multi-kernel primitimive
-GPU_Debug:  - OV_GPU_PrintInputDataShapes                          Print data_shapes of input layers for benchmark_app.
-GPU_Debug:  - OV_GPU_DisableUsm                                    Disable usm usage
-GPU_Debug:  - OV_GPU_DisableOnednn                                 Disable onednn for discrete GPU (no effect for integrated GPU)
-GPU_Debug:  - OV_GPU_DisableOnednnOptPostOps                       Disable onednn optimize post operators
+$ OV_VERBOSE=1 ./benchmark_app
 ...
-<application is terminated right after the help message>
-```
-
-You can also check the message from the debug-config parser. As shown below, if env variable is detected, it will print the variable name and configuration.
-```
-$ OV_GPU_Verbose=1 OV_GPU_DumpGraphs=graph/ ./benchmark_app -m resnet.xml -d GPU
-[Step 1/11] Parsing and validating input arguments
-[ INFO ] Parsing input parameters
-[Step 2/11] Loading OpenVINO Runtime
-[ INFO ] OpenVINO:
-[ INFO ] Build ................................. 2024.2.0
-[ INFO ]
-[ INFO ] Device info:
-GPU_Debug: Config Verbose = 1               # OV_GPU_Verbose is recognized
-GPU_Debug: Config DumpGraphs = graph/       # OV_GPU_DumpGraphs is recognized
-[ INFO ] GPU
-[ INFO ] Build ................................. 2024.2.0
-[ INFO ]
-[Step 3/11] Setting device configuration
+Non default env value for VERBOSE = 1
 ...
 ```
 
-
 ## Dump execution graph
 
 The execution graph (also known as a runtime graph) is a device-specific graph after all transformations applied by the plugin. It is a very useful
@@ -195,7 +147,7 @@ So it allows you to quickly check the execution time of some operation on the de
 
 *Intel_GPU* plugin allows you to dump some info about intermediate stages in the graph optimizer.
 
-* You can dump graphs with `OV_GPU_DumpGraphs` of debug config. For the usage of debug config, see the [link](#debug-config).
+* You can dump graphs with `OV_GPU_DUMP_GRAPHS_PATH` of debug config. For the usage of debug config, see the [link](#debug-config).
 
 
 For each stage, it dumps:
@@ -213,7 +165,7 @@ The main graph usually has `program_id = 0`. Graphs with other `program_id` valu
 
 Since *Intel_GPU* source tree contains only *templates* of the OpenCL™ kernels, it is quite important to get full kernels source code.
 
-* You can use `OV_GPU_DumpSources` of debug config. For the usage of debug config, see [link](#debug-config).
+* You can use `OV_GPU_DUMP_SOURCES_PATH` of debug config. For the usage of debug config, see [link](#debug-config).
 
 
 When this key is enabled, the plugin dumps multiple files with the following names:
@@ -245,17 +197,17 @@ When the source is dumped, it contains a huge amount of macros(`#define`). For r
 ## Layer in/out buffer dumps
 
 In some cases, you might want to get actual values in each layer execution to compare it with some reference blob. To do that, choose the
-`OV_GPU_DumpLayersPath` option in debug config. For the usage of debug config, see [link](#debug-config).
+`OV_GPU_DUMP_TENSORS_PATH` option in debug config. For the usage of debug config, see [link](#debug-config).
 
 As a prerequisite, enable `ENABLE_DEBUG_CAPS` from the cmake configuration.
 
-Then, check the runtime layer name by executing *benchmark_app* with `OV_GPU_Verbose=1`. It is better to check it with `OV_GPU_Verbose=1` than through IR because this may be slightly different. `OV_GPU_Verbose=1` will show the log of execution of each layer.
+Then, check the runtime layer name by executing *benchmark_app* with `OV_VERBOSE=1`. It is better to check it with `OV_VERBOSE=1` than through IR because this may be slightly different. `OV_VERBOSE=1` will show the log of execution of each layer.
 
 ```
 # As a prerequisite, enable ENABLE_DEBUG_CAPS from cmake configuration.
-export OV_GPU_DumpLayersPath=path/to/dir
-export OV_GPU_DumpLayers="layer_name_to_dump1 layer_name_to_dump2"
-export OV_GPU_DumpLayersDstOnly=1              # Set as 1 when you want to dump dest buff only
+export OV_GPU_DUMP_TENSORS_PATH=path/to/dir
+export OV_GPU_DUMP_LAYER_NAMES="layer_name_to_dump1 layer_name_to_dump2"
+export OV_GPU_DUMP_TENSORS=out              # only out tensors should be saved
 ```
 
 Dump files are named in the following convention:
@@ -271,17 +223,6 @@ shape: [b:1, f:1280, x:1, y:1, z:1, w:1, g:1] (count: 1280, original format: b_f
 For troubleshooting the accuracy, you may want to compare the results of GPU plugin and CPU plugin. For CPU dump, see [Blob dumping](https://github.com/openvinotoolkit/openvino/blob/master/src/plugins/intel_cpu/docs/debug_capabilities/blob_dumping.md)
 
 
-## Run int8 model on Gen9 HW
-
-As Gen9 HW does not have hardware acceleration, low-precision transformations are disabled by default. Therefore, quantized networks are executed in full precision (FP16 or FP32), with explicit execution of quantize operations.
-If you do not have Gen12 HW, but want to debug the network's accuracy or performance of simple operations (which does not require dp4a support), then you can enable low precision pipeline on Gen9, with one of the following approaches:
-1. Add `ov::intel_gpu::enable_lp_transformations(true)` option to the plugin config.
-2. Enforce `supports_imad = true` [here](https://github.com/openvinotoolkit/openvino/blob/master/inference-engine/thirdparty/clDNN/src/gpu/device_info.cpp#L226)
-3. Enforce `conf.enableInt8 = true` [here](https://github.com/openvinotoolkit/openvino/blob/master/inference-engine/src/cldnn_engine/cldnn_engine.cpp#L366)
-
-After that, the plugin will run exactly the same scope of transformations as on Gen12 HW and generate similar kernels (a small difference is possible due to different EUs count).
-
-
 ## Checking OpenCL execution
 
 OpenVINO GPU plugin runs on top of opencl. [opencl-intercept-layer](https://github.com/intel/opencl-intercept-layer/) is a very handy tool to check opencl execution.
diff --git a/src/plugins/intel_gpu/include/intel_gpu/graph/network.hpp b/src/plugins/intel_gpu/include/intel_gpu/graph/network.hpp
index 2a99b9dfef4b76..dabfe8ce09acd6 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/graph/network.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/graph/network.hpp
@@ -197,7 +197,7 @@ struct network {
     void set_reuse_variable_mem(bool reuse = false);
     bool is_reuse_variable_mem() { return _reuse_variable_mem; }
 
-    const ExecutionConfig& get_config() const { return _config; }
+    const ExecutionConfig& get_config() const { return _program->get_config(); }
 
     std::shared_ptr<ShapePredictor> get_shape_predictor() { return _shape_predictor; }
     void set_shape_predictor(std::shared_ptr<ShapePredictor> shape_predictor) { _shape_predictor = shape_predictor; }
@@ -210,7 +210,6 @@ struct network {
     using output_chains_map = std::map<primitive_id, std::vector<primitive_inst*>>;
     uint32_t net_id = 0;
     program::ptr _program;
-    ExecutionConfig _config;
     engine& _engine;
     stream::ptr _stream;
     std::unique_ptr<memory_pool> _memory_pool;
diff --git a/src/plugins/intel_gpu/include/intel_gpu/graph/program.hpp b/src/plugins/intel_gpu/include/intel_gpu/graph/program.hpp
index c775537a514dde..96bfff48820aaa 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/graph/program.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/graph/program.hpp
@@ -309,12 +309,11 @@ struct program {
     std::vector<primitive_id> allocating_order;
     std::unique_ptr<pass_manager> pm;
     std::unique_ptr<layout_optimizer> _layout_optimizer;
-    bool is_internal;
-    bool _is_body_program;
+    bool is_internal = false;
+    bool _is_body_program = false;
     // if subgraph can be optimized if it consists of only inputs and corresponding outputs
     bool _can_be_optimized;
     std::unique_ptr<ImplementationsCache> _impls_cache;
-    const size_t _impls_cache_capacity = 300;
     std::shared_ptr<ICompilationContext> _compilation_context;
     bool _loaded_from_cache = false;
 
diff --git a/src/plugins/intel_gpu/include/intel_gpu/plugin/common_utils.hpp b/src/plugins/intel_gpu/include/intel_gpu/plugin/common_utils.hpp
index e4340bc167ccbb..3889833aca4fc9 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/plugin/common_utils.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/plugin/common_utils.hpp
@@ -34,9 +34,8 @@ enum class TensorType {
 #define TensorValue(val) static_cast<cldnn::tensor::value_type>(val)
 
 inline bool can_use_usm_host(cldnn::engine& engine, const uint64_t total_output_bytes) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->use_usm_host == 1) { return true; }
-    GPU_DEBUG_IF(debug_config->use_usm_host == 2) { return false; }
+    GPU_DEBUG_IF(ExecutionConfig::get_usm_policy() == 1) { return true; }
+    GPU_DEBUG_IF(ExecutionConfig::get_usm_policy() == 2) { return false; }
 
     auto can_use_usm = engine.use_unified_shared_memory();
     // When output size is large, it is better not to write to usm_host directly
diff --git a/src/plugins/intel_gpu/include/intel_gpu/plugin/plugin.hpp b/src/plugins/intel_gpu/include/intel_gpu/plugin/plugin.hpp
index 869d32825b8761..cec27660baa2b4 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/plugin/plugin.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/plugin/plugin.hpp
@@ -43,7 +43,6 @@ class Plugin : public ov::IPlugin {
 
     bool is_metric(const std::string& name) const;
     ov::Any get_metric(const std::string& name, const ov::AnyMap& arguments) const;
-    void set_cache_info(const std::shared_ptr<const ov::Model>& model, ExecutionConfig& properties) const;
 
 public:
     Plugin();
diff --git a/src/plugins/intel_gpu/include/intel_gpu/plugin/program_builder.hpp b/src/plugins/intel_gpu/include/intel_gpu/plugin/program_builder.hpp
index 51087405f09769..389c7f7e2b54a1 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/plugin/program_builder.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/plugin/program_builder.hpp
@@ -79,7 +79,7 @@ struct PerfCounter {
 
 class ProgramBuilder final {
 public:
-    ProgramBuilder(std::shared_ptr<ov::Model> model, cldnn::engine& engine, const ExecutionConfig& config, bool partialBuild = false,
+    ProgramBuilder(std::shared_ptr<ov::Model> model, cldnn::engine& engine, const ExecutionConfig& config,
             std::shared_ptr<ov::threading::IStreamsExecutor> task_executor = nullptr,
             std::shared_ptr<cldnn::ICompilationContext> compilation_context = nullptr,
             bool innerProgram = false);
@@ -137,8 +137,7 @@ class ProgramBuilder final {
 
     void add_primitive(const ov::Node& op, std::shared_ptr<cldnn::primitive> prim, std::vector<std::string> aliases = {});
 
-    bool use_new_shape_infer() const { return allow_new_shape_infer; }
-    bool requires_new_shape_infer(const std::shared_ptr<ov::Node>& op) const;
+    bool use_new_shape_infer() const { return m_config.get_allow_new_shape_infer(); }
     bool is_inner_program() const { return m_is_inner_program; }
     bool is_query_mode() { return queryMode; }
 
@@ -156,8 +155,6 @@ class ProgramBuilder final {
     std::shared_ptr<cldnn::topology> m_topology;
     CustomLayerMap m_custom_layers;
 
-    bool allow_new_shape_infer = false;
-
     bool queryMode;
 
     std::shared_ptr<ov::threading::IStreamsExecutor> m_task_executor;
@@ -171,8 +168,7 @@ class ProgramBuilder final {
     void prepare_build();
     void cleanup_build();
 
-    // TODO(eunsoo): remove createTopolpgyOnly argument and add another method to create topology from ngraph function
-    std::shared_ptr<cldnn::program> build(const std::vector<std::shared_ptr<ov::Node>>& ops, bool partialBuild = false, bool innerProgram = false);
+    std::shared_ptr<cldnn::program> build(const std::vector<std::shared_ptr<ov::Node>>& ops, bool innerProgram = false);
 
     void CreateSingleLayerPrimitive(const std::shared_ptr<ov::Node>& op);
 };
diff --git a/src/plugins/intel_gpu/include/intel_gpu/plugin/remote_context.hpp b/src/plugins/intel_gpu/include/intel_gpu/plugin/remote_context.hpp
index 8440bd6824ef9e..8f7e7ac45bca2e 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/plugin/remote_context.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/plugin/remote_context.hpp
@@ -19,7 +19,6 @@
 #include <string>
 #include <map>
 #include <memory>
-#include <atomic>
 
 namespace ov::intel_gpu {
 
@@ -37,6 +36,7 @@ class RemoteContextImpl : public ov::IRemoteContext {
     ov::SoPtr<ov::IRemoteTensor> create_tensor(const ov::element::Type& type, const ov::Shape& shape, const ov::AnyMap& params) override;
 
     cldnn::engine& get_engine() { return *m_engine; }
+    const cldnn::engine& get_engine() const { return *m_engine; }
     ov::intel_gpu::gpu_handle_param get_external_queue() const { return m_external_queue; }
 
     cldnn::memory::ptr try_get_cached_memory(size_t hash);
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/debug_configuration.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/debug_configuration.hpp
index 2ce1397c44bb68..4367d2062d7325 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/debug_configuration.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/debug_configuration.hpp
@@ -4,12 +4,10 @@
 
 #pragma once
 #include <cstring>
-#include <mutex>
-#include <vector>
-#include <set>
-#include <string>
 #include <iostream>
+#include <filesystem>
 
+#include "intel_gpu/runtime/execution_config.hpp"
 namespace ov::intel_gpu {
 
 // Verbose log levels:
@@ -39,145 +37,65 @@ enum class LogLevel : int8_t {
     TRACE_DETAIL = 4
 };
 
+std::ostream& get_verbose_stream();
 }  // namespace ov::intel_gpu
 
 #ifdef GPU_DEBUG_CONFIG
-#if defined(_WIN32)
-#define SEPARATE '\\'
-#else
-#define SEPARATE '/'
-#endif
-#define GPU_FILENAME (strrchr(__FILE__, SEPARATE) ? strrchr(__FILE__, SEPARATE) + 1 : __FILE__)
+
+namespace color {
+static constexpr const char dark_gray[] = "\033[1;30m";
+static constexpr const char blue[]      = "\033[1;34m";
+static constexpr const char purple[]    = "\033[1;35m";
+static constexpr const char cyan[]      = "\033[1;36m";
+static constexpr const char reset[]     = "\033[0m";
+}  // namespace color
+
+static constexpr const char prefix[] = "GPU_Debug: ";
+
 #define GPU_DEBUG_IF(cond) if (cond)
+#define GPU_DEBUG_VALUE_OR(debug_value, release_value) debug_value
 #define GPU_DEBUG_CODE(...) __VA_ARGS__
+
 #define GPU_DEBUG_DEFINE_MEM_LOGGER(stage) \
-    cldnn::instrumentation::mem_usage_logger mem_logger{stage, cldnn::debug_configuration::get_instance()->verbose >= 2};
-#define GPU_DEBUG_PROFILED_STAGE(stage) \
-    auto stage_prof = cldnn::instrumentation::profiled_stage<primitive_inst>(\
-        !cldnn::debug_configuration::get_instance()->dump_profiling_data.empty(), *this, stage)
+    cldnn::instrumentation::mem_usage_logger mem_logger{stage, ov::intel_gpu::ExecutionConfig::get_verbose() >= 2};
+
+#define GPU_DEBUG_PROFILED_STAGE(stage)                                       \
+    auto stage_prof = cldnn::instrumentation::profiled_stage<primitive_inst>( \
+        !get_config().get_dump_profiling_data_path().empty(), *this, stage)
+
 #define GPU_DEBUG_PROFILED_STAGE_CACHE_HIT(val) stage_prof.set_cache_hit(val)
 #define GPU_DEBUG_PROFILED_STAGE_MEMALLOC_INFO(info) stage_prof.add_memalloc_info(info)
 
-#define GPU_DEBUG_LOG_RAW_INT(min_verbose_level) if (cldnn::debug_configuration::get_instance()->verbose >= min_verbose_level) \
-    ((cldnn::debug_configuration::get_instance()->verbose_color == 0) ? GPU_DEBUG_LOG_PREFIX : GPU_DEBUG_LOG_COLOR_PREFIX)
-#define GPU_DEBUG_LOG_RAW(min_verbose_level) GPU_DEBUG_LOG_RAW_INT(static_cast<std::underlying_type<ov::intel_gpu::LogLevel>::type>(min_verbose_level))
-#define GPU_DEBUG_LOG_PREFIX  \
-    *cldnn::debug_configuration::verbose_stream << cldnn::debug_configuration::prefix << GPU_FILENAME << ":" <<__LINE__ << ":" << __func__ << ": "
-#define GPU_DEBUG_LOG_COLOR_PREFIX  *cldnn::debug_configuration::verbose_stream << DARK_GRAY << cldnn::debug_configuration::prefix << \
-    BLUE << GPU_FILENAME << ":" << PURPLE <<  __LINE__ << ":" << CYAN << __func__ << ": " << RESET
-#define DARK_GRAY   "\033[1;30m"
-#define BLUE        "\033[1;34m"
-#define PURPLE      "\033[1;35m"
-#define CYAN        "\033[1;36m"
-#define RESET       "\033[0m"
+#define GPU_DEBUG_LOG_PREFIX ov::intel_gpu::get_verbose_stream() \
+                             << prefix \
+                             << std::filesystem::path(__FILE__).filename().generic_string() << ":" \
+                             << std::to_string(__LINE__) << ":" \
+                             << __func__ << ": "
+
+#define GPU_DEBUG_LOG_COLOR_PREFIX ov::intel_gpu::get_verbose_stream() \
+                                   << color::dark_gray << std::string(prefix) \
+                                   << color::blue << std::filesystem::path(__FILE__).filename().generic_string() << ":" \
+                                   << color::purple << std::to_string(__LINE__) << ":" \
+                                   << color::cyan << __func__ << ": " << color::reset
+
+#define GPU_DEBUG_LOG_RAW_INT(min_verbose_level) if (ov::intel_gpu::ExecutionConfig::get_verbose() >= min_verbose_level) \
+    (ov::intel_gpu::ExecutionConfig::get_verbose_color() ? GPU_DEBUG_LOG_COLOR_PREFIX : GPU_DEBUG_LOG_PREFIX)
+
+#define GPU_DEBUG_LOG_RAW(min_verbose_level) \
+    GPU_DEBUG_LOG_RAW_INT(static_cast<std::underlying_type<ov::intel_gpu::LogLevel>::type>(min_verbose_level))
 #else
 #define GPU_DEBUG_IF(cond) if (0)
+#define GPU_DEBUG_VALUE_OR(debug_value, release_value) release_value
 #define GPU_DEBUG_CODE(...)
 #define GPU_DEBUG_DEFINE_MEM_LOGGER(stage)
 #define GPU_DEBUG_PROFILED_STAGE(stage)
 #define GPU_DEBUG_PROFILED_STAGE_CACHE_HIT(val)
 #define GPU_DEBUG_PROFILED_STAGE_MEMALLOC_INFO(info)
-#define GPU_DEBUG_LOG_RAW(min_verbose_level) if (0) *cldnn::debug_configuration::verbose_stream << cldnn::debug_configuration::prefix
+#define GPU_DEBUG_LOG_RAW(min_verbose_level) if (0) ov::intel_gpu::get_verbose_stream()
 #endif
 
-// Macro below is inserted to avoid unused variable warning when GPU_DEBUG_CONFIG is OFF
-#define GPU_DEBUG_GET_INSTANCE(name) auto name = cldnn::debug_configuration::get_instance(); (void)(name);
-
 #define GPU_DEBUG_COUT              GPU_DEBUG_LOG_RAW(ov::intel_gpu::LogLevel::DISABLED)
 #define GPU_DEBUG_INFO              GPU_DEBUG_LOG_RAW(ov::intel_gpu::LogLevel::INFO)
 #define GPU_DEBUG_LOG               GPU_DEBUG_LOG_RAW(ov::intel_gpu::LogLevel::LOG)
 #define GPU_DEBUG_TRACE             GPU_DEBUG_LOG_RAW(ov::intel_gpu::LogLevel::TRACE)
 #define GPU_DEBUG_TRACE_DETAIL      GPU_DEBUG_LOG_RAW(ov::intel_gpu::LogLevel::TRACE_DETAIL)
-
-namespace cldnn {
-
-class debug_configuration {
-private:
-    debug_configuration();
-
-public:
-    static const char *prefix;
-    int help;                                                   // Print help messages
-    int verbose;                                                // Verbose execution
-    int verbose_color;                                          // Print verbose color
-    std::string verbose_file;                                   // Verbose log to file
-    int list_layers;                                            // Print list layers
-    int print_multi_kernel_perf;                                // Print execution time of each kernel in multi-kernel primitimive
-    int print_input_data_shapes;                                // Print the input data_shape for benchmark_app.
-    int disable_usm;                                            // Disable usm usage
-    int disable_onednn;                                         // Disable onednn for discrete GPU (no effect for integrated GPU)
-    int disable_onednn_opt_post_ops;                            // Disable onednn optimize post operators
-    std::string dump_profiling_data;                            // Enables dump of extended performance profiling to specified dir
-    int dump_profiling_data_per_iter;                           // Enables dump of extended performance profiling to specified dir for each iteration
-    int host_time_profiling;                                    // Enables measurement of scheduling time spend on the host
-    std::string dump_graphs;                                    // Dump optimized graph
-    std::string dump_sources;                                   // Dump opencl sources
-    std::string dump_layers_path;                               // Enable dumping intermediate buffers and set the dest path
-    std::vector<std::string> dump_layers;                       // Dump intermediate buffers of specified layers only
-    std::string dry_run_path;                                   // Dry run and serialize execution graph into the specified path
-    int dump_layers_dst_only;                                   // Dump only output of layers
-    int dump_layers_result;                                     // Dump result layers
-    int dump_layers_input;                                      // Dump input layers
-    int dump_layers_limit_batch;                                // Limit the size of batch to dump
-    int dump_layers_raw;                                        // Dump raw data.
-    int dump_layers_binary;                                     // Dump binary data.
-    int dump_memory_pool;                               // Dump memory pool status at each iteration
-    std::set<int64_t> dump_memory_pool_iters;           // List of iteration's memory pool status
-    std::string dump_memory_pool_path;                  // Enable dumping memory pool status to csv file and set the dest path
-    int base_batch_for_memory_estimation;                       // Base batch size to be used in memory estimation
-    std::vector<std::string> after_proc;                        // Start inference after the listed processes
-    int serialize_compile;                                      // Serialize creating primitives and compiling kernels
-    std::vector<std::string> forced_impl_types;                 // Force implementation type either ocl or onednn
-    int max_kernels_per_batch;                                  // Maximum number of kernels in a batch during compiling kernels
-    int impls_cache_capacity;                                   // The maximum number of entries in the kernel impl cache
-    int enable_sdpa;                                            // Allows to control SDPA decomposition
-    int disable_async_compilation;                              // Disable async compilation
-    int disable_winograd_conv;                                  // Disable Winograd conv
-    int disable_dynamic_impl;                                   // Disable dynamic implementation
-    int disable_runtime_buffer_fusing;                          // Disable runtime buffer fusing
-    int disable_memory_reuse;                                   // Disable memmory reuse among layers
-    int disable_build_time_weight_reorder_for_dynamic_nodes;    // Disable build time weight reordering for dynamic nodes
-    int disable_runtime_skip_reorder;                           // Disable runtime skip reorder
-    int disable_primitive_fusing;                               // Disable primitive fusing
-    int disable_fake_alignment;                                 // Disable fake alignment
-    int use_usm_host;                                           // Set explicit usm_host usage for network input and output
-    std::vector<std::string> dynamic_quantize_layers_without_onednn;  // Specify Fully-connected layers which enable Dynamic quantization
-    int use_kv_cache_compression;                               // Enable KV-cache compression
-    int dynamic_quantize_group_size;                            // Enable Dynamic quantization for fully connected primitive by specified group size
-    int dynamic_quantize_asym;                                  // Use asymmetric dynamic quantization
-    int disable_horizontal_fc_fusion;                           // Disable fc horizontal fusion
-    int disable_fc_swiglu_fusion;                               // Disable swiglu fusion to fc
-    std::set<int64_t> dump_iteration;                           // Dump n-th execution of network.
-    std::vector<std::string> load_layers_raw_dump;              // List of layers to load dumped raw binary and filenames
-    static const debug_configuration *get_instance();
-    bool is_target_dump_prof_data_iteration(int64_t iteration) const;
-    std::vector<std::string> get_filenames_for_matched_layer_loading_binaries(const std::string& id) const;
-    std::string get_name_for_dump(const std::string& file_name) const;
-    bool is_layer_for_dumping(const std::string& layerName, bool is_output = false, bool is_input = false) const;
-    bool is_target_iteration(int64_t iteration) const;
-    std::string get_matched_from_filelist(const std::vector<std::string>& file_names, std::string pattern) const;
-    bool is_layer_name_matched(const std::string& layer_name, const std::string& pattern) const;
-
-    struct memory_preallocation_params {
-        bool is_initialized = false;
-
-        // Iterations mode preallocation
-        size_t next_iters_preallocation_count = 0;
-        size_t max_per_iter_size = 0;
-        size_t max_per_dim_diff = 0;
-
-        // Percentage mode preallocation
-        float buffers_preallocation_ratio = 0.0f;
-    } mem_preallocation_params;
-
-    struct dump_profiling_data_iter_params {
-        bool is_enabled = false;
-        int64_t start = 0;
-        int64_t end = 0;
-    } dump_prof_data_iter_params;
-
-    static std::ostream* verbose_stream;
-    static const int DYNAMIC_QUANTIZE_GROUP_SIZE_NOT_SET = -2;
-};
-
-}  // namespace cldnn
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/execution_config.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/execution_config.hpp
index 96e09605eaa998..fe7f8547d433d0 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/execution_config.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/execution_config.hpp
@@ -1,177 +1,54 @@
-// Copyright (C) 2022 Intel Corporation
+// Copyright (C) 2024 Intel Corporation
 // SPDX-License-Identifier: Apache-2.0
 //
 
 #pragma once
 
+#include "openvino/core/any.hpp"
+#include "openvino/runtime/plugin_config.hpp"
+#include "intel_gpu/runtime/device_info.hpp"
 #include "intel_gpu/runtime/internal_properties.hpp"
-#include "intel_gpu/runtime/device.hpp"
+#include "openvino/runtime/internal_properties.hpp"
+#include <thread>
 
 namespace ov::intel_gpu {
 
-enum class PropertyVisibility {
-    INTERNAL = 0,
-    PUBLIC = 1
-};
-
-inline std::ostream& operator<<(std::ostream& os, const PropertyVisibility& visibility) {
-    switch (visibility) {
-    case PropertyVisibility::PUBLIC: os << "PUBLIC"; break;
-    case PropertyVisibility::INTERNAL: os << "INTERNAL"; break;
-    default: os << "UNKNOWN"; break;
-    }
-
-    return os;
-}
-
-class BaseValidator {
-public:
-    using Ptr = std::shared_ptr<BaseValidator>;
-    virtual ~BaseValidator() = default;
-    virtual bool is_valid(const ov::Any& v) const = 0;
-};
-
-class FuncValidator : public BaseValidator {
-public:
-explicit FuncValidator(std::function<bool(const ov::Any)> func) : m_func(func) { }
-    bool is_valid(const ov::Any& v) const override {
-        return m_func(v);
-    }
-
-private:
-    std::function<bool(const ov::Any)> m_func;
-};
-
-// PropertyTypeValidator ensures that value can be converted to given property type
-template<typename T>
-class PropertyTypeValidator : public BaseValidator {
-public:
-    bool is_valid(const ov::Any& v) const override {
-        try {
-            v.as<T>();
-            return true;
-        } catch (ov::Exception&) {
-            return false;
-        }
-    }
-};
-
-class ExecutionConfig {
-public:
+struct ExecutionConfig : public ov::PluginConfig {
     ExecutionConfig();
     ExecutionConfig(std::initializer_list<ov::AnyMap::value_type> values) : ExecutionConfig() { set_property(ov::AnyMap(values)); }
     explicit ExecutionConfig(const ov::AnyMap& properties) : ExecutionConfig() { set_property(properties); }
     explicit ExecutionConfig(const ov::AnyMap::value_type& property) : ExecutionConfig() { set_property(property); }
 
-    void set_default();
-    void set_property(const ov::AnyMap& properties);
-    void set_user_property(const ov::AnyMap& properties);
-    Any get_property(const std::string& name) const;
-    bool is_set_by_user(const std::string& name) const;
-    bool is_supported(const std::string& name) const;
-    void register_property_impl(const std::pair<std::string, ov::Any>& propertiy, PropertyVisibility visibility, BaseValidator::Ptr validator);
-
-    template <PropertyVisibility visibility, typename... PropertyInitializer, typename std::enable_if<(sizeof...(PropertyInitializer) == 0), bool>::type = true>
-    void register_property_impl() { }
-
-    template <PropertyVisibility visibility, typename T,  PropertyMutability mutability, typename ValueT, typename... PropertyInitializer>
-    void register_property_impl(const std::tuple<ov::Property<T, mutability>, ValueT>& property, PropertyInitializer&&... properties) {
-        auto p = std::get<0>(property)(std::get<1>(property));
-        auto v = std::dynamic_pointer_cast<BaseValidator>(std::make_shared<PropertyTypeValidator<T>>());
-        register_property_impl(std::move(p), visibility, std::move(v));
-        register_property_impl<visibility>(properties...);
-    }
+    // Default operators copy config as is including finalized flag state
+    // In case if the config need updates after finalization clone() method shall be used as it resets finalized flag value.
+    // That's needed to avoid unexpected options update as we call finalization twice: in transformation pipeline
+    // and in cldnn::program c-tor (which is needed to handle unit tests mainly). So this second call may cause unwanted side effects
+    // if config is not marked as finalized, which could have easily happened if copy operator reset finalization flag
+    ExecutionConfig(const ExecutionConfig& other);
+    ExecutionConfig& operator=(const ExecutionConfig& other);
+    ExecutionConfig clone() const;
 
-    template <PropertyVisibility visibility,
-              typename T,
-              PropertyMutability mutability,
-              typename ValueT,
-              typename ValidatorT,
-              typename... PropertyInitializer>
-    typename std::enable_if<std::is_base_of<BaseValidator, ValidatorT>::value, void>::type
-    register_property_impl(const std::tuple<ov::Property<T, mutability>, ValueT, ValidatorT>& property, PropertyInitializer&&... properties) {
-        auto p = std::get<0>(property)(std::get<1>(property));
-        auto v = std::dynamic_pointer_cast<BaseValidator>(std::make_shared<ValidatorT>(std::get<2>(property)));
-        register_property_impl(std::move(p), visibility, std::move(v));
-        register_property_impl<visibility>(properties...);
-    }
+    void finalize(cldnn::engine& engine);
+    using ov::PluginConfig::finalize;
 
-    template <PropertyVisibility visibility,
-              typename T,
-              PropertyMutability mutability,
-              typename ValueT,
-              typename ValidatorT,
-              typename... PropertyInitializer>
-    typename std::enable_if<std::is_same<std::function<bool(const ov::Any&)>, ValidatorT>::value, void>::type
-    register_property_impl(const std::tuple<ov::Property<T, mutability>, ValueT, ValidatorT>& property, PropertyInitializer&&... properties) {
-        auto p = std::get<0>(property)(std::get<1>(property));
-        auto v = std::dynamic_pointer_cast<BaseValidator>(std::make_shared<FuncValidator>(std::get<2>(property)));
-        register_property_impl(std::move(p), visibility, std::move(v));
-        register_property_impl<visibility>(properties...);
-    }
+    const ov::AnyMap& get_user_properties() const { return m_user_properties; }
 
-    template <PropertyVisibility visibility, typename... PropertyInitializer>
-    void register_property(PropertyInitializer&&... properties) {
-        register_property_impl<visibility>(properties...);
-    }
-
-    template <typename... Properties>
-    util::EnableIfAllStringAny<void, Properties...> set_property(Properties&&... properties) {
-        set_property(ov::AnyMap{std::forward<Properties>(properties)...});
-    }
-
-    template <typename... Properties>
-    util::EnableIfAllStringAny<void, Properties...> set_user_property(Properties&&... properties) {
-        set_user_property(ov::AnyMap{std::forward<Properties>(properties)...});
-    }
-
-    template <typename T, PropertyMutability mutability>
-    bool is_set_by_user(const ov::Property<T, mutability>& property) const {
-        return is_set_by_user(property.name());
-    }
-
-    template <typename T, PropertyMutability mutability>
-    T get_property(const ov::Property<T, mutability>& property) const {
-        return get_property(property.name()).template as<T>();
-    }
+protected:
+    void finalize_impl(const IRemoteContext* context) override;
+    void apply_model_specific_options(const IRemoteContext* context, const ov::Model& model) override;
+    void apply_rt_info(const IRemoteContext* context, const ov::RTMap& rt_info, bool is_llm);
 
     void apply_user_properties(const cldnn::device_info& info);
-
-    // Note that RT info property value has lower priority than values set by user via core.set_property or passed to compile_model call
-    // So this method should be called after setting all user properties, but before apply_user_properties() call.
-    void apply_rt_info(const cldnn::device_info& info, const ov::RTMap& rt_info, const bool is_llm);
-
-    std::string to_string() const;
-
-protected:
     void apply_hints(const cldnn::device_info& info);
     void apply_execution_hints(const cldnn::device_info& info);
     void apply_performance_hints(const cldnn::device_info& info);
     void apply_priority_hints(const cldnn::device_info& info);
-    void apply_debug_options(const cldnn::device_info& info);
-
-    template <typename T, PropertyMutability mutability>
-    void apply_rt_info_property(const ov::Property<T, mutability>& property, const ov::RTMap& rt_info) {
-        if (!is_set_by_user(property)) {
-            auto rt_info_val = rt_info.find(property.name());
-            if (rt_info_val != rt_info.end()) {
-                set_user_property(property(rt_info_val->second.template as<T>()));
-            }
-        }
-    }
 
-private:
-    ov::AnyMap internal_properties;
-    ov::AnyMap user_properties;
-
-    std::map<std::string, PropertyVisibility> supported_properties;
-    std::map<std::string, BaseValidator::Ptr> property_validators;
-
-    bool finalized = false;
+    #include "intel_gpu/runtime/options.inl"
 };
 
 }  // namespace ov::intel_gpu
 
 namespace cldnn {
 using ov::intel_gpu::ExecutionConfig;
-}  // namespace cldnn
+}
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/internal_properties.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/internal_properties.hpp
index 765333e971842e..5ef5f00b636f8d 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/internal_properties.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/internal_properties.hpp
@@ -4,6 +4,7 @@
 
 #pragma once
 
+#include "intel_gpu/runtime/shape_predictor.hpp"
 #include "openvino/runtime/properties.hpp"
 #include "openvino/runtime/intel_gpu/properties.hpp"
 
@@ -35,6 +36,83 @@ inline std::ostream& operator<<(std::ostream& os, const QueueTypes& val) {
     return os;
 }
 
+inline std::istream& operator>>(std::istream& is, QueueTypes& val) {
+    std::string str;
+    is >> str;
+    if (str == "in-order") {
+        val = QueueTypes::in_order;
+    } else if (str == "out-of-order") {
+        val = QueueTypes::out_of_order;
+    } else {
+        OPENVINO_THROW("Unsupported QueueTypes value: ", str);
+    }
+    return is;
+}
+
+enum class DumpFormat : uint8_t {
+    binary = 0,
+    text = 1,
+    text_raw = 2,
+};
+
+inline std::ostream& operator<<(std::ostream& os, const DumpFormat& val) {
+    switch (val) {
+        case DumpFormat::binary: os << "binary"; break;
+        case DumpFormat::text: os << "text"; break;
+        case DumpFormat::text_raw: os << "text_raw"; break;
+        default: os << "unknown";
+    }
+
+    return os;
+}
+
+inline std::istream& operator>>(std::istream& is, DumpFormat& val) {
+    std::string str;
+    is >> str;
+    if (str == "binary") {
+        val = DumpFormat::binary;
+    } else if (str == "text") {
+        val = DumpFormat::text;
+    } else if (str == "text_raw") {
+        val = DumpFormat::text_raw;
+    } else {
+        OPENVINO_THROW("Unsupported DumpFormat value: ", str);
+    }
+    return is;
+}
+
+enum class DumpTensors : uint8_t {
+    all = 0,
+    in = 1,
+    out = 2,
+};
+
+inline std::ostream& operator<<(std::ostream& os, const DumpTensors& val) {
+    switch (val) {
+        case DumpTensors::all: os << "all"; break;
+        case DumpTensors::in: os << "in"; break;
+        case DumpTensors::out: os << "out"; break;
+        default: os << "unknown";
+    }
+
+    return os;
+}
+
+inline std::istream& operator>>(std::istream& is, DumpTensors& val) {
+    std::string str;
+    is >> str;
+    if (str == "all") {
+        val = DumpTensors::all;
+    } else if (str == "in") {
+        val = DumpTensors::in;
+    } else if (str == "out") {
+        val = DumpTensors::out;
+    } else {
+        OPENVINO_THROW("Unsupported DumpTensors value: ", str);
+    }
+    return is;
+}
+
 /**
  * @brief Defines queue type that must be used for model execution
  */
@@ -45,17 +123,48 @@ static constexpr Property<bool, PropertyMutability::RW> optimize_data{"GPU_OPTIM
 static constexpr Property<bool, PropertyMutability::RW> allow_static_input_reorder{"GPU_ALLOW_STATIC_INPUT_REORDER"};
 static constexpr Property<bool, PropertyMutability::RW> partial_build_program{"GPU_PARTIAL_BUILD"};
 static constexpr Property<bool, PropertyMutability::RW> allow_new_shape_infer{"GPU_ALLOW_NEW_SHAPE_INFER"};
-static constexpr Property<bool, PropertyMutability::RW> use_only_static_kernels_for_dynamic_shape{"GPU_USE_ONLY_STATIC_KERNELS_FOR_DYNAMIC_SHAPE"};
-static constexpr Property<std::string, PropertyMutability::RW> dump_graphs{"GPU_DUMP_GRAPHS"};
 static constexpr Property<std::vector<std::string>, PropertyMutability::RW> custom_outputs{"GPU_CUSTOM_OUTPUTS"};
 static constexpr Property<ImplForcingMap, PropertyMutability::RW> force_implementations{"GPU_FORCE_IMPLEMENTATIONS"};
 static constexpr Property<std::string, PropertyMutability::RW> config_file{"CONFIG_FILE"};
-static constexpr Property<bool, PropertyMutability::RW> enable_lp_transformations{"LP_TRANSFORMS_MODE"};
-static constexpr Property<size_t, PropertyMutability::RW> max_dynamic_batch{"DYN_BATCH_LIMIT"};
-static constexpr Property<bool, PropertyMutability::RW> nv12_two_inputs{"GPU_NV12_TWO_INPUTS"};
 static constexpr Property<float, PropertyMutability::RW> buffers_preallocation_ratio{"GPU_BUFFERS_PREALLOCATION_RATIO"};
 static constexpr Property<size_t, PropertyMutability::RW> max_kernels_per_batch{"GPU_MAX_KERNELS_PER_BATCH"};
-static constexpr Property<bool, PropertyMutability::RW> use_onednn{"USE_ONEDNN"};
+static constexpr Property<bool, PropertyMutability::RW> use_onednn{"GPU_USE_ONEDNN"};
+
+static constexpr Property<bool, ov::PropertyMutability::RW> help{"HELP"};
+static constexpr Property<size_t, ov::PropertyMutability::RW> verbose{"VERBOSE"};
+static constexpr Property<bool, ov::PropertyMutability::RW> verbose_color{"VERBOSE_COLOR"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> debug_config{"GPU_DEBUG_CONFIG"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> log_to_file{"GPU_LOG_TO_FILE"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_usm{"GPU_DISABLE_USM"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_onednn_post_ops_opt{"GPU_DISABLE_ONEDNN_POST_OPS_OPT"};
+static constexpr Property<std::string, PropertyMutability::RW> dump_graphs_path{"GPU_DUMP_GRAPHS_PATH"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> dump_profiling_data_path{"GPU_DUMP_PROFILING_DATA_PATH"};
+static constexpr Property<bool, ov::PropertyMutability::RW> dump_profiling_data_per_iter{"GPU_DUMP_PROFILING_DATA_PER_ITER"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> dump_sources_path{"GPU_DUMP_SOURCES_PATH"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> dump_tensors_path{"GPU_DUMP_TENSORS_PATH"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> dry_run_path{"GPU_DRY_RUN_PATH"};
+static constexpr Property<DumpTensors, ov::PropertyMutability::RW> dump_tensors{"GPU_DUMP_TENSORS"};
+static constexpr Property<std::vector<std::string>, ov::PropertyMutability::RW> dump_layer_names{"GPU_DUMP_LAYER_NAMES"};
+static constexpr Property<DumpFormat, ov::PropertyMutability::RW> dump_tensors_format{"GPU_DUMP_TENSORS_FORMAT"};
+static constexpr Property<std::string, ov::PropertyMutability::RW> dump_memory_pool_path{"GPU_DUMP_MEMORY_POOL_PATH"};
+static constexpr Property<bool, ov::PropertyMutability::RW> dump_memory_pool{"GPU_DUMP_MEMORY_POOL"};
+static constexpr Property<int32_t, ov::PropertyMutability::RW> dump_batch_limit{"GPU_DUMP_BATCH_LIMIT"};
+static constexpr Property<std::set<int64_t>, ov::PropertyMutability::RW> dump_iterations{"GPU_DUMP_ITERATIONS"};
+static constexpr Property<size_t, ov::PropertyMutability::RW> host_time_profiling{"GPU_HOST_TIME_PROFILING"};
+static constexpr Property<size_t, ov::PropertyMutability::RW> impls_cache_capacity{"GPU_IMPLS_CACHE_CAPACITY"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_async_compilation{"GPU_DISABLE_ASYNC_COMPILATION"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_runtime_buffer_fusing{"GPU_DISABLE_RUNTIME_BUFFER_FUSING"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_memory_reuse{"GPU_DISABLE_MEMORY_REUSE"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_post_ops_fusions{"GPU_DISABLE_POST_OPS_FUSIONS"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_horizontal_fc_fusion{"GPU_DISABLE_HORIZONTAL_FC_FUSION"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_fc_swiglu_fusion{"GPU_DISABLE_FC_SWIGLU_FUSION"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_fake_alignment{"GPU_DISABLE_FAKE_ALIGNMENT"};
+static constexpr Property<bool, ov::PropertyMutability::RW> disable_runtime_skip_reorder{"GPU_DISABLE_RUNTIME_SKIP_REORDER"};
+static constexpr Property<size_t, ov::PropertyMutability::RW> usm_policy{"GPU_USM_POLICY"};
+static constexpr Property<bool, ov::PropertyMutability::RW> asym_dynamic_quantization{"GPU_ASYM_DYNAMIC_QUANTIZATION"};
+static constexpr Property<ShapePredictor::Settings, ov::PropertyMutability::RW> shape_predictor_settings{"GPU_SHAPE_PREDICTOR_SETTINGS"};
+static constexpr Property<std::vector<std::string>, ov::PropertyMutability::RW> load_dump_raw_binary{"GPU_LOAD_DUMP_RAW_BINARY"};
+static constexpr Property<std::vector<std::string>, ov::PropertyMutability::RW> start_after_processes{"GPU_START_AFTER_PROCESSES"};
 
 }  // namespace ov::intel_gpu
 
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/memory_pool.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/memory_pool.hpp
index 87e0b2990b7902..1d27eaf63efb86 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/memory_pool.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/memory_pool.hpp
@@ -4,6 +4,7 @@
 
 #pragma once
 
+#include "intel_gpu/runtime/execution_config.hpp"
 #include "layout.hpp"
 #include "memory_caps.hpp"
 #include "utils.hpp"
@@ -110,8 +111,6 @@ struct padded_pool_comparer {
 // - Improve memory consumption
 
 class memory_pool {
-    memory_pool();
-
     memory_ptr alloc_memory(const layout& layout, allocation_type type, bool reset = true);
     static bool has_conflict(const memory_set&, const std::unordered_set<size_t>&, uint32_t network_id);
 
@@ -119,9 +118,10 @@ class memory_pool {
     std::map<layout, std::list<memory_record>, padded_pool_comparer> _padded_pool;
     std::multimap<uint64_t, memory_record> _no_reusable_pool;
     engine* _engine;
+    const ExecutionConfig& _config;
 
 public:
-    explicit memory_pool(engine& engine);
+    explicit memory_pool(engine& engine, const ExecutionConfig& config);
     ~memory_pool();
     memory_ptr get_memory(const layout& layout,
                           const primitive_id& id,
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/options.inl b/src/plugins/intel_gpu/include/intel_gpu/runtime/options.inl
new file mode 100644
index 00000000000000..6e89da62ebf1e9
--- /dev/null
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/options.inl
@@ -0,0 +1,82 @@
+// Copyright (C) 2024 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+// Namespace, property name, default value, [validator], description
+OV_CONFIG_RELEASE_OPTION(ov, enable_profiling, false, "Enable profiling for the plugin")
+OV_CONFIG_RELEASE_OPTION(ov::device, id, "0", "ID of the current device")
+OV_CONFIG_RELEASE_OPTION(ov, cache_dir, "", "Directory where model cache can be stored. Caching is disabled if empty")
+OV_CONFIG_RELEASE_OPTION(ov, num_streams, 1, "Number of streams to be used for inference")
+OV_CONFIG_RELEASE_OPTION(ov, compilation_num_threads, std::max(1, static_cast<int>(std::thread::hardware_concurrency())), "Max number of CPU threads used for model compilation for the stages that supports parallelism")
+OV_CONFIG_RELEASE_OPTION(ov::hint, inference_precision, ov::element::f16, "Model floating-point inference precision. Supported values: { f16, f32, undefined }", [](ov::element::Type t) { return t == ov::element::f16 || t == ov::element::f32 || t == ov::element::undefined; })
+OV_CONFIG_RELEASE_OPTION(ov::hint, model_priority, ov::hint::Priority::MEDIUM, "High-level hint that defines the priority of the model. It may impact number of threads used for model compilton and inference as well as device queue settings")
+OV_CONFIG_RELEASE_OPTION(ov::hint, performance_mode, ov::hint::PerformanceMode::LATENCY, "High-level hint that defines target model inference mode. It may impact number of streams, auto batching, etc")
+OV_CONFIG_RELEASE_OPTION(ov::hint, execution_mode, ov::hint::ExecutionMode::PERFORMANCE, "High-level hint that defines the most important metric for the model. Performance mode allows unsafe optimizations that may reduce the model accuracy")
+OV_CONFIG_RELEASE_OPTION(ov::hint, num_requests, 0, "Hint that provides number of requests populated by the application")
+OV_CONFIG_RELEASE_OPTION(ov::hint, enable_cpu_pinning, false, "Controls if CPU threads are pinned to the cores or not")
+OV_CONFIG_RELEASE_OPTION(ov::hint, enable_cpu_reservation, false, "Cpu Reservation means reserve cpus which will not be used by other plugin or compiled model")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu::hint, host_task_priority, ov::hint::Priority::MEDIUM, "Low-level hint that controls core types used for host tasks")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu::hint, queue_throttle, ov::intel_gpu::hint::ThrottleLevel::MEDIUM, "Low-level hint that controls the queue throttle level")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu::hint, queue_priority, ov::hint::Priority::MEDIUM, "Low-level hint that controls queue priority property")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu::hint, enable_sdpa_optimization, true, "Enable/Disable fused SDPA primitive execution")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu, enable_loop_unrolling, true, "Enable/Disable Loop/TensorIterator operation unrolling")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu, disable_winograd_convolution, false, "Enable/Disable winograd convolution implementation if available")
+OV_CONFIG_RELEASE_OPTION(ov::internal, exclusive_async_requests, false, "")
+OV_CONFIG_RELEASE_OPTION(ov::internal, query_model_ratio, 1.0f, "")
+OV_CONFIG_RELEASE_OPTION(ov, cache_mode, ov::CacheMode::OPTIMIZE_SPEED, "Cache mode defines the trade-off between the model compilation time and the disk space required for the cache")
+OV_CONFIG_RELEASE_OPTION(ov, cache_encryption_callbacks, ov::EncryptionCallbacks{}, "Callbacks used to encrypt/decrypt the model")
+OV_CONFIG_RELEASE_OPTION(ov::hint, dynamic_quantization_group_size, 0, "")
+OV_CONFIG_RELEASE_OPTION(ov::hint, kv_cache_precision, ov::element::undefined, "")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu::hint, enable_kernels_reuse, false, "")
+OV_CONFIG_RELEASE_OPTION(ov, weights_path, "", "Path to the model weights file used for weightless caching")
+OV_CONFIG_RELEASE_OPTION(ov::hint, activations_scale_factor, -1.0f, "Scalar floating point value that is used for runtime activation tensor scaling with fp16 inference precision")
+OV_CONFIG_RELEASE_OPTION(ov::internal, enable_lp_transformations, false, "Enable/Disable Low precision transformations set")
+OV_CONFIG_RELEASE_OPTION(ov::intel_gpu, config_file, "", "Path to custom layers config file")
+
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, shape_predictor_settings, {10, 16 * 1024, 2, 1.1f}, "Preallocation settings")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, queue_type, QueueTypes::out_of_order, "Type of the queue that must be used for model execution. May be in-order or out-of-order")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, optimize_data, false, "Enable/Disable data flow optimizations for cldnn::program")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, enable_memory_pool, true, "Enable/Disable memory pool usage")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, allow_static_input_reorder, false, "Controls if weights tensors can be reordered during model compilation to more friendly layout for specific kernel")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, custom_outputs, std::vector<std::string>{}, "List of output primitive names")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, force_implementations, ImplForcingMap{}, "Specifies the list of forced implementations for the primitives")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, partial_build_program, false, "Early exit from model compilation process which allows faster execution graph dumping")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, allow_new_shape_infer, false, "Switch between new and old shape inference flow. Shall be removed soon")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, use_onednn, false, "Enable/Disable onednn for usage for particular model/platform")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, max_kernels_per_batch, 8, "Controls how many kernels we combine into batch for more efficient ocl compilation")
+OV_CONFIG_RELEASE_INTERNAL_OPTION(ov::intel_gpu, impls_cache_capacity, 300, "Controls capacity of LRU implementations cache that is created for each program object for dynamic models")
+
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, help, false, "Print help message for all config options")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, verbose, 0, "Enable logging for debugging purposes. The higher value the more verbose output. 0 - Disabled, 4 - Maximum verbosity")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, verbose_color, true, "Enable coloring for verbose logs")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, disable_usm, false, "Disable USM memory allocations and use only cl_mem")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, usm_policy, 0, "0: default, 1: use usm_host, 2: do not use usm_host")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, dump_batch_limit, std::numeric_limits<int32_t>::max(), "Max number of batch elements to dump")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, dump_profiling_data_per_iter, false, "Save profiling data w/o per-iteration aggregation")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, log_to_file, "", "Save verbose log to specified file")
+OV_CONFIG_DEBUG_GLOBAL_OPTION(ov::intel_gpu, debug_config, "", "Path to debug config in json format")
+
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_onednn_post_ops_opt, false, "Disable optimization pass for onednn post-ops")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_profiling_data_path, "", "Save csv file with per-stage and per-primitive profiling data to specified folder")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_graphs_path, "", "Save intermediate graph representations during model compilation pipeline to specified folder")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_sources_path, "", "Save generated sources for each kernel to specified folder")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_tensors_path, "", "Save intermediate in/out tensors of each primitive to specified folder")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_tensors, ov::intel_gpu::DumpTensors::all, "Tensor types to dump. Supported values: all, inputs, outputs")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_tensors_format, ov::intel_gpu::DumpFormat::text, "Format of the tensors dump. Supported values: binary, text, text_raw")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_layer_names, std::vector<std::string>{}, "Activate dump for specified layers only")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_memory_pool_path, "", "Save csv file with memory pool info to specified folder")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_memory_pool, false, "Enable verbose output for memory pool")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dump_iterations, std::set<int64_t>{}, "Space separated list of iterations where other dump options should be enabled")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, host_time_profiling, 0, "Measre and print host time spent from the beginning of the infer until all host work is done and plugin is ready to block thread on the final clFinish() call")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_async_compilation, false, "Disable feature that allows to asyncrhonously prepare static-shaped implementations for the primitives with shape-agnostic kernels selected during compilation")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_runtime_buffer_fusing, false, "Disable runtime inplace optimizations for operations like concat and crop")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_post_ops_fusions, false, "Disable fusions of operations as post-ops/fused-ops")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_horizontal_fc_fusion, false, "Disable pass which merges QKV projections into single MatMul")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_fc_swiglu_fusion, false, "Disable pass which merges FC and SwiGLU ops")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_fake_alignment, false, "Disable fake alignment feature which tries to keep gpu friendly memory alignment for arbitrary tensor shapes")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_memory_reuse, false, "Disable memory reuse for activation tensors")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, disable_runtime_skip_reorder, false, "Disable skip reorder optimization applied in runtime")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, asym_dynamic_quantization, false, "Enforce asymmetric mode for dynamically quantized activations")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, load_dump_raw_binary, std::vector<std::string>{}, "List of layers to load raw binary")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, start_after_processes, std::vector<std::string>{}, "Start inference after specified list of processes")
+OV_CONFIG_DEBUG_OPTION(ov::intel_gpu, dry_run_path, "", "Enables mode which partially compiles a model and stores runtime model into specified directory")
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/profiling.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/profiling.hpp
index b3eca9a78fba89..7d0dba80e7c017 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/profiling.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/profiling.hpp
@@ -9,6 +9,7 @@
 #include <vector>
 #include <string>
 #include <fstream>
+#include "intel_gpu/runtime/execution_config.hpp"
 
 #if defined(_WIN32)
 #ifndef NOMINMAX
@@ -157,7 +158,7 @@ class profiled_stage {
         , _obj(obj)
         , _stage(stage) {
         GPU_DEBUG_IF(profiling_enabled) {
-            _per_iter_mode = cldnn::debug_configuration::get_instance()->dump_profiling_data_per_iter != 0;
+            _per_iter_mode = GPU_DEBUG_VALUE_OR(ov::intel_gpu::ExecutionConfig::get_dump_profiling_data_per_iter(), false);
             _start = std::chrono::high_resolution_clock::now();
         }
     }
diff --git a/src/plugins/intel_gpu/include/intel_gpu/runtime/shape_predictor.hpp b/src/plugins/intel_gpu/include/intel_gpu/runtime/shape_predictor.hpp
index 469c676b4b0311..a246c6d1fdda8f 100644
--- a/src/plugins/intel_gpu/include/intel_gpu/runtime/shape_predictor.hpp
+++ b/src/plugins/intel_gpu/include/intel_gpu/runtime/shape_predictor.hpp
@@ -14,23 +14,20 @@ class engine;
 
 struct ShapePredictor {
 public:
-    using Ptr = std::shared_ptr<ShapePredictor>;
-    ShapePredictor(const engine* engine, float buffers_preallocation_ratio)
-        : _engine(engine)
-        , _buffers_preallocation_ratio(buffers_preallocation_ratio) {
-        static_assert(_max_deque_size >= 2, "[GPU] Deque is supposed to contain at least 2 elements for prediction");
-    }
+    struct Settings {
+        // Iterations mode preallocation
+        size_t next_iters_preallocation_count = 10;
+        size_t max_per_iter_size = 16 * 1024;
+        size_t max_per_dim_diff = 2;
 
-    ShapePredictor(const engine* engine,
-                   size_t next_iters_preallocation_count,
-                   size_t max_per_iter_size,
-                   size_t max_per_dim_diff,
-                   float buffers_preallocation_ratio)
+        // Percentage mode preallocation
+        float buffers_preallocation_ratio = 1.1f;
+    };
+
+    using Ptr = std::shared_ptr<ShapePredictor>;
+    ShapePredictor(const engine* engine, const Settings& settings)
         : _engine(engine)
-        , _next_iters_preallocation_count(next_iters_preallocation_count)
-        , _max_per_iter_size(max_per_iter_size)
-        , _max_per_dim_diff(max_per_dim_diff)
-        , _buffers_preallocation_ratio(buffers_preallocation_ratio) {
+        , _settings(settings) {
         static_assert(_max_deque_size >= 2, "[GPU] Deque is supposed to contain at least 2 elements for prediction");
     }
 
@@ -73,13 +70,7 @@ struct ShapePredictor {
     std::map<std::string, std::deque<ov::Shape>> _shapes_info;
     const engine* _engine;
 
-    // Iterations mode preallocation
-    const size_t _next_iters_preallocation_count = 10;
-    const size_t _max_per_iter_size = 16 * 1024; // 16KB => maximum preallocation size is 16KB * 10iters = 160KB
-    const size_t _max_per_dim_diff = 2;
-
-    // Percentage mode preallocation
-    const float _buffers_preallocation_ratio = 1.0f;
+    const Settings _settings;
 };
 
 }  // namespace cldnn
diff --git a/src/plugins/intel_gpu/src/graph/broadcast.cpp b/src/plugins/intel_gpu/src/graph/broadcast.cpp
index 0f69379fa8e217..95d060ef0b760e 100644
--- a/src/plugins/intel_gpu/src/graph/broadcast.cpp
+++ b/src/plugins/intel_gpu/src/graph/broadcast.cpp
@@ -149,7 +149,7 @@ void broadcast_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs[0] = input_memory_ptr();
diff --git a/src/plugins/intel_gpu/src/graph/crop.cpp b/src/plugins/intel_gpu/src/graph/crop.cpp
index d9f6ebd8b71872..fec36fb9ff5c81 100644
--- a/src/plugins/intel_gpu/src/graph/crop.cpp
+++ b/src/plugins/intel_gpu/src/graph/crop.cpp
@@ -278,7 +278,7 @@ void crop_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs[0] = _network.get_engine().reinterpret_buffer(input_memory(), _impl_params->get_output_layout());
diff --git a/src/plugins/intel_gpu/src/graph/debug_helper.cpp b/src/plugins/intel_gpu/src/graph/debug_helper.cpp
index b69d10e137010e..fb1a618c27cf60 100644
--- a/src/plugins/intel_gpu/src/graph/debug_helper.cpp
+++ b/src/plugins/intel_gpu/src/graph/debug_helper.cpp
@@ -3,6 +3,9 @@
 //
 
 #include "debug_helper.hpp"
+#include <regex>
+#include "intel_gpu/runtime/execution_config.hpp"
+#include "intel_gpu/runtime/internal_properties.hpp"
 #include "openvino/util/file_util.hpp"
 
 #ifdef GPU_DEBUG_CONFIG
@@ -44,8 +47,7 @@ template <class T>
 void dump(memory::ptr mem, stream& stream, std::ofstream& file_stream, bool dump_raw) {
     auto&& size = mem->get_layout().get_tensor();
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    auto batch_size = std::max(std::min(debug_config->dump_layers_limit_batch, size.batch[0]), 1);
+    auto batch_size = std::max(std::min(ExecutionConfig::get_dump_batch_limit(), size.batch[0]), 1);
     tensor tmp_size(size);
     tmp_size.batch[0] = batch_size;
     if (tmp_size == size) {
@@ -121,8 +123,7 @@ void unpack(cldnn::data_types type, uint8_t input, int8_t &v0, int8_t &v1) {
 void dump_i4u4(cldnn::data_types type, memory::ptr mem, stream& stream, std::ofstream& file_stream, bool dump_raw) {
     auto&& size = mem->get_layout().get_tensor();
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    auto batch_size = std::max(std::min(debug_config->dump_layers_limit_batch, size.batch[0]), 1);
+    auto batch_size = std::max(std::min(ExecutionConfig::get_dump_batch_limit(), size.batch[0]), 1);
     tensor tmp_size(size);
     tmp_size.batch[0] = batch_size;
     if (tmp_size == size) {
@@ -160,11 +161,16 @@ void dump_i4u4(cldnn::data_types type, memory::ptr mem, stream& stream, std::ofs
     file_stream << buffer.str();
 }
 
-void log_memory_to_file(memory::ptr mem, layout data_layout, stream& stream, std::string layerName, bool dump_raw) {
-    std::cout << "Dump " << (dump_raw ? "raw " : "") << layerName << std::endl;
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    std::string filename = debug_config->get_name_for_dump(layerName);
-    filename = debug_config->dump_layers_path + filename + ".txt";
+std::string get_name_for_dump(const std::string& file_name) {
+    std::string filename = file_name;
+    std::replace(filename.begin(), filename.end(), '\\', '_');
+    std::replace(filename.begin(), filename.end(), '/', '_');
+    std::replace(filename.begin(), filename.end(), ' ', '_');
+    std::replace(filename.begin(), filename.end(), ':', '_');
+    return filename;
+}
+
+void log_memory_to_file(memory::ptr mem, layout data_layout, stream& stream, std::string filename, bool dump_raw) {
     std::ofstream file_stream(filename);
     if (!mem) {
         file_stream << "Empty" << std::endl;
@@ -195,9 +201,7 @@ void log_memory_to_file(memory::ptr mem, layout data_layout, stream& stream, std
         std::cout << "Dump for this data type is not supported: " << dt_to_str(mem_dt) << std::endl;
 }
 
-}  // namespace
-
-static std::string get_file_path_for_binary_dump(cldnn::layout layout, std::string name) {
+std::string get_file_path_for_binary_dump(cldnn::layout layout, const std::string& name, const std::string& dump_layers_path) {
     std::string filename;
     std::string data_type = ov::element::Type(layout.data_type).get_type_name();
     std::string format = layout.format.to_string();
@@ -207,64 +211,148 @@ static std::string get_file_path_for_binary_dump(cldnn::layout layout, std::stri
         tensor += ("_" + to_string(dims[r]));
     }
 
-#ifdef GPU_DEBUG_CONFIG
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    std::string layer_name = debug_config->get_name_for_dump(name);
-    filename = debug_config->dump_layers_path + layer_name
-                + "__" + data_type + "_" + tensor + "__" + format + ".bin";
-#endif
+    std::string layer_name = get_name_for_dump(name);
+    filename = dump_layers_path + layer_name + "__" + data_type + "_" + tensor + "__" + format + ".bin";
     return filename;
 }
 
+bool is_target_iteration(int64_t iteration, const std::set<int64_t> dump_iteration) {
+    if (iteration < 0)
+        return true;
+
+    if (dump_iteration.empty())
+        return true;
+
+    if (dump_iteration.find(iteration) == std::end(dump_iteration))
+        return false;
+
+    return true;
+}
+
+std::string get_matched_from_filelist(const std::vector<std::string>& file_names, std::string pattern) {
+    for (const auto& file : file_names) {
+        auto found = file.find(pattern);
+        if (found != std::string::npos) {
+            return file;
+        }
+    }
+
+    return std::string();
+}
+
+bool is_layer_name_matched(const std::string& layer_name, const std::string& pattern) {
+    auto upper_layer_name = std::string(layer_name.length(), '\0');
+    std::transform(layer_name.begin(), layer_name.end(), upper_layer_name.begin(), ::toupper);
+    auto upper_pattern = std::string(pattern.length(), '\0');
+    std::transform(pattern.begin(), pattern.end(), upper_pattern.begin(), ::toupper);
+
+    // Check pattern from exec_graph
+    size_t pos = upper_layer_name.find(':');
+    auto upper_exec_graph_name = upper_layer_name.substr(pos + 1, upper_layer_name.size());
+    if (upper_exec_graph_name.compare(upper_pattern) == 0) {
+        return true;
+    }
+
+    // Check pattern with regular expression
+    std::regex re(upper_pattern);
+    return std::regex_match(upper_layer_name, re);
+}
+
+bool is_layer_for_dumping(const ExecutionConfig& config, const std::string& layer_name) {
+    const auto& dump_layers = config.get_dump_layer_names();
+    if (dump_layers.empty())
+        return true;
+
+    auto iter = std::find_if(dump_layers.begin(), dump_layers.end(), [&](const std::string& dl){
+        return is_layer_name_matched(layer_name, dl);
+    });
+    return (iter != dump_layers.end());
+}
+
+std::vector<std::string> get_filenames_for_matched_layer_loading_binaries(const ExecutionConfig& config, const std::string& id) {
+    std::vector<std::string> file_names;
+    if (config.get_load_dump_raw_binary().empty())
+        return file_names;
+
+    for (const auto& load_layer : config.get_load_dump_raw_binary()) {
+        size_t file = load_layer.rfind(":");
+        if (file != std::string::npos) {
+            if (id == load_layer.substr(0, file)) {
+                auto file_name_str = load_layer.substr(file + 1);
+                size_t head = 0;
+                size_t found = 0;
+                do {
+                    found = file_name_str.find(",", head);
+                    if (found != std::string::npos)
+                        file_names.push_back(file_name_str.substr(head, (found - head)));
+                    else
+                        file_names.push_back(file_name_str.substr(head));
+
+                    head = found+1;
+                    GPU_DEBUG_LOG << " Layer name loading raw dump : " << load_layer.substr(0, file) << " / the dump file : "
+                                << file_names.back() << std::endl;
+                } while (found != std::string::npos);
+
+                return file_names;
+            }
+        }
+    }
+
+    return file_names;
+}
+
+}  // namespace
+
 NodeDebugHelper::NodeDebugHelper(const primitive_inst& inst)
     : m_inst(inst)
     , m_stream(inst.get_network().get_stream())
     , m_network(inst.get_network())
     , m_program(inst.get_network().get_program().get())
     , m_iter(m_network.iteration) {
+    const auto& config = m_network.get_config();
     // Load binary dump for input layers
-    if (!debug_config->load_layers_raw_dump.empty()) {
+    if (!config.get_load_dump_raw_binary().empty()) {
         const std::string layer_name = m_inst.id();
-        auto files = debug_config->get_filenames_for_matched_layer_loading_binaries(layer_name);
+        auto files = get_filenames_for_matched_layer_loading_binaries(config, layer_name);
         if (!files.empty()) {
             if (m_inst.is_input()) {
                 // Loading binary dumps for output tensors of input-layers : only one output exists or index(dstN) exists
-                auto dump_file = debug_config->get_matched_from_filelist(files, "_dst0__");
+                auto dump_file = get_matched_from_filelist(files, "_dst0__");
                 OPENVINO_ASSERT((files.size() == 1 || dump_file.length() != 0), "Unexpected binary dump for input layer");
 
-                OPENVINO_ASSERT(files.size() == m_inst.outputs_memory_count(), "Mis-match dump file count");
+                OPENVINO_ASSERT(files.size() == m_inst.outputs_memory_count(), "Mismatch dump file count");
 
                 for (size_t i = 0; i < m_inst.outputs_memory_count(); i++) {
                     auto dump_file = files[0];
                     if (files.size() > 1 || m_inst.outputs_memory_count() != 1) {
                         std::string pattern = "_dst" + std::to_string(i) + "__";
-                        dump_file = debug_config->get_matched_from_filelist(files, pattern);
+                        dump_file = get_matched_from_filelist(files, pattern);
                     }
                     OPENVINO_ASSERT((dump_file.length() > 0), "Could not find expected pattern '_dst[N]__' for binary dump");
                     GPU_DEBUG_COUT << " Load binary dump : " << dump_file << " for " << layer_name << std::endl;
 
                     std::vector<uint8_t> bin = ov::util::load_binary(dump_file);
-                    OPENVINO_ASSERT(!bin.empty(), "Failure loading binary from OV_GPU_LoadDumpRawBinary : " + dump_file);
+                    OPENVINO_ASSERT(!bin.empty(), "Failure loading binary from OV_LOAD_DUMP_RAW_BINARY : " + dump_file);
 
                     auto output_mem = m_inst.output_memory_ptr(i);
-                    OPENVINO_ASSERT(output_mem->size() == bin.size(), "memory size mis-match for OV_GPU_LoadDumpRawBinary : " + layer_name
+                    OPENVINO_ASSERT(output_mem->size() == bin.size(), "memory size mis-match for OV_LOAD_DUMP_RAW_BINARY : " + layer_name
                                     + "\n Expected size : " + to_string(output_mem->size()) + ", Binary : " + to_string(bin.size()));
 
                     output_mem->copy_from(m_stream, static_cast<void *>(&bin[0]), true);
                 }
             } else {
-                auto check_dst = debug_config->get_matched_from_filelist(files, "_dst0__");
+                auto check_dst = get_matched_from_filelist(files, "_dst0__");
                 OPENVINO_ASSERT(check_dst.length() == 0, "Expected to load binaries for inputs of " + layer_name);
 
                 // Loading input tensors for any layer
-                auto dump_file = debug_config->get_matched_from_filelist(files, "_src0__");
+                auto dump_file = get_matched_from_filelist(files, "_src0__");
                 OPENVINO_ASSERT(dump_file.length() != 0, "Could not find expected pattern '_src[N]__' for binary dump input : " + layer_name);
 
                 for (size_t i = 0; i < m_inst.dependencies().size(); i++) {
                     auto dump_file = files[0];
                     if (files.size() > 1 || m_inst.dependencies().size() != 1) {
                         std::string pattern = "_src" + std::to_string(i) + "__";
-                        dump_file = debug_config->get_matched_from_filelist(files, pattern);
+                        dump_file = get_matched_from_filelist(files, pattern);
                     }
                     if (dump_file.length() == 0) {
                         GPU_DEBUG_COUT  << " Skip loading for  input(" << i << ") of " << layer_name << std::endl;
@@ -274,11 +362,11 @@ NodeDebugHelper::NodeDebugHelper(const primitive_inst& inst)
                     GPU_DEBUG_COUT  << " Load binary dump : " << dump_file << " for input(" << i << ") of " << layer_name << std::endl;
 
                     std::vector<uint8_t> bin = ov::util::load_binary(dump_file);
-                    OPENVINO_ASSERT(!bin.empty(), "Failure loading binary from OV_GPU_LoadDumpRawBinary : " + dump_file);
+                    OPENVINO_ASSERT(!bin.empty(), "Failure loading binary from OV_LOAD_DUMP_RAW_BINARY : " + dump_file);
 
                     auto input_mem = m_inst.dep_memory_ptr(i);
                     if (input_mem->size() != bin.size()) {
-                        std::cout << "WARNING: memory size mis-match for OV_GPU_LoadDumpRawBinary : " + layer_name
+                        std::cout << "WARNING: memory size mis-match for OV_LOAD_DUMP_RAW_BINARY : " + layer_name
                                     << "  " << input_mem->size() << " / " << bin.size() << std::endl;
                         bin.resize(input_mem->size());
                     }
@@ -290,12 +378,12 @@ NodeDebugHelper::NodeDebugHelper(const primitive_inst& inst)
     }
 
     // Dump input buffers of 'inst'
-    if (debug_config->dump_layers_path.length() > 0) {
-        const std::string layer_name = inst.id();
+    if (config.get_dump_tensors_path().length() > 0) {
+        const std::string& layer_name = inst.id();
 
-        if (debug_config->is_target_iteration(m_iter) &&
-            debug_config->dump_layers_dst_only == 0 && debug_config->is_layer_for_dumping(layer_name)) {
-            std::string debug_str_for_bin_load = " Command for loading : OV_GPU_LoadDumpRawBinary=\"" + layer_name + ":";
+        if (is_target_iteration(m_iter, config.get_dump_iterations()) &&
+            config.get_dump_tensors() != ov::intel_gpu::DumpTensors::out && is_layer_for_dumping(config, layer_name)) {
+            std::string debug_str_for_bin_load = " Command for loading : OV_LOAD_DUMP_RAW_BINARY=\"" + layer_name + ":";
             for (size_t i = 0; i < m_inst.dependencies().size(); i++) {
                 std::string name = get_file_prefix() + "_src" + std::to_string(i);
                 auto input_mem = m_inst.dep_memory_ptr(i);
@@ -306,24 +394,27 @@ NodeDebugHelper::NodeDebugHelper(const primitive_inst& inst)
 
                 auto dep = m_inst.dependencies().at(i);
                 auto input_layout = dep.first->get_output_layout(dep.second);
-                GPU_DEBUG_IF(debug_config->dump_layers_binary) {
+                if (config.get_dump_tensors_format() == ov::intel_gpu::DumpFormat::binary) {
                     // Binary dump : raw
-                    auto filename = get_file_path_for_binary_dump(input_layout, name);
+                    auto filename = get_file_path_for_binary_dump(input_layout, name, config.get_dump_tensors_path());
 
                     mem_lock<char, mem_lock_type::read> lock(input_mem, m_stream);
                     ov::util::save_binary(filename, lock.data(), input_mem->size());
-                    GPU_DEBUG_COUT  << " Dump layer src : " << layer_name << " to " << filename << std::endl;
+                    GPU_DEBUG_COUT << " Dump layer src : " << layer_name << " to " << filename << std::endl;
                     debug_str_for_bin_load += (filename + ",");
                 } else {
+                    const bool dump_raw = config.get_dump_tensors_format() == ov::intel_gpu::DumpFormat::text_raw;
+                    GPU_DEBUG_COUT << " Dump " << (dump_raw ? "raw " : "") << name << std::endl;
+                    auto filename = config.get_dump_tensors_path() + get_name_for_dump(name) + ".txt";
                     log_memory_to_file(input_mem,
                                        input_layout,
                                        m_stream,
-                                       name,
-                                       debug_config->dump_layers_raw);
+                                       filename,
+                                       dump_raw);
                 }
             }
 
-            if (debug_config->dump_layers_binary && !inst.is_input()) {
+            if (config.get_dump_tensors_format() == ov::intel_gpu::DumpFormat::binary && !inst.is_input()) {
                 debug_str_for_bin_load[debug_str_for_bin_load.size()-1] = '\"';
                 GPU_DEBUG_COUT << debug_str_for_bin_load << std::endl;
             }
@@ -333,14 +424,16 @@ NodeDebugHelper::NodeDebugHelper(const primitive_inst& inst)
 
 
 NodeDebugHelper::~NodeDebugHelper() {
+    const auto& config = m_network.get_config();
     // Dump output buffers of 'inst'
-    if (debug_config->dump_layers_path.length() > 0) {
+    if (config.get_dump_tensors_path().length() > 0) {
         m_stream.finish();
         const std::string layer_name = m_inst.id();
 
-        GPU_DEBUG_IF(debug_config->is_target_iteration(m_iter) &&
-                    debug_config->is_layer_for_dumping(layer_name, m_inst.is_output(), m_inst.is_input())) {
-            std::string debug_str_for_bin_load = " Command for loading : OV_GPU_LoadDumpRawBinary=\""
+        if (is_target_iteration(m_iter, config.get_dump_iterations()) &&
+            config.get_dump_tensors() != ov::intel_gpu::DumpTensors::in &&
+            is_layer_for_dumping(config, layer_name)) {
+            std::string debug_str_for_bin_load = " Command for loading : OV_LOAD_DUMP_RAW_BINARY=\""
                                                     + layer_name + ":";
             for (size_t i = 0; i < m_inst.outputs_memory_count(); i++) {
                 std::string name = get_file_prefix() + "_dst" + std::to_string(i);
@@ -350,22 +443,29 @@ NodeDebugHelper::~NodeDebugHelper() {
                     continue;
                 }
 
-                GPU_DEBUG_IF(debug_config->dump_layers_binary) {
+                if (config.get_dump_tensors_format() == ov::intel_gpu::DumpFormat::binary) {
                     // Binary dump : raw
                     auto output_layout = m_inst.get_output_layout(i);
-                    auto filename = get_file_path_for_binary_dump(output_layout, name);
+                    auto filename = get_file_path_for_binary_dump(output_layout, name, config.get_dump_tensors_path());
 
                     mem_lock<char, mem_lock_type::read> lock(output_mem, m_stream);
                     ov::util::save_binary(filename, lock.data(), output_mem->size());
                     GPU_DEBUG_COUT  << " Dump layer dst : " << layer_name << " to " << filename << std::endl;
                     debug_str_for_bin_load += (filename + ",");
                 } else {
+                    const bool dump_raw = config.get_dump_tensors_format() == ov::intel_gpu::DumpFormat::text_raw;
+                    GPU_DEBUG_COUT << " Dump " << (dump_raw ? "raw " : "") << name << std::endl;
+                    auto filename = config.get_dump_tensors_path() + get_name_for_dump(name) + ".txt";
                     // Text dump
-                    log_memory_to_file(output_mem, m_inst.get_output_layout(i), m_stream, name, debug_config->dump_layers_raw);
+                    log_memory_to_file(output_mem,
+                                       m_inst.get_output_layout(i),
+                                       m_stream,
+                                       filename,
+                                       dump_raw);
                 }
             }
 
-            GPU_DEBUG_IF(debug_config->dump_layers_binary && m_inst.is_input()) {
+            if (config.get_dump_tensors_format() == ov::intel_gpu::DumpFormat::binary && m_inst.is_input()) {
                 debug_str_for_bin_load[debug_str_for_bin_load.size()-1] = '\"';
                 GPU_DEBUG_COUT << debug_str_for_bin_load << std::endl;;
             }
@@ -377,13 +477,14 @@ NetworkDebugHelper::NetworkDebugHelper(const network& net)
     : m_network(net)
     , m_iter(net.iteration) {
     auto net_id = m_network.get_id();
-    GPU_DEBUG_IF(debug_config->dump_memory_pool > 0) {
-        auto& iters = debug_config->dump_memory_pool_iters;
+    const auto& config = m_network.get_config();
+    if (config.get_dump_memory_pool()) {
+        auto& iters = config.get_dump_iterations();
         if (iters.empty() || iters.find(m_iter) != iters.end()) {
             GPU_DEBUG_COUT << "============================================================================" << std::endl;
             GPU_DEBUG_COUT << "Start network execution (net_id : " << net_id << ", iter :" << m_iter << ")" << std::endl;
             if (m_iter == 0 && net_id > 0) {
-                dump_memory_pool(debug_config->dump_memory_pool_path, m_iter);
+                dump_memory_pool(config.get_dump_memory_pool_path(), m_iter);
                 GPU_DEBUG_COUT << "============================================================================" << std::endl;
             }
         }
@@ -391,38 +492,14 @@ NetworkDebugHelper::NetworkDebugHelper(const network& net)
         GPU_DEBUG_TRACE << "============================================================================" << std::endl;
         GPU_DEBUG_TRACE << "Start network execution (net_id : " << net_id << ", iter :" << m_iter << ")" << std::endl;
     }
-
-    if (debug_config->list_layers == 1) {
-        for (auto& inst : m_network._exec_order) {
-            GPU_DEBUG_COUT << inst->id() << std::endl;
-            if (inst->get_node().is_type<loop>()) {
-                auto& loop_node = inst->get_node().as<loop>();
-                for (auto& prim : loop_node.get_body_program()->get_processing_order()) {
-                    GPU_DEBUG_COUT << "\t" << prim->id() << std::endl;
-                }
-            } else if (inst->get_node().is_type<condition>()) {
-                auto& cond_node = inst->get_node().as<condition>();
-                GPU_DEBUG_COUT << "* Branch_True" << std::endl;
-                for (auto& prim : cond_node.get_branch_true().inner_program->get_processing_order()) {
-                    GPU_DEBUG_COUT << "\t" << prim->id() << std::endl;
-                }
-                GPU_DEBUG_COUT << "* Branch_False" << std::endl;
-                for (auto& prim : cond_node.get_branch_false().inner_program->get_processing_order()) {
-                    GPU_DEBUG_COUT << "\t" << prim->id() << std::endl;
-                }
-            }
-        }
-
-        if (!m_network.is_internal())
-            exit(0);
-    }
 }
 
 NetworkDebugHelper::~NetworkDebugHelper() {
     auto prog = m_network.get_program().get();
     auto net_id = m_network.get_id();
+    const auto& config = prog->get_config();
     // print '-data_shape' option for benchmark_app
-    if (debug_config->print_input_data_shapes == 1) {
+    if (config.get_verbose() >= 4) {
         std::stringstream data_shape_str;
         auto add_string = [&data_shape_str](std::string str) {
             data_shape_str << ((data_shape_str.rdbuf()->in_avail() == 0) ? " -data_shape " : ",") << str;
@@ -443,7 +520,7 @@ NetworkDebugHelper::~NetworkDebugHelper() {
                        << data_shape_str.str() << std::endl;
     }
 
-    if (!debug_config->dump_graphs.empty() && debug_config->is_target_iteration(m_iter)) {
+    if (!config.get_dump_graphs_path().empty() && is_target_iteration(m_iter, config.get_dump_iterations())) {
         auto get_fixed_str = [](int value, int length = 2) -> std::string {
             std::ostringstream ss;
             ss << std::setw(length) << std::setfill('0') << std::to_string(value);
@@ -459,10 +536,10 @@ NetworkDebugHelper::~NetworkDebugHelper() {
         }
     }
 
-    if (debug_config->dump_memory_pool > 0) {
-        auto& iters = debug_config->dump_memory_pool_iters;
+    if (config.get_dump_memory_pool()) {
+        auto& iters = config.get_dump_iterations();
         if (iters.empty() || iters.find(m_iter) != iters.end()) {
-            dump_memory_pool(debug_config->dump_memory_pool_path, m_iter);
+            dump_memory_pool(config.get_dump_memory_pool_path(), m_iter);
             GPU_DEBUG_COUT << "============================================================================" << std::endl;
         }
     }
diff --git a/src/plugins/intel_gpu/src/graph/debug_helper.hpp b/src/plugins/intel_gpu/src/graph/debug_helper.hpp
index 61572433cea494..e2137733cf73fc 100644
--- a/src/plugins/intel_gpu/src/graph/debug_helper.hpp
+++ b/src/plugins/intel_gpu/src/graph/debug_helper.hpp
@@ -39,8 +39,6 @@ class NodeDebugHelper {
     const network& m_network;
     const program* m_program;
     const size_t m_iter;
-
-    const debug_configuration* debug_config = cldnn ::debug_configuration ::get_instance();
 };
 
 class NetworkDebugHelper {
@@ -52,8 +50,6 @@ class NetworkDebugHelper {
     void dump_memory_pool(std::string dump_path, int64_t curr_iter) const;
     const network& m_network;
     const size_t m_iter;
-
-    const debug_configuration* debug_config = cldnn ::debug_configuration ::get_instance();
 };
 
 #define NETWORK_DEBUG(net) NetworkDebugHelper __network_debug_helper(net)
diff --git a/src/plugins/intel_gpu/src/graph/eltwise.cpp b/src/plugins/intel_gpu/src/graph/eltwise.cpp
index 7805cb575aed9a..581f3f08dc120d 100644
--- a/src/plugins/intel_gpu/src/graph/eltwise.cpp
+++ b/src/plugins/intel_gpu/src/graph/eltwise.cpp
@@ -393,7 +393,7 @@ eltwise_inst::typed_primitive_inst(network& network, eltwise_node const& node) :
                                       "");
         }
     } else {
-        bool use_new_shape_infer = network.get_config().get_property(ov::intel_gpu::allow_new_shape_infer);
+        bool use_new_shape_infer = network.get_config().get_allow_new_shape_infer();
         auto input0_pshape = node.get_input_pshape(0);
 
         for (size_t i = 1; i < inputs_count; ++i) {
diff --git a/src/plugins/intel_gpu/src/graph/fully_connected.cpp b/src/plugins/intel_gpu/src/graph/fully_connected.cpp
index d8324cfb2e047a..d9f88477a124d0 100644
--- a/src/plugins/intel_gpu/src/graph/fully_connected.cpp
+++ b/src/plugins/intel_gpu/src/graph/fully_connected.cpp
@@ -250,8 +250,7 @@ kernel_impl_params fully_connected_inst::get_fake_aligned_params(kernel_impl_par
         }
     }
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_fake_alignment) {
+    GPU_DEBUG_IF(orig_impl_param.get_program().get_config().get_disable_fake_alignment()) {
         can_apply_fake_alignment = false;
     }
 
diff --git a/src/plugins/intel_gpu/src/graph/gather.cpp b/src/plugins/intel_gpu/src/graph/gather.cpp
index 2020f10015f916..7d503faf8a2255 100644
--- a/src/plugins/intel_gpu/src/graph/gather.cpp
+++ b/src/plugins/intel_gpu/src/graph/gather.cpp
@@ -150,7 +150,7 @@ void gather_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs[0] = input_memory_ptr();
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/add_required_reorders.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/add_required_reorders.cpp
index 333afe18775e0b..cffb4457000380 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/add_required_reorders.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/add_required_reorders.cpp
@@ -161,7 +161,7 @@ bool add_required_reorders::test_format(cldnn::program_node& node, format reques
 }
 
 void add_required_reorders::run(program& p) {
-    bool optimize_data = p.get_config().get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = p.get_config().get_optimize_data();
     auto usr_itr = p.get_processing_order().begin();
     while (usr_itr != p.get_processing_order().end()) {
         auto& usr = *usr_itr++;
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/build_implementations.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/build_implementations.cpp
index 4c1b1008434144..ef4300c33bfea1 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/build_implementations.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/build_implementations.cpp
@@ -11,7 +11,7 @@ using namespace cldnn;
 
 void build_implementations::run(program& p) {
     OV_ITT_SCOPED_TASK(ov::intel_gpu::itt::domains::intel_gpu_plugin, "pass::build_implementations");
-    if (p.get_config().get_property(ov::intel_gpu::partial_build_program)) {
+    if (p.get_config().get_partial_build_program()) {
         return;
     }
 
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/graph_initializations.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/graph_initializations.cpp
index eec55260e2ea4b..6c38bce8dd9e31 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/graph_initializations.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/graph_initializations.cpp
@@ -17,7 +17,7 @@ using namespace cldnn;
 namespace cldnn {
 
 void graph_initializations::set_outputs(program& p) {
-    auto custom_outputs = p.get_config().get_property(ov::intel_gpu::custom_outputs);
+    auto custom_outputs = p.get_config().get_custom_outputs();
     if (!custom_outputs.empty()) {
         for (auto const& output : custom_outputs) {
             OPENVINO_ASSERT(p.has_node(output), "not found custom output node in current cldnn::program: ", output);
@@ -37,7 +37,7 @@ void graph_initializations::set_outputs(program& p) {
 void graph_initializations::run(program& p) {
     set_outputs(p);
 
-    auto forcing_map = p.get_config().get_property(ov::intel_gpu::force_implementations);
+    auto forcing_map = p.get_config().get_force_implementations();
     for (auto& kv : forcing_map) {
         if (p.has_node(kv.first)) {
             p.get_node(kv.first).set_forced_impl_type(kv.second.impl_type);
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/post_optimize_weights.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/post_optimize_weights.cpp
index 4d21869dfa3953..2786a9e8e85b99 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/post_optimize_weights.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/post_optimize_weights.cpp
@@ -43,10 +43,6 @@ void post_optimize_weights::optimize_weights(T& node, program& p) {
         return;
 
     if (impl->is_dynamic()) {
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-        GPU_DEBUG_IF(debug_config->disable_build_time_weight_reorder_for_dynamic_nodes) {
-            return;
-        }
         // TODO: To relax current limitation w.r.t the future optimization of weight reorder process
         // In dynamic shape, selected weight format can change in runtime. However reordering blocked format to blocked format is not fully verified yet.
         // So we need to enable other primitives such as convolution with verifying reorder b/w the possible layouts
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_buffer_fusing.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_buffer_fusing.cpp
index 03e4af4d16359b..1c79ab27101808 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_buffer_fusing.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_buffer_fusing.cpp
@@ -80,8 +80,7 @@ bool concat_in_place_optimization::match(const program_node& concat_node,
     if (concat_node.is_output() || concat_params.fused_desc.size() > 0 || concat_node.is_in_shape_of_subgraph())
         return false;
     bool do_runtime_buffer_fusing = true;
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_runtime_buffer_fusing) {
+    GPU_DEBUG_IF(concat_node.get_config().get_disable_runtime_buffer_fusing()) {
         do_runtime_buffer_fusing = false;
     }
 
@@ -522,8 +521,7 @@ bool crop_in_place_optimization::match(const program_node& node,
         return false;
 
     if (node.get_users().size() > 0) {
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-        GPU_DEBUG_IF(debug_config->disable_runtime_buffer_fusing && node.is_dynamic()) {
+        GPU_DEBUG_IF(node.get_config().get_disable_runtime_buffer_fusing() && node.is_dynamic()) {
             return false;
         }
 
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing.cpp
index ce5333f95a1b59..622b7cff4101ad 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing.cpp
@@ -56,6 +56,9 @@
 using namespace cldnn;
 
 void prepare_primitive_fusing::run(program& p) {
+    GPU_DEBUG_IF(p.get_config().get_disable_post_ops_fusions())
+        return;
+
     fuse_reorders(p);
     remove_redundant_reshape(p);
     fuse_swiglu(p);
@@ -165,10 +168,7 @@ void prepare_primitive_fusing::fuse_reorders(program &p) {
 }
 
 void prepare_primitive_fusing::fuse_swiglu(program &p) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    bool disable_fc_swiglu_fusion = false;
-    GPU_DEBUG_IF(debug_config->disable_fc_swiglu_fusion == 1)
-        disable_fc_swiglu_fusion = true;
+    bool disable_fc_swiglu_fusion = GPU_DEBUG_VALUE_OR(p.get_config().get_disable_fc_swiglu_fusion(), false);
     // Apply only for high performant GPU
     if (disable_fc_swiglu_fusion || p.get_engine().get_device_info().execution_units_count < 128)
         return;
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing_through.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing_through.cpp
index f63f1bf4efbe21..33320126a9d910 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing_through.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/prepare_primitive_fusing_through.cpp
@@ -16,6 +16,9 @@
 using namespace cldnn;
 
 void prepare_primitive_fusing_through::run(program& p) {
+    GPU_DEBUG_IF(p.get_config().get_disable_post_ops_fusions())
+        return;
+
     auto try_fuse_through = [&](program_node& node) -> std::vector<program_node*> {
         // This function tries to fuse peer_node to first non reorder or reshape previous primitive.
         // It returns chain of primitives (reshapes and reorders) including potential fused_node (e.g. Conv, FC, etc)
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/propagate_constants.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/propagate_constants.cpp
index 34314155837197..435b67cafaf7e5 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/propagate_constants.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/propagate_constants.cpp
@@ -2,6 +2,7 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+#include "intel_gpu/runtime/internal_properties.hpp"
 #include "pass_manager.h"
 #include "program_node.h"
 #include "intel_gpu/runtime/engine.hpp"
@@ -132,9 +133,10 @@ propagate_constants::calculate(engine& engine,
     if (!has_non_trivial_constants)
         return {};
 
-    ExecutionConfig cf_config = config;
+    ExecutionConfig cf_config = config.clone();
     cf_config.set_property(ov::intel_gpu::optimize_data(false));
     cf_config.set_property(ov::intel_gpu::custom_outputs(const_outputs));
+    cf_config.finalize(engine);
     network::ptr net = network::build_network(engine, nodes, cf_config, task_executor, true);
     std::map<primitive_id, cache_tuple> weightless_cache_map;
     for (auto& cin : const_inputs) {
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/reorder_inputs.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/reorder_inputs.cpp
index 7b3cbdabe639a0..088afd84f5ff6a 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/reorder_inputs.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/reorder_inputs.cpp
@@ -679,8 +679,6 @@ void insert_reorders(program& p, const std::map<program_node*, format::type>& fm
 }  // namespace
 
 void reorder_inputs::run(program& p, reorder_factory& rf) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-
     auto& lo = p.get_layout_optimizer();
 
     auto fmt_map = get_preferred_formats(p, lo);
@@ -704,7 +702,7 @@ void reorder_inputs::run(program& p, reorder_factory& rf) {
         GPU_DEBUG_LOG_PASS << "  " << node_ptr->id() << " " << fmt_to_str(fmt) << std::endl;
     }
 
-    GPU_DEBUG_IF(debug_config->verbose >= 2) {
+    GPU_DEBUG_IF(p.get_config().get_verbose() >= 2) {
         reorder_cnt total_reorder_count =
             std::accumulate(p.get_processing_order().begin(),
                             p.get_processing_order().end(),
diff --git a/src/plugins/intel_gpu/src/graph/graph_optimizer/select_preferred_formats.cpp b/src/plugins/intel_gpu/src/graph/graph_optimizer/select_preferred_formats.cpp
index a4e6d989543837..8b3a73c74f3aa6 100644
--- a/src/plugins/intel_gpu/src/graph/graph_optimizer/select_preferred_formats.cpp
+++ b/src/plugins/intel_gpu/src/graph/graph_optimizer/select_preferred_formats.cpp
@@ -74,7 +74,7 @@ void select_preferred_formats::run(program& p) {
     }
 #endif  // ENABLE_ONEDNN_FOR_GPU
 
-    auto forcing_map = p.get_config().get_property(ov::intel_gpu::force_implementations);
+    auto forcing_map = p.get_config().get_force_implementations();
 
     for (auto n : p.get_processing_order()) {
         n->recalc_output_layout();
@@ -121,7 +121,7 @@ void select_preferred_formats::run(program& p) {
                     optimize_conv_permute(*n);
                 }
             } catch (std::exception& exception) {
-                GPU_DEBUG_INFO << "WARNING(select_preferred_formats): " << exception.what() << std::endl;
+                GPU_DEBUG_LOG << "WARNING(select_preferred_formats): " << exception.what() << std::endl;
             }
             print_selected_formats(*n);
         }
diff --git a/src/plugins/intel_gpu/src/graph/impls/ocl/fully_connected.cpp b/src/plugins/intel_gpu/src/graph/impls/ocl/fully_connected.cpp
index d7813c03d80f99..b33a391dadea4c 100644
--- a/src/plugins/intel_gpu/src/graph/impls/ocl/fully_connected.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/ocl/fully_connected.cpp
@@ -203,7 +203,7 @@ struct fully_connected_impl : typed_primitive_impl_ocl<fully_connected> {
             params.quantization = kernel_selector::QuantizationType::NONE;
         }
 
-        params.dynamic_quantization_group_size = impl_param.get_program().get_config().get_property(ov::hint::dynamic_quantization_group_size);
+        params.dynamic_quantization_group_size = impl_param.get_program().get_config().get_dynamic_quantization_group_size();
 
         return params;
     }
diff --git a/src/plugins/intel_gpu/src/graph/impls/ocl/kernel_selector_helper.cpp b/src/plugins/intel_gpu/src/graph/impls/ocl/kernel_selector_helper.cpp
index 624db86e38342c..9b73d9711a5a32 100644
--- a/src/plugins/intel_gpu/src/graph/impls/ocl/kernel_selector_helper.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/ocl/kernel_selector_helper.cpp
@@ -1204,13 +1204,13 @@ void set_params(const kernel_impl_params& param_info, kernel_selector::params& p
     params.engineInfo.ip_version = device_info.ip_version;
     params.engineInfo.arch = kernel_selector::gpu_arch(static_cast<std::underlying_type<gpu_arch>::type>(device_info.arch));
 
-    auto impl_forcing = config.get_property(ov::intel_gpu::force_implementations);
+    auto impl_forcing = config.get_force_implementations();
 
     if (impl_forcing.count(param_info.desc->id) != 0) {
         params.forceImplementation = impl_forcing.at(param_info.desc->id).kernel_name;
     }
 
-    params.allowStaticInputReordering = config.get_property(ov::intel_gpu::optimize_data) || config.get_property(ov::intel_gpu::allow_static_input_reorder);
+    params.allowStaticInputReordering = config.get_optimize_data() || config.get_allow_static_input_reorder();
     params.allowInputReordering = false;
 }
 
diff --git a/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.cpp b/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.cpp
index cf7ac0f7b3f5a3..195a2443016dfd 100644
--- a/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.cpp
@@ -111,7 +111,7 @@ namespace cldnn {
 std::mutex kernels_cache::_mutex;
 
 std::string kernels_cache::get_cache_path() const {
-    auto path = _config.get_property(ov::cache_dir);
+    auto path = _config.get_cache_dir();
     if (path.empty()) {
         return {};
     }
@@ -123,20 +123,12 @@ std::string kernels_cache::get_cache_path() const {
 }
 
 bool kernels_cache::is_cache_enabled() const {
-    if (!_config.get_property(ov::intel_gpu::allow_new_shape_infer) &&
-        (_config.get_property(ov::cache_mode) == ov::CacheMode::OPTIMIZE_SPEED)) {
+    if (!_config.get_allow_new_shape_infer() &&
+        (_config.get_cache_mode() == ov::CacheMode::OPTIMIZE_SPEED)) {
         return false;
     }
 
-    return !_config.get_property(ov::cache_dir).empty();
-}
-
-size_t kernels_cache::get_max_kernels_per_batch() const {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->max_kernels_per_batch >= 1) {
-        return static_cast<size_t>(debug_config->max_kernels_per_batch);
-    }
-    return _config.get_property(ov::intel_gpu::max_kernels_per_batch);
+    return !_config.get_cache_dir().empty();
 }
 
 void kernels_cache::get_program_source(const kernels_code& kernels_source_code, std::vector<kernels_cache::batch_program>* all_batches) const {
@@ -205,7 +197,7 @@ void kernels_cache::get_program_source(const kernels_code& kernels_source_code,
 
             // Create new kernels batch when the limit is reached
             // and current kernel's entry_point is duplicated in this kernels batch
-            if (current_bucket.back().kernels_counter >= get_max_kernels_per_batch()
+            if (current_bucket.back().kernels_counter >= _config.get_max_kernels_per_batch()
                 || current_bucket.back().entry_point_to_id.find(entry_point) != current_bucket.back().entry_point_to_id.end()
                 || need_separate_batch(entry_point)) {
                 const auto& batch_id = static_cast<int32_t>(current_bucket.size());
@@ -246,11 +238,7 @@ void kernels_cache::get_program_source(const kernels_code& kernels_source_code,
 
             b.hash_value = std::hash<std::string>()(full_code);
 
-            std::string dump_sources_dir = "";
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(!debug_config->dump_sources.empty()) {
-                dump_sources_dir = debug_config->dump_sources;
-            }
+            std::string dump_sources_dir = GPU_DEBUG_VALUE_OR(_config.get_dump_sources_path(), "");
 
             // Add -g -s to build options to allow IGC assembly dumper to associate assembler sources with corresponding OpenCL kernel code lines
             // Should be used with the IGC_ShaderDump option
@@ -306,11 +294,9 @@ void kernels_cache::build_batch(const batch_program& batch, compiled_kernels& co
     auto& cl_build_device = dynamic_cast<const ocl::ocl_device&>(*_device);
 
     bool dump_sources = batch.dump_custom_program;
-    std::string dump_sources_dir = "";
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->dump_sources.empty()) {
+    std::string dump_sources_dir = GPU_DEBUG_VALUE_OR(_config.get_dump_sources_path(), "");
+    GPU_DEBUG_IF(!dump_sources_dir.empty()) {
         dump_sources = true;
-        dump_sources_dir = debug_config->dump_sources;
     }
 
     std::string err_log;  // accumulated build log from all program's parts (only contains messages from parts which
@@ -385,7 +371,7 @@ void kernels_cache::build_batch(const batch_program& batch, compiled_kernels& co
             if (is_cache_enabled()) {
                 // If kernels caching is enabled, then we save compiled bucket to binary file with name ${code_hash_value}.cl_cache
                 // Note: Bin file contains full bucket, not separate kernels, so kernels reuse across different models is quite limited
-                // Bucket size can be changed in get_max_kernels_per_batch() method, but forcing it to 1 will lead to much longer
+                // Bucket size can be changed by max_kernels_per_batch config option, but forcing it to 1 will lead to much longer
                 // compile time.
                 std::lock_guard<std::mutex> lock(cacheAccessMutex);
                 ov::intel_gpu::save_binary(cached_bin_name, getProgramBinaries(std::move(program)));
diff --git a/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp b/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp
index 79ccfd050f4a93..5eeb314339a613 100644
--- a/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/ocl/kernels_cache.hpp
@@ -114,7 +114,6 @@ class kernels_cache {
 
     std::string get_cache_path() const;
     bool is_cache_enabled() const;
-    size_t get_max_kernels_per_batch() const;
 
     bool _reuse_kernels = false;
 
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/concatenation_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/concatenation_onednn.hpp
index 3e46b3bc2dfbd0..167f712a687ed6 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/concatenation_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/concatenation_onednn.hpp
@@ -18,8 +18,9 @@ struct ConcatenationImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<concatenation>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         static const std::vector<ov::element::Type_t> supported_types = { ov::element::f16, ov::element::u8, ov::element::i8 };
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.cpp b/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.cpp
index 6f8502423047b6..0f8d271bc3a6cd 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.cpp
@@ -157,7 +157,6 @@ struct convolution_onednn : typed_primitive_onednn_impl<convolution> {
             dnnl::memory::desc desc = onednn::layout_to_memory_desc(a_zp->get_layout(), dnnl::memory::format_tag::a, true);
             args.insert({DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_SRC, a_zp->get_onednn_memory(desc)});
 
-            GPU_DEBUG_GET_INSTANCE(debug_config);
             GPU_DEBUG_TRACE_DETAIL << instance.id() << " activations_zero_points: "
                 << " " << a_zp->get_layout().to_short_string() << std::endl;
         }
@@ -167,7 +166,6 @@ struct convolution_onednn : typed_primitive_onednn_impl<convolution> {
             dnnl::memory::desc desc = onednn::layout_to_memory_desc(w_zp->get_layout(), dnnl::memory::format_tag::a, true);
             args.insert({DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_WEIGHTS, w_zp->get_onednn_memory(desc)});
 
-            GPU_DEBUG_GET_INSTANCE(debug_config);
             GPU_DEBUG_TRACE_DETAIL << instance.id() << " weights_zero_points: "
                 << " " << w_zp->get_layout().to_short_string() << std::endl;
         }
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.hpp
index c3f599fc5db9f6..430c42dee57f75 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/convolution_onednn.hpp
@@ -23,8 +23,9 @@ struct ConvolutionImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<convolution>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         const auto& conv_node = node.as<convolution>();
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/deconvolution_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/deconvolution_onednn.hpp
index 039cf36261caa0..238214f82dc6fb 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/deconvolution_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/deconvolution_onednn.hpp
@@ -19,8 +19,9 @@ struct DeconvolutionImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<deconvolution>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         const auto& deconv_node = node.as<deconvolution>();
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/fully_connected_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/fully_connected_onednn.hpp
index c4dc5f7faa6531..731a83372a9dfc 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/fully_connected_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/fully_connected_onednn.hpp
@@ -21,8 +21,9 @@ struct FullyConnectedImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<fully_connected>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         const auto& fc_node = node.as<fully_connected>();
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/gemm_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/gemm_onednn.hpp
index 6c576d177043ee..3d64d2009490c0 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/gemm_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/gemm_onednn.hpp
@@ -18,8 +18,9 @@ struct GemmImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<gemm>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         const auto& gemm_node = node.as<gemm>();
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/lstm_seq_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/lstm_seq_onednn.hpp
index 6fd16a4dd04acf..4b2615c62e2747 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/lstm_seq_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/lstm_seq_onednn.hpp
@@ -22,10 +22,10 @@ struct LSTMSeqImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<lstm_seq>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (info.arch == gpu_arch::unknown)
+        if (info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
-
         const auto& lstm_seq_node = node.as<lstm_seq>();
         const auto& in_layout = lstm_seq_node.get_input_layout(0);
         const auto& out_layout = lstm_seq_node.get_output_layout(0);
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/pooling_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/pooling_onednn.hpp
index 4710b0c77b83c7..ced0316e13a08f 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/pooling_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/pooling_onednn.hpp
@@ -19,8 +19,9 @@ struct PoolingImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<pooling>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         const auto& in_layout = node.get_input_layout(0);
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/primitive_onednn_base.h b/src/plugins/intel_gpu/src/graph/impls/onednn/primitive_onednn_base.h
index 05a3dc5b2a9e4b..fe5920355e29c7 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/primitive_onednn_base.h
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/primitive_onednn_base.h
@@ -47,12 +47,11 @@ struct typed_primitive_onednn_impl : public typed_primitive_impl<PType> {
         _engine(&engine),
         _attrs(attrs),
         _pd(pd) {
-            _enable_profiling = config.get_property(ov::enable_profiling);
+            _enable_profiling = config.get_enable_profiling();
 
             _scratchpad_md = _pd.scratchpad_desc();
 
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(debug_config->verbose >= 4) {
+            GPU_DEBUG_IF(config.get_verbose() >= 4) {
                 if (_scratchpad_md.get_size() > 0) {
                     static std::atomic_llong total{0};
                     int64_t size = _scratchpad_md.get_size() / 1048576;
@@ -70,9 +69,8 @@ struct typed_primitive_onednn_impl : public typed_primitive_impl<PType> {
         _engine(&engine),
         _pd(),
         _prim() {
-            _enable_profiling = config.get_property(ov::enable_profiling);
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(!debug_config->dump_profiling_data.empty()) {
+            _enable_profiling = config.get_enable_profiling();
+            GPU_DEBUG_IF(!config.get_dump_profiling_data_path().empty()) {
                 _enable_profiling = true;
             }
         }
@@ -318,7 +316,7 @@ struct typed_primitive_onednn_impl : public typed_primitive_impl<PType> {
 
 private:
     std::string get_cache_directory(const ExecutionConfig& config) const {
-        auto path = config.get_property(ov::cache_dir);
+        auto path = config.get_cache_dir();
         if (path.empty()) {
             return {};
         }
@@ -343,7 +341,7 @@ struct typed_primitive_onednn_impl : public typed_primitive_impl<PType> {
     void build_primitive(const ExecutionConfig& config) {
         auto cache_outpath = get_cache_directory(config);
 
-        if (!config.get_property(ov::intel_gpu::allow_new_shape_infer)) {
+        if (!config.get_allow_new_shape_infer()) {
             cache_outpath = "";
         }
 
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/reduce_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/reduce_onednn.hpp
index 68d963fd9e369f..4a4a4c60df032d 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/reduce_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/reduce_onednn.hpp
@@ -48,8 +48,9 @@ struct ReduceImplementationManager : public ImplementationManager {
 
     bool validate_impl(const program_node& node) const override {
         assert(node.is_type<reduce>());
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         const auto& reduce_node = node.as<reduce>();
diff --git a/src/plugins/intel_gpu/src/graph/impls/onednn/reorder_onednn.hpp b/src/plugins/intel_gpu/src/graph/impls/onednn/reorder_onednn.hpp
index c4117058da88e9..824069f56b9583 100644
--- a/src/plugins/intel_gpu/src/graph/impls/onednn/reorder_onednn.hpp
+++ b/src/plugins/intel_gpu/src/graph/impls/onednn/reorder_onednn.hpp
@@ -56,8 +56,9 @@ struct ReorderImplementationManager : public ImplementationManager {
         if (output_fmt == format::custom)
             return true;
 
+        const auto& config = node.get_program().get_config();
         const auto& info = node.get_program().get_engine().get_device_info();
-        if (!info.supports_immad || info.arch == gpu_arch::unknown)
+        if (!info.supports_immad || info.arch == gpu_arch::unknown || !config.get_use_onednn())
             return false;
 
         if (!one_of(input_fmt.value, supported_formats) || !one_of(output_fmt.value, supported_formats))
diff --git a/src/plugins/intel_gpu/src/graph/impls/registry/implementation_manager.cpp b/src/plugins/intel_gpu/src/graph/impls/registry/implementation_manager.cpp
index fdb2f151de8986..0ce180380f14b5 100644
--- a/src/plugins/intel_gpu/src/graph/impls/registry/implementation_manager.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/registry/implementation_manager.cpp
@@ -58,7 +58,7 @@ std::unique_ptr<primitive_impl> ImplementationManager::create(const program_node
     if (auto impl = create_impl(node, params)) {
         update_impl(*impl, params);
         impl->set_node_params(node);
-        impl->can_share_kernels = node.get_program().get_config().get_property(ov::intel_gpu::hint::enable_kernels_reuse);
+        impl->can_share_kernels = node.get_program().get_config().get_enable_kernels_reuse();
         return impl;
     }
 
diff --git a/src/plugins/intel_gpu/src/graph/impls/registry/non_max_suppression_impls.cpp b/src/plugins/intel_gpu/src/graph/impls/registry/non_max_suppression_impls.cpp
index d974b78f8e6d14..ce461632631d15 100644
--- a/src/plugins/intel_gpu/src/graph/impls/registry/non_max_suppression_impls.cpp
+++ b/src/plugins/intel_gpu/src/graph/impls/registry/non_max_suppression_impls.cpp
@@ -59,7 +59,7 @@ const std::vector<std::shared_ptr<cldnn::ImplementationManager>>& Registry<non_m
                             const size_t kBatchNum = static_cast<size_t>(scores_layout.get_partial_shape()[0].get_length());
                             const size_t kClassNum = static_cast<size_t>(scores_layout.get_partial_shape()[1].get_length());
                             const size_t kNStreams =
-                                    static_cast<size_t>(node.get_program().get_config().get_property(ov::streams::num));
+                                    static_cast<size_t>(node.get_program().get_config().get_num_streams());
                             const size_t kKeyValue = kBatchNum * std::min(kClassNum, static_cast<size_t>(8)) * kNStreams;
                             return kKeyValue > 64;
                         }
diff --git a/src/plugins/intel_gpu/src/graph/include/primitive_inst.h b/src/plugins/intel_gpu/src/graph/include/primitive_inst.h
index 01286a1c6d04bc..619693f3b1a6fc 100644
--- a/src/plugins/intel_gpu/src/graph/include/primitive_inst.h
+++ b/src/plugins/intel_gpu/src/graph/include/primitive_inst.h
@@ -199,6 +199,8 @@ class primitive_inst {
     program_node const& get_node() const { return *_node; }
     network& get_network() const { return _network; }
     uint32_t get_network_id() const;
+    const ExecutionConfig& get_config() const { return get_network().get_config(); }
+
     virtual event::ptr set_output_memory(memory::ptr mem, bool check = true, size_t idx = 0);
     void check_memory_to_set(const memory& mem, const layout& layout) const;
     const std::list<const cldnn::program_node *>& get_users() const { return _node->get_users(); }
diff --git a/src/plugins/intel_gpu/src/graph/include/program_node.h b/src/plugins/intel_gpu/src/graph/include/program_node.h
index 269a3c30fd293c..229dec6a80c77e 100644
--- a/src/plugins/intel_gpu/src/graph/include/program_node.h
+++ b/src/plugins/intel_gpu/src/graph/include/program_node.h
@@ -158,6 +158,7 @@ struct program_node {
 
     program& get_program() { return myprog; }
     program& get_program() const { return myprog; }
+    const ExecutionConfig& get_config() const { return myprog.get_config(); }
 
     primitive_impl* get_selected_impl() const { return selected_impl.get(); }
     void set_selected_impl(std::unique_ptr<primitive_impl> impl);
diff --git a/src/plugins/intel_gpu/src/graph/layout_optimizer.cpp b/src/plugins/intel_gpu/src/graph/layout_optimizer.cpp
index 167b254a247637..dfd65cd9b58067 100644
--- a/src/plugins/intel_gpu/src/graph/layout_optimizer.cpp
+++ b/src/plugins/intel_gpu/src/graph/layout_optimizer.cpp
@@ -435,15 +435,10 @@ bool should_use_winograd_2x3_s1(const convolution_node& node,
                                 layout const& input_layout,
                                 layout const& weights_layout,
                                 bool output_size_handling_enabled) {
-    bool disable_winograd_conv = node.get_program().get_config().get_property(ov::intel_gpu::disable_winograd_convolution);
+    bool disable_winograd_conv = node.get_program().get_config().get_disable_winograd_convolution();
     if (disable_winograd_conv)
         return false;
 
-    // cases when NOT to use winograd
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_winograd_conv == 1)
-        return false;
-
     auto prim = node.get_primitive();
     if (input_layout.data_type != data_types::f16
         || (input_layout.is_static() && input_layout.feature() % 64 != 0)  // current algorithm is effective for ifm to be multiply of 64
@@ -1134,73 +1129,12 @@ bool layout_optimizer::is_primitive_implemented_for_onednn(program_node& node) {
     return false;
 }
 
-impl_types layout_optimizer::get_forced_impl_type_by_config(program_node& node) {
-#ifdef GPU_DEBUG_CONFIG
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->forced_impl_types.empty()) {
-        // Forcing impl type of one primitive
-        for (const auto& forced_impl_type : debug_config->forced_impl_types) {
-            if (node.is_type<fully_connected>()) {
-                if (forced_impl_type == "fc:ocl")
-                    return impl_types::ocl;
-                else if (forced_impl_type == "fc:onednn")
-                    return impl_types::onednn;
-            } else if (node.is_type<gemm>()) {
-                if (forced_impl_type == "gemm:ocl")
-                    return impl_types::ocl;
-                else if (forced_impl_type == "gemm:onednn")
-                    return impl_types::onednn;
-            } else if (node.is_type<detection_output>()) {
-                if (forced_impl_type == "do:cpu")
-                    return impl_types::cpu;
-                else if (forced_impl_type == "do:ocl")
-                    return impl_types::ocl;
-            } else if (node.is_type<reduce>()) {
-                if (forced_impl_type == "reduce:ocl")
-                    return impl_types::ocl;
-                else if (forced_impl_type == "reduce:onednn")
-                    return impl_types::onednn;
-            } else if (node.is_type<concatenation>()) {
-                if (forced_impl_type == "concat:ocl")
-                    return impl_types::ocl;
-                else if (forced_impl_type == "concat:onednn")
-                    return impl_types::onednn;
-            }
-
-            // Forcing one layer
-            size_t found_type = forced_impl_type.rfind(":");
-            if (found_type != std::string::npos) {
-                impl_types preferred_type = impl_types::any;
-                auto impl_type = forced_impl_type.substr(found_type + 1);
-                if (impl_type == "ocl")
-                    preferred_type = impl_types::ocl;
-                else if (impl_type == "onednn")
-                    preferred_type = impl_types::onednn;
-                else if (impl_type == "cpu")
-                    preferred_type = impl_types::cpu;
-
-                if (node.id() == forced_impl_type.substr(0, found_type)) {
-                    GPU_DEBUG_LOG << " Forced implementation type : " << forced_impl_type.substr(0, found_type) << " : "
-                                << forced_impl_type.substr(found_type + 1) << std::endl;
-                    return preferred_type;
-                }
-            }
-        }
-    }
-#endif
-
-    return impl_types::any;
-}
-
 impl_types layout_optimizer::get_preferred_impl_type(program_node& node, format preferred_format) {
     if (!_forcing_map.empty() && _forcing_map.count(node.id()) != 0) {
         auto forced_impl = _forcing_map.at(node.id()).second;
         if (forced_impl != impl_types::any)
             return forced_impl;
     }
-    auto forced_impl = get_forced_impl_type_by_config(node);
-    if (forced_impl != impl_types::any)
-        return forced_impl;
 
     auto shape_type = shape_types::any;
 
diff --git a/src/plugins/intel_gpu/src/graph/network.cpp b/src/plugins/intel_gpu/src/graph/network.cpp
index aa7c9a55775e6d..1b310fd4542f86 100644
--- a/src/plugins/intel_gpu/src/graph/network.cpp
+++ b/src/plugins/intel_gpu/src/graph/network.cpp
@@ -60,7 +60,7 @@ namespace cldnn {
 namespace {
 
 #ifdef GPU_DEBUG_CONFIG
-void dump_perf_data_raw(std::string dump_path, const std::list<std::shared_ptr<primitive_inst>>& exec_order) {
+void dump_perf_data_raw(std::string dump_path, bool per_iter_mode, const std::list<std::shared_ptr<primitive_inst>>& exec_order) {
     auto layouts_to_str = [](const std::vector<layout>& layouts) -> std::string {
         std::stringstream s;
         for (size_t i = 0; i < layouts.size(); i++) {
@@ -71,7 +71,6 @@ void dump_perf_data_raw(std::string dump_path, const std::list<std::shared_ptr<p
         return s.str();
     };
 
-    const bool per_iter_mode = cldnn::debug_configuration::get_instance()->dump_profiling_data_per_iter != 0;
     const std::string perf_raw_csv_header = per_iter_mode ? "prim_id,prim_type,stage,net_in_shapes,in_shapes,out_shapes,impl,iter,time_usec\n"
                                                           : "prim_id,prim_type,stage,net_in_shapes,in_shapes,out_shapes,impl,iters,time_usec\n";
     std::ofstream of(dump_path);
@@ -139,13 +138,12 @@ void dump_perf_data_raw(std::string dump_path, const std::list<std::shared_ptr<p
     }
 }
 
-void wait_for_the_turn() {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
+void wait_for_the_turn(const std::vector<std::string>& pids) {
     bool need_to_wait;
     do {
         need_to_wait = false;
         struct stat buffer;
-        for (auto pid : debug_config->after_proc) {
+        for (auto pid : pids) {
             auto path = "/proc/" + pid;
             std::cout << "check " + path << std::endl;
             if (stat(path.c_str(), &buffer) == 0) {
@@ -158,8 +156,7 @@ void wait_for_the_turn() {
 }
 
 #else
-void dump_perf_data_raw(std::string, const std::list<std::shared_ptr<primitive_inst>>&) {}
-void wait_for_the_turn() {}
+void dump_perf_data_raw(std::string, bool per_iter_mode, const std::list<std::shared_ptr<primitive_inst>>&) {}
 #endif
 }  // namespace
 
@@ -174,33 +171,22 @@ opt pass).
 */
 network::network(program::ptr program, stream::ptr stream, bool is_internal, bool is_primary_stream)
     : _program(program)
-    , _config(program->get_config())
     , _engine(program->get_engine())
     , _stream(stream)
-    , _memory_pool(new memory_pool(program->get_engine()))
+    , _memory_pool(new memory_pool(program->get_engine(), program->get_config()))
     , _internal(is_internal)
     , _is_primary_stream(is_primary_stream)
-    , _enable_profiling(program->get_config().get_property(ov::enable_profiling))
+    , _enable_profiling(program->get_config().get_enable_profiling())
     , _reset_arguments(true)
-    , _shape_predictor(new ShapePredictor(&program->get_engine(), program->get_config().get_property(ov::intel_gpu::buffers_preallocation_ratio))) {
+    , _shape_predictor(new ShapePredictor(&program->get_engine(), program->get_config().get_shape_predictor_settings())) {
     if (!_internal) {
         net_id = get_unique_net_id();
     }
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->after_proc.size() != 0) {
-        wait_for_the_turn();
-    }
-
-    GPU_DEBUG_IF(debug_config->mem_preallocation_params.is_initialized) {
-        auto& mem_preallocation_params = debug_config->mem_preallocation_params;
-        _shape_predictor.reset(new ShapePredictor(&program->get_engine(),
-                                                  mem_preallocation_params.next_iters_preallocation_count,
-                                                  mem_preallocation_params.max_per_iter_size,
-                                                  mem_preallocation_params.max_per_dim_diff,
-                                                  mem_preallocation_params.buffers_preallocation_ratio));
-    }
-
+    GPU_DEBUG_CODE(
+        if (get_config().get_start_after_processes().size() != 0) {
+            wait_for_the_turn(get_config().get_start_after_processes());
+    });
     calculate_weights_cache_capacity();
     allocate_primitives();
     configure_primitives_second_output();
@@ -238,9 +224,9 @@ network::~network() {
     if (_program != nullptr)
         _program->cancel_compilation_context();
     _memory_pool->clear_pool_for_network(net_id);
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->dump_profiling_data.empty()) {
-        dump_perf_data_raw(debug_config->dump_profiling_data + "/perf_raw" + std::to_string(net_id) + ".csv", _exec_order);
+    std::string dump_path = GPU_DEBUG_VALUE_OR(get_config().get_dump_profiling_data_path(), "");
+    GPU_DEBUG_IF(!dump_path.empty()) {
+        dump_perf_data_raw(dump_path + "/perf_raw" + std::to_string(net_id) + ".csv", false, _exec_order);
     }
 }
 
@@ -398,7 +384,7 @@ void network::calculate_weights_cache_capacity() {
     }
 
     // Sum all weights constants for each stream
-    required_mem_size += weights_const_size * _config.get_property(ov::streams::num);
+    required_mem_size += weights_const_size * get_config().get_num_streams();
     // Add all other constants (shared between streams)
     required_mem_size += total_const_size - weights_const_size;
 
diff --git a/src/plugins/intel_gpu/src/graph/non_max_suppression.cpp b/src/plugins/intel_gpu/src/graph/non_max_suppression.cpp
index 2732476a063f8f..df29ed36a7fd12 100644
--- a/src/plugins/intel_gpu/src/graph/non_max_suppression.cpp
+++ b/src/plugins/intel_gpu/src/graph/non_max_suppression.cpp
@@ -157,7 +157,7 @@ void non_max_suppression_gather_inst::update_output_memory() {
         // Can_be_optimized nodes are allocating from memory_pool too. In this case,
         // we need release the legacy output memory from memory pool explicitly.
         if (static_cast<bool>(_outputs[i]) &&
-            _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+            _node->get_program().get_config().get_enable_memory_pool()) {
             _network.get_memory_pool().release_memory(_outputs[i].get(), _node->get_unique_id(), _node->id(), _network.get_id());
         }
         _outputs[i] = {_network.get_engine().reinterpret_buffer(input_memory(i), _impl_params->get_output_layout(i))};
diff --git a/src/plugins/intel_gpu/src/graph/permute.cpp b/src/plugins/intel_gpu/src/graph/permute.cpp
index bf87e78e4bbbc5..c4fddfde978c2d 100644
--- a/src/plugins/intel_gpu/src/graph/permute.cpp
+++ b/src/plugins/intel_gpu/src/graph/permute.cpp
@@ -146,7 +146,7 @@ void permute_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs = {_network.get_engine().reinterpret_buffer(input_memory(), _impl_params->get_output_layout())};
diff --git a/src/plugins/intel_gpu/src/graph/primitive_inst.cpp b/src/plugins/intel_gpu/src/graph/primitive_inst.cpp
index 5774c828b2d59a..14a1072422f442 100644
--- a/src/plugins/intel_gpu/src/graph/primitive_inst.cpp
+++ b/src/plugins/intel_gpu/src/graph/primitive_inst.cpp
@@ -164,7 +164,7 @@ static memory::ptr get_memory_from_pool(engine& _engine,
     OPENVINO_ASSERT(!layout.is_dynamic() || layout.has_upper_bound(),
                     "[GPU] Can't allocate output for dynamic layout without upper bound");
     // Use layout with max tensor for dynamic shape with upper bound
-    if (_node.get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+    if (_node.get_program().get_config().get_enable_memory_pool()) {
         if (curr_memory != nullptr)
             pool.release_memory(curr_memory, _node.get_unique_id(), _node.id(), net_id);
         return pool.get_memory(layout,
@@ -558,7 +558,6 @@ void primitive_inst::clear_output_memory() {
 
 void primitive_inst::realloc_if_needed(bool prev_execution_skipped) {
     OV_ITT_SCOPED_TASK(ov::intel_gpu::itt::domains::intel_gpu_plugin, openvino::itt::handle("realloc_if_needed: " + id()));
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     GPU_DEBUG_PROFILED_STAGE(instrumentation::pipeline_stage::memory_allocation);
 
     const auto& users = get_user_insts();
@@ -837,11 +836,6 @@ void primitive_inst::realloc_if_needed(bool prev_execution_skipped) {
     }
 
     int32_t tmp_prealloc_count = get_prealloc_iter_num();
-    GPU_DEBUG_IF(debug_config->mem_preallocation_params.is_initialized) {
-        // If debug config is set, repsect the config most
-        tmp_prealloc_count = -1;
-    }
-
     // If we allocated too large memory, reclaim the memory.
     for (size_t i = 0; i < updated_layouts.size(); ++i) {
         bool reclaim = 0;
@@ -1083,8 +1077,7 @@ void primitive_inst::realloc_if_needed(bool prev_execution_skipped) {
 }
 
 bool primitive_inst::use_async_compilation() {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_async_compilation) {
+    GPU_DEBUG_IF(get_config().get_disable_async_compilation()) {
         return false;
     }
 
@@ -1276,8 +1269,7 @@ void primitive_inst::update_paddings() {
 
 void primitive_inst::do_runtime_skip_reorder() {
     OV_ITT_SCOPED_TASK(ov::intel_gpu::itt::domains::intel_gpu_plugin, openvino::itt::handle("do_runtime_skip_reorder: " + id()));
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_runtime_skip_reorder) {
+    GPU_DEBUG_IF(get_config().get_disable_runtime_skip_reorder()) {
         return;
     }
     if (can_be_optimized())
@@ -1582,8 +1574,7 @@ void primitive_inst::do_runtime_in_place_concat() {
         return false;
     };
     OV_ITT_SCOPED_TASK(ov::intel_gpu::itt::domains::intel_gpu_plugin, openvino::itt::handle("do_runtime_in_place_concat: " + id()));
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_runtime_buffer_fusing) {
+    GPU_DEBUG_IF(get_config().get_disable_runtime_buffer_fusing()) {
         return;
     }
     if (update_shape_done_by_other) {
@@ -1692,8 +1683,7 @@ void primitive_inst::do_runtime_skip_scatter_update() {
 
 void primitive_inst::do_runtime_in_place_crop() {
     OV_ITT_SCOPED_TASK(ov::intel_gpu::itt::domains::intel_gpu_plugin, openvino::itt::handle("do_runtime_in_place_crop: " + id()));
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_runtime_buffer_fusing) {
+    GPU_DEBUG_IF(get_config().get_disable_runtime_buffer_fusing()) {
         return;
     }
 
@@ -1986,8 +1976,7 @@ void primitive_inst::execute() {
 
     set_out_event(_impl->execute(_impl_params->dep_events, *this));
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->dump_profiling_data.empty()) {
+    GPU_DEBUG_IF(!get_config().get_dump_profiling_data_path().empty()) {
         auto ev = _impl_params->out_event;
         get_network().get_stream().wait_for_events({ev});
 
@@ -2043,7 +2032,7 @@ primitive_inst::primitive_inst(network & network, program_node const& node, bool
     : _network(network)
     , _node(&node)
     , _node_output_layout(node.get_output_layout())
-    , _use_shared_kernels(node.get_program().get_config().get_property(ov::intel_gpu::hint::enable_kernels_reuse))
+    , _use_shared_kernels(node.get_program().get_config().get_enable_kernels_reuse())
     , _impl_params(node.get_kernel_impl_params())
     , _impl(node.get_selected_impl() ? node.get_selected_impl()->clone() : nullptr)
     , _runtime_memory_dependencies(node.get_memory_dependencies())
@@ -2324,8 +2313,7 @@ void primitive_inst::update_weights() {
             reorder_impl->set_arguments(*reorder_inst, args);
             add_dep_event(reorder_impl->execute({}, *reorder_inst));
 
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(!debug_config->dump_profiling_data.empty()) {
+            GPU_DEBUG_IF(!get_config().get_dump_profiling_data_path().empty()) {
                 stream.wait_for_events(_impl_params->dep_events);
             }
 
@@ -2600,8 +2588,8 @@ cldnn::network::ptr primitive_inst::get_unfused_subgraph() {
         ExecutionConfig subgraph_config{
             ov::intel_gpu::allow_static_input_reorder(true),
             ov::intel_gpu::allow_new_shape_infer(true),
-            ov::enable_profiling(get_network().get_config().get_property(ov::enable_profiling)),
-            ov::intel_gpu::use_onednn(get_network().get_config().get_property(ov::intel_gpu::use_onednn))
+            ov::enable_profiling(get_network().get_config().get_enable_profiling()),
+            ov::intel_gpu::use_onednn(get_network().get_config().get_use_onednn())
         };
         auto prog = program::build_program(get_network().get_engine(),
                                            t,
@@ -2759,42 +2747,31 @@ bool primitive_inst::is_valid_fusion() const {
 }
 
 void primitive_inst::add_profiling_data(instrumentation::pipeline_stage stage, bool cache_hit, std::string memalloc_info, int64_t time, bool per_iter_mode) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-#ifdef GPU_DEBUG_CONFIG
-    int64_t curr_iter = -1;
-    GPU_DEBUG_IF(debug_config->dump_prof_data_iter_params.is_enabled) {
-        curr_iter = get_network().get_current_iteration_num();
-    }
-    GPU_DEBUG_IF(curr_iter < 0 || debug_config->is_target_dump_prof_data_iteration(curr_iter)) {
-#else
-    {
-#endif
-        instrumentation::perf_counter_key key {
-                _network.get_input_layouts(),
-                _impl_params->input_layouts,
-                _impl_params->output_layouts,
-                get_implementation_name(),
-                stage,
+    instrumentation::perf_counter_key key {
+            _network.get_input_layouts(),
+            _impl_params->input_layouts,
+            _impl_params->output_layouts,
+            get_implementation_name(),
+            stage,
 #ifdef GPU_DEBUG_CONFIG
-                per_iter_mode ? get_network().get_current_iteration_num() : 0,
+            per_iter_mode ? get_network().get_current_iteration_num() : 0,
 #else
-                0,
+            0,
 #endif
-                cache_hit,
-                memalloc_info
-        };
-
-        auto hash = instrumentation::perf_counter_hash()(key);
-        auto& d = _profiling_data[hash];
-        if (_profiling_info.find(hash) == _profiling_info.end()) {
-            _profiling_info.emplace(hash, key);
-        }
+            cache_hit,
+            memalloc_info
+    };
 
-        auto& total_time = std::get<0>(d);
-        auto& total_iter = std::get<1>(d);
-        total_time += time;
-        total_iter++;
+    auto hash = instrumentation::perf_counter_hash()(key);
+    auto& d = _profiling_data[hash];
+    if (_profiling_info.find(hash) == _profiling_info.end()) {
+        _profiling_info.emplace(hash, key);
     }
+
+    auto& total_time = std::get<0>(d);
+    auto& total_iter = std::get<1>(d);
+    total_time += time;
+    total_iter++;
 }
 
 std::string primitive_inst::get_implementation_name() const {
diff --git a/src/plugins/intel_gpu/src/graph/program.cpp b/src/plugins/intel_gpu/src/graph/program.cpp
index c3de17f8a196d3..df03981a6057d5 100644
--- a/src/plugins/intel_gpu/src/graph/program.cpp
+++ b/src/plugins/intel_gpu/src/graph/program.cpp
@@ -16,7 +16,6 @@
 #include "intel_gpu/runtime/compilation_context.hpp"
 #include "intel_gpu/graph/program.hpp"
 
-#include "auto_tuner.h"
 #include "layout_optimizer.h"
 #include "pass_manager.h"
 #include "primitive_type.h"
@@ -91,7 +90,6 @@
 #include <map>
 #include <memory>
 #include <set>
-#include <sstream>
 #include <stdio.h>
 #include <string>
 #include <utility>
@@ -107,8 +105,8 @@ using namespace cldnn;
 using namespace ov::intel_gpu;
 
 static ov::threading::IStreamsExecutor::Config make_task_executor_config(const ExecutionConfig& config, std::string tags, int num_streams = 0) {
-    int streams = (num_streams > 0) ? num_streams : config.get_property(ov::compilation_num_threads);
-    auto priority = config.get_property(ov::intel_gpu::hint::host_task_priority);
+    int streams = (num_streams > 0) ? num_streams : config.get_compilation_num_threads();
+    auto priority = config.get_host_task_priority();
     auto core_type = ov::hint::SchedulingCoreType::ANY_CORE;
     switch (priority) {
         case ov::hint::Priority::LOW: core_type = ov::hint::SchedulingCoreType::ECORE_ONLY; break;
@@ -116,7 +114,7 @@ static ov::threading::IStreamsExecutor::Config make_task_executor_config(const E
         case ov::hint::Priority::HIGH: core_type = ov::hint::SchedulingCoreType::PCORE_ONLY; break;
         default: OPENVINO_ASSERT(false, "[GPU] Can't create task executor: invalid host task priority value: ", priority);
     }
-    bool enable_cpu_pinning = config.get_property(ov::hint::enable_cpu_pinning);
+    bool enable_cpu_pinning = config.get_enable_cpu_pinning();
 
     ov::threading::IStreamsExecutor::Config task_executor_config(tags,
                                                                  streams,
@@ -162,7 +160,7 @@ program::program(engine& engine_ref,
     program_node::reset_unique_id();
     if (no_optimizations) {
         init_graph();
-        _config.apply_user_properties(_engine.get_device_info());
+        _config.finalize(_engine);
     } else {
         build_program(is_internal);
         if (_is_body_program) {
@@ -198,7 +196,7 @@ program::program(engine& engine_ref,
       _task_executor(std::move(task_executor)),
       processing_order(),
       is_internal(is_internal) {
-    _config.apply_user_properties(_engine.get_device_info());
+    _config.finalize(_engine);
     init_primitives();
     init_program();
     prepare_nodes(nodes);
@@ -211,8 +209,8 @@ program::program(engine& engine, const ExecutionConfig& config)
       _config(config),
       processing_order() {
     init_primitives();
-    _config.apply_user_properties(_engine.get_device_info());
-    new_shape_infer = _config.get_property(ov::intel_gpu::allow_new_shape_infer);
+    _config.finalize(_engine);
+    new_shape_infer = _config.get_allow_new_shape_infer();
     _layout_optimizer = std::make_unique<layout_optimizer>();
 }
 
@@ -220,11 +218,10 @@ program::~program() {
 }
 
 void program::init_program() {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     set_options();
 
     pm = std::unique_ptr<pass_manager>(new pass_manager(*this));
-    new_shape_infer = _config.get_property(ov::intel_gpu::allow_new_shape_infer);
+    new_shape_infer = _config.get_allow_new_shape_infer();
 
     if (_task_executor == nullptr)
         _task_executor = program::make_task_executor(_config);
@@ -232,19 +229,14 @@ void program::init_program() {
                                                                       kernel_selector::KernelBase::get_db().get_batch_headers(),
                                                                       kernel_selector::KernelBase::get_db().get_cm_batch_headers()));
 
-    _kernels_cache->set_kernels_reuse(get_config().get_property(ov::intel_gpu::hint::enable_kernels_reuse));
+    _kernels_cache->set_kernels_reuse(_config.get_enable_kernels_reuse());
 
     if (!_compilation_context)
         _compilation_context = program::make_compilation_context(_config);
 
 
     _layout_optimizer = std::make_unique<layout_optimizer>();
-    size_t impls_cache_capacity = _impls_cache_capacity;
-    GPU_DEBUG_IF(debug_config->impls_cache_capacity >= 0) {
-        impls_cache_capacity = debug_config->impls_cache_capacity;
-    }
-
-    _impls_cache = std::make_unique<ImplementationsCache>(impls_cache_capacity);
+    _impls_cache = std::make_unique<ImplementationsCache>(get_config().get_impls_cache_capacity());
     // Remove items of compilation context's internal queue when some impl is popped in kernels_cache
     // compilation context's queue check duplication of inserted task
     _impls_cache->set_remove_item_callback([this](ImplementationsCache::ItemType& item) {
@@ -486,26 +478,17 @@ void program::set_options() {
     static std::atomic<uint32_t> id_gen{0};
     prog_id = ++id_gen;
     assert(prog_id != 0);
-    if (!_config.get_property(ov::intel_gpu::force_implementations).empty()) {
-        _config.set_property(ov::intel_gpu::optimize_data(true));
-    }
-
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->dump_graphs.empty()) {
-        _config.set_property(ov::intel_gpu::dump_graphs(debug_config->dump_graphs));
-    }
 }
 
 void program::build_program(bool is_internal) {
     init_graph();
-    _config.apply_user_properties(_engine.get_device_info());
+    _config.finalize(_engine);
     { pre_optimize_graph(is_internal); }
     run_graph_compilation();
     { post_optimize_graph(is_internal); }
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
 #ifdef GPU_DEBUG_CONFIG
-    if (debug_config->dry_run_path.empty() || is_internal) {
+    if (get_config().get_dry_run_path().empty() || is_internal) {
 #else
     {
 #endif
@@ -528,10 +511,6 @@ void program::init_graph() {
     for (auto& node : processing_order) {
         if (!node->is_type<data>())
             node->get_output_layouts();
-        if (node->is_type<lstm_seq>()) {
-            _config.set_property(ov::intel_gpu::use_onednn(true));
-            _config.set_property(ov::intel_gpu::queue_type(QueueTypes::in_order));
-        }
     }
     // Perform initial shape_of subgraphs markup
     apply_opt_pass<mark_shape_of_subgraphs>();
@@ -549,7 +528,7 @@ void program::pre_optimize_graph(bool is_internal) {
 
     bool output_size_handling_enabled = analyze_output_size_handling_need();
 
-    bool optimize_data = _config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = _config.get_optimize_data();
     if (optimize_data) {
         apply_opt_pass<prepare_quantization>();
     }
@@ -559,26 +538,13 @@ void program::pre_optimize_graph(bool is_internal) {
 
     reorder_factory rf;
     if (optimize_data) {
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-#ifdef GPU_DEBUG_CONFIG
-        GPU_DEBUG_IF(!debug_config->disable_primitive_fusing) {
-#else
-        {
-#endif
-            apply_opt_pass<prepare_primitive_fusing_through>();
-        }
+        apply_opt_pass<prepare_primitive_fusing_through>();
 
         apply_opt_pass<pre_replace_deconv>();
 
         apply_opt_pass<reorder_transfer>();
 
-#ifdef GPU_DEBUG_CONFIG
-        GPU_DEBUG_IF(!debug_config->disable_primitive_fusing) {
-#else
-        {
-#endif
-            apply_opt_pass<prepare_primitive_fusing>();
-        }
+        apply_opt_pass<prepare_primitive_fusing>();
 
         apply_opt_pass<select_preferred_formats>();
 
@@ -626,7 +592,7 @@ void program::post_optimize_graph(bool is_internal) {
 
     reorder_factory rf;
 
-    bool optimize_data = _config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = _config.get_optimize_data();
 
     if (!is_internal) {
         apply_opt_pass<post_optimize_weights>(rf);
@@ -634,10 +600,9 @@ void program::post_optimize_graph(bool is_internal) {
 
     apply_opt_pass<remove_redundant_reorders>(false, true);  // TODO: do we need it at this place also?
 
-    auto partial_build = _config.get_property(ov::intel_gpu::partial_build_program);
+    auto partial_build = _config.get_partial_build_program();
 #ifdef GPU_DEBUG_CONFIG
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    if (!is_internal && (!partial_build || !debug_config->dry_run_path.empty())) {
+    if (!is_internal && (!partial_build || !_config.get_dry_run_path().empty())) {
 #else
     if (!is_internal && !partial_build) {
 #endif
@@ -653,7 +618,7 @@ void program::post_optimize_graph(bool is_internal) {
 
     // Recalculate processing order after all graph transformation to keep optimal primitives ordering
     // for OOO queue
-    if (_config.get_property(ov::intel_gpu::queue_type) == QueueTypes::out_of_order)
+    if (_config.get_queue_type() == QueueTypes::out_of_order)
         get_processing_order().calculate_BFS_processing_order();
 
     apply_opt_pass<mark_state_init_subgraphs>();
@@ -777,7 +742,7 @@ const std::vector<primitive_id>& program::get_allocating_order(bool forced_updat
 }
 
 void program::prepare_memory_dependencies() {
-    if (!_config.get_property(ov::intel_gpu::enable_memory_pool))
+    if (!_config.get_enable_memory_pool())
         return;
     for (auto& node : get_processing_order()) {
         node->add_memory_dependency(node->get_unique_id());
@@ -1408,8 +1373,7 @@ program::primitives_info program::get_current_stage_info() const {
 }
 
 void program::save_pass_info(std::string pass_name) {
-    // TODO: Directory path here can be probably changed to some bool flag
-    if (!_config.get_property(ov::intel_gpu::dump_graphs).empty())
+    GPU_DEBUG_IF(!_config.get_dump_graphs_path().empty())
         optimizer_passes_info.emplace_back(pass_name, get_current_stage_info());
 }
 
@@ -1437,7 +1401,7 @@ const program::primitives_info& program::get_primitives_info() const { return pr
 void program::apply_opt_pass(base_pass& pass) { pm->run(*this, pass); }
 
 void program::set_layout_optimizer_attributes(layout_optimizer& lo) {
-    lo.set_implementation_forcing(_config.get_property(ov::intel_gpu::force_implementations));
+    lo.set_implementation_forcing(_config.get_force_implementations());
 
 
     // first pass to set layout optimization_attributes for topology
@@ -1663,15 +1627,15 @@ void program::set_layout_optimizer_attributes(layout_optimizer& lo) {
         lo.set_optimization_attribute(layout_optimizer::optimization_attributes_type::bs_fs_yx_bsv16_fsv16_network, 1);
 
 #ifdef ENABLE_ONEDNN_FOR_GPU
-    bool enable_onednn_for_tests = get_config().get_property(ov::intel_gpu::optimize_data) || is_internal_program();
+    bool enable_onednn_for_tests = get_config().get_optimize_data() || is_internal_program();
     auto& engine = get_engine();
     if (engine.get_device_info().vendor_id == INTEL_VENDOR_ID &&
-        get_config().get_property(ov::intel_gpu::queue_type) == QueueTypes::in_order &&
+        get_config().get_queue_type() == QueueTypes::in_order &&
         enable_onednn_for_tests) {
             if (engine.get_device_info().supports_immad) {
                 lo.add_all_onednn_impls_optimization_attribute();
             } else {
-                if (get_config().get_property(ov::intel_gpu::use_onednn)) {
+                if (get_config().get_use_onednn()) {
                     lo.enable_onednn_for<lstm_seq>();
                 }
             }
@@ -1681,7 +1645,7 @@ void program::set_layout_optimizer_attributes(layout_optimizer& lo) {
 
 std::pair<int64_t, int64_t> program::get_estimated_device_mem_usage() {
     auto max_alloc_size = get_engine().get_device_info().max_alloc_mem_size;
-    memory_pool pool(get_engine());
+    memory_pool pool(get_engine(), get_config());
     int64_t const_sum = 0;
 
 #ifdef __unix__
@@ -1885,8 +1849,8 @@ void program::load(cldnn::BinaryInputBuffer& ib) {
     init_program();
 
     std::shared_ptr<ov::MappedMemory> mapped_memory = nullptr;
-    std::string weights_path = _config.get_property(ov::weights_path);
-    if (_config.get_property(ov::cache_mode) == ov::CacheMode::OPTIMIZE_SIZE &&
+    std::string weights_path = _config.get_weights_path();
+    if (_config.get_cache_mode() == ov::CacheMode::OPTIMIZE_SIZE &&
         ov::util::validate_weights_path(weights_path)) {
         mapped_memory = ov::load_mmap_object(weights_path);
     }
diff --git a/src/plugins/intel_gpu/src/graph/program_dump_graph.cpp b/src/plugins/intel_gpu/src/graph/program_dump_graph.cpp
index 6a09fcd10eb513..eb5c152a361a16 100644
--- a/src/plugins/intel_gpu/src/graph/program_dump_graph.cpp
+++ b/src/plugins/intel_gpu/src/graph/program_dump_graph.cpp
@@ -3,6 +3,7 @@
 //
 
 #include "program_dump_graph.h"
+#include "intel_gpu/runtime/debug_configuration.hpp"
 #include "to_string_utils.h"
 #include "data_inst.h"
 #include "condition_inst.h"
@@ -139,7 +140,6 @@ void close_stream(std::ofstream& graph) { graph.close(); }
 std::string get_node_id(const program_node* ptr) { return "node_" + std::to_string(reinterpret_cast<uintptr_t>(ptr)); }
 
 void dump_full_node(std::ofstream& out, const program_node* node) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     try {
         out << node->type()->to_string(*node);
     } catch(const std::exception& e) {
@@ -157,7 +157,7 @@ void dump_full_node(std::ofstream& out, const program_node* node) {
 }  // namespace
 
 std::string get_dir_path(const ExecutionConfig& config) {
-    auto path = config.get_property(ov::intel_gpu::dump_graphs);
+    std::string path = GPU_DEBUG_VALUE_OR(config.get_dump_graphs_path(), "");
     if (path.empty()) {
         return {};
     }
diff --git a/src/plugins/intel_gpu/src/graph/program_node.cpp b/src/plugins/intel_gpu/src/graph/program_node.cpp
index b7767c14f9abff..65df228d6c733f 100644
--- a/src/plugins/intel_gpu/src/graph/program_node.cpp
+++ b/src/plugins/intel_gpu/src/graph/program_node.cpp
@@ -1851,8 +1851,7 @@ void program_node::create_onednn_primitive_attributes(
         // Trying to combine multiplications and additions which are placed one after another.
         // We do it in the cycle because some optimization cases can be simplified again from time to time
         do {
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(debug_config->disable_onednn_opt_post_ops)
+            GPU_DEBUG_IF(get_config().get_disable_onednn_post_ops_opt())
                 break;
             optimized_post_ops = try_optimize_post_ops(fused_ops, optimized_post_ops, attrs, optimization_is_finished);
         } while (!optimization_is_finished);
diff --git a/src/plugins/intel_gpu/src/graph/reorder.cpp b/src/plugins/intel_gpu/src/graph/reorder.cpp
index 76b15ca54bcff8..75a4011eeefc25 100644
--- a/src/plugins/intel_gpu/src/graph/reorder.cpp
+++ b/src/plugins/intel_gpu/src/graph/reorder.cpp
@@ -287,7 +287,7 @@ void reorder_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
 
diff --git a/src/plugins/intel_gpu/src/graph/reshape.cpp b/src/plugins/intel_gpu/src/graph/reshape.cpp
index fc874e29f70ac4..b6e5b23a0f6476 100644
--- a/src/plugins/intel_gpu/src/graph/reshape.cpp
+++ b/src/plugins/intel_gpu/src/graph/reshape.cpp
@@ -320,7 +320,7 @@ void reshape_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs = {_network.get_engine().reinterpret_buffer(input_memory(), _impl_params->get_output_layout())};
diff --git a/src/plugins/intel_gpu/src/graph/scatter_elements_update.cpp b/src/plugins/intel_gpu/src/graph/scatter_elements_update.cpp
index 316acef0e492e8..a651baa50002fa 100644
--- a/src/plugins/intel_gpu/src/graph/scatter_elements_update.cpp
+++ b/src/plugins/intel_gpu/src/graph/scatter_elements_update.cpp
@@ -75,7 +75,7 @@ void scatter_elements_update_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs = {_network.get_engine().reinterpret_buffer(input_memory(), _impl_params->get_output_layout())};
diff --git a/src/plugins/intel_gpu/src/graph/scatter_nd_update.cpp b/src/plugins/intel_gpu/src/graph/scatter_nd_update.cpp
index 2f109f83df428f..3dbec05dbbe3b3 100644
--- a/src/plugins/intel_gpu/src/graph/scatter_nd_update.cpp
+++ b/src/plugins/intel_gpu/src/graph/scatter_nd_update.cpp
@@ -86,7 +86,7 @@ void scatter_nd_update_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs = {_network.get_engine().reinterpret_buffer(input_memory(), _impl_params->get_output_layout())};
diff --git a/src/plugins/intel_gpu/src/graph/scatter_update.cpp b/src/plugins/intel_gpu/src/graph/scatter_update.cpp
index 4291ee67caa3ef..947507533796e0 100644
--- a/src/plugins/intel_gpu/src/graph/scatter_update.cpp
+++ b/src/plugins/intel_gpu/src/graph/scatter_update.cpp
@@ -66,7 +66,7 @@ void scatter_update_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs = {_network.get_engine().reinterpret_buffer(input_memory(), _impl_params->get_output_layout())};
diff --git a/src/plugins/intel_gpu/src/graph/select.cpp b/src/plugins/intel_gpu/src/graph/select.cpp
index 5435de5598bea0..a3b6ad9166c964 100644
--- a/src/plugins/intel_gpu/src/graph/select.cpp
+++ b/src/plugins/intel_gpu/src/graph/select.cpp
@@ -95,7 +95,7 @@ select_inst::typed_primitive_inst(network& network, select_node const& node) : p
                                 3,
                                 "");
 
-    bool allow_new_shape_infer = network.get_program()->get_config().get_property(ov::intel_gpu::allow_new_shape_infer);
+    bool allow_new_shape_infer = network.get_program()->get_config().get_allow_new_shape_infer();
     // Broadcast check is performed in ngraph shape infer of select when allow_new_shape_infer=true
     if (!allow_new_shape_infer) {
         if (node.get_primitive()->broadcast_spec.m_type == ov::op::AutoBroadcastType::NONE) {
diff --git a/src/plugins/intel_gpu/src/graph/strided_slice.cpp b/src/plugins/intel_gpu/src/graph/strided_slice.cpp
index 007553b8a9d192..674e7649bc9820 100644
--- a/src/plugins/intel_gpu/src/graph/strided_slice.cpp
+++ b/src/plugins/intel_gpu/src/graph/strided_slice.cpp
@@ -208,7 +208,7 @@ void strided_slice_inst::update_output_memory() {
     // Can_be_optimized nodes are allocating from memory_pool too. In this case,
     // we need release the legacy output memory from memory pool explicitly.
     if (static_cast<bool>(_outputs[0]) &&
-        _node->get_program().get_config().get_property(ov::intel_gpu::enable_memory_pool)) {
+        _node->get_program().get_config().get_enable_memory_pool()) {
         _network.get_memory_pool().release_memory(_outputs[0].get(), _node->get_unique_id(), _node->id(), _network.get_id());
     }
     _outputs[0] = input_memory_ptr();
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernels/dynamic_quantize/dynamic_quantize_kernel_ref.cpp b/src/plugins/intel_gpu/src/kernel_selector/kernels/dynamic_quantize/dynamic_quantize_kernel_ref.cpp
index a103a159faaf5d..72f3cc9120b9f1 100644
--- a/src/plugins/intel_gpu/src/kernel_selector/kernels/dynamic_quantize/dynamic_quantize_kernel_ref.cpp
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernels/dynamic_quantize/dynamic_quantize_kernel_ref.cpp
@@ -70,7 +70,6 @@ JitConstants DynamicQuantizeKernelRef::GetJitConstants(const dynamic_quantize_pa
 }
 
 CommonDispatchData DynamicQuantizeKernelRef::SetDefault(const dynamic_quantize_params& params) const {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     CommonDispatchData dispatchData;
 
     OPENVINO_ASSERT(params.outputs[0].GetLayout() == DataLayout::bfyx, "It supports only 4d tensor");
diff --git a/src/plugins/intel_gpu/src/kernel_selector/kernels/fully_connected/fully_connected_kernel_bf_tiled.cpp b/src/plugins/intel_gpu/src/kernel_selector/kernels/fully_connected/fully_connected_kernel_bf_tiled.cpp
index d0d3f293fe8797..e2f740fde9600b 100644
--- a/src/plugins/intel_gpu/src/kernel_selector/kernels/fully_connected/fully_connected_kernel_bf_tiled.cpp
+++ b/src/plugins/intel_gpu/src/kernel_selector/kernels/fully_connected/fully_connected_kernel_bf_tiled.cpp
@@ -89,26 +89,6 @@ static bool is_per_token_dynamic_quantize(const fully_connected_params& params)
 static size_t get_dynamic_quantize_group_size(const fully_connected_params& params) {
     auto dynamic_quantization_group_size = params.dynamic_quantization_group_size;
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->dynamic_quantize_group_size != debug_config->DYNAMIC_QUANTIZE_GROUP_SIZE_NOT_SET) {
-        dynamic_quantization_group_size = debug_config->dynamic_quantize_group_size;
-
-        // Specify which Fully-connected layer would be dynamic-quantized
-        GPU_DEBUG_IF(!debug_config->dynamic_quantize_layers_without_onednn.empty()) {
-            auto layers = debug_config->dynamic_quantize_layers_without_onednn;
-            auto iter = std::find_if(layers.begin(), layers.end(), [&](const std::string& pattern){
-                return debug_config->is_layer_name_matched(params.layerID, pattern);
-            });
-
-            if (iter != layers.end()) {
-                dynamic_quantization_group_size = debug_config->dynamic_quantize_group_size;
-                GPU_DEBUG_COUT << "Found specified Fully-connected layer [" << params.layerID << "]. Enable Dynamic-quantize." << std::endl;
-            } else {
-                dynamic_quantization_group_size = 0;
-            }
-        }
-    }
-
     size_t scale_group_size = get_scale_group_size(params);
     size_t zp_group_num = params.decompression_zero_point.Feature().v;
     size_t zp_group_size = 0;
diff --git a/src/plugins/intel_gpu/src/plugin/compiled_model.cpp b/src/plugins/intel_gpu/src/plugin/compiled_model.cpp
index 42ba3e46f83d01..eb6952eaed28f4 100644
--- a/src/plugins/intel_gpu/src/plugin/compiled_model.cpp
+++ b/src/plugins/intel_gpu/src/plugin/compiled_model.cpp
@@ -5,6 +5,7 @@
 #include "openvino/runtime/iplugin.hpp"
 #include "openvino/runtime/intel_gpu/properties.hpp"
 #include "openvino/runtime/internal_properties.hpp"
+#include "openvino/runtime/plugin_config.hpp"
 #include "openvino/util/weights_path.hpp"
 
 #include "intel_gpu/graph/serialization/binary_buffer.hpp"
@@ -20,17 +21,17 @@ namespace ov::intel_gpu {
 namespace {
 std::shared_ptr<ov::threading::ITaskExecutor> create_task_executor(const std::shared_ptr<const ov::IPlugin>& plugin,
                                                                    const ExecutionConfig& config) {
-    if (config.get_property(ov::internal::exclusive_async_requests)) {
+    if (config.get_exclusive_async_requests()) {
         // exclusive_async_requests essentially disables the streams (and hence should be checked first) => aligned with
         // the CPU behavior
         return plugin->get_executor_manager()->get_executor("GPU");
-    } else if (config.get_property(ov::hint::enable_cpu_pinning) ||
-               config.get_property(ov::hint::enable_cpu_reservation)) {
-        bool enable_cpu_pinning = config.get_property(ov::hint::enable_cpu_pinning);
-        bool enable_cpu_reservation = config.get_property(ov::hint::enable_cpu_reservation);
+    } else if (config.get_enable_cpu_pinning() ||
+               config.get_enable_cpu_reservation()) {
+        bool enable_cpu_pinning = config.get_enable_cpu_pinning();
+        bool enable_cpu_reservation = config.get_enable_cpu_reservation();
         return std::make_shared<ov::threading::CPUStreamsExecutor>(
             ov::threading::IStreamsExecutor::Config{"Intel GPU plugin executor",
-                                                    config.get_property(ov::num_streams),
+                                                    config.get_num_streams(),
                                                     1,
                                                     ov::hint::SchedulingCoreType::PCORE_ONLY,
                                                     enable_cpu_reservation,
@@ -38,7 +39,7 @@ std::shared_ptr<ov::threading::ITaskExecutor> create_task_executor(const std::sh
     } else {
         return std::make_shared<ov::threading::CPUStreamsExecutor>(
             ov::threading::IStreamsExecutor::Config{"Intel GPU plugin executor",
-                                                    config.get_property(ov::num_streams),
+                                                    config.get_num_streams(),
                                                     0,
                                                     ov::hint::SchedulingCoreType::ANY_CORE,
                                                     false,
@@ -62,7 +63,7 @@ CompiledModel::CompiledModel(std::shared_ptr<ov::Model> model,
       m_outputs(ov::ICompiledModel::outputs()),
       m_loaded_from_cache(false) {
     auto graph_base = std::make_shared<Graph>(model, m_context, m_config, 0);
-    for (uint16_t n = 0; n < m_config.get_property(ov::num_streams); n++) {
+    for (uint16_t n = 0; n < m_config.get_num_streams(); n++) {
         auto graph = n == 0 ? graph_base : std::make_shared<Graph>(graph_base, n);
         m_graphs.push_back(graph);
     }
@@ -157,7 +158,7 @@ CompiledModel::CompiledModel(cldnn::BinaryInputBuffer& ib,
     }
 
     auto graph_base = std::make_shared<Graph>(ib, context, m_config, 0);
-    for (uint16_t n = 0; n < m_config.get_property(ov::num_streams); n++) {
+    for (uint16_t n = 0; n < m_config.get_num_streams(); n++) {
         auto graph = n == 0 ? graph_base : std::make_shared<Graph>(graph_base, n);
         m_graphs.push_back(graph);
     }
@@ -179,8 +180,8 @@ std::shared_ptr<ov::IAsyncInferRequest> CompiledModel::create_infer_request() co
 void CompiledModel::export_model(std::ostream& model) const {
     // If ov::CacheMode::OPTIMIZE_SIZE is set, do the export iff it's possible to do weightless caching
     // which requires the weights_path.
-    ov::CacheMode cache_mode = m_config.get_property(ov::cache_mode);
-    std::string weights_path = m_config.get_property(ov::weights_path);
+    ov::CacheMode cache_mode = m_config.get_cache_mode();
+    std::string weights_path = m_config.get_weights_path();
     if (cache_mode == ov::CacheMode::OPTIMIZE_SIZE &&
         !ov::util::validate_weights_path(weights_path))
         return;
@@ -188,7 +189,7 @@ void CompiledModel::export_model(std::ostream& model) const {
     OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "CompiledModel::export_model");
     OPENVINO_ASSERT(!m_graphs.empty(), "[GPU] Model not loaded");
 
-    const ov::EncryptionCallbacks encryption_callbacks = m_config.get_property(ov::cache_encryption_callbacks);
+    const ov::EncryptionCallbacks encryption_callbacks = m_config.get_cache_encryption_callbacks();
 
     // Do not allow encryption for CacheMode::OPTIMIZE_SPEED - the cache size may cause severe memory penalty.
     const bool encryption_enabled = encryption_callbacks.encrypt && cache_mode == ov::CacheMode::OPTIMIZE_SIZE;
@@ -291,15 +292,15 @@ ov::Any CompiledModel::get_property(const std::string& name) const {
     } else if (name == ov::loaded_from_cache) {
         return decltype(ov::loaded_from_cache)::value_type {m_loaded_from_cache};
     } else if (name == ov::optimal_number_of_infer_requests) {
-        unsigned int nr = m_config.get_property(ov::num_streams);
-        if (m_config.get_property(ov::hint::performance_mode) != ov::hint::PerformanceMode::LATENCY)
+        unsigned int nr = m_config.get_num_streams();
+        if (m_config.get_performance_mode() != ov::hint::PerformanceMode::LATENCY)
             nr *= 2;
         return decltype(ov::optimal_number_of_infer_requests)::value_type {nr};
     } else if (name == ov::execution_devices) {
         return decltype(ov::execution_devices)::value_type{m_context->get_device_name()};
     }
 
-    return m_config.get_property(name);
+    return m_config.get_property(name, OptionVisibility::RELEASE);
 }
 
 std::shared_ptr<ov::ISyncInferRequest> CompiledModel::create_sync_infer_request() const {
diff --git a/src/plugins/intel_gpu/src/plugin/graph.cpp b/src/plugins/intel_gpu/src/plugin/graph.cpp
index 6859728076fb6a..cba0d6aab9276d 100644
--- a/src/plugins/intel_gpu/src/plugin/graph.cpp
+++ b/src/plugins/intel_gpu/src/plugin/graph.cpp
@@ -2,7 +2,10 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+#include "intel_gpu/graph/serialization/helpers.hpp"
 #include "intel_gpu/runtime/layout.hpp"
+#include "openvino/core/any.hpp"
+#include "openvino/runtime/plugin_config.hpp"
 #include "openvino/runtime/threading/executor_manager.hpp"
 #include "openvino/runtime/exec_model_info.hpp"
 #include "openvino/pass/serialize.hpp"
@@ -38,7 +41,7 @@ Graph::Graph(std::shared_ptr<ov::Model> model, const RemoteContextImpl::Ptr& con
     : m_context(context)
     , m_config(config)
     , m_stream_id(stream_id) {
-    auto program_builder = std::make_shared<ProgramBuilder>(model, get_engine(), config, false);
+    auto program_builder = std::make_shared<ProgramBuilder>(model, get_engine(), config);
     m_config = program_builder->get_config();
 
     build(program_builder->get_compiled_program());
@@ -85,15 +88,11 @@ Graph::Graph(cldnn::BinaryInputBuffer &ib, const RemoteContextImpl::Ptr& context
             ib >> perfEntry.parentPrimitive;
         }
     }
-    {
-        bool bool_prop_value;
-        ib >> bool_prop_value;
-        m_config.set_property(ov::intel_gpu::partial_build_program(bool_prop_value));
-        ib >> bool_prop_value;
-        m_config.set_property(ov::intel_gpu::optimize_data(bool_prop_value));
-        ib >> bool_prop_value;
-        m_config.set_property(ov::intel_gpu::allow_new_shape_infer(bool_prop_value));
-    }
+
+    IstreamAttributeVisitor<cldnn::BinaryInputBuffer> visitor(ib);
+    m_config.visit_attributes(visitor);
+    m_config.set_user_property(config.get_user_properties()); // Copy user properties if those were modified on import call
+    m_config.finalize(context.get(), nullptr);
 
     auto imported_prog = std::make_shared<cldnn::program>(get_engine(), m_config);
     imported_prog->load(ib);
@@ -114,9 +113,8 @@ Graph::Graph(std::shared_ptr<Graph> graph, uint16_t stream_id)
 }
 
 Graph::~Graph() {
-    GPU_DEBUG_IF(cldnn::debug_configuration::get_instance()->host_time_profiling) {
-        const auto log_level = cldnn::debug_configuration::get_instance()->host_time_profiling;
-
+    auto log_level = GPU_DEBUG_VALUE_OR(m_config.get_host_time_profiling(), 0);
+    GPU_DEBUG_IF(log_level) {
         auto get_time_str = [](int64_t time_mcs, int64_t iters_num = 1) {
             double time = static_cast<double>(time_mcs);
             time /= iters_num;
@@ -177,25 +175,26 @@ void Graph::build(std::shared_ptr<cldnn::program> program) {
 
     auto external_queue = m_context->get_external_queue();
     if (external_queue) {
-        OPENVINO_ASSERT(m_config.get_property(ov::num_streams) == 1, "[GPU] Throughput streams can't be used with shared queue!");
+        OPENVINO_ASSERT(m_config.get_num_streams() == 1, "[GPU] Throughput streams can't be used with shared queue!");
         const auto &engine = program->get_engine();
         m_network = std::make_shared<cldnn::network>(program, engine.create_stream(m_config, external_queue), m_stream_id);
     } else {
         m_network = std::make_shared<cldnn::network>(program, m_stream_id);
     }
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->dry_run_path.empty()) {
-        ov::pass::Serialize(debug_config->dry_run_path, "").run_on_model(get_runtime_model());
+    std::string dry_run_path = GPU_DEBUG_VALUE_OR(m_config.get_dry_run_path(), "");
+    std::string dump_graphs_path = GPU_DEBUG_VALUE_OR(m_config.get_dump_graphs_path(), "");
+    GPU_DEBUG_IF(!dry_run_path.empty()) {
+        ov::pass::Serialize(dry_run_path, "").run_on_model(get_runtime_model());
         exit(0);
     }
 
-    GPU_DEBUG_IF(!debug_config->dump_graphs.empty() && m_stream_id == 0) {
+    GPU_DEBUG_IF(!dump_graphs_path.empty() && m_stream_id == 0) {
         static int net_id = 0;
         auto steps_info = get_network()->get_optimizer_passes_info();
         size_t step_idx = 0;
         for (auto& step : steps_info) {
-            auto xml_path = debug_config->dump_graphs + std::to_string(net_id) + "_" + std::to_string(step_idx) + "_" + step.first + "_graph.xml";
+            auto xml_path = dump_graphs_path + std::to_string(net_id) + "_" + std::to_string(step_idx) + "_" + step.first + "_graph.xml";
             ov::pass::Serialize(xml_path, "").run_on_model(get_runtime_model(step.second, true));
             step_idx++;
         }
@@ -209,7 +208,7 @@ bool Graph::use_external_queue() const {
 
 std::shared_ptr<ov::Model> Graph::get_runtime_model(std::vector<cldnn::primitive_info>& primitives_info, bool filter_const_primitives) {
     OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "Graph::get_runtime_model");
-    if (m_config.get_property(ov::enable_profiling)) {
+    if (m_config.get_enable_profiling()) {
         try {
             // Update may throw an exception for step-by-step runtime graph dump,
             // since network->get_executed_primitives() method can't be called before network execution
@@ -520,11 +519,8 @@ void Graph::export_model(cldnn::BinaryOutputBuffer &ob) {
             ob << perf_item.second.second.parentPrimitive;
         }
     }
-    {
-        ob << m_config.get_property(ov::intel_gpu::partial_build_program);
-        ob << m_config.get_property(ov::intel_gpu::optimize_data);
-        ob << m_config.get_property(ov::intel_gpu::allow_new_shape_infer);
-    }
+    OstreamAttributeVisitor<cldnn::BinaryOutputBuffer> visitor(ob);
+    m_config.visit_attributes(visitor);
 
     ob.set_stream(m_network->get_stream_ptr().get());
     m_network->get_program()->save(ob);
diff --git a/src/plugins/intel_gpu/src/plugin/ops/condition.cpp b/src/plugins/intel_gpu/src/plugin/ops/condition.cpp
index 5c797b622aa28b..da080544363d00 100644
--- a/src/plugins/intel_gpu/src/plugin/ops/condition.cpp
+++ b/src/plugins/intel_gpu/src/plugin/ops/condition.cpp
@@ -1,6 +1,7 @@
 // Copyright (C) 2023 Intel Corporation
 // SPDX-License-Identifier: Apache-2.0
 //
+#include "intel_gpu/runtime/internal_properties.hpp"
 #include "openvino/op/if.hpp"
 #include "intel_gpu/plugin/program_builder.hpp"
 #include "intel_gpu/primitives/condition.hpp"
@@ -20,17 +21,12 @@ static cldnn::condition::branch gen_branch(ProgramBuilder& p, const std::shared_
                     << internal_body->get_friendly_name()
                     << ", num inputs: " << op->get_input_size() << std::endl;
 
-    auto config = p.get_config();
-    {
-        auto custom_outputs = config.get_property(ov::intel_gpu::custom_outputs);
-        if (!custom_outputs.empty()) {
-            config.set_property(ov::intel_gpu::custom_outputs(std::vector<std::string>({})));
-        }
-    }
-    config.set_property(ov::intel_gpu::max_dynamic_batch(1));
+    auto config = p.get_config().clone();
+    config.set_property(ov::intel_gpu::custom_outputs(std::vector<std::string>({})));
     config.set_property(ov::intel_gpu::allow_new_shape_infer(op->is_dynamic() || p.use_new_shape_infer()));
+    config.finalize(p.get_engine());
 
-    ProgramBuilder prog(internal_body, p.get_engine(), config, false, p.get_task_executor(), p.get_compilation_context(), true);
+    ProgramBuilder prog(internal_body, p.get_engine(), config, p.get_task_executor(), p.get_compilation_context(), true);
     branch.inner_program = prog.get_compiled_program();
 
     auto& input_map = branch.input_map;
diff --git a/src/plugins/intel_gpu/src/plugin/ops/loop.cpp b/src/plugins/intel_gpu/src/plugin/ops/loop.cpp
index 3e052c134390ae..556738c5df52ea 100644
--- a/src/plugins/intel_gpu/src/plugin/ops/loop.cpp
+++ b/src/plugins/intel_gpu/src/plugin/ops/loop.cpp
@@ -297,13 +297,12 @@ static void CreateCommonLoopOp(ProgramBuilder& p, const std::shared_ptr<ov::op::
 
     auto output_names_vec = GetOutputNames(layerName, body_execution_condition_id, output_primitive_maps, back_edges);
 
-    auto config = p.get_config();
+    auto config = p.get_config().clone();
     config.set_property(ov::intel_gpu::custom_outputs(output_names_vec));
-    config.set_property(ov::intel_gpu::max_dynamic_batch(1));
-    config.set_property(ov::intel_gpu::allow_new_shape_infer(is_dynamic));
+    config.finalize(p.get_engine());
 
     // get body program from ov::Model
-    ProgramBuilder prog(ov_model, p.get_engine(), config, false, p.get_task_executor(), p.get_compilation_context(), true);
+    ProgramBuilder prog(ov_model, p.get_engine(), config, p.get_task_executor(), p.get_compilation_context(), true);
     auto body_program = prog.get_compiled_program();
 
     GPU_DEBUG_LOG << "* trip_count_id                 : " << trip_count_id << std::endl;
diff --git a/src/plugins/intel_gpu/src/plugin/plugin.cpp b/src/plugins/intel_gpu/src/plugin/plugin.cpp
index c1081a6df34840..cad527a9f7d63a 100644
--- a/src/plugins/intel_gpu/src/plugin/plugin.cpp
+++ b/src/plugins/intel_gpu/src/plugin/plugin.cpp
@@ -7,7 +7,6 @@
 #include <algorithm>
 #include <cctype>
 #include <cmath>
-#include <limits>
 #include <map>
 #include <memory>
 #include <mutex>
@@ -24,22 +23,19 @@
 #include "intel_gpu/runtime/debug_configuration.hpp"
 #include "intel_gpu/runtime/device_query.hpp"
 #include "intel_gpu/runtime/execution_config.hpp"
+#include "intel_gpu/runtime/internal_properties.hpp"
 #include "intel_gpu/runtime/itt.hpp"
+#include "openvino/core/any.hpp"
 #include "openvino/core/deprecated.hpp"
-#include "openvino/op/gather.hpp"
-#include "openvino/op/concat.hpp"
-#include "openvino/op/paged_attention.hpp"
 #include "openvino/pass/manager.hpp"
-#include "openvino/pass/pattern/op/wrap_type.hpp"
-#include "openvino/pass/pattern/op/or.hpp"
 #include "openvino/pass/visualize_tree.hpp"
 #include "openvino/runtime/device_id_parser.hpp"
 #include "openvino/runtime/intel_gpu/properties.hpp"
 #include "openvino/runtime/internal_properties.hpp"
 #include "openvino/runtime/make_tensor.hpp"
 #include "openvino/runtime/performance_heuristics.hpp"
+#include "openvino/runtime/plugin_config.hpp"
 #include "openvino/runtime/properties.hpp"
-#include "openvino/util/common_util.hpp"
 #include "openvino/util/weights_path.hpp"
 #include "transformations/common_optimizations/dimension_tracking.hpp"
 #include "transformations/init_node_info.hpp"
@@ -66,33 +62,6 @@ namespace ov::intel_gpu {
 #include "intel_gpu/plugin/primitives_list.hpp"
 #undef REGISTER_FACTORY
 
-const auto is_llm = [](const std::shared_ptr<const ov::Model>& model) -> bool {
-    using namespace ov::pass::pattern;
-
-    auto past = wrap_type<ov::op::v6::ReadValue>();
-    auto convert_past = wrap_type<ov::op::v0::Convert>({past});
-    auto gather_input = std::make_shared<ov::pass::pattern::op::Or>(OutputVector{past, convert_past});
-    auto beam_idx = wrap_type<ov::op::v0::Parameter>();
-    auto gather_past = wrap_type<ov::op::v8::Gather>({gather_input, beam_idx, wrap_type<ov::op::v0::Constant>()});
-    auto gather_convert = wrap_type<ov::op::v0::Convert>({gather_past});
-    auto concat_past_input = std::make_shared<ov::pass::pattern::op::Or>(OutputVector{past, convert_past, gather_past, gather_convert});
-    auto concat = wrap_type<ov::op::v0::Concat>({concat_past_input, any_input()});
-    auto convert_present = wrap_type<ov::op::v0::Convert>({concat});
-    auto present_input = std::make_shared<ov::pass::pattern::op::Or>(OutputVector{concat, convert_present});
-    auto present = wrap_type<ov::op::v6::Assign>({present_input});
-
-    auto kvcache_matcher = std::make_shared<ov::pass::pattern::Matcher>(present, "KVCacheMatcher");
-
-    for (auto& op : model->get_ordered_ops()) {
-        if (kvcache_matcher->match(op) ||
-            ov::is_type<ov::op::PagedAttentionExtension>(op)) {
-            return true;
-        }
-    }
-
-    return false;
-};
-
 void Plugin::register_primitives() const {
     #define REGISTER_FACTORY(op_version, op_name) FACTORY_CALL(op_version, op_name)
     #include "intel_gpu/plugin/primitives_list.hpp"
@@ -128,18 +97,30 @@ std::shared_ptr<ov::Model> Plugin::clone_and_transform_model(const std::shared_p
                                                              const ExecutionConfig& config,
                                                              const std::shared_ptr<RemoteContextImpl>& context) const {
     OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "Plugin::clone_and_transform_model");
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     GPU_DEBUG_DEFINE_MEM_LOGGER("Plugin::clone_and_transform_model");
 
     auto cloned_model = model->clone();
     OPENVINO_ASSERT(cloned_model != nullptr, "[GPU] Failed to clone model!");
 
-    GPU_DEBUG_IF(!debug_config->dump_graphs.empty()) {
-        auto path_base = debug_config->dump_graphs + "/" + cloned_model->get_name();
+    // Here we create a copy of the config to finalize it and ensure that transformation pipe can use correct options values
+    // This is manily needed to correctly update lower level properties when higher level option is set by user
+    // For example, transformation use inference_precision hint which may be updated by execution_mode property.
+    // Update itself will happen on finalization stage, so we must call it to have correct passes flow.
+    // The reason why we can't do finalization once and then just run all graph transformations is that
+    // part of the tranformations may actually impact some properties. For example, LSTMSequence op presense
+    // impacts value of use_onednn property. But in order to understand if there's an op of this type we have to run
+    // common optimizations which may do subgraph fusion to LSTMSequence op. So basically, final value of use_onednn
+    // property can be computed for transformed model only.
+    auto config_copy = config.clone();
+    config_copy.finalize(context.get(), model.get());
+
+    std::string dump_path = GPU_DEBUG_VALUE_OR(config_copy.get_dump_graphs_path(), "");
+    GPU_DEBUG_IF(!dump_path.empty()) {
+        auto path_base = dump_path + "/" + cloned_model->get_name();
         ov::pass::VisualizeTree(path_base + ".svg").run_on_model(cloned_model);
     }
 
-    transform_model(cloned_model, config, context);
+    transform_model(cloned_model, config_copy, context);
 
     // Transformations for some reason may drop output tensor names, so here we copy those from the original model
     auto new_results = cloned_model->get_results();
@@ -154,8 +135,8 @@ std::shared_ptr<ov::Model> Plugin::clone_and_transform_model(const std::shared_p
         new_res->set_friendly_name(old_res->get_friendly_name());
     }
 
-    GPU_DEBUG_IF(!debug_config->dump_graphs.empty()) {
-        auto path_base = debug_config->dump_graphs + "/" + cloned_model->get_name() + "_" +  "transformed_func";
+    GPU_DEBUG_IF(!dump_path.empty()) {
+        auto path_base = dump_path + "/" + cloned_model->get_name() + "_" +  "transformed_func";
         ov::pass::VisualizeTree(path_base + ".svg").run_on_model(cloned_model);
     }
     return cloned_model;
@@ -194,22 +175,6 @@ Plugin::Plugin() {
     m_compiled_model_runtime_properties["OV_VERSION"] = ov_version.buildNumber;
 }
 
-void Plugin::set_cache_info(const std::shared_ptr<const ov::Model>& model, ExecutionConfig& config) const {
-    // WEIGHTS_PATH is used for the weightless cache mechanism which is used only with
-    // ov::CacheMode::OPTIMIZE_SIZE setting. Not setting WEIGHTS_PATH will result in not
-    // using that mechanism.
-    if (config.get_property(ov::cache_mode) != ov::CacheMode::OPTIMIZE_SIZE) {
-        return;
-    }
-
-    const auto& rt_info = model->get_rt_info();
-    auto weights_path = rt_info.find("__weights_path");
-    if (weights_path != rt_info.end()) {
-        ov::AnyMap weights_path_property{{"WEIGHTS_PATH", weights_path->second}};
-        config.set_property(weights_path_property);
-    }
-}
-
 std::shared_ptr<ov::ICompiledModel> Plugin::compile_model(const std::shared_ptr<const ov::Model>& model, const ov::AnyMap& orig_config) const {
     OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "Plugin::compile_model");
     std::string device_id = get_device_id(orig_config);
@@ -219,14 +184,11 @@ std::shared_ptr<ov::ICompiledModel> Plugin::compile_model(const std::shared_ptr<
     OPENVINO_ASSERT(m_configs_map.find(device_id) != m_configs_map.end(), "[GPU] compile_model: Couldn't find config for GPU with id ", device_id);
 
     ExecutionConfig config = m_configs_map.at(device_id);
-    config.set_user_property(orig_config);
-    if (model->has_rt_info("runtime_options"))
-        config.apply_rt_info(context->get_engine().get_device_info(), model->get_rt_info<ov::AnyMap>("runtime_options"), is_llm(model));
-    config.apply_user_properties(context->get_engine().get_device_info());
-
-    set_cache_info(model, config);
+    config.set_user_property(orig_config, OptionVisibility::RELEASE);
 
     auto transformed_model = clone_and_transform_model(model, config, context);
+
+    config.finalize(context.get(), transformed_model.get());
     {
         OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "Plugin::compile_model::CreateCompiledModel");
         return std::make_shared<CompiledModel>(transformed_model, shared_from_this(), context, config);
@@ -242,14 +204,12 @@ std::shared_ptr<ov::ICompiledModel> Plugin::compile_model(const std::shared_ptr<
     OPENVINO_ASSERT(m_configs_map.find(device_id) != m_configs_map.end(), "[GPU] compile_model: Couldn't find config for GPU with id ", device_id);
 
     ExecutionConfig config = m_configs_map.at(device_id);
-    config.set_user_property(orig_config);
-    if (model->has_rt_info("runtime_options"))
-        config.apply_rt_info(context_impl->get_engine().get_device_info(), model->get_rt_info<ov::AnyMap>("runtime_options"), is_llm(model));
-    config.apply_user_properties(context_impl->get_engine().get_device_info());
-
-    set_cache_info(model, config);
+    config.set_user_property(orig_config, OptionVisibility::RELEASE);
 
     auto transformed_model = clone_and_transform_model(model, config, context_impl);
+
+    config.finalize(context_impl.get(), transformed_model.get());
+
     return std::make_shared<CompiledModel>(transformed_model, shared_from_this(), context_impl, config);
 }
 
@@ -277,7 +237,7 @@ ov::SoPtr<ov::IRemoteContext> Plugin::get_default_context(const AnyMap& params)
 
 void Plugin::set_property(const ov::AnyMap &config) {
     auto update_config = [](ExecutionConfig& config, const ov::AnyMap& user_config) {
-        config.set_user_property(user_config);
+        config.set_user_property(user_config, OptionVisibility::RELEASE);
         // Check that custom layers config can be loaded
         if (user_config.find(ov::intel_gpu::config_file.name()) != user_config.end()) {
             CustomLayerMap custom_layers;
@@ -312,14 +272,12 @@ ov::SupportedOpsMap Plugin::query_model(const std::shared_ptr<const ov::Model>&
     auto ctx = get_default_context(device_id);
 
     ExecutionConfig config = m_configs_map.at(device_id);
-    config.set_user_property(orig_config);
-    if (model->has_rt_info("runtime_options"))
-        config.apply_rt_info(ctx->get_engine().get_device_info(), model->get_rt_info<ov::AnyMap>("runtime_options"), is_llm(model));
-    config.apply_user_properties(ctx->get_engine().get_device_info());
+    config.set_user_property(orig_config, OptionVisibility::RELEASE);
+    config.finalize(ctx.get(), model.get());
 
     ProgramBuilder prog(ctx->get_engine(), config);
 
-    float query_model_ratio = config.get_property(ov::internal::query_model_ratio.name()).as<float>();
+    float query_model_ratio = config.get_query_model_ratio();
 
     auto supported = ov::get_supported_nodes(model,
         [&config,&ctx,this](std::shared_ptr<ov::Model>& model) {
@@ -369,11 +327,10 @@ std::shared_ptr<ov::ICompiledModel> Plugin::import_model(std::istream& model,
     }
 
     ExecutionConfig config = m_configs_map.at(device_id);
-    config.set_user_property(_orig_config);
-    config.apply_user_properties(context_impl->get_engine().get_device_info());
+    config.set_user_property(_orig_config, OptionVisibility::RELEASE);
 
-    ov::CacheMode cache_mode = config.get_property(ov::cache_mode);
-    ov::EncryptionCallbacks encryption_callbacks = config.get_property(ov::cache_encryption_callbacks);
+    ov::CacheMode cache_mode = config.get_cache_mode();
+    ov::EncryptionCallbacks encryption_callbacks = config.get_cache_encryption_callbacks();
     const bool encryption_enabled = encryption_callbacks.decrypt && cache_mode == ov::CacheMode::OPTIMIZE_SIZE;
 
     std::unique_ptr<cldnn::BinaryInputBuffer> ib_ptr =
@@ -390,9 +347,8 @@ std::shared_ptr<ov::ICompiledModel> Plugin::import_model(std::istream& model,
         return nullptr;
     }
 
-    std::string weights_path = config.get_property(ov::weights_path);
-    if (config.get_property(ov::cache_mode) == ov::CacheMode::OPTIMIZE_SIZE &&
-        !ov::util::validate_weights_path(weights_path)) {
+    std::string weights_path = config.get_weights_path();
+    if (config.get_cache_mode() == ov::CacheMode::OPTIMIZE_SIZE && !ov::util::validate_weights_path(weights_path)) {
         return nullptr;
     }
 
@@ -478,7 +434,7 @@ ov::Any Plugin::get_property(const std::string& name, const ov::AnyMap& options)
     OPENVINO_ASSERT(m_configs_map.find(device_id) != m_configs_map.end(), "[GPU] get_property: Couldn't find config for GPU with id ", device_id);
 
     const auto& c = m_configs_map.at(device_id);
-    return c.get_property(name);
+    return c.get_property(name, OptionVisibility::RELEASE);
 }
 
 auto StringRightTrim = [](std::string string, std::string substring, bool case_sensitive = true) {
@@ -512,8 +468,6 @@ bool Plugin::is_metric(const std::string& name) const {
 
 ov::Any Plugin::get_metric(const std::string& name, const ov::AnyMap& options) const {
     OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "Plugin::get_metric");
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-
     auto device_id = get_property(ov::device::id.name(), options).as<std::string>();
 
     auto iter = m_device_map.find(std::to_string(cldnn::device_query::device_id));
@@ -687,12 +641,12 @@ std::vector<std::string> Plugin::get_device_capabilities(const cldnn::device_inf
 }
 
 uint32_t Plugin::get_max_batch_size(const ov::AnyMap& options) const {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     auto device_id = get_property(ov::device::id.name(), options).as<std::string>();
     auto context = get_default_contexts().at(device_id);
     const auto& device_info = context->get_engine().get_device_info();
-    const auto& config = m_configs_map.at(device_id);
-    uint32_t n_streams = static_cast<uint32_t>(config.get_property(ov::num_streams));
+    auto config = m_configs_map.at(device_id);
+    config.set_property(ov::intel_gpu::partial_build_program(true));
+    uint32_t n_streams = static_cast<uint32_t>(config.get_num_streams());
     uint64_t occupied_device_mem = 0;
     auto statistic_result = get_metric(ov::intel_gpu::memory_statistics.name(), options).as<std::map<std::string, uint64_t>>();
     auto occupied_usm_dev = statistic_result.find("usm_device_current");
@@ -744,17 +698,14 @@ uint32_t Plugin::get_max_batch_size(const ov::AnyMap& options) const {
         OPENVINO_THROW("[GPU_MAX_BATCH_SIZE] ov::hint::model should be std::shared_ptr<ov::Model> type");
     }
 
+    config.finalize(context.get(), model.get());
+
     size_t base_batch_size = 16; // empirically decided for DG1
 
     auto& engine = get_default_context(device_id)->get_engine();
 
     std::shared_ptr<ProgramBuilder> program;
 
-    GPU_DEBUG_IF(debug_config->base_batch_for_memory_estimation > 0) {
-        size_t user_specified_base_batch_size = debug_config->base_batch_for_memory_estimation;
-        base_batch_size = (user_specified_base_batch_size != base_batch_size) ? user_specified_base_batch_size : base_batch_size;
-    }
-
     auto cloned_model = model->clone();
 
     try {
@@ -809,7 +760,7 @@ uint32_t Plugin::get_max_batch_size(const ov::AnyMap& options) const {
 
         TransformationsPipeline transformations(config, context);
         transformations.apply(cloned_model);
-        program = std::make_shared<ProgramBuilder>(cloned_model, engine, config, true);
+        program = std::make_shared<ProgramBuilder>(cloned_model, engine, config);
         std::pair<int64_t, int64_t> device_memory_usage = program->get_compiled_program()->get_estimated_device_mem_usage();
         if (device_memory_usage.first == static_cast<int64_t>(-1L) && device_memory_usage.second == static_cast<int64_t>(-1L)) {
             return static_cast<uint32_t>(max_batch_size);
diff --git a/src/plugins/intel_gpu/src/plugin/program_builder.cpp b/src/plugins/intel_gpu/src/plugin/program_builder.cpp
index 2abc8bb65df6ac..66e4133a4dc4c5 100644
--- a/src/plugins/intel_gpu/src/plugin/program_builder.cpp
+++ b/src/plugins/intel_gpu/src/plugin/program_builder.cpp
@@ -2,6 +2,7 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+#include "intel_gpu/runtime/internal_properties.hpp"
 #include "openvino/core/rt_info/weightless_caching_attributes.hpp"
 #include "openvino/op/constant.hpp"
 #include "openvino/op/split.hpp"
@@ -11,7 +12,7 @@
 #include "openvino/op/loop.hpp"
 #include "openvino/op/search_sorted.hpp"
 #include "openvino/op/stft.hpp"
-#include "ov_ops/dynamic_quantize.hpp"
+#include "openvino/runtime/properties.hpp"
 
 #include "intel_gpu/plugin/common_utils.hpp"
 #include "intel_gpu/plugin/program_builder.hpp"
@@ -61,7 +62,6 @@ std::string layer_type_name_ID(const std::shared_ptr<ov::Node>& op) {
 }
 
 ProgramBuilder::ProgramBuilder(std::shared_ptr<ov::Model> model, cldnn::engine& engine, const ExecutionConfig& config,
-                               bool partial_build,
                                std::shared_ptr<ov::threading::IStreamsExecutor> task_executor,
                                std::shared_ptr<cldnn::ICompilationContext> compilation_context,
                                bool is_inner_program)
@@ -105,20 +105,11 @@ ProgramBuilder::ProgramBuilder(std::shared_ptr<ov::Model> model, cldnn::engine&
     config_path += "/cldnn_global_custom_kernels/cldnn_global_custom_kernels.xml";
 
     CustomLayer::LoadFromFile(config_path, m_custom_layers, true);
-    auto custom_layers_config = m_config.get_property(ov::intel_gpu::config_file);
+    auto custom_layers_config = m_config.get_config_file();
     CustomLayer::LoadFromFile(custom_layers_config, m_custom_layers, custom_layers_config.empty());
 
     auto ops = model->get_ordered_ops();
-    // In the case of dynamic models, because most of the layers are mapped to shape agnostic kernels,
-    // smaller # of kernels are built compared to static models.
-    // So having smaller batch size is even better for dynamic model as we can do more parallel build.
-    if (model->is_dynamic()) {
-        m_config.set_property(ov::intel_gpu::max_kernels_per_batch(4));
-    } else {
-        m_config.set_property(ov::intel_gpu::max_kernels_per_batch(8));
-    }
-
-    m_program = build(ops, partial_build, is_inner_program);
+    m_program = build(ops, is_inner_program);
 }
 
 ProgramBuilder::ProgramBuilder(cldnn::engine& engine, const ExecutionConfig& config)
@@ -148,24 +139,8 @@ void ProgramBuilder::cleanup_build() {
 #endif
 }
 
-std::shared_ptr<cldnn::program> ProgramBuilder::build(const std::vector<std::shared_ptr<ov::Node>>& ops, bool partial_build, bool is_inner_program) {
+std::shared_ptr<cldnn::program> ProgramBuilder::build(const std::vector<std::shared_ptr<ov::Node>>& ops, bool is_inner_program) {
     OV_ITT_SCOPED_TASK(itt::domains::intel_gpu_plugin, "ProgramBuilder::build");
-    // In the case of inner program, allow_new_shape_infer flag is setted by outside of program.
-    // So, do not check allow_new_shape_infer for inner program build
-    for (const auto& op : ops) {
-        if (requires_new_shape_infer(op)) {
-            allow_new_shape_infer = true;
-            break;
-        }
-    }
-
-    if (is_inner_program) {
-        allow_new_shape_infer = (m_config.get_property(ov::intel_gpu::allow_new_shape_infer) || allow_new_shape_infer);
-    }
-
-    m_config.set_property(ov::intel_gpu::partial_build_program(partial_build));
-    m_config.set_property(ov::intel_gpu::optimize_data(true));
-    m_config.set_property(ov::intel_gpu::allow_new_shape_infer(allow_new_shape_infer));
 
     prepare_build();
     {
@@ -211,7 +186,6 @@ bool ProgramBuilder::is_op_supported(const std::shared_ptr<ov::Node>& op) {
         if (!data_types_are_supported(op.get()))
             return false;
 
-        allow_new_shape_infer = requires_new_shape_infer(op);
         CreateSingleLayerPrimitive(op);
         cleanup_build();
         DisableQueryMode();
@@ -268,7 +242,7 @@ std::vector<cldnn::input_info> ProgramBuilder::GetInputInfo(const std::shared_pt
         // Note: Currently Split/Variadic Split are divided to multiple crops
         // LSTMCell contains its own body network, and each output has a unique pid
         // But there is no need to maintain output port index for the next node e.g. Result
-        bool is_legacy_multiple_outputs = !allow_new_shape_infer
+        bool is_legacy_multiple_outputs = !use_new_shape_infer()
                                           || ov::is_type<ov::op::v1::Split>(prevOp)
                                           || ov::is_type<ov::op::v1::VariadicSplit>(prevOp)
                                           || ov::is_type<ov::op::v4::LSTMCell>(prevOp);
@@ -309,7 +283,7 @@ void ProgramBuilder::add_primitive(const ov::Node& op, std::shared_ptr<cldnn::pr
     prim->origin_op_name = op.get_friendly_name();
     prim->origin_op_type_name = op.get_type_name();
 
-    if (this->m_config.get_property(ov::cache_mode) == ov::CacheMode::OPTIMIZE_SIZE) {
+    if (this->m_config.get_cache_mode() == ov::CacheMode::OPTIMIZE_SIZE) {
         if (auto data_prim = dynamic_cast<cldnn::data*>(prim.get())) {
             auto rt_info = op.get_rt_info();
 
@@ -340,7 +314,7 @@ void ProgramBuilder::add_primitive(const ov::Node& op, std::shared_ptr<cldnn::pr
             prim->origin_op_type_name = prim->type_string();
     }
 
-    if (this->m_config.get_property(ov::enable_profiling) && should_profile) {
+    if (this->m_config.get_enable_profiling() && should_profile) {
         profiling_ids.push_back(prim_id);
         init_profile_info(*prim);
     }
@@ -352,51 +326,6 @@ void ProgramBuilder::add_primitive(const ov::Node& op, std::shared_ptr<cldnn::pr
     m_topology->add_primitive(prim);
 }
 
-bool ProgramBuilder::requires_new_shape_infer(const std::shared_ptr<ov::Node>& op) const {
-    if (op->is_dynamic()) {
-        return true;
-    }
-
-    // HACK: SearchSorted has specific shape requirements.
-    // E.g. static input shapes: sorted:[8], values:[2,3,4] are prefectly fine,
-    // but sorted:[8,1,1,1], values:[2,3,4,1] is not valid.
-    // Similar case for STFT.
-    if (ov::is_type<ov::op::v15::SearchSorted>(op) || ov::is_type<ov::op::v15::STFT>(op))
-        return true;
-
-    if (ov::is_type<ov::op::internal::DynamicQuantize>(op))
-        return true;
-
-    if (ov::is_type<ov::op::v5::Loop>(op)) {
-        const auto body_function = std::static_pointer_cast<ov::op::v5::Loop>(op)->get_function();
-        if (body_function->is_dynamic())
-            return true;
-    }
-
-    if (ov::is_type<ov::op::v5::LSTMSequence>(op) || ov::is_type<ov::op::v4::LSTMCell>(op)) {
-        return true;
-    }
-    // When input node has dynamic shape with 4 dimension, this function return false
-    // because op.is_dynamic() which only checks input shapes return false.
-    // So, in the case of input data, we need to check output shape.
-    for (size_t i = 0; i < op->get_output_size(); i++) {
-        if (op->get_output_partial_shape(i).is_dynamic())
-            return true;
-    }
-
-    for (size_t i = 0; i < op->get_output_size(); i++) {
-        if (op->get_output_partial_shape(i).size() > 6)
-            return true;
-    }
-
-    for (size_t i = 0; i < op->get_input_size(); i++) {
-        if (op->get_input_partial_shape(i).size() > 6)
-            return true;
-    }
-
-    return false;
-}
-
 int64_t ProgramBuilder::get_parameter_index(const std::shared_ptr<ov::op::v0::Parameter>& parameter) const {
     return m_model->get_parameter_index(parameter);
 }
diff --git a/src/plugins/intel_gpu/src/plugin/sync_infer_request.cpp b/src/plugins/intel_gpu/src/plugin/sync_infer_request.cpp
index 2e6d2c21343977..bff069461d8685 100644
--- a/src/plugins/intel_gpu/src/plugin/sync_infer_request.cpp
+++ b/src/plugins/intel_gpu/src/plugin/sync_infer_request.cpp
@@ -91,20 +91,9 @@ SyncInferRequest::SyncInferRequest(const std::shared_ptr<const CompiledModel>& c
     : ov::ISyncInferRequest(compiled_model)
     , m_graph(compiled_model->get_graph(0))
     , m_context(std::static_pointer_cast<RemoteContextImpl>(compiled_model->get_context_impl()))
-    , m_shape_predictor(new cldnn::ShapePredictor(&m_graph->get_engine(), m_graph->get_config().get_property(ov::intel_gpu::buffers_preallocation_ratio)))
-    , m_enable_profiling(m_graph->get_config().get_property(ov::enable_profiling))
+    , m_shape_predictor(new cldnn::ShapePredictor(&m_graph->get_engine(), m_graph->get_config().get_shape_predictor_settings()))
+    , m_enable_profiling(m_graph->get_config().get_enable_profiling())
     , m_use_external_queue(m_graph->use_external_queue()) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->mem_preallocation_params.is_initialized) {
-        auto& mem_preallocation_params = debug_config->mem_preallocation_params;
-        m_shape_predictor.reset(
-            new cldnn::ShapePredictor(&m_graph->get_engine(),
-                                      mem_preallocation_params.next_iters_preallocation_count,
-                                      mem_preallocation_params.max_per_iter_size,
-                                      mem_preallocation_params.max_per_dim_diff,
-                                      mem_preallocation_params.buffers_preallocation_ratio));
-    }
-
     init_mappings();
     allocate_inputs();
     allocate_outputs();
@@ -295,15 +284,16 @@ void SyncInferRequest::enqueue() {
     m_internal_outputs = network->execute(dependencies);
     auto network_enqueue_end = std::chrono::high_resolution_clock::now();
 
+    [[maybe_unused]] const auto& config = network->get_config();
+
     // If dump layers path is set, only runs first inference.
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->dump_layers_path.length() > 0 && debug_config->dump_iteration.empty()) {
+    GPU_DEBUG_IF(!config.get_dump_tensors_path().empty() && config.get_dump_iterations().empty()) {
         GPU_DEBUG_INFO << "Only run first inference to dump layers." << std::endl;
         exit(0);
     }
 
     auto enqueue_end = std::chrono::high_resolution_clock::now();
-    GPU_DEBUG_IF(cldnn::debug_configuration::get_instance()->host_time_profiling) {
+    GPU_DEBUG_IF(config.get_host_time_profiling()) {
         network_enqueue_time = std::chrono::duration_cast<std::chrono::microseconds>(network_enqueue_end - network_enqueue_start).count();
 
         const uint64_t total_time = std::chrono::duration_cast<std::chrono::microseconds>(enqueue_end - enqueue_start).count();
@@ -400,7 +390,7 @@ void SyncInferRequest::wait() {
             auto mem_shape = output_layout.get_shape();
             // In case of old shape infer we need to shrink out tensor shape to avoid redudnant dimensions that occur due to rank extension
             // For new shape infer this shouldn't happen, thus remove that WA once we migrate to ngraph-based shape infer for all cases
-            if (!m_graph->get_config().get_property(ov::intel_gpu::allow_new_shape_infer)) {
+            if (!m_graph->get_config().get_allow_new_shape_infer()) {
                 OPENVINO_ASSERT(port.get_partial_shape().is_static(), "[GPU] Unexpected dynamic shape for legacy shape inference");
                 OPENVINO_ASSERT(ov::shape_size(port.get_shape()) == ov::shape_size(mem_shape), "[GPU] Unexpected elements count for output tensor");
                 mem_shape = port.get_shape();
@@ -481,7 +471,7 @@ void SyncInferRequest::wait() {
     }
 
     auto wait_end = std::chrono::high_resolution_clock::now();
-    GPU_DEBUG_IF(cldnn::debug_configuration::get_instance()->host_time_profiling) {
+    GPU_DEBUG_IF(m_graph->get_config().get_host_time_profiling()) {
         auto& exec_time_info = m_graph->host_exec_times.back();
 
         const uint64_t total_time = std::chrono::duration_cast<std::chrono::microseconds>(wait_end - wait_start).count();
@@ -873,7 +863,7 @@ std::vector<cldnn::event::ptr> SyncInferRequest::prepare_input(const std::string
 
     auto memory = device_tensor->get_memory();
     // WA to extend shape to ranks expected by legacy shape infer. Remove after full migration to new shape infer
-    if (!m_graph->get_config().get_property(ov::intel_gpu::allow_new_shape_infer)) {
+    if (!m_graph->get_config().get_allow_new_shape_infer()) {
         auto new_layout = memory->get_layout();
         new_layout.set_partial_shape(m_graph->get_input_layouts().at(input_idx).get_shape());
         memory = engine.reinterpret_buffer(*memory, new_layout);
diff --git a/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.cpp b/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.cpp
index 6c0d50be96e7ae..66fe9d9c9e0fc6 100644
--- a/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.cpp
+++ b/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.cpp
@@ -16,9 +16,8 @@
 
 namespace ov::intel_gpu {
 
-DynamicQuantizeFullyConnected::DynamicQuantizeFullyConnected(uint64_t group_size)
+DynamicQuantizeFullyConnected::DynamicQuantizeFullyConnected(uint64_t group_size, bool asymmetric)
     : ov::pass::MatcherPass() {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     using namespace ov::pass::pattern;
     using QuantizationType = ov::op::internal::DynamicQuantize::QuantizationType;
 
@@ -55,9 +54,7 @@ DynamicQuantizeFullyConnected::DynamicQuantizeFullyConnected(uint64_t group_size
         config.scale_dt = element::f16;
         config.group_sizes = shape_group_size;
 
-        // AZP does not support grouped size dyn-quan
-        // XXX: This is currently wrapped as GPU_DEBUG_IF as dynamic_quantize_asym is not exposed through public API.
-        GPU_DEBUG_IF(debug_config->dynamic_quantize_asym && group_size == UINT64_MAX) {
+        if (asymmetric && group_size == UINT64_MAX) {
             config.quantization_type = QuantizationType::Asymmetric;
             config.quantization_dt = element::u8;
             config.zp_dt = element::u8; // it supports u8 only now
diff --git a/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.hpp b/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.hpp
index 85d32fbfdcea84..f8b13685389f1d 100644
--- a/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.hpp
+++ b/src/plugins/intel_gpu/src/plugin/transformations/dynamic_quantize_fully_connected.hpp
@@ -11,7 +11,7 @@ namespace ov::intel_gpu {
 class DynamicQuantizeFullyConnected: public ov::pass::MatcherPass {
 public:
     OPENVINO_MATCHER_PASS_RTTI("DynamicQuantizeFullyConnected");
-    DynamicQuantizeFullyConnected(uint64_t group_size);
+    DynamicQuantizeFullyConnected(uint64_t group_size, bool asymmetric = false);
 };
 
 }   // namespace ov::intel_gpu
diff --git a/src/plugins/intel_gpu/src/plugin/transformations/fc_horizontal_fusion.cpp b/src/plugins/intel_gpu/src/plugin/transformations/fc_horizontal_fusion.cpp
index 8568c334682548..68e78de7a23f16 100644
--- a/src/plugins/intel_gpu/src/plugin/transformations/fc_horizontal_fusion.cpp
+++ b/src/plugins/intel_gpu/src/plugin/transformations/fc_horizontal_fusion.cpp
@@ -20,7 +20,6 @@ namespace ov::intel_gpu {
 FullyConnectedHorizontalFusion::FullyConnectedHorizontalFusion(bool fuse_mlp_swiglu) {
     using namespace ov::pass::pattern;
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     // Three FCs connected to the same input
     size_t min_num_fcs_to_fuse = 3;
     // Note:
diff --git a/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp b/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp
index 6fe6cb14cd54c4..261cff11586fa8 100644
--- a/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp
+++ b/src/plugins/intel_gpu/src/plugin/transformations_pipeline.cpp
@@ -335,7 +335,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
     const ov::element::TypeVector supported_woq_types = {ov::element::u8, ov::element::i8, ov::element::u4, ov::element::i4};
     bool enableInt8;
     ov::element::Type infer_precision = ov::element::undefined;
-    bool unroll_loop = config.get_property(ov::intel_gpu::enable_loop_unrolling);
+    bool unroll_loop = config.get_enable_loop_unrolling();
     {
         ov::pass::Manager manager("Plugin:GPU");
         auto pass_config = manager.get_pass_config();
@@ -348,7 +348,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         }
 
         auto is_model_quantized = ov::pass::low_precision::LowPrecision::isFunctionQuantized(func);
-        enableInt8 = config.get_property(ov::intel_gpu::enable_lp_transformations) && is_model_quantized;
+        enableInt8 = config.get_enable_lp_transformations() && is_model_quantized;
 
         manager.register_pass<ov::pass::MarkDequantization>(
             std::vector<ov::element::Type>{ ov::element::i8, ov::element::u8, ov::element::i4, ov::element::u4 },
@@ -381,7 +381,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         };
 
         // Add conversion from FP data types to infer precision if it's specified
-        infer_precision = config.get_property(ov::hint::inference_precision);
+        infer_precision = config.get_inference_precision();
         if (infer_precision != ov::element::undefined) {
             if (!fp_precision_supported(infer_precision))
                 infer_precision = fallback_precision;
@@ -459,11 +459,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         manager.register_pass<ov::pass::CommonOptimizations>();
 
         pass_config->set_callback<ov::pass::ScaledDotProductAttentionDecomposition>([&](const std::shared_ptr<const ov::Node> node){
-            GPU_DEBUG_IF(cldnn::debug_configuration::get_instance()->enable_sdpa != -1) {
-                GPU_DEBUG_CODE(return cldnn::debug_configuration::get_instance()->enable_sdpa == 1);
-            }
-
-            if (!config.get_property(ov::intel_gpu::hint::enable_sdpa_optimization))
+            if (!config.get_enable_sdpa_optimization())
                 return false;
 
             auto sdpa = ov::as_type_ptr<const ov::op::v13::ScaledDotProductAttention>(node);
@@ -1024,7 +1020,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         // This Validate is needed for proper data type propagation after applying IncreasePositionIdsPrecision pass
         manager.register_pass<ov::pass::Validate>();
 
-        float activations_scale_factor = config.get_property(ov::hint::activations_scale_factor);
+        float activations_scale_factor = config.get_activations_scale_factor();
 
         if (activations_scale_factor > 0.f && infer_precision == ov::element::f16) {
             using namespace ov::pass::low_precision;
@@ -1089,13 +1085,9 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         manager.register_pass<ov::intel_gpu::MoveFCReshapeToWeights>();
         manager.register_pass<ov::intel_gpu::ConvertFullyConnectedToFullyConnectedCompressed>();
 
-        bool disable_horizontal_fc_fusion = false;
-        bool disable_fc_swiglu_fusion = false;
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-        GPU_DEBUG_IF(debug_config->disable_horizontal_fc_fusion == 1)
-            disable_horizontal_fc_fusion = true;
-        GPU_DEBUG_IF(debug_config->disable_fc_swiglu_fusion == 1)
-            disable_fc_swiglu_fusion = true;
+        bool disable_horizontal_fc_fusion = GPU_DEBUG_VALUE_OR(config.get_disable_horizontal_fc_fusion(), false);
+        bool disable_fc_swiglu_fusion = GPU_DEBUG_VALUE_OR(config.get_disable_fc_swiglu_fusion(), false);
+
         // mlp fusion is only supported for cldnn on high performant GPUis
         bool fuse_mlp_swiglu = !device_info.supports_immad &&
                                device_info.execution_units_count >= 128 &&
@@ -1133,7 +1125,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         manager.register_pass<ov::pass::GLUFusion>();
         manager.register_pass<ov::intel_gpu::IndirectKVCache>();
 
-        auto kv_cache_compression_dt = config.get_property(ov::hint::kv_cache_precision);
+        auto kv_cache_compression_dt = config.get_kv_cache_precision();
         manager.register_pass<ov::intel_gpu::KVCacheCompression>(kv_cache_compression_dt, device_info.supports_immad);
 
         manager.register_pass<ov::intel_gpu::ConvertConvolutionToInternal>();
@@ -1151,7 +1143,8 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         manager.register_pass<ov::intel_gpu::SinkReshape>();
 
         if (device_info.supports_immad) {
-            auto dynamic_quantization_group_size = config.get_property(ov::hint::dynamic_quantization_group_size);
+            bool asymmetric_dyn_quant = GPU_DEBUG_VALUE_OR(config.get_asym_dynamic_quantization(), false);
+            auto dynamic_quantization_group_size = config.get_dynamic_quantization_group_size();
             pass_config->set_callback<ov::intel_gpu::DynamicQuantizeFullyConnected>([=](const_node_ptr& root) -> bool {
                 for (size_t i = 0 ; i < root->get_input_node_shared_ptr(0)->get_output_size(); ++i) {
                     if (root->get_input_node_shared_ptr(0)->get_output_element_type(i) == ov::element::Type_t::f32) {
@@ -1169,14 +1162,14 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
 
                 // AZP does not support 8bit weight
                 // XXX: This is currently wrapped as GPU_DEBUG_IF as dynamic_quantize_asym is not exposed through public API.
-                GPU_DEBUG_IF(debug_config->dynamic_quantize_asym
+                GPU_DEBUG_IF(asymmetric_dyn_quant
                     && (root->get_input_element_type(1) == ov::element::i8 || root->get_input_element_type(1) == ov::element::u8)) {
                     GPU_DEBUG_TRACE << root->get_friendly_name() << "  dyn_quan is turned off: asym quantization does not support 8bit weight" << std::endl;
                     return true;
                 }
 
                 // AZP does not support grouped size dyn-quan
-                GPU_DEBUG_IF(debug_config->dynamic_quantize_asym && (dynamic_quantization_group_size != UINT64_MAX)) {
+                GPU_DEBUG_IF(asymmetric_dyn_quant && (dynamic_quantization_group_size != UINT64_MAX)) {
                     GPU_DEBUG_TRACE << root->get_friendly_name() << "  dyn_quan is turned off: asym quantization does not support grouped quantization" <<
                                                                    " ('DynamicQuantizeAsym' is enabled with grouped size dyn-quan)" << std::endl;
                     return true;
@@ -1193,7 +1186,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
 
                 return false;
             });
-            manager.register_pass<ov::intel_gpu::DynamicQuantizeFullyConnected>(dynamic_quantization_group_size);
+            manager.register_pass<ov::intel_gpu::DynamicQuantizeFullyConnected>(dynamic_quantization_group_size, asymmetric_dyn_quant);
         }
 
         // Remove Pad in front of MaxPool if both the pads_begin and pads_end are zero.
@@ -1202,7 +1195,7 @@ void TransformationsPipeline::apply(std::shared_ptr<ov::Model> func) {
         // This is supposed to be the last pass to ensure that we don't have name collisions until
         // GPU plugin stops using friendly names for program creation
         manager.register_pass<ov::pass::ResolveNameCollisions>(true);
-        GPU_DEBUG_IF(cldnn::debug_configuration::get_instance()->verbose >= 1) {
+        GPU_DEBUG_IF(config.get_verbose() >= 1) {
             manager.register_pass<ov::intel_gpu::PrintModelStatistics>();
         }
         manager.run_passes(func);
diff --git a/src/plugins/intel_gpu/src/runtime/debug_configuration.cpp b/src/plugins/intel_gpu/src/runtime/debug_configuration.cpp
index 550d740f772a16..cb36a8e0349457 100644
--- a/src/plugins/intel_gpu/src/runtime/debug_configuration.cpp
+++ b/src/plugins/intel_gpu/src/runtime/debug_configuration.cpp
@@ -3,604 +3,23 @@
 //
 
 #include "intel_gpu/runtime/debug_configuration.hpp"
-#include <algorithm>
-#include <iomanip>
+#include "intel_gpu/runtime/execution_config.hpp"
 #include <iostream>
-#include <memory>
-#include <regex>
-#include <sstream>
-#include <vector>
 #include <fstream>
 
-namespace cldnn {
-const char *debug_configuration::prefix = "GPU_Debug: ";
-std::ostream* debug_configuration::verbose_stream;
-
-// Default policy is that dump_configuration will override other configuration from IE.
-
-#ifdef GPU_DEBUG_CONFIG
-
-#define GPU_DEBUG_COUT_ std::cout << cldnn::debug_configuration::prefix
-
-template<typename T>
-void print_option(std::string option_name, T option_value) {
-    GPU_DEBUG_COUT_ << "Config " << option_name << " = " << option_value << std::endl;
-}
-
-static std::string to_upper_case(const std::string& var) {
-    std::stringstream s;
-
-    for (size_t i = 0; i < var.size(); i++) {
-        if (std::isupper(var[i])) {
-            if (i != 0) {
-                s << "_";
-            }
-            s << var[i];
-        } else {
-            s << static_cast<char>(std::toupper(var[i]));
-        }
-    }
-
-    return s.str();
-}
-
-static std::vector<std::string> get_possible_option_names(const std::string& var, std::vector<std::string> allowed_option_prefixes) {
-    std::vector<std::string> result;
-
-    for (auto& prefix : allowed_option_prefixes) {
-        result.push_back(prefix + var);
-        result.push_back(prefix + to_upper_case(var));
-    }
-
-    return result;
-}
-
-template <typename T>
-T convert_to(const std::string &str) {
-    std::istringstream ss(str);
-    T res;
-    ss >> res;
-    return res;
-}
-
-template <>
-std::string convert_to(const std::string &str) {
-    return str;
-}
-
-static std::set<int64_t> parse_int_set(std::string& str) {
-    std::set<int64_t> int_array;
-    // eliminate '"' from string to avoid parsing error
-    str.erase(std::remove_if(str.begin(), str.end(), [](char c) {
-                return c == '\"'; }), str.end());
-    if (str.size() > 0) {
-        str = " " + str + " ";
-        std::istringstream ss(str);
-        std::string token;
-        while (ss >> token) {
-            try {
-                int_array.insert(static_cast<int64_t>(std::stol(token)));
-            } catch(const std::exception &) {
-                int_array.clear();
-                GPU_DEBUG_COUT << "Argument was ignored. It cannot be parsed to integer array: " << str << std::endl;
-                break;
-            }
-        }
-    }
-    return int_array;
-}
-
-template<typename T>
-void get_debug_env_var(const std::string &var, T &val, std::vector<std::string> allowed_option_prefixes) {
-    bool found = false;
-    for (auto o : get_possible_option_names(var, allowed_option_prefixes)) {
-        if (const auto env_var = std::getenv(o.c_str())) {
-            val = convert_to<T>(env_var);
-            found = true;
-        }
-    }
-
-    if (found) {
-        print_option(var, val);
-    }
-}
-
-template<typename T>
-void get_gpu_debug_env_var(const std::string &var, T &val) {
-    return get_debug_env_var(var, val, {"OV_GPU_"});
-}
-
-template<typename T>
-void get_common_debug_env_var(const std::string &var, T &val) {
-    // The list below should be prioritized from lowest to highest prefix priority
-    // If an option is set several times with different prefixes, version with the highest priority will be actually used.
-    // This may allow to enable global option with some value and override this value for GPU plugin
-    // For example: OV_GPU_Verbose=2 OV_Verbose=1 ./my_app => this->verbose == 2
-    // In that case we enable Verbose (with level = 1) for all OV components that support this option, but for GPU plugin we increase verbose level to 2
-    std::vector<std::string> allowed_option_prefixes = {
-        "OV_",
-        "OV_GPU_"
-    };
-
-    return get_debug_env_var(var, val, allowed_option_prefixes);
-}
-
-static void print_help_messages() {
-    std::vector<std::pair<std::string, std::string>> message_list;
-    message_list.emplace_back("OV_GPU_Help", "Print help messages");
-    message_list.emplace_back("OV_GPU_Verbose", "Verbose execution");
-    message_list.emplace_back("OV_GPU_VerboseColor", "Print verbose color");
-    message_list.emplace_back("OV_GPU_VerboseFile", "Filename to dump verbose log");
-    message_list.emplace_back("OV_GPU_ListLayers", "Print layers names");
-    message_list.emplace_back("OV_GPU_PrintMultiKernelPerf", "Print execution time of each kernel in multi-kernel primitimive");
-    message_list.emplace_back("OV_GPU_PrintInputDataShapes",  "Print data_shapes of input layers for benchmark_app.");
-    message_list.emplace_back("OV_GPU_DisableUsm", "Disable usm usage");
-    message_list.emplace_back("OV_GPU_DisableOnednn", "Disable onednn for discrete GPU (no effect for integrated GPU)");
-    message_list.emplace_back("OV_GPU_DisableOnednnOptPostOps", "Disable onednn optimize post operators");
-    message_list.emplace_back("OV_GPU_DumpProfilingData", "Enables dump of extended profiling information to specified directory."
-                              " Please use OV_GPU_DumpProfilingDataPerIter=1 env variable to collect performance per iteration."
-                              " Note: Performance impact may be significant as this option enforces host side sync after each primitive");
-    message_list.emplace_back("OV_GPU_DumpProfilingDataIteration", "Enable collecting profiling data only at iterations with requested range. "
-                              "For example for dump profiling data only when iteration is from 10 to 20, you can use "
-                              "OV_GPU_DumpProfilingDataIteration='10..20'. Additionally, you can dump profiling data only "
-                              "from one specific iteration by giving the same values for the start and end, and the open "
-                              "ended range is also available by range from given start to the last iteration as -1. e.g. "
-                              "OV_GPU_DumpProfilingDataIteration='10..-1'");
-    message_list.emplace_back("OV_GPU_HostTimeProfiling", "Enable collecting of model enqueue time spent on the host");
-    message_list.emplace_back("OV_GPU_DumpGraphs", "1) dump ngraph before and after transformation. 2) dump graph in model compiling."
-                              "3) dump graph in execution.");
-    message_list.emplace_back("OV_GPU_DumpSources", "Dump opencl sources");
-    message_list.emplace_back("OV_GPU_DumpLayersPath", "Enable dumping intermediate buffers and set the dest path");
-    message_list.emplace_back("OV_GPU_DumpLayers", "Dump intermediate buffers of specified layers only, separated by space."
-                               " Support case-insensitive and regular expression. For example .*conv.*");
-    message_list.emplace_back("OV_GPU_DumpLayersResult", "Dump output buffers of result layers only");
-    message_list.emplace_back("OV_GPU_DumpLayersInput",  "Dump intermediate buffers of input layers only");
-    message_list.emplace_back("OV_GPU_DumpLayersDstOnly", "Dump only output of layers");
-    message_list.emplace_back("OV_GPU_DumpLayersLimitBatch", "Limit the size of batch to dump");
-    message_list.emplace_back("OV_GPU_DumpLayersRaw", "If true, dump data is stored in raw memory format.");
-    message_list.emplace_back("OV_GPU_DumpLayersRawBinary", "If true, dump data is stored in binary format.");
-    message_list.emplace_back("OV_GPU_DryRunPath", "Dry run and serialize execution graph into the specified path");
-    message_list.emplace_back("OV_GPU_BaseBatchForMemEstimation", "Base batch size to be used in memory estimation");
-    message_list.emplace_back("OV_GPU_AfterProc", "Run inference after the specified process PIDs are finished, separated by space."
-                              " Supported on only on linux.");
-    message_list.emplace_back("OV_GPU_SerialCompile", "Serialize creating primitives and compiling kernels");
-    message_list.emplace_back("OV_GPU_ForceImplTypes", "Force implementation type of a target primitive or layer. [primitive or layer_name]:[impl_type]"
-                              " For example fc:onednn gemm:onednn reduce:ocl do:cpu"
-                              " For primitives fc, gemm, do, reduce, concat are supported. Separated by space.");
-    message_list.emplace_back("OV_GPU_MaxKernelsPerBatch", "Maximum number of kernels in a batch during compiling kernels");
-    message_list.emplace_back("OV_GPU_ImplsCacheCapacity", "The maximum number of entries in the kernel impl cache");
-    message_list.emplace_back("OV_GPU_DisableAsyncCompilation", "Disable async compilation");
-    message_list.emplace_back("OV_GPU_DisableWinogradConv", "Disable Winograd convolution");
-    message_list.emplace_back("OV_GPU_DisableDynamicImpl", "Disable dynamic implementation");
-    message_list.emplace_back("OV_GPU_DisableRuntimeBufferFusing", "Disable runtime buffer fusing");
-    message_list.emplace_back("OV_GPU_DisableMemoryReuse", "Disable memory reuse");
-    message_list.emplace_back("OV_GPU_EnableSDPA", "This allows the enforcement of SDPA decomposition logic: 0 completely disables SDPA kernel usage, "
-                              "and 1 enables it for all the cases.");
-    message_list.emplace_back("OV_GPU_DumpMemoryPool", "Dump memory pool contents of each iteration");
-    message_list.emplace_back("OV_GPU_DumpMemoryPoolIters", "List of iterations to dump memory pool status, separated by space.");
-    message_list.emplace_back("OV_GPU_DumpMemoryPoolPath", "Enable dumping memory pool status to csv file and set the dest path");
-    message_list.emplace_back("OV_GPU_DisableBuildTimeWeightReorderForDynamicNodes", "Disable build time weight reorder for dynmaic nodes.");
-    message_list.emplace_back("OV_GPU_DisableRuntimeSkipReorder", "Disable runtime skip reorder.");
-    message_list.emplace_back("OV_GPU_DisablePrimitiveFusing", "Disable primitive fusing");
-    message_list.emplace_back("OV_GPU_DisableFakeAlignment", "Disable fake alignment");
-    message_list.emplace_back("OV_GPU_UseUsmHost", "Set explicit policy for usm host usage for network input/output. "
-                              "0: default, 1: use usm_host, 2: do not use usm_host");
-    message_list.emplace_back("OV_GPU_KVCacheCompression", "Enable/Disable KV-cache compression");
-    message_list.emplace_back("OV_GPU_DynamicQuantizeLayersWithoutOnednn", "Enable Dynamic quantization for specified Fully connected layers only, "
-                                "separated by space. Support case-insensitive and regular expression. For example .*fully_connected.*");
-    message_list.emplace_back("OV_GPU_DynamicQuantizeGroupSize", "Specify a group size of dynamic quantization to enable "
-                              "dynamic quantization for Fully-connected primitive.");
-    message_list.emplace_back("OV_GPU_DynamicQuantizeAsym", "Enable asymmetric dynamic quantization when set as 1.");
-    message_list.emplace_back("OV_GPU_DisableHorizontalFCFusion", "Disable horizontal fc fusion");
-    message_list.emplace_back("OV_GPU_DisableFCSwigluFusion", "Disable fc + swiglu fusion");
-    message_list.emplace_back("OV_GPU_DumpIteration", "Dump n-th execution of network, separated by space.");
-    message_list.emplace_back("OV_GPU_MemPreallocationOptions", "Controls buffer pre-allocation feature. Expects 4 values separated by space in "
-                              "the following order: number of iterations for pre-allocation(int), max size of single iteration in bytes(int), "
-                              "max per-dim allowed diff(int), unconditional buffers preallocation ratio(float). For example for disabling memory "
-                              "preallocation at all, you can use OV_GPU_MemPreallocationOptions='0 0 0 1.0'");
-    message_list.emplace_back("OV_GPU_LoadDumpRawBinary",
-                               "Specified layers which are loading dumped binary files generated by OV_GPU_DumpLayersRawBinary debug-config."
-                               " Currently, other layers except input-layer('parameter' type) are loading binaries for only input."
-                               " Different input or output tensors are seperated by ','. Different layers are separated by space. For example, "
-                               " \"[input_layer_name1]:[binary_dumped_file1],[binary_dump_file2] [input_layer_name2]:[binary_dump_1],[binary_dump_2]\"");
-
-    auto max_name_length_item = std::max_element(message_list.begin(), message_list.end(),
-        [](std::pair<std::string, std::string>& a, std::pair<std::string, std::string>& b){
-            return a.first.size() < b.first.size();
-    });
-    int name_width = static_cast<int>(max_name_length_item->first.size()) + 2;
-
-    GPU_DEBUG_COUT_ << "Supported environment variables for debugging" << std::endl;
-    for (auto& p : message_list) {
-        GPU_DEBUG_COUT_ << " - " << std::left << std::setw(name_width) << p.first + "  " << p.second << std::endl;
-    }
-}
-
-#endif
-
-debug_configuration::debug_configuration()
-        : help(0)
-        , verbose(0)
-        , verbose_color(0)
-        , verbose_file()
-        , list_layers(0)
-        , print_multi_kernel_perf(0)
-        , print_input_data_shapes(0)
-        , disable_usm(0)
-        , disable_onednn(0)
-        , disable_onednn_opt_post_ops(0)
-        , dump_profiling_data(std::string(""))
-        , dump_profiling_data_per_iter(0)
-        , host_time_profiling(0)
-        , dump_graphs(std::string())
-        , dump_sources(std::string())
-        , dump_layers_path(std::string())
-        , dry_run_path(std::string())
-        , dump_layers_dst_only(0)
-        , dump_layers_result(0)
-        , dump_layers_input(0)
-        , dump_layers_limit_batch(std::numeric_limits<int>::max())
-        , dump_layers_raw(0)
-        , dump_layers_binary(0)
-        , dump_memory_pool(0)
-        , dump_memory_pool_path(std::string())
-        , base_batch_for_memory_estimation(-1)
-        , serialize_compile(0)
-        , max_kernels_per_batch(0)
-        , impls_cache_capacity(-1)
-        , enable_sdpa(-1)
-        , disable_async_compilation(0)
-        , disable_winograd_conv(0)
-        , disable_dynamic_impl(0)
-        , disable_runtime_buffer_fusing(0)
-        , disable_memory_reuse(0)
-        , disable_build_time_weight_reorder_for_dynamic_nodes(0)
-        , disable_runtime_skip_reorder(0)
-        , disable_primitive_fusing(0)
-        , disable_fake_alignment(0)
-        , use_usm_host(0)
-        , use_kv_cache_compression(-1)
-        , dynamic_quantize_group_size(DYNAMIC_QUANTIZE_GROUP_SIZE_NOT_SET)
-        , dynamic_quantize_asym(0)
-        , disable_horizontal_fc_fusion(0)
-        , disable_fc_swiglu_fusion(0) {
+namespace ov::intel_gpu {
+std::ostream& get_verbose_stream() {
 #ifdef GPU_DEBUG_CONFIG
-    get_gpu_debug_env_var("Help", help);
-    get_common_debug_env_var("Verbose", verbose);
-    get_gpu_debug_env_var("VerboseColor", verbose_color);
-    get_gpu_debug_env_var("VerboseFile", verbose_file);
-    get_gpu_debug_env_var("ListLayers", list_layers);
-    get_gpu_debug_env_var("PrintMultiKernelPerf", print_multi_kernel_perf);
-    get_gpu_debug_env_var("PrintInputDataShapes", print_input_data_shapes);
-    get_gpu_debug_env_var("DisableUsm", disable_usm);
-    get_gpu_debug_env_var("DumpGraphs", dump_graphs);
-    get_gpu_debug_env_var("DumpSources", dump_sources);
-    get_gpu_debug_env_var("DumpLayersPath", dump_layers_path);
-    get_gpu_debug_env_var("DumpLayersLimitBatch", dump_layers_limit_batch);
-    get_gpu_debug_env_var("DumpLayersRaw", dump_layers_raw);
-    get_gpu_debug_env_var("DumpLayersRawBinary", dump_layers_binary);
-    get_gpu_debug_env_var("DumpLayersDstOnly", dump_layers_dst_only);
-    get_gpu_debug_env_var("DumpLayersResult", dump_layers_result);
-    get_gpu_debug_env_var("DumpLayersInput", dump_layers_input);
-    get_gpu_debug_env_var("DisableOnednn", disable_onednn);
-    get_gpu_debug_env_var("DisableOnednnOptPostOps", disable_onednn_opt_post_ops);
-    get_gpu_debug_env_var("DumpProfilingData", dump_profiling_data);
-    get_gpu_debug_env_var("DumpProfilingDataPerIter", dump_profiling_data_per_iter);
-    get_gpu_debug_env_var("HostTimeProfiling", host_time_profiling);
-    std::string dump_prof_data_iter_str;
-    get_gpu_debug_env_var("DumpProfilingDataIteration", dump_prof_data_iter_str);
-    get_gpu_debug_env_var("DryRunPath", dry_run_path);
-    get_gpu_debug_env_var("DumpMemoryPool", dump_memory_pool);
-    std::string dump_runtime_memory_pool_iters_str;
-    get_gpu_debug_env_var("DumpMemoryPoolIters", dump_runtime_memory_pool_iters_str);
-    get_gpu_debug_env_var("DumpMemoryPoolPath", dump_memory_pool_path);
-    get_gpu_debug_env_var("BaseBatchForMemEstimation", base_batch_for_memory_estimation);
-    std::string dump_layers_str;
-    get_gpu_debug_env_var("DumpLayers", dump_layers_str);
-    std::string after_proc_str;
-    get_gpu_debug_env_var("AfterProc", after_proc_str);
-    get_gpu_debug_env_var("SerialCompile", serialize_compile);
-    std::string forced_impl_types_str;
-    get_gpu_debug_env_var("ForceImplTypes", forced_impl_types_str);
-    get_gpu_debug_env_var("MaxKernelsPerBatch", max_kernels_per_batch);
-    get_gpu_debug_env_var("ImplsCacheCapacity", impls_cache_capacity);
-    get_gpu_debug_env_var("EnableSDPA", enable_sdpa);
-    get_gpu_debug_env_var("DisableAsyncCompilation", disable_async_compilation);
-    get_gpu_debug_env_var("DisableWinogradConv", disable_winograd_conv);
-    get_gpu_debug_env_var("DisableDynamicImpl", disable_dynamic_impl);
-    get_gpu_debug_env_var("DisableRuntimeBufferFusing", disable_runtime_buffer_fusing);
-    get_gpu_debug_env_var("DisableMemoryReuse", disable_memory_reuse);
-    get_gpu_debug_env_var("DisableBuildTimeWeightReorderForDynamicNodes", disable_build_time_weight_reorder_for_dynamic_nodes);
-    get_gpu_debug_env_var("DisableRuntimeSkipReorder", disable_runtime_skip_reorder);
-    get_gpu_debug_env_var("DisablePrimitiveFusing", disable_primitive_fusing);
-    get_gpu_debug_env_var("DisableFakeAlignment", disable_fake_alignment);
-    get_gpu_debug_env_var("UseUsmHost", use_usm_host);
-    get_gpu_debug_env_var("KVCacheCompression", use_kv_cache_compression);
-    get_gpu_debug_env_var("DynamicQuantizeGroupSize", dynamic_quantize_group_size);
-    get_gpu_debug_env_var("DynamicQuantizeAsym", dynamic_quantize_asym);
-    get_gpu_debug_env_var("DisableHorizontalFCFusion", disable_horizontal_fc_fusion);
-    get_gpu_debug_env_var("DisableFCSwigluFusion", disable_fc_swiglu_fusion);
-    std::string dump_iteration_str;
-    get_gpu_debug_env_var("DumpIteration", dump_iteration_str);
-    std::string mem_preallocation_params_str;
-    get_gpu_debug_env_var("MemPreallocationOptions", mem_preallocation_params_str);
-    std::string load_dump_raw_bin_str;
-    get_gpu_debug_env_var("LoadDumpRawBinary", load_dump_raw_bin_str);
-    std::string dynamic_quantize_layers_without_onednn_str;
-    get_gpu_debug_env_var("DynamicQuantizeLayersWithoutOnednn", dynamic_quantize_layers_without_onednn_str);
-
-    if (help > 0) {
-        print_help_messages();
-        exit(0);
-    }
-
-    if (verbose_file.length() > 0) {
+    if (ExecutionConfig::get_log_to_file().length() > 0) {
         static std::ofstream fout;
-        fout.open(verbose_file);
-        verbose_stream = &fout;
+        if (!fout.is_open())
+            fout.open(ExecutionConfig::get_log_to_file());
+        return fout;
     } else {
-        verbose_stream = &std::cout;
-    }
-
-    if (dump_prof_data_iter_str.length() > 0) {
-        dump_prof_data_iter_str = " " + dump_prof_data_iter_str + " ";
-        std::istringstream iss(dump_prof_data_iter_str);
-        char dot;
-        int64_t start, end;
-        bool is_valid_range = false;
-        if (iss >> start >> dot >> dot >> end) {
-            if (start <= end || end == -1) {
-                try {
-                    is_valid_range = true;
-                    dump_prof_data_iter_params.start = start;
-                    dump_prof_data_iter_params.end = end;
-                } catch(const std::exception &) {
-                    is_valid_range = false;
-                }
-            }
-        }
-        if (!is_valid_range)
-            std::cout << "OV_GPU_DumpProfilingDataIteration was ignored. It cannot be parsed to valid iteration range." << std::endl;
-        dump_prof_data_iter_params.is_enabled = is_valid_range;
-    }
-
-    if (dump_layers_str.length() > 0) {
-        // Insert delimiter for easier parsing when used
-        dump_layers_str = " " + dump_layers_str + " ";
-        std::stringstream ss(dump_layers_str);
-        std::string layer;
-        while (ss >> layer) {
-            dump_layers.push_back(layer);
-        }
-    }
-
-    if (dynamic_quantize_layers_without_onednn_str.length() > 0) {
-        // Insert delimiter for easier parsing when used
-        dynamic_quantize_layers_without_onednn_str = " " + dynamic_quantize_layers_without_onednn_str + " ";
-        std::stringstream ss(dynamic_quantize_layers_without_onednn_str);
-        std::string layer;
-        while (ss >> layer) {
-            dynamic_quantize_layers_without_onednn.push_back(layer);
-        }
-    }
-
-    if (forced_impl_types_str.length() > 0) {
-        forced_impl_types_str = " " + forced_impl_types_str + " ";
-        std::stringstream ss(forced_impl_types_str);
-        std::string type;
-        while (ss >> type) {
-            forced_impl_types.push_back(type);
-        }
-    }
-
-    // Parsing for loading binary files
-    if (load_dump_raw_bin_str.length() > 0) {
-        load_dump_raw_bin_str = " " + load_dump_raw_bin_str + " ";
-        std::stringstream ss(load_dump_raw_bin_str);
-        std::string type;
-        while (ss >> type) {
-            load_layers_raw_dump.push_back(type);
-        }
-    }
-
-    if (dump_iteration_str.size() > 0) {
-        dump_iteration = parse_int_set(dump_iteration_str);
-    }
-
-    if (dump_runtime_memory_pool_iters_str.size() > 0) {
-        dump_memory_pool_iters = parse_int_set(dump_runtime_memory_pool_iters_str);
-    }
-
-    if (mem_preallocation_params_str.size() > 0) {
-        mem_preallocation_params_str = " " + mem_preallocation_params_str + " ";
-        std::istringstream ss(mem_preallocation_params_str);
-        std::vector<std::string> params;
-        std::string param;
-        while (ss >> param)
-            params.push_back(param);
-
-        bool correct_params = params.size() == 4;
-        if (correct_params) {
-            try {
-                mem_preallocation_params.next_iters_preallocation_count = std::stol(params[0]);
-                mem_preallocation_params.max_per_iter_size = std::stol(params[1]);
-                mem_preallocation_params.max_per_dim_diff = std::stol(params[2]);
-                mem_preallocation_params.buffers_preallocation_ratio = std::stof(params[3]);
-            } catch(const std::exception &) {
-                correct_params = false;
-            }
-        }
-
-        if (!correct_params)
-            GPU_DEBUG_COUT_ << "OV_GPU_MemPreallocationOptions were ignored, because they cannot be parsed.\n";
-
-        mem_preallocation_params.is_initialized = correct_params;
-    }
-
-    if (after_proc_str.length() > 0) {
-#ifdef _WIN32
-        GPU_DEBUG_COUT_ << "Warning: OV_GPU_AfterProc is supported only on linux" << std::endl;
-#else
-        after_proc_str = " " + after_proc_str + " "; // Insert delimiter for easier parsing when used
-        std::stringstream ss(after_proc_str);
-        std::string pid;
-        while (ss >> pid) {
-            after_proc.push_back(pid);
-        }
-#endif
-    }
-#endif
-}
-
-const debug_configuration *debug_configuration::get_instance() {
-    static std::unique_ptr<debug_configuration> instance(nullptr);
-#ifdef GPU_DEBUG_CONFIG
-    static std::mutex _m;
-    std::lock_guard<std::mutex> lock(_m);
-    if (nullptr == instance)
-        instance.reset(new debug_configuration());
-    return instance.get();
-#else
-    return nullptr;
-#endif
-}
-
-bool debug_configuration::is_target_dump_prof_data_iteration(int64_t iteration) const {
-#ifdef GPU_DEBUG_CONFIG
-    if (iteration < 0)
-        return true;
-
-    if (dump_prof_data_iter_params.start > iteration)
-        return false;
-
-    if (dump_prof_data_iter_params.start <= dump_prof_data_iter_params.end &&
-        dump_prof_data_iter_params.end < iteration)
-        return false;
-
-    return true;
-#else
-    return false;
-#endif
-}
-
-std::vector<std::string> debug_configuration::get_filenames_for_matched_layer_loading_binaries(const std::string& id) const {
-    std::vector<std::string> file_names;
-#ifdef GPU_DEBUG_CONFIG
-    if (load_layers_raw_dump.empty())
-        return file_names;
-
-    for (const auto& load_layer : load_layers_raw_dump) {
-        size_t file = load_layer.rfind(":");
-        if (file != std::string::npos) {
-            if (id == load_layer.substr(0, file)) {
-                auto file_name_str = load_layer.substr(file + 1);
-                size_t head = 0;
-                size_t found = 0;
-                do {
-                    found = file_name_str.find(",", head);
-                    if (found != std::string::npos)
-                        file_names.push_back(file_name_str.substr(head, (found - head)));
-                    else
-                        file_names.push_back(file_name_str.substr(head));
-
-                    head = found+1;
-                    GPU_DEBUG_LOG << " Layer name loading raw dump : " << load_layer.substr(0, file) << " / the dump file : "
-                                << file_names.back() << std::endl;
-                } while (found != std::string::npos);
-
-                return file_names;
-            }
-        }
-    }
-#endif
-
-    return file_names;
-}
-
-std::string debug_configuration::get_matched_from_filelist(const std::vector<std::string>& file_names, std::string pattern) const {
-#ifdef GPU_DEBUG_CONFIG
-    for (const auto& file : file_names) {
-        auto found = file.find(pattern);
-        if (found != std::string::npos) {
-            return file;
-        }
+        return std::cout;
     }
-#endif
-    return std::string();
-}
-
-std::string debug_configuration::get_name_for_dump(const std::string& file_name) const {
-    std::string filename = file_name;
-#ifdef GPU_DEBUG_CONFIG
-    std::replace(filename.begin(), filename.end(), '\\', '_');
-    std::replace(filename.begin(), filename.end(), '/', '_');
-    std::replace(filename.begin(), filename.end(), ' ', '_');
-    std::replace(filename.begin(), filename.end(), ':', '_');
-#endif
-    return filename;
-}
-
-bool debug_configuration::is_layer_name_matched(const std::string& layer_name, const std::string& pattern) const {
-#ifdef GPU_DEBUG_CONFIG
-    auto upper_layer_name = std::string(layer_name.length(), '\0');
-    std::transform(layer_name.begin(), layer_name.end(), upper_layer_name.begin(), ::toupper);
-    auto upper_pattern = std::string(pattern.length(), '\0');
-    std::transform(pattern.begin(), pattern.end(), upper_pattern.begin(), ::toupper);
-
-    // Check pattern from exec_graph
-    size_t pos = upper_layer_name.find(':');
-    auto upper_exec_graph_name = upper_layer_name.substr(pos + 1, upper_layer_name.size());
-    if (upper_exec_graph_name.compare(upper_pattern) == 0) {
-        return true;
-    }
-
-    // Check pattern with regular expression
-    std::regex re(upper_pattern);
-    return std::regex_match(upper_layer_name, re);
-#else
-    return false;
-#endif
-}
-
-bool debug_configuration::is_layer_for_dumping(const std::string& layer_name, bool is_output, bool is_input) const {
-#ifdef GPU_DEBUG_CONFIG
-    // Dump result layer
-    if (is_output == true && dump_layers_result == 1 &&
-        (layer_name.find("constant:") == std::string::npos))
-        return true;
-    // Dump all layers
-    if (dump_layers.empty() && dump_layers_result == 0 && dump_layers_input == 0)
-        return true;
-
-    // Dump input layers
-    size_t pos = layer_name.find(':');
-    auto type = layer_name.substr(0, pos);
-    if (is_input == true && type == "parameter" && dump_layers_input == 1)
-        return true;
-
-    auto iter = std::find_if(dump_layers.begin(), dump_layers.end(), [&](const std::string& dl){
-        return is_layer_name_matched(layer_name, dl);
-    });
-    return (iter != dump_layers.end());
-#else
-    return false;
-#endif
-}
-
-bool debug_configuration::is_target_iteration(int64_t iteration) const {
-#ifdef GPU_DEBUG_CONFIG
-    if (iteration < 0)
-        return true;
-
-    if (dump_iteration.empty())
-        return true;
-
-    if (dump_iteration.find(iteration) == std::end(dump_iteration))
-        return false;
-
-    return true;
 #else
-    return false;
+    return std::cout;
 #endif
 }
-} // namespace cldnn
+}  // namespace ov::intel_gpu
diff --git a/src/plugins/intel_gpu/src/runtime/device.cpp b/src/plugins/intel_gpu/src/runtime/device.cpp
index fa027ebe9e2e33..428d18f6c51775 100644
--- a/src/plugins/intel_gpu/src/runtime/device.cpp
+++ b/src/plugins/intel_gpu/src/runtime/device.cpp
@@ -65,8 +65,7 @@ float device::get_gops(cldnn::data_types dt) const {
 }
 
 bool device::use_unified_shared_memory() const {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_usm) {
+    GPU_DEBUG_IF(ExecutionConfig::get_disable_usm()) {
         return false;
     }
     if (get_mem_caps().supports_usm()) {
diff --git a/src/plugins/intel_gpu/src/runtime/engine.cpp b/src/plugins/intel_gpu/src/runtime/engine.cpp
index b5ec7da3fab705..73bceb8bea8659 100644
--- a/src/plugins/intel_gpu/src/runtime/engine.cpp
+++ b/src/plugins/intel_gpu/src/runtime/engine.cpp
@@ -71,8 +71,7 @@ const device::ptr engine::get_device() const {
 }
 
 bool engine::use_unified_shared_memory() const {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_usm) {
+    GPU_DEBUG_IF(ExecutionConfig::get_disable_usm()) {
         return false;
     }
     if (_device->get_mem_caps().supports_usm()) {
diff --git a/src/plugins/intel_gpu/src/runtime/execution_config.cpp b/src/plugins/intel_gpu/src/runtime/execution_config.cpp
index 7d2a9d5f90fc8b..bc52d991247492 100644
--- a/src/plugins/intel_gpu/src/runtime/execution_config.cpp
+++ b/src/plugins/intel_gpu/src/runtime/execution_config.cpp
@@ -1,308 +1,305 @@
-// Copyright (C) 2022 Intel Corporation
+// Copyright (C) 2024 Intel Corporation
 // SPDX-License-Identifier: Apache-2.0
 //
 
 #include "intel_gpu/runtime/execution_config.hpp"
-#include "intel_gpu/runtime/debug_configuration.hpp"
+#include "intel_gpu/plugin/remote_context.hpp"
+#include "openvino/core/any.hpp"
+#include "openvino/core/model.hpp"
+#include "openvino/op/concat.hpp"
+#include "openvino/op/convert.hpp"
+#include "openvino/op/gather.hpp"
+#include "openvino/op/loop.hpp"
+#include "openvino/op/lstm_sequence.hpp"
+#include "openvino/op/paged_attention.hpp"
+#include "openvino/op/search_sorted.hpp"
+#include "openvino/op/stft.hpp"
+#include "openvino/pass/pattern/matcher.hpp"
+#include "openvino/pass/pattern/op/label.hpp"
+#include "openvino/pass/pattern/op/or.hpp"
+#include "openvino/pass/pattern/op/wrap_type.hpp"
+#include "ov_ops/dynamic_quantize.hpp"
 #include "openvino/runtime/internal_properties.hpp"
+#include "intel_gpu/runtime/internal_properties.hpp"
+#include "openvino/runtime/plugin_config.hpp"
 #include "openvino/runtime/properties.hpp"
 
-#include <thread>
 
 namespace ov::intel_gpu {
 
-ExecutionConfig::ExecutionConfig() {
-    set_default();
-}
+namespace {
 
-class InferencePrecisionValidator : public BaseValidator {
-public:
-    bool is_valid(const ov::Any& v) const override {
-        auto precision = v.as<ov::element::Type>();
-        return precision == ov::element::f16 || precision == ov::element::f32 || precision == ov::element::undefined;
-    }
-};
-
-class PerformanceModeValidator : public BaseValidator {
-public:
-    bool is_valid(const ov::Any& v) const override {
-        auto mode = v.as<ov::hint::PerformanceMode>();
-        return mode == ov::hint::PerformanceMode::CUMULATIVE_THROUGHPUT ||
-               mode == ov::hint::PerformanceMode::THROUGHPUT ||
-               mode == ov::hint::PerformanceMode::LATENCY;
+ov::RTMap get_rt_info(const ov::Model& model) {
+    ov::RTMap rt_info;
+    if (model.has_rt_info("runtime_options"))
+        rt_info = model.get_rt_info<ov::AnyMap>("runtime_options");
+
+    if (model.has_rt_info("__weights_path")) {
+        rt_info[ov::weights_path.name()] = model.get_rt_info<ov::Any>("__weights_path");
     }
-};
-
-void ExecutionConfig::set_default() {
-    register_property<PropertyVisibility::PUBLIC>(
-        std::make_tuple(ov::device::id, "0"),
-        std::make_tuple(ov::enable_profiling, false),
-        std::make_tuple(ov::cache_dir, ""),
-        std::make_tuple(ov::num_streams, 1),
-        std::make_tuple(ov::compilation_num_threads, std::max(1, static_cast<int>(std::thread::hardware_concurrency()))),
-        std::make_tuple(ov::hint::inference_precision, ov::element::f16, InferencePrecisionValidator()),
-        std::make_tuple(ov::hint::model_priority, ov::hint::Priority::MEDIUM),
-        std::make_tuple(ov::hint::performance_mode, ov::hint::PerformanceMode::LATENCY, PerformanceModeValidator()),
-        std::make_tuple(ov::hint::execution_mode, ov::hint::ExecutionMode::PERFORMANCE),
-        std::make_tuple(ov::hint::num_requests, 0),
-        std::make_tuple(ov::hint::enable_cpu_pinning, false),
-        std::make_tuple(ov::hint::enable_cpu_reservation, false),
-
-        std::make_tuple(ov::intel_gpu::hint::host_task_priority, ov::hint::Priority::MEDIUM),
-        std::make_tuple(ov::intel_gpu::hint::queue_throttle, ov::intel_gpu::hint::ThrottleLevel::MEDIUM),
-        std::make_tuple(ov::intel_gpu::hint::queue_priority, ov::hint::Priority::MEDIUM),
-        std::make_tuple(ov::intel_gpu::hint::enable_sdpa_optimization, true),
-        std::make_tuple(ov::intel_gpu::enable_loop_unrolling, true),
-        std::make_tuple(ov::intel_gpu::disable_winograd_convolution, false),
-        std::make_tuple(ov::internal::exclusive_async_requests, false),
-        std::make_tuple(ov::internal::query_model_ratio, 1.0f),
-        std::make_tuple(ov::cache_mode, ov::CacheMode::OPTIMIZE_SPEED),
-        std::make_tuple(ov::cache_encryption_callbacks, EncryptionCallbacks{}),
-        std::make_tuple(ov::hint::dynamic_quantization_group_size, 0),
-        std::make_tuple(ov::hint::kv_cache_precision, ov::element::f16),
-        std::make_tuple(ov::intel_gpu::hint::enable_kernels_reuse, false),
-        std::make_tuple(ov::weights_path, ""),
-        std::make_tuple(ov::hint::activations_scale_factor, -1.f),
-
-        // Legacy API properties
-        std::make_tuple(ov::intel_gpu::nv12_two_inputs, false),
-        std::make_tuple(ov::intel_gpu::config_file, ""),
-        std::make_tuple(ov::intel_gpu::enable_lp_transformations, false));
-
-    register_property<PropertyVisibility::INTERNAL>(
-        std::make_tuple(ov::intel_gpu::max_dynamic_batch, 1),
-        std::make_tuple(ov::intel_gpu::queue_type, QueueTypes::out_of_order),
-        std::make_tuple(ov::intel_gpu::optimize_data, false),
-        std::make_tuple(ov::intel_gpu::enable_memory_pool, true),
-        std::make_tuple(ov::intel_gpu::allow_static_input_reorder, false),
-        std::make_tuple(ov::intel_gpu::custom_outputs, std::vector<std::string>{}),
-        std::make_tuple(ov::intel_gpu::dump_graphs, ""),
-        std::make_tuple(ov::intel_gpu::force_implementations, ImplForcingMap{}),
-        std::make_tuple(ov::intel_gpu::partial_build_program, false),
-        std::make_tuple(ov::intel_gpu::allow_new_shape_infer, false),
-        std::make_tuple(ov::intel_gpu::use_only_static_kernels_for_dynamic_shape, false),
-        std::make_tuple(ov::intel_gpu::buffers_preallocation_ratio, 1.1f),
-        std::make_tuple(ov::intel_gpu::max_kernels_per_batch, 8),
-        std::make_tuple(ov::intel_gpu::use_onednn, false));
+    return rt_info;
 }
 
-void ExecutionConfig::register_property_impl(const std::pair<std::string, ov::Any>& property, PropertyVisibility visibility, BaseValidator::Ptr validator) {
-    property_validators[property.first] = validator;
-    supported_properties[property.first] = visibility;
-    internal_properties[property.first] = property.second;
-}
 
-void ExecutionConfig::set_property(const AnyMap& config) {
-    for (auto& kv : config) {
-        auto& name = kv.first;
-        auto& val = kv.second;
-        OPENVINO_ASSERT(is_supported(kv.first), "[GPU] Attempt to set property ", name, " (", val.as<std::string>(), ") which was not registered!\n");
-        OPENVINO_ASSERT(property_validators.at(name)->is_valid(val), "[GPU] Invalid value for property ", name,  ": ", val.as<std::string>());
-        internal_properties[name] = val;
+bool requires_new_shape_infer(const std::shared_ptr<ov::Node>& op) {
+    if (op->is_dynamic()) {
+        return true;
     }
-}
 
-bool ExecutionConfig::is_supported(const std::string& name) const {
-    bool supported = supported_properties.find(name) != supported_properties.end();
-    bool has_validator = property_validators.find(name) != property_validators.end();
+    // HACK: SearchSorted has specific shape requirements.
+    // E.g. static input shapes: sorted:[8], values:[2,3,4] are prefectly fine,
+    // but sorted:[8,1,1,1], values:[2,3,4,1] is not valid.
+    // Similar case for STFT.
+    if (ov::is_type<ov::op::v15::SearchSorted>(op) || ov::is_type<ov::op::v15::STFT>(op))
+        return true;
 
-    return supported && has_validator;
-}
+    if (ov::is_type<ov::op::internal::DynamicQuantize>(op))
+        return true;
 
-bool ExecutionConfig::is_set_by_user(const std::string& name) const {
-    return user_properties.find(name) != user_properties.end();
-}
+    if (ov::is_type<ov::op::v5::Loop>(op)) {
+        const auto body_function = std::static_pointer_cast<ov::op::v5::Loop>(op)->get_function();
+        if (body_function->is_dynamic())
+            return true;
+    }
 
-void ExecutionConfig::set_user_property(const AnyMap& config) {
-    for (auto& kv : config) {
-        auto& name = kv.first;
-        auto& val = kv.second;
-        bool supported = is_supported(name) && supported_properties.at(name) == PropertyVisibility::PUBLIC;
-        OPENVINO_ASSERT(supported, "[GPU] Attempt to set user property ", name, " (", val.as<std::string>(), ") which was not registered or internal!\n");
-        OPENVINO_ASSERT(property_validators.at(name)->is_valid(val), "[GPU] Invalid value for property ", name,  ": `", val.as<std::string>(), "`");
+    if (ov::is_type<ov::op::v5::LSTMSequence>(op) || ov::is_type<ov::op::v4::LSTMCell>(op)) {
+        return true;
+    }
+    // When input node has dynamic shape with 4 dimension, this function return false
+    // because op.is_dynamic() which only checks input shapes return false.
+    // So, in the case of input data, we need to check output shape.
+    for (size_t i = 0; i < op->get_output_size(); i++) {
+        if (op->get_output_partial_shape(i).is_dynamic())
+            return true;
+    }
 
-        user_properties[kv.first] = kv.second;
+    for (size_t i = 0; i < op->get_output_size(); i++) {
+        if (op->get_output_partial_shape(i).size() > 6)
+            return true;
     }
-}
 
-Any ExecutionConfig::get_property(const std::string& name) const {
-    if (user_properties.find(name) != user_properties.end()) {
-        return user_properties.at(name);
+    for (size_t i = 0; i < op->get_input_size(); i++) {
+        if (op->get_input_partial_shape(i).size() > 6)
+            return true;
     }
 
-    OPENVINO_ASSERT(internal_properties.find(name) != internal_properties.end(), "[GPU] Can't get internal property with name ", name);
-    return internal_properties.at(name);
+    return false;
 }
 
-void ExecutionConfig::apply_execution_hints(const cldnn::device_info& info) {
-    if (is_set_by_user(ov::hint::execution_mode)) {
-        const auto mode = get_property(ov::hint::execution_mode);
-        if (!is_set_by_user(ov::hint::inference_precision)) {
-            if (mode == ov::hint::ExecutionMode::ACCURACY) {
-                set_property(ov::hint::inference_precision(ov::element::undefined));
-            } else if (mode == ov::hint::ExecutionMode::PERFORMANCE) {
-                if (info.supports_fp16)
-                    set_property(ov::hint::inference_precision(ov::element::f16));
-                else
-                    set_property(ov::hint::inference_precision(ov::element::f32));
-            }
+bool is_llm(const ov::Model& model) {
+    using namespace ov::pass::pattern;
+
+    auto past = wrap_type<ov::op::v6::ReadValue>();
+    auto convert_past = wrap_type<ov::op::v0::Convert>({past});
+    auto gather_input = std::make_shared<ov::pass::pattern::op::Or>(OutputVector{past, convert_past});
+    auto beam_idx = wrap_type<ov::op::v0::Parameter>();
+    auto gather_past = wrap_type<ov::op::v8::Gather>({gather_input, beam_idx, wrap_type<ov::op::v0::Constant>()});
+    auto gather_convert = wrap_type<ov::op::v0::Convert>({gather_past});
+    auto concat_past_input = std::make_shared<ov::pass::pattern::op::Or>(OutputVector{past, convert_past, gather_past, gather_convert});
+    auto concat = wrap_type<ov::op::v0::Concat>({concat_past_input, any_input()});
+    auto convert_present = wrap_type<ov::op::v0::Convert>({concat});
+    auto present_input = std::make_shared<ov::pass::pattern::op::Or>(OutputVector{concat, convert_present});
+    auto present = wrap_type<ov::op::v6::Assign>({present_input});
+
+    auto kvcache_matcher = std::make_shared<ov::pass::pattern::Matcher>(present, "KVCacheMatcher");
+
+    for (auto& op : model.get_ordered_ops()) {
+        if (kvcache_matcher->match(op) || ov::is_type<ov::op::PagedAttentionExtension>(op)) {
+            return true;
         }
     }
+
+    return false;
 }
 
-void ExecutionConfig::apply_performance_hints(const cldnn::device_info& info) {
-    if (is_set_by_user(ov::hint::performance_mode)) {
-        const auto mode = get_property(ov::hint::performance_mode);
-        if (!is_set_by_user(ov::num_streams)) {
-            if (mode == ov::hint::PerformanceMode::LATENCY) {
-                set_property(ov::num_streams(1));
-            } else if (mode == ov::hint::PerformanceMode::THROUGHPUT) {
-                set_property(ov::num_streams(ov::streams::AUTO));
-            }
-        }
-    }
+} // namespace
 
-    if (get_property(ov::num_streams) == ov::streams::AUTO) {
-        int32_t n_streams = std::max<int32_t>(info.num_ccs, 2);
-        set_property(ov::num_streams(n_streams));
-    }
+ExecutionConfig::ExecutionConfig() : ov::PluginConfig() { }
 
-    if (get_property(ov::internal::exclusive_async_requests)) {
-        set_property(ov::num_streams(1));
+ExecutionConfig::ExecutionConfig(const ExecutionConfig& other) : ExecutionConfig() {
+    m_user_properties = other.m_user_properties;
+    m_is_finalized = other.m_is_finalized;
+    for (const auto& kv : other.m_options_map) {
+        m_options_map.at(kv.first)->set_any(kv.second->get_any());
     }
+}
 
-    // Allow kernels reuse only for single-stream scenarios
-    if (get_property(ov::intel_gpu::hint::enable_kernels_reuse)) {
-        if (get_property(ov::num_streams) != 1) {
-            set_property(ov::intel_gpu::hint::enable_kernels_reuse(false));
-        }
+ExecutionConfig& ExecutionConfig::operator=(const ExecutionConfig& other) {
+    m_user_properties = other.m_user_properties;
+    m_is_finalized = other.m_is_finalized;
+    for (const auto& kv : other.m_options_map) {
+        m_options_map.at(kv.first)->set_any(kv.second->get_any());
     }
+    return *this;
 }
 
-void ExecutionConfig::apply_priority_hints(const cldnn::device_info& info) {
-    if (is_set_by_user(ov::hint::model_priority)) {
-        const auto priority = get_property(ov::hint::model_priority);
-        if (!is_set_by_user(ov::intel_gpu::hint::queue_priority)) {
-            set_property(ov::intel_gpu::hint::queue_priority(priority));
-        }
-    }
+ExecutionConfig ExecutionConfig::clone() const {
+    ExecutionConfig new_config = *this;
+    new_config.m_is_finalized = false;
+    return new_config;
 }
 
-void ExecutionConfig::apply_debug_options(const cldnn::device_info& info) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(!debug_config->dump_graphs.empty()) {
-        set_property(ov::intel_gpu::dump_graphs(debug_config->dump_graphs));
-    }
+void ExecutionConfig::finalize(cldnn::engine& engine) {
+    auto ctx = std::make_shared<RemoteContextImpl>("GPU", std::vector<cldnn::device::ptr>{engine.get_device()});
+    PluginConfig::finalize(ctx.get(), nullptr);
+}
 
-    GPU_DEBUG_IF(debug_config->serialize_compile == 1) {
-        set_property(ov::compilation_num_threads(1));
+void ExecutionConfig::apply_rt_info(const IRemoteContext* context, const ov::RTMap& rt_info, bool is_llm) {
+    const auto& info = dynamic_cast<const RemoteContextImpl*>(context)->get_engine().get_device_info();
+    if (!info.supports_immad) {
+        apply_rt_info_property(ov::hint::kv_cache_precision, rt_info);
     }
+    if (!is_llm)
+        apply_rt_info_property(ov::hint::activations_scale_factor, rt_info);
 
-    GPU_DEBUG_IF(!debug_config->dump_profiling_data.empty()) {
-        GPU_DEBUG_COUT << "[WARNING] ov::enable_profiling property was forced because of enabled OV_GPU_DumpProfilingData debug option\n";
-        set_property(ov::enable_profiling(true));
-    }
+    apply_rt_info_property(ov::hint::dynamic_quantization_group_size, rt_info);
 
-    GPU_DEBUG_IF(debug_config->disable_dynamic_impl == 1) {
-        set_property(ov::intel_gpu::use_only_static_kernels_for_dynamic_shape(true));
+    // WEIGHTS_PATH is used for the weightless cache mechanism which is used only with
+    // ov::CacheMode::OPTIMIZE_SIZE setting. Not setting WEIGHTS_PATH will result in not
+    // using that mechanism.
+    if (get_cache_mode() == ov::CacheMode::OPTIMIZE_SIZE) {
+        apply_rt_info_property(ov::weights_path, rt_info);
     }
+}
 
-    GPU_DEBUG_IF(debug_config->dynamic_quantize_group_size != debug_config->DYNAMIC_QUANTIZE_GROUP_SIZE_NOT_SET) {
-        if (debug_config->dynamic_quantize_group_size == -1)
-            set_property(ov::hint::dynamic_quantization_group_size(UINT64_MAX));
-        else
-            set_property(ov::hint::dynamic_quantization_group_size(debug_config->dynamic_quantize_group_size));
-    }
+void ExecutionConfig::apply_model_specific_options(const IRemoteContext* context, const ov::Model& model) {
+    apply_rt_info(context, get_rt_info(model), is_llm(model));
 
-    GPU_DEBUG_IF(debug_config->use_kv_cache_compression != -1) {
-        GPU_DEBUG_IF(debug_config->use_kv_cache_compression == 1) {
-            set_property(ov::hint::kv_cache_precision(ov::element::i8));
-        } else {
-            set_property(ov::hint::kv_cache_precision(ov::element::undefined));
+    const auto& ops = model.get_ops();
+
+    std::function<void(std::shared_ptr<Node>)> process_op = [&, this](std::shared_ptr<Node> op) {
+        if (requires_new_shape_infer(op)) {
+            m_allow_new_shape_infer = true;
+        }
+        // In the case of dynamic models, because most of the layers are mapped to shape agnostic kernels,
+        // smaller # of kernels are built compared to static models.
+        // So having smaller batch size is even better for dynamic model as we can do more parallel build.
+        if (op->is_dynamic()) {
+            m_max_kernels_per_batch = 4;
+        }
+
+        // Allow using onednn for models with LSTMSequence op as it's much more performant than existing ocl impl
+        if (ov::is_type<ov::op::v5::LSTMSequence>(op)) {
+            m_use_onednn = true;
+        }
+
+        if (auto multi_subgraph_op = ov::as_type_ptr<op::util::MultiSubGraphOp>(op)) {
+            for (const auto& sub_graph : multi_subgraph_op->get_functions()) {
+                for (auto& sub_op : sub_graph->get_ops()) {
+                    process_op(sub_op);
+                }
+            }
         }
+    };
+
+    for (const auto& op : ops) {
+        process_op(op);
     }
-}
 
-void ExecutionConfig::apply_hints(const cldnn::device_info& info) {
-    apply_execution_hints(info);
-    apply_performance_hints(info);
-    apply_priority_hints(info);
-    apply_debug_options(info);
+    m_optimize_data = true;
 }
 
-void ExecutionConfig::apply_user_properties(const cldnn::device_info& info) {
-    if (finalized)
-        return;
-
-    // Copy internal properties before applying hints to ensure that
-    // a property set by hint won't be overriden by a value in user config.
-    // E.g num_streams=AUTO && hint=THROUGHPUT
-    // If we apply hints first and then copy all values from user config to internal one,
-    // then we'll get num_streams=AUTO in final config while some integer number is expected.
-    for (auto& kv : user_properties) {
-        internal_properties[kv.first] = kv.second;
+void ExecutionConfig::finalize_impl(const IRemoteContext* context) {
+    GPU_DEBUG_IF(get_help()) {
+        print_help();
+        exit(-1);
     }
+
+    const auto& info = dynamic_cast<const RemoteContextImpl*>(context)->get_engine().get_device_info();
     apply_hints(info);
-    if (!is_set_by_user(ov::intel_gpu::enable_lp_transformations)) {
-        set_property(ov::intel_gpu::enable_lp_transformations(info.supports_imad || info.supports_immad));
-    }
-    if (info.supports_immad) {
-        set_property(ov::intel_gpu::use_onednn(true));
+    if (!is_set_by_user(ov::internal::enable_lp_transformations)) {
+        m_enable_lp_transformations = info.supports_imad || info.supports_immad;
     }
-    if (get_property(ov::intel_gpu::use_onednn)) {
-        set_property(ov::intel_gpu::queue_type(QueueTypes::in_order));
+    if (!is_set_by_user(ov::intel_gpu::use_onednn) && info.supports_immad) {
+        m_use_onednn = true;
     }
-    if (!is_set_by_user(ov::hint::enable_cpu_reservation)) {
-        if (get_property(ov::hint::enable_cpu_pinning)) {
-            set_property(ov::hint::enable_cpu_reservation(true));
-        }
-    }
-    if (get_property(ov::hint::enable_cpu_reservation)) {
-        if (!is_set_by_user(ov::hint::enable_cpu_pinning)) {
-            set_property(ov::hint::enable_cpu_pinning(true));
-        }
+    if (get_use_onednn()) {
+        m_queue_type = QueueTypes::in_order;
     }
 
-    if (!is_set_by_user(ov::hint::kv_cache_precision) || get_property(ov::hint::kv_cache_precision) == ov::element::undefined) {
+    if (!is_set_by_user(ov::hint::kv_cache_precision) || get_kv_cache_precision() == ov::element::undefined) {
         if (info.supports_immad) {  // MFDNN-11755
-            set_property(ov::hint::kv_cache_precision(get_property(ov::hint::inference_precision)));
+            m_kv_cache_precision = get_inference_precision();
         } else {
             // Enable KV-cache compression by default for non-systolic platforms only
-            set_property(ov::hint::kv_cache_precision(ov::element::i8));
+            m_kv_cache_precision = ov::element::i8;
         }
     }
 
     // Enable dynamic quantization by default for non-systolic platforms
-    if (!is_set_by_user(ov::hint::dynamic_quantization_group_size) &&
-         get_property(ov::hint::dynamic_quantization_group_size) == 0 && !info.supports_immad) {
-        set_property(ov::hint::dynamic_quantization_group_size(32));
+    if (!is_set_by_user(ov::hint::dynamic_quantization_group_size) && get_dynamic_quantization_group_size() == 0 && !info.supports_immad) {
+        m_dynamic_quantization_group_size = 32;
     }
 
-    finalized = true;
+    if (!get_force_implementations().empty()) {
+        m_optimize_data = true;
+    }
 
-    user_properties.clear();
+#ifdef ENABLE_DEBUG_CAPS
+    // For now we apply env/config only for build with debug caps, but it can be updated in the future to allow
+    // reading release options for any build type
+    apply_config_options(context->get_device_name(), get_debug_config());
+#endif // ENABLE_DEBUG_CAPS
 }
 
-void ExecutionConfig::apply_rt_info(const cldnn::device_info& info, const ov::RTMap& rt_info, const bool is_llm) {
-    if (!info.supports_immad) {
-        apply_rt_info_property(ov::hint::kv_cache_precision, rt_info);
+void ExecutionConfig::apply_hints(const cldnn::device_info& info) {
+    apply_execution_hints(info);
+    apply_performance_hints(info);
+    apply_priority_hints(info);
+}
+
+void ExecutionConfig::apply_execution_hints(const cldnn::device_info& info) {
+    if (is_set_by_user(ov::hint::execution_mode)) {
+        const auto mode = get_execution_mode();
+        if (!is_set_by_user(ov::hint::inference_precision)) {
+            if (mode == ov::hint::ExecutionMode::ACCURACY) {
+                m_inference_precision = ov::element::undefined;
+            } else if (mode == ov::hint::ExecutionMode::PERFORMANCE) {
+                if (info.supports_fp16)
+                    m_inference_precision = ov::element::f16;
+                else
+                    m_inference_precision = ov::element::f32;
+            }
+        }
     }
-    if (!is_llm)
-        apply_rt_info_property(ov::hint::activations_scale_factor, rt_info);
-    apply_rt_info_property(ov::hint::dynamic_quantization_group_size, rt_info);
 }
 
-std::string ExecutionConfig::to_string() const {
-    std::stringstream s;
-    s << "internal properties:\n";
-    for (auto& kv : internal_properties) {
-        s << "\t" << kv.first << ": " << kv.second.as<std::string>() << std::endl;
+void ExecutionConfig::apply_performance_hints(const cldnn::device_info& info) {
+    if (is_set_by_user(ov::hint::performance_mode)) {
+        const auto mode = get_performance_mode();
+        if (!is_set_by_user(ov::num_streams)) {
+            if (mode == ov::hint::PerformanceMode::LATENCY) {
+                m_num_streams = 1;
+            } else if (mode == ov::hint::PerformanceMode::THROUGHPUT) {
+                m_num_streams = ov::streams::AUTO;
+            }
+        }
     }
-    s << "user properties:\n";
-    for (auto& kv : user_properties) {
-        s << "\t" << kv.first << ": " << kv.second.as<std::string>() << std::endl;
+
+    if (get_num_streams() == ov::streams::AUTO) {
+        int32_t n_streams = std::max<int32_t>(info.num_ccs, 2);
+        m_num_streams = n_streams;
+    }
+
+    if (get_exclusive_async_requests()) {
+        m_num_streams = 1;
+    }
+
+    // Allow kernels reuse only for single-stream scenarios
+    if (get_enable_kernels_reuse()) {
+        if (get_num_streams() != 1) {
+            m_enable_kernels_reuse = false;
+        }
+    }
+}
+
+void ExecutionConfig::apply_priority_hints(const cldnn::device_info& info) {
+    if (is_set_by_user(ov::hint::model_priority)) {
+        const auto priority = get_model_priority();
+        if (!is_set_by_user(ov::intel_gpu::hint::queue_priority)) {
+            m_queue_priority = priority;
+        }
     }
-    return s.str();
 }
 
 }  // namespace ov::intel_gpu
diff --git a/src/plugins/intel_gpu/src/runtime/memory_pool.cpp b/src/plugins/intel_gpu/src/runtime/memory_pool.cpp
index 1417680c985632..a899f78eb565d3 100644
--- a/src/plugins/intel_gpu/src/runtime/memory_pool.cpp
+++ b/src/plugins/intel_gpu/src/runtime/memory_pool.cpp
@@ -52,7 +52,6 @@ void memory_pool::release_memory(memory* mem, const size_t& unique_id, primitive
     auto type = mem->get_allocation_type();
     const auto _layout_bytes_count = _layout.bytes_count();
 
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     {
         auto it = _non_padded_pool.lower_bound(_layout_bytes_count);
 
@@ -67,7 +66,7 @@ void memory_pool::release_memory(memory* mem, const size_t& unique_id, primitive
                 }
                 if (it->second._users.empty()) {
 #ifdef GPU_DEBUG_CONFIG
-                    GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+                    GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                         auto released_mem_size = it->first;
                         total_mem_size_non_padded_pool -= released_mem_size;
                         if (type == allocation_type::usm_host)
@@ -104,7 +103,7 @@ void memory_pool::release_memory(memory* mem, const size_t& unique_id, primitive
                     }
                     if (list_itr->_users.empty()) {
 #ifdef GPU_DEBUG_CONFIG
-                        GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+                        GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                             auto released_mem_size = mem->size();
                             total_mem_size_padded_pool -= released_mem_size;
                             if (type == allocation_type::usm_host)
@@ -128,14 +127,14 @@ void memory_pool::release_memory(memory* mem, const size_t& unique_id, primitive
         }
     }
 #ifdef GPU_DEBUG_CONFIG
-    GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+    GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
         auto iter = std::find_if(_no_reusable_mems.begin(), _no_reusable_mems.end(), [&](const cldnn::memory_record& r) {
             return (network_id == r._network_id
                 && type == r._type
                 && mem->get_internal_params().mem == r._memory->get_internal_params().mem);
         });
         if (iter != _no_reusable_mems.end()) {
-            GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+            GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                 auto released_mem_size = iter->_users.begin()->_mem_size;
                 total_mem_size_no_reusable -= released_mem_size;
                 if (type == allocation_type::usm_host)
@@ -183,8 +182,7 @@ memory::ptr memory_pool::get_from_non_padded_pool(const layout& layout,
                                  memory_record({{MEM_USER(unique_id, network_id, prim_id, layout_bytes_count)}}, mem, network_id, type));
 #ifdef GPU_DEBUG_CONFIG
         {
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+            GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                 total_mem_size_non_padded_pool += layout_bytes_count;
                 if (type == allocation_type::usm_host)
                     mem_size_non_padded_pool_host += layout_bytes_count;
@@ -225,8 +223,7 @@ memory::ptr memory_pool::get_from_padded_pool(const layout& layout,
             memory_record({{MEM_USER(unique_id, network_id, prim_id, mem->size())}}, mem, network_id, type));
 #ifdef GPU_DEBUG_CONFIG
         {
-            GPU_DEBUG_GET_INSTANCE(debug_config);
-            GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+            GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                 const auto allocated_mem_size = mem->size();
                 total_mem_size_padded_pool += allocated_mem_size;
                 if (type == allocation_type::usm_host)
@@ -242,8 +239,7 @@ memory::ptr memory_pool::get_from_padded_pool(const layout& layout,
     _padded_pool.emplace(layout, std::move(list));
 #ifdef GPU_DEBUG_CONFIG
     {
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-        GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+        GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
             const auto allocated_mem_size = mem->size();
             total_mem_size_padded_pool += allocated_mem_size;
             if (type == allocation_type::usm_host)
@@ -300,8 +296,7 @@ memory::ptr memory_pool::get_memory(const layout& layout,
                                     bool reset,
                                     bool is_dynamic) {
     bool do_reuse = reusable_across_network;
-    GPU_DEBUG_GET_INSTANCE(debug_config);
-    GPU_DEBUG_IF(debug_config->disable_memory_reuse) {
+    GPU_DEBUG_IF(_config.get_disable_memory_reuse()) {
         do_reuse = false;
     }
     if (do_reuse) {
@@ -316,7 +311,7 @@ memory::ptr memory_pool::get_memory(const layout& layout,
             // images (reuse not yet implemented)
             auto mem = alloc_memory(layout, type, reset);
 #ifdef GPU_DEBUG_CONFIG
-            GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+            GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                 auto allocated_mem_size = mem->size();
                 _no_reusable_mems.push_back(
                                         memory_record({{MEM_USER(unique_id, network_id, prim_id, allocated_mem_size)}}, mem, network_id, type));
@@ -330,7 +325,7 @@ memory::ptr memory_pool::get_memory(const layout& layout,
     } else {
         auto mem = alloc_memory(layout, type, reset);
 #ifdef GPU_DEBUG_CONFIG
-        GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+        GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
             auto allocated_mem_size = mem->size();
             _no_reusable_mems.push_back(
                                     memory_record({{MEM_USER(unique_id, network_id, prim_id, allocated_mem_size)}}, mem, network_id, type));
@@ -344,7 +339,6 @@ memory::ptr memory_pool::get_memory(const layout& layout,
 }
 
 void memory_pool::clear_pool_for_network(uint32_t network_id) {
-    GPU_DEBUG_GET_INSTANCE(debug_config);
     // free up _non_padded_pool for this network
     {
         auto itr = _non_padded_pool.begin();
@@ -354,7 +348,7 @@ void memory_pool::clear_pool_for_network(uint32_t network_id) {
 
             if (record._network_id == network_id) {
 #ifdef GPU_DEBUG_CONFIG
-                GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+                GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                     auto released_mem_size = itr->first;
                     total_mem_size_non_padded_pool -= released_mem_size;
                     if (record._type == allocation_type::usm_host)
@@ -388,7 +382,7 @@ void memory_pool::clear_pool_for_network(uint32_t network_id) {
 
             if (list.empty()) {
 #ifdef GPU_DEBUG_CONFIG
-                GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+                GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                     auto released_mem_size = itr->first.bytes_count();
                     total_mem_size_padded_pool -= released_mem_size;
                     if (type == allocation_type::usm_host)
@@ -404,12 +398,12 @@ void memory_pool::clear_pool_for_network(uint32_t network_id) {
 
 #ifdef GPU_DEBUG_CONFIG
     // free up _no_reusable_mems for this network
-    GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+    GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
         auto itr = _no_reusable_mems.begin();
         while (itr != _no_reusable_mems.end()) {
             auto& record = *itr;
             if (itr->_network_id == network_id) {
-                GPU_DEBUG_IF(debug_config->dump_memory_pool) {
+                GPU_DEBUG_IF(_config.get_dump_memory_pool()) {
                     auto released_mem_size = itr->_users.begin()->_mem_size;
                     total_mem_size_no_reusable -= released_mem_size;
                     if (record._type == allocation_type::usm_host)
@@ -439,7 +433,9 @@ void memory_pool::clear_pool_for_network(uint32_t network_id) {
     }
 }
 
-memory_pool::memory_pool(engine& engine) : _engine(&engine) { }
+memory_pool::memory_pool(engine& engine, const ExecutionConfig& config) : _engine(&engine), _config(config) {
+    (void)(_config); // Silence unused warning
+}
 
 #ifdef GPU_DEBUG_CONFIG
 inline std::string get_mb_size(size_t size) {
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp
index 6e2e15fadd43ff..f6a6ee00469427 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_device.cpp
@@ -295,9 +295,6 @@ device_info init_device_info(const cl::Device& device, const cl::Context& contex
         GPU_DEBUG_INFO << "GPU version: "
             << static_cast<int>(info.gfx_ver.major) << "." << static_cast<int>(info.gfx_ver.minor) << "." << static_cast<int>(info.gfx_ver.revision)
             << (info.has_separate_cache ? " with separate cache" : "") << std::endl;
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-        GPU_DEBUG_IF(debug_config->disable_onednn)
-            info.supports_immad = false;
     } else if (nv_device_attr_supported) {
         info.gfx_ver = {static_cast<uint16_t>(device.getInfo<CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV>()),
                         static_cast<uint8_t>(device.getInfo<CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV>()),
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_engine.cpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_engine.cpp
index 11fab0106bff83..d4c0e0e46b281d 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_engine.cpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_engine.cpp
@@ -64,7 +64,7 @@ void ocl_engine::create_onednn_engine(const ExecutionConfig& config) {
         auto casted = std::dynamic_pointer_cast<ocl_device>(_device);
         OPENVINO_ASSERT(casted, "[GPU] Invalid device type stored in ocl_engine");
 
-        std::string cache_dir = config.get_property(ov::cache_dir);
+        const auto& cache_dir = config.get_cache_dir();
         if (cache_dir.empty()) {
             _onednn_engine = std::make_shared<dnnl::engine>(dnnl::ocl_interop::make_engine(casted->get_device().get(), casted->get_context().get()));
         } else {
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_event.cpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_event.cpp
index dbf2a01aa4eadf..d722b5f3bc1bfd 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_event.cpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_event.cpp
@@ -219,16 +219,6 @@ bool ocl_events::get_profiling_info_impl(std::list<instrumentation::profiling_in
             sum += (duration.second - duration.first);
         }
 
-        GPU_DEBUG_GET_INSTANCE(debug_config);
-        GPU_DEBUG_IF(debug_config->print_multi_kernel_perf) {
-            if (period.stage == instrumentation::profiling_stage::executing) {
-                GPU_DEBUG_TRACE << "Multi-kernel time: ";
-                for (auto& duration : all_durations[period.stage])
-                    GPU_DEBUG_TRACE << "  " << (duration.second - duration.first) / 1000;
-                GPU_DEBUG_TRACE << " Total " << sum / 1000 << std::endl;
-            }
-        }
-
         info.push_back(get_profiling_interval(period.stage, 0, sum));
     }
 
diff --git a/src/plugins/intel_gpu/src/runtime/ocl/ocl_stream.cpp b/src/plugins/intel_gpu/src/runtime/ocl/ocl_stream.cpp
index e227c94c7dc06d..bc01a8174292e4 100644
--- a/src/plugins/intel_gpu/src/runtime/ocl/ocl_stream.cpp
+++ b/src/plugins/intel_gpu/src/runtime/ocl/ocl_stream.cpp
@@ -189,22 +189,22 @@ void set_arguments_impl(ocl_kernel_type& kernel,
 }  // namespace
 
 ocl_stream::ocl_stream(const ocl_engine &engine, const ExecutionConfig& config)
-    : stream(config.get_property(ov::intel_gpu::queue_type), stream::get_expected_sync_method(config))
+    : stream(config.get_queue_type(), stream::get_expected_sync_method(config))
     , _engine(engine) {
     auto context = engine.get_cl_context();
     auto device = engine.get_cl_device();
     ocl::command_queues_builder queue_builder;
-    queue_builder.set_profiling(config.get_property(ov::enable_profiling));
+    queue_builder.set_profiling(config.get_enable_profiling());
     queue_builder.set_out_of_order(m_queue_type == QueueTypes::out_of_order);
 
     OPENVINO_ASSERT(m_sync_method != SyncMethods::none || m_queue_type == QueueTypes::in_order,
                     "[GPU] Unexpected sync method (none) is specified for out_of_order queue");
 
     bool priorty_extensions = engine.extension_supported("cl_khr_priority_hints") && engine.extension_supported("cl_khr_create_command_queue");
-    queue_builder.set_priority_mode(config.get_property(ov::intel_gpu::hint::queue_priority), priorty_extensions);
+    queue_builder.set_priority_mode(config.get_queue_priority(), priorty_extensions);
 
     bool throttle_extensions = engine.extension_supported("cl_khr_throttle_hints") && engine.extension_supported("cl_khr_create_command_queue");
-    queue_builder.set_throttle_mode(config.get_property(ov::intel_gpu::hint::queue_throttle), throttle_extensions);
+    queue_builder.set_throttle_mode(config.get_queue_throttle(), throttle_extensions);
 
     bool queue_families_extension = engine.get_device_info().supports_queue_families;
     queue_builder.set_supports_queue_families(queue_families_extension);
diff --git a/src/plugins/intel_gpu/src/runtime/shape_predictor.cpp b/src/plugins/intel_gpu/src/runtime/shape_predictor.cpp
index 3b925f07361fff..3a028218a3f62f 100644
--- a/src/plugins/intel_gpu/src/runtime/shape_predictor.cpp
+++ b/src/plugins/intel_gpu/src/runtime/shape_predictor.cpp
@@ -67,7 +67,7 @@ std::pair<bool, ov::Shape> ShapePredictor::predict_preallocation_shape(const std
                                                                        int32_t custom_prealloc_dim) {
     size_t next_iters_prealloc_count = custom_next_iters_prealloc_count > 0
                                            ? static_cast<size_t>(custom_next_iters_prealloc_count)
-                                           : _next_iters_preallocation_count;
+                                           : _settings.next_iters_preallocation_count;
     const auto& current_shape = layout.get_shape();
     auto dt_bitwidth = ov::element::Type(layout.data_type).bitwidth();
 
@@ -122,7 +122,7 @@ std::pair<bool, ov::Shape> ShapePredictor::predict_preallocation_shape(const std
         // to avoid huge unexpected memory preallocations
         if (can_use_iterations_preallocation) {
             for (size_t i = 0; i < diffs[0].size(); ++i) {
-                if (diffs[0][i] > _max_per_dim_diff) {
+                if (diffs[0][i] > _settings.max_per_dim_diff) {
                     can_use_iterations_preallocation = false;
                     break;
                 }
@@ -132,7 +132,7 @@ std::pair<bool, ov::Shape> ShapePredictor::predict_preallocation_shape(const std
             for (size_t i = 0; i < current_shape.size(); ++i)
                 single_iter_shape.push_back(diffs[0][i] == 0 ? current_shape[i] : 1);
 
-            if (ceil_div(ov::shape_size(single_iter_shape) * dt_bitwidth, 8) > _max_per_iter_size)
+            if (ceil_div(ov::shape_size(single_iter_shape) * dt_bitwidth, 8) > _settings.max_per_iter_size)
                 can_use_iterations_preallocation = false;
         }
 
@@ -142,13 +142,13 @@ std::pair<bool, ov::Shape> ShapePredictor::predict_preallocation_shape(const std
             auto preallocation_shape = diffs[0] * mul_shape;
             auto new_shape = current_shape + preallocation_shape;
             return {true, new_shape};
-        } else if (_buffers_preallocation_ratio > 1.0f) {
+        } else if (_settings.buffers_preallocation_ratio > 1.0f) {
             if (format::is_blocked(layout.format))
                 return {false, {}};
             // Apply percentage buffer preallocation
             auto current_shape_size = ov::shape_size(current_shape);
             ov::Shape new_shape_size(current_shape.size(), 1);
-            new_shape_size[0] = static_cast<size_t>(current_shape_size * _buffers_preallocation_ratio);
+            new_shape_size[0] = static_cast<size_t>(current_shape_size * _settings.buffers_preallocation_ratio);
             return {true, new_shape_size};
         }
     }
diff --git a/src/plugins/intel_gpu/src/runtime/stream.cpp b/src/plugins/intel_gpu/src/runtime/stream.cpp
index 0516a551f19177..913d84d8f476f5 100644
--- a/src/plugins/intel_gpu/src/runtime/stream.cpp
+++ b/src/plugins/intel_gpu/src/runtime/stream.cpp
@@ -20,8 +20,8 @@ QueueTypes stream::detect_queue_type(engine_types engine_type, void* queue_handl
 }
 
 SyncMethods stream::get_expected_sync_method(const ExecutionConfig& config) {
-    auto profiling = config.get_property(ov::enable_profiling);
-    auto queue_type = config.get_property(ov::intel_gpu::queue_type);
+    auto profiling = config.get_enable_profiling();
+    auto queue_type = config.get_queue_type();
     return profiling ? SyncMethods::events : queue_type == QueueTypes::out_of_order ? SyncMethods::barriers
                                                                                     : SyncMethods::none;
 }
diff --git a/src/plugins/intel_gpu/tests/functional/concurrency/gpu_reservation_test.cpp b/src/plugins/intel_gpu/tests/functional/concurrency/gpu_reservation_test.cpp
index fb9711e7605859..c78b472b9c54cb 100644
--- a/src/plugins/intel_gpu/tests/functional/concurrency/gpu_reservation_test.cpp
+++ b/src/plugins/intel_gpu/tests/functional/concurrency/gpu_reservation_test.cpp
@@ -28,6 +28,10 @@ TEST_F(GpuReservationTest, Mutiple_CompiledModel_Reservation) {
     models.emplace_back(ov::test::utils::make_multi_single_conv());
 
     auto core = ov::test::utils::PluginCache::get().core();
+
+    auto available_devices = core->get_available_devices();
+    if (std::find(available_devices.begin(), available_devices.end(), ov::test::utils::DEVICE_CPU) == available_devices.end())
+        GTEST_SKIP();
     core->set_property(target_devices[1], config);
 
     ov::AnyMap property_config = {{ov::num_streams.name(), 1},
@@ -54,4 +58,4 @@ TEST_F(GpuReservationTest, Mutiple_CompiledModel_Reservation) {
         if (thread.joinable())
             thread.join();
     }
-}
\ No newline at end of file
+}
diff --git a/src/plugins/intel_gpu/tests/unit/fusions/convolution_fusion_test.cpp b/src/plugins/intel_gpu/tests/unit/fusions/convolution_fusion_test.cpp
index 6d8f231b93576a..6fb20181eb1936 100644
--- a/src/plugins/intel_gpu/tests/unit/fusions/convolution_fusion_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/fusions/convolution_fusion_test.cpp
@@ -318,7 +318,7 @@ class WeightsPrimitiveFusingTestOneDNN : public BaseFusingTest<convolution_test_
 
         auto input_prim = p.data_type == data_types::u8 ? get_mem(get_input_layout(p), 0, 10) : get_mem(get_input_layout(p));
 
-        auto impl_forcing = cfg_fused.get_property(ov::intel_gpu::force_implementations);
+        auto impl_forcing = cfg_fused.get_force_implementations();
 
         ov::intel_gpu::ImplementationDesc conv_impl = { format::any, "", impl_types::onednn };
 
diff --git a/src/plugins/intel_gpu/tests/unit/fusions/fully_connected_fusion_test.cpp b/src/plugins/intel_gpu/tests/unit/fusions/fully_connected_fusion_test.cpp
index 1540709023a4a9..f85cfa0607a0dd 100644
--- a/src/plugins/intel_gpu/tests/unit/fusions/fully_connected_fusion_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/fusions/fully_connected_fusion_test.cpp
@@ -96,7 +96,7 @@ class FullyConnectedFusingTestOneDNN : public BaseFusingTest<fully_connected_tes
 
         auto input_prim = p.data_type == data_types::u8 ? get_mem(get_input_layout(p), 0, 10) : get_mem(get_input_layout(p), -1, 1);
 
-        auto impl_forcing = cfg_fused.get_property(ov::intel_gpu::force_implementations);
+        auto impl_forcing = cfg_fused.get_force_implementations();
         auto forcing_format = p.input_format;
         for (auto& forcing : impl_forcing)
             if (forcing.first == "fc_prim")
@@ -1007,13 +1007,13 @@ class fc_fp16_fuse_bias_and_find_eltwise_4d : public FullyConnectedFusingTest {
     void run_test() {
         auto p = GetParam();
         auto test_input_layout = get_input_layout(p);
-        auto in_layout = layout{ ov::PartialShape::dynamic(test_input_layout.get_partial_shape().size()), 
-                                 test_input_layout.data_type, 
+        auto in_layout = layout{ ov::PartialShape::dynamic(test_input_layout.get_partial_shape().size()),
+                                 test_input_layout.data_type,
                                  test_input_layout.format };
         auto data_layout = layout{ p.out_shape, p.default_type, p.default_format };
         auto weight = layout{ { 29, 512 }, data_types::f16, format::bfyx };
         auto bias = layout{ { 1, 1, 1, 29 }, data_types::f16, format::bfyx };
-        
+
         create_topologies(
             input_layout("input", in_layout),
             data("weights", get_mem(get_weights_layout(p))),
diff --git a/src/plugins/intel_gpu/tests/unit/fusions/gemm_fusion_test.cpp b/src/plugins/intel_gpu/tests/unit/fusions/gemm_fusion_test.cpp
index cfde721efc2ae3..5f88a5e41f823c 100644
--- a/src/plugins/intel_gpu/tests/unit/fusions/gemm_fusion_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/fusions/gemm_fusion_test.cpp
@@ -336,7 +336,6 @@ TEST_P(gemm_2in_add, eltwise_postop_dynamic) {
     if (engine.get_device_info().supports_immad) {
         ov::intel_gpu::ImplementationDesc gemmv_impl = { cldnn::format::type::any, "", impl_types::onednn };
         cfg_fused.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ { "gemm_prim", gemmv_impl } }));
-        cfg_fused.set_property(ov::intel_gpu::use_only_static_kernels_for_dynamic_shape(true));
     }
 
     auto add_data_layout = get_output_layout(p);
@@ -434,7 +433,6 @@ TEST_P(gemm_2in_add, eltwise_postop_scalar_dynamic) {
     if (engine.get_device_info().supports_immad) {
         ov::intel_gpu::ImplementationDesc gemmv_impl = { cldnn::format::type::any, "", impl_types::onednn };
         cfg_fused.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ { "gemm_prim", gemmv_impl } }));
-        cfg_fused.set_property(ov::intel_gpu::use_only_static_kernels_for_dynamic_shape(true));
     }
 
     auto add_data_layout = get_output_layout(p);
diff --git a/src/plugins/intel_gpu/tests/unit/fusions/loop_fusion_test.cpp b/src/plugins/intel_gpu/tests/unit/fusions/loop_fusion_test.cpp
index 1fbd1c096e7c6e..0b8c1b153c8f5d 100644
--- a/src/plugins/intel_gpu/tests/unit/fusions/loop_fusion_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/fusions/loop_fusion_test.cpp
@@ -55,7 +55,6 @@ program::ptr build_program(engine& engine,
     ExecutionConfig config = get_test_default_config(engine);
     config.set_property(ov::intel_gpu::optimize_data(true));
     config.set_property(ov::intel_gpu::custom_outputs(output_names_vec));
-    config.set_property(ov::intel_gpu::max_dynamic_batch(1));
 
     return program::build_program(engine, body_topology, config, false, false, true);
 }
diff --git a/src/plugins/intel_gpu/tests/unit/module_tests/graph_manipulation_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/module_tests/graph_manipulation_gpu_test.cpp
index ef377b82de9cd9..0cc25b0659f8d6 100644
--- a/src/plugins/intel_gpu/tests/unit/module_tests/graph_manipulation_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/module_tests/graph_manipulation_gpu_test.cpp
@@ -184,7 +184,7 @@ TEST(processing_order, bfs_order_restoring) {
     ExecutionConfig config = get_test_default_config(engine);
     config.set_property(ov::intel_gpu::optimize_data(true));
 
-    if (config.get_property(ov::intel_gpu::queue_type) != QueueTypes::out_of_order)
+    if (config.get_queue_type() != QueueTypes::out_of_order)
         GTEST_SKIP();
 
     auto input = engine.allocate_memory({ data_types::f32, format::bfyx, { 1, 3, 8, 8 } });
diff --git a/src/plugins/intel_gpu/tests/unit/module_tests/shape_predictor_test.cpp b/src/plugins/intel_gpu/tests/unit/module_tests/shape_predictor_test.cpp
index 637add35fd4fd8..6d4b8fd7388e76 100644
--- a/src/plugins/intel_gpu/tests/unit/module_tests/shape_predictor_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/module_tests/shape_predictor_test.cpp
@@ -23,7 +23,9 @@ TEST_P(shape_predictor_tests, prediction) {
     auto& expected_predicted_shape = p.expected_predicted_shape;
     auto& engine = get_test_engine();
 
-    ShapePredictor sp(&engine, p.buffers_preallocation_ratio);
+    ShapePredictor::Settings settings;
+    settings.buffers_preallocation_ratio = p.buffers_preallocation_ratio;
+    ShapePredictor sp(&engine, settings);
     std::pair<bool, ov::Shape> result;
 
     for (auto& shape : in_shapes)
@@ -74,7 +76,9 @@ TEST_P(shape_predictor_tests_b_fs_yx_fsv16, prediction) {
     auto& expected_predicted_shape = p.expected_predicted_shape;
     auto& engine = get_test_engine();
 
-    ShapePredictor sp(&engine, p.buffers_preallocation_ratio);
+    ShapePredictor::Settings settings;
+    settings.buffers_preallocation_ratio = p.buffers_preallocation_ratio;
+    ShapePredictor sp(&engine, settings);
     std::pair<bool, ov::Shape> result;
 
     for (auto& shape : in_shapes)
@@ -121,8 +125,10 @@ INSTANTIATE_TEST_SUITE_P(smoke, shape_predictor_tests_b_fs_yx_fsv16,
 TEST(shape_predictor_tests, check_max_buffer_size) {
     auto& engine = get_test_engine();
 
-    const auto& buffers_preallocation_ratio = 1.1;
-    ShapePredictor sp(&engine, buffers_preallocation_ratio);
+    const auto& buffers_preallocation_ratio = 1.1f;
+    ShapePredictor::Settings settings;
+    settings.buffers_preallocation_ratio = buffers_preallocation_ratio;
+    ShapePredictor sp(&engine, settings);
 
     const auto max_alloc_mem_size = engine.get_device_info().max_alloc_mem_size;
     auto layout = cldnn::layout({static_cast<int64_t>(max_alloc_mem_size)}, ov::element::u8, format::bfyx);
diff --git a/src/plugins/intel_gpu/tests/unit/passes/prepare_primitive_fusing_test.cpp b/src/plugins/intel_gpu/tests/unit/passes/prepare_primitive_fusing_test.cpp
index cd400128a55234..3ef21c0288f0c8 100644
--- a/src/plugins/intel_gpu/tests/unit/passes/prepare_primitive_fusing_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/passes/prepare_primitive_fusing_test.cpp
@@ -525,7 +525,7 @@ TEST(prepare_primitive_fusing, fuse_constant_transposes_removal_check) {
 
     auto prog = program::build_program(engine, topology, config, false, true);
 
-    prog->get_layout_optimizer().set_implementation_forcing(config.get_property(ov::intel_gpu::force_implementations));
+    prog->get_layout_optimizer().set_implementation_forcing(config.get_force_implementations());
     program_wrapper::apply_opt_pass<prepare_primitive_fusing>(*prog);
 
     ASSERT_TRUE(!has_node(*prog, "permute"));
diff --git a/src/plugins/intel_gpu/tests/unit/passes/remove_redundant_reorders_tests.cpp b/src/plugins/intel_gpu/tests/unit/passes/remove_redundant_reorders_tests.cpp
index 1fbeab7e67ac2d..b46033f15d77db 100644
--- a/src/plugins/intel_gpu/tests/unit/passes/remove_redundant_reorders_tests.cpp
+++ b/src/plugins/intel_gpu/tests/unit/passes/remove_redundant_reorders_tests.cpp
@@ -136,7 +136,7 @@ TEST(remove_redundant_reorders, skip_reorder_fusing_when_sibling_not_support_pad
     auto prog = program::build_program(engine, topology, config, false, true);
     config.set_property(ov::intel_gpu::optimize_data(true));
 
-    bool optimize_data = config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = config.get_optimize_data();
     program_wrapper::apply_opt_pass<remove_redundant_reorders>(*prog, optimize_data);
 
     ASSERT_NE(prog, nullptr);
@@ -165,7 +165,7 @@ TEST(remove_redundant_reorders, not_to_fuse_reshape_with_fused_prims) {
     auto prog = program::build_program(engine, topology, config, false, true);
 
     program_wrapper::apply_opt_pass<prepare_primitive_fusing>(*prog);
-    bool optimize_data = config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = config.get_optimize_data();
     program_wrapper::apply_opt_pass<remove_redundant_reorders>(*prog, optimize_data);
 
     ASSERT_NE(prog, nullptr);
@@ -204,7 +204,7 @@ TEST(remove_redundant_reorders, not_to_fuse_permute) {
     auto prog = program::build_program(engine, topology, config, false, true);
     ASSERT_NE(prog, nullptr);
 
-    bool opt_data = config.get_property(ov::intel_gpu::optimize_data);
+    bool opt_data = config.get_optimize_data();
 
     program_wrapper::apply_opt_pass<prepare_primitive_fusing>(*prog);
     program_wrapper::apply_opt_pass<remove_redundant_reorders>(*prog, opt_data);
@@ -266,7 +266,7 @@ TEST(remove_redundant_reorders, remove_fused) {
     auto prog = program::build_program(engine, topology, config, false, true);
 
     program_wrapper::apply_opt_pass<prepare_primitive_fusing>(*prog);
-    bool optimize_data = config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = config.get_optimize_data();
     program_wrapper::apply_opt_pass<remove_redundant_reorders>(*prog, optimize_data);
 
     ASSERT_NE(prog, nullptr);
@@ -293,7 +293,7 @@ TEST(remove_redundant_reorders, fuse_reorder_to_prev_mvn_dyn) {
     config.set_property(ov::intel_gpu::optimize_data(true));
     auto prog = program::build_program(engine, topology, config, false, true);
 
-    bool optimize_data = config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = config.get_optimize_data();
     program_wrapper::apply_opt_pass<remove_redundant_reorders>(*prog, optimize_data);
 
     ASSERT_NE(prog, nullptr);
@@ -336,7 +336,7 @@ TEST(remove_redundant_reorders, fuse_reorder_to_prev_concat_dyn) {
     config.set_property(ov::intel_gpu::optimize_data(true));
     auto prog = program::build_program(engine, topology, config, false, true);
 
-    bool optimize_data = config.get_property(ov::intel_gpu::optimize_data);
+    bool optimize_data = config.get_optimize_data();
     program_wrapper::apply_opt_pass<remove_redundant_reorders>(*prog, optimize_data);
 
     ASSERT_NE(prog, nullptr);
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp
index ebcad325112310..f5f8a5a0ba2429 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/concatenation_gpu_test.cpp
@@ -1487,7 +1487,7 @@ struct concat_gpu_4d_implicit : public concat_gpu {
         }
         auto outputs = concat_network->execute();
 
-        bool concat_opt_enabled = config.get_property(ov::intel_gpu::optimize_data);
+        bool concat_opt_enabled = config.get_optimize_data();
         bool concat_opt_result = std::static_pointer_cast<concatenation_inst>(concat_network->get_primitive("concat"))->can_be_optimized();
         EXPECT_EQ(concat_opt_enabled, concat_opt_result);
 
@@ -1707,7 +1707,7 @@ struct concat_gpu_4d_implicit_onednn : public concat_gpu {
         }
         auto outputs = concat_network.execute();
 
-        bool concat_opt_enabled = config.get_property(ov::intel_gpu::optimize_data);
+        bool concat_opt_enabled = config.get_optimize_data();
         bool concat_opt_result = std::static_pointer_cast<concatenation_inst>(concat_network.get_primitive("concat"))->node->can_be_optimized();
         EXPECT_EQ(concat_opt_enabled, concat_opt_result);
 
@@ -1875,7 +1875,7 @@ struct concat_gpu_4d_implicit_mix_types_onednn : public concat_gpu {
         }
         auto outputs = concat_network.execute();
 
-        bool concat_opt_enabled = config.get_property(ov::intel_gpu::optimize_data);
+        bool concat_opt_enabled = config.get_optimize_data();
         bool concat_opt_result = std::static_pointer_cast<concatenation_inst>(concat_network.get_primitive("concat_final"))->node->can_be_optimized();
         EXPECT_EQ(concat_opt_enabled, concat_opt_result);
 
@@ -2022,7 +2022,7 @@ struct concat_gpu_4d_explicit : public concat_gpu {
         }
         auto outputs = concat_network.execute();
 
-        bool concat_opt_enabled = config.get_property(ov::intel_gpu::optimize_data);
+        bool concat_opt_enabled = config.get_optimize_data();
         bool concat_opt_result = std::static_pointer_cast<concatenation_inst>(concat_network.get_primitive("concat"))->node->can_be_optimized();
 
         // If sibling is using onednn impl and batch > 1, the onednn impl cannot process the implicit concat'ed buffer.
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp
index 385c6bf812cd41..3085ece407f3f5 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/crop_gpu_test.cpp
@@ -1316,7 +1316,6 @@ TEST_P(crop_gpu_dynamic, i32_in2x3x2x2_crop_offsets) {
             }
         }
     }
-    config2.set_property(ov::intel_gpu::use_only_static_kernels_for_dynamic_shape(true));
     network network2(engine, topology, config2); // run with static kernel
     network2.set_input_data("input", input);
     auto outputs2 = network2.execute();
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/debug_config_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/debug_config_gpu_test.cpp
index 6a96b694eea1c5..7c08fe85c07eeb 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/debug_config_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/debug_config_gpu_test.cpp
@@ -10,7 +10,7 @@ using namespace ::tests;
 
 TEST(debug_config_test, check_debug_config_off_on_release) {
 #ifdef NDEBUG
-    GPU_DEBUG_GET_INSTANCE(debug_config);
+    auto config = get_test_default_config(get_test_engine());
     GPU_DEBUG_IF(1) {
         GTEST_FAIL();   /* This should be disabled in case of release build */
     }
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/loop_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/loop_gpu_test.cpp
index 4939630fab3c57..fc20272b2dec6b 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/loop_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/loop_gpu_test.cpp
@@ -55,7 +55,6 @@ static program::ptr build_program(engine& engine,
     ExecutionConfig config = get_test_default_config(engine);
     config.set_property(ov::intel_gpu::optimize_data(true));
     config.set_property(ov::intel_gpu::custom_outputs(output_names_vec));
-    config.set_property(ov::intel_gpu::max_dynamic_batch(1));
     config.set_property(ov::intel_gpu::allow_new_shape_infer(allow_new_shape_infer));
 
     return program::build_program(engine, body_topology, config, false, false, true);
@@ -837,7 +836,7 @@ static void test_loop_gpu_multiple_shapes(ov::PartialShape body_input_layout,
         permute("permute1", input_info("input_origin"), {0, 1, 2, 3}),
         concatenation("input1", {input_info("permute1"), input_info("input_origin")}, 0),
         loop("loop",
-             {input_info(actual_iteration_count_id), input_info(initial_condition_id), input_info("input1"), input_info("input2")}, 
+             {input_info(actual_iteration_count_id), input_info(initial_condition_id), input_info("input1"), input_info("input2")},
              body_program, trip_count_id, initial_condition_id, actual_iteration_count_id,
              input_primitive_maps, output_primitive_maps, back_edges,
              num_iterations, body_current_iteration_id, body_execution_condition_id, 2),
@@ -1105,7 +1104,6 @@ static void test_loop_gpu_wo_trip_count_update_primitive_id(ov::PartialShape bod
     auto body_program = build_program(engine, body, body_execution_condition_id, output_primitive_maps, back_edges, true);
 
     auto const_shape = engine.allocate_memory({ov::PartialShape{4}, data_types::i32, format::bfyx});
-    
 
     std::vector<int32_t> body_input_layouts;
     for (size_t i = 0; i < body_input_layout.size(); i++) {
diff --git a/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp b/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp
index 60fc52135f2068..1aaca9f68124fa 100644
--- a/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_cases/reorder_gpu_test.cpp
@@ -1913,7 +1913,7 @@ TEST(reorder_gpu_opt, non_trivial_remove_redundant)
     auto outputs = net.execute();
     auto executed_primitives = net.get_executed_primitives();
 
-    if (config.get_property(ov::intel_gpu::queue_type) != QueueTypes::out_of_order)
+    if (config.get_queue_type() != QueueTypes::out_of_order)
         GTEST_SKIP();
 
     ASSERT_TRUE(executed_primitives.count("in") == 1);
diff --git a/src/plugins/intel_gpu/tests/unit/test_utils/program_wrapper.h b/src/plugins/intel_gpu/tests/unit/test_utils/program_wrapper.h
index 77b519d8e3cf5f..09c081abbb6fe6 100644
--- a/src/plugins/intel_gpu/tests/unit/test_utils/program_wrapper.h
+++ b/src/plugins/intel_gpu/tests/unit/test_utils/program_wrapper.h
@@ -38,7 +38,9 @@ namespace cldnn
             p.prepare_memory_dependencies();
         }
         static void update_configs_properties(program& p, const ov::AnyMap& properties) {
-            p._config.set_property(properties);
+            auto config_copy = p._config.clone();
+            config_copy.set_property(properties);
+            p._config = config_copy;
         }
     };
 
diff --git a/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp b/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp
index 8536813a4481c6..1ef614715e4337 100644
--- a/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp
+++ b/src/plugins/intel_gpu/tests/unit/test_utils/test_utils.cpp
@@ -54,14 +54,14 @@ void generic_test::run_single_test(bool is_caching_test) {
             }
         }
         std::string input_name = "input" + std::to_string(i);
-        if ((i == 0) && generic_params->network_config.get_property(ov::intel_gpu::optimize_data)) {
+        if ((i == 0) && generic_params->network_config.get_optimize_data()) {
             // Add reorder after the first input in case of optimize data flag since it might change the input layout.
             input_name = "input0_init";
         }
 
         // First input is provided to the network as input_layout.
         // Other inputs are provided as input_layout if optimize data flag is off. Otherwise they are provided as data.
-        if ((i == 0) || !generic_params->network_config.get_property(ov::intel_gpu::optimize_data)) {
+        if ((i == 0) || !generic_params->network_config.get_optimize_data()) {
             topology.add(input_layout(input_name, input_mems[i]->get_layout()));
             input_layouts_names.push_back(input_name);
         } else {
@@ -74,7 +74,7 @@ void generic_test::run_single_test(bool is_caching_test) {
         }
     }
 
-    if (generic_params->network_config.get_property(ov::intel_gpu::optimize_data)) {
+    if (generic_params->network_config.get_optimize_data()) {
         // Add reorder after the first input in case of optimize data flag since it might change the input layout.
         topology.add(reorder("input0", input_info("input0_init"), input_mems[0]->get_layout()));
     }

From ad8e7939f909784f18904c24218f79290ee535b3 Mon Sep 17 00:00:00 2001
From: Katarzyna Mitrus <katarzyna.mitrus@intel.com>
Date: Tue, 18 Feb 2025 13:12:41 +0100
Subject: [PATCH 10/20] [Op][Spec] ISTFT-16 specification (#28807)

### Details:
 - ISTFT-16 specification

### Tickets:
 - 159378

---------

Co-authored-by: Mateusz Mikolajczyk <mateusz.mikolajczyk@intel.com>
---
 .../operation-specs/signals/istft-16.rst      | 217 ++++++++++++++++++
 1 file changed, 217 insertions(+)
 create mode 100644 docs/articles_en/documentation/openvino-ir-format/operation-sets/operation-specs/signals/istft-16.rst

diff --git a/docs/articles_en/documentation/openvino-ir-format/operation-sets/operation-specs/signals/istft-16.rst b/docs/articles_en/documentation/openvino-ir-format/operation-sets/operation-specs/signals/istft-16.rst
new file mode 100644
index 00000000000000..872f3303ecade2
--- /dev/null
+++ b/docs/articles_en/documentation/openvino-ir-format/operation-sets/operation-specs/signals/istft-16.rst
@@ -0,0 +1,217 @@
+.. {#openvino_docs_ops_signals_ISTFT_16}
+
+Inverse Short Time Fourier Transformation (ISTFT)
+=================================================
+
+.. meta::
+  :description: Learn about ISTFT-16 - a signal processing operation
+
+**Versioned name**: *ISTFT-16*
+
+**Category**: *Signal processing*
+
+**Short description**: *ISTFT* operation performs Inverse Short-Time Fourier Transform (complex-to-real).
+
+**Detailed description**: *ISTFT* performs Inverse Short-Time Fourier Transform of complex-valued input tensor 
+of shape ``[fft_results, frames, 2]`` or ``[batch, fft_results, frames, 2]``, where:
+
+  * ``batch`` is a batch size dimension
+  * ``frames`` is a number of frames calculated as ``((signal_length - frame_size) / frame_step) + 1`` of the original signal if not centered, or ``(signal_length / frame_step) + 1`` otherwise.
+  * ``fft_results`` is a number calculated as ``(frame_size / 2) + 1`` of the original signal
+  * ``2`` is the last dimension for complex value represented by floating-point values pair (real and imaginary part accordingly)
+
+The output is a restored real-valued signal in a discrete time domain. The shape of the output is 1D ``[signal_length]`` or 2D ``[batch, signal_length]``.
+If the ``signal_length`` is not provided as an input value, it is calculated according to the following rules:
+
+  * ``default_signal_length = (frames - 1) * frame_step`` for ``center == true`` 
+  * ``default_signal_length = (frames - 1) * frame_step + frame_size`` for ``center == false`` 
+
+If the ``signal_length`` input is provided, the number of output values will be adjusted accordingly. 
+  * If ``signal_length > default_signal_length`` the output is padded with zeros at the end.
+  * If ``signal_length < default_signal_length`` any additional generated samples are cut to the ``signal_length`` size.
+
+The ``window_length`` can not be larger than ``frame_size``, but if smaller the window values will be padded with zeros on the left and right side. The size of the left padding is calculated as ``(frame_size - window_length) // 2``, then right padding size is filled to match the ``frame_size``.  
+
+**Attributes**:
+
+* *center*
+
+  * **Description**: Flag that indicates whether padding has been applied to the original signal. It affects output shape, if the ``signal_length`` input is not provided.
+  * **Range of values**:
+
+    * ``false`` - padding has not been applied, default signal length is calculated as ``(frames - 1) * frame_step + frame_size``
+    * ``true`` - padding has been applied, default signal length is calculated as ``(frames - 1) * frame_step``
+  * **Type**: ``boolean``
+  * **Required**: *yes*
+
+* *normalized*
+
+  * **Description**: Flag that indicates whether the input has been normalized. It is needed to correctly restore the signal and denormalize the output. Output of the STFT is divided by ``sqrt(frame_size)``, when normalized.
+  * **Range of values**:
+
+    * ``false`` - input has not been normalized
+    * ``true`` - input has been normalized
+  * **Type**: ``boolean``
+  * **Required**: *yes*
+
+
+**Inputs**
+
+* **1**: ``data`` - Tensor of type *T*, the ISTFT data input (compatible with a result of STFT operation). **Required.**
+
+  * The data input shape can be 3D ``[fft_results, frames, 2]`` or 4D ``[batch, fft_results, frames, 2]``.
+* **2**: ``window`` - Tensor of type *T* and 1D shape ``[window_length]``, specifying the window values applied to restore the signal. The ``window_length`` is required to be equal or smaller than ``frame_size``, if smaller the window will be padded with zeros on the left and right sides. **Required.**
+* **3**: ``frame_size`` - Scalar tensor of type *T_INT* describing the size of a single frame of the signal to be provided as input to FFT. **Required.**
+* **4**: ``frame_step`` - Scalar tensor of type *T_INT* describing the distance (number of samples) between successive frames. **Required.**
+* **5**: ``signal_length`` - Scalar or single element 1D tensor of type *T_INT* describing the desired length of the output signal, if not provided it's calculated accordingly to the rules presented in the detailed description above. **Optional.**
+
+
+**Outputs**
+
+* **1**: ``signal`` - Tensor of type *T* and 1D shape ``[signal_length]`` or 2D shape ``[batch, signal_length]`` with a real valued signal data. **Required.**
+
+**Types**
+
+* *T*: any supported floating-point type.
+
+* *T_INT*: ``int64`` or ``int32``.
+
+
+**Examples**:
+
+*Example 3D input, 1D output signal, center=false, default signal_length:*
+
+.. code-block:: xml
+   :force:
+
+    <layer ... type="ISTFT" ... >
+        <data center="false" ... />
+        <input>
+            <port id="0">
+                <dim>6</dim>
+                <dim>16</dim>
+                <dim>2</dim>
+            </port>
+            <port id="1">
+                <dim>7</dim>
+            </port>
+            <port id="2"></port> <!-- frame_size value: 11 -->
+            <port id="3"></port> <!-- frame_step value: 3 -->
+        </input>
+        <output>
+            <port id="4">
+                <dim>56</dim>
+            </port>
+        </output>
+    </layer>
+
+*Example 4D input, 2D output signal, center=false, default signal_length:*
+
+.. code-block:: xml
+   :force:
+
+    <layer ... type="ISTFT" ... >
+        <data center="false" ... />
+        <input>
+            <port id="0">
+                <dim>4</dim>
+                <dim>6</dim>
+                <dim>16</dim>
+                <dim>2</dim>
+            </port>
+            <port id="1">
+                <dim>7</dim>
+            </port>
+            <port id="2"></port> <!-- frame_size value: 11 -->
+            <port id="3"></port> <!-- frame_step value: 3 -->
+        </input>
+        <output>
+            <port id="4">
+                <dim>4</dim>
+                <dim>56</dim>
+            </port>
+        </output>
+    </layer>
+
+
+*Example 3D input, 1D output signal, center=true, default signal_length:*
+
+.. code-block:: xml
+   :force:
+
+    <layer ... type="ISTFT" ... >
+        <data center="true" ... />
+        <input>
+            <port id="0">
+                <dim>6</dim>
+                <dim>16</dim>
+                <dim>2</dim>
+            </port>
+            <port id="1">
+                <dim>7</dim>
+            </port>
+            <port id="2"></port> <!-- frame_size value: 11 -->
+            <port id="3"></port> <!-- frame_step value: 3 -->
+        </input>
+        <output>
+            <port id="4">
+                <dim>45</dim>
+            </port>
+        </output>
+    </layer>
+
+*Example 4D input, 2D output signal, center=true, default signal_length:*
+
+.. code-block:: xml
+   :force:
+
+    <layer ... type="ISTFT" ... >
+        <data center="true" ... />
+        <input>
+            <port id="0">
+                <dim>4</dim>
+                <dim>6</dim>
+                <dim>16</dim>
+                <dim>2</dim>
+            </port>
+            <port id="1">
+                <dim>7</dim>
+            </port>
+            <port id="2"></port> <!-- frame_size value: 11 -->
+            <port id="3"></port> <!-- frame_step value: 3 -->
+        </input>
+        <output>
+            <port id="4">
+                <dim>4</dim>
+                <dim>45</dim>
+            </port>
+        </output>
+    </layer>
+
+
+*Example 3D input, 1D output signal, center=false, signal_length input provided:*
+
+.. code-block:: xml
+   :force:
+
+    <layer ... type="ISTFT" ... >
+        <data center="false" ... />
+        <input>
+            <port id="0">
+                <dim>6</dim>
+                <dim>16</dim>
+                <dim>2</dim>
+            </port>
+            <port id="1">
+                <dim>7</dim>
+            </port>
+            <port id="2"></port> <!-- frame_size value: 11 -->
+            <port id="3"></port> <!-- frame_step value: 3 -->
+            <port id="4"></port> <!-- signal_length value: 64 -->
+        </input>
+        <output>
+            <port id="5">
+                <dim>64</dim>
+            </port>
+        </output>
+    </layer>

From 3efb13a79685f57a69db3fe50b0b72097220e843 Mon Sep 17 00:00:00 2001
From: Chen Xu <chen.xu@intel.com>
Date: Tue, 18 Feb 2025 21:17:59 +0800
Subject: [PATCH 11/20] Implement 2-step conversion from fp32 to fp8 (#28501)

### Details:
- *Implement reference conversion from fp16 to f8e4m3, and apply 2-step
conversion, i.e., apply fp32->fp16, then fp16->fp8 for conversions from
fp32 to fp8.*

### Tickets:
 - *[CVS-160375](https://jira.devtools.intel.com/browse/CVS-160375)*
---
 src/core/src/type/float8_e4m3.cpp             | 74 +++++++++++--------
 src/core/tests/float8_e4m3.cpp                |  8 +-
 .../single_layer_tests/classes/conversion.cpp | 28 ++++---
 .../skip_tests_config.cpp                     |  2 -
 4 files changed, 65 insertions(+), 47 deletions(-)

diff --git a/src/core/src/type/float8_e4m3.cpp b/src/core/src/type/float8_e4m3.cpp
index a68613836aff45..403a7e232c4196 100644
--- a/src/core/src/type/float8_e4m3.cpp
+++ b/src/core/src/type/float8_e4m3.cpp
@@ -9,6 +9,7 @@
 #include <limits>
 
 #include "openvino/core/type/float_util.hpp"
+#include "openvino/core/type/float16.hpp"
 
 namespace ov {
 
@@ -48,33 +49,40 @@ constexpr uint8_t f8e4m3_e_max = 0x0f;   // f8e4m3 exponent max value
 constexpr uint8_t f8e4m3_m_size = 3;     // f8e4m3 mantissa bits size
 constexpr uint8_t f8e4m3_m_mask = 0x07;  // f8e4m3 mantissa bit mask
 
-uint8_t f32_to_f8e4m3_bits(const float value) {
-    constexpr uint32_t f32_s_mask = 0x80000000;  // f32 sign bit mask
-    constexpr uint32_t f32_e_mask = 0x7F800000;  // f32 exponent bits mask
-    constexpr uint32_t f32_e_bias = 127;         // f32 exponent bias
-    constexpr uint32_t f32_e_size = 8;           // f32 exponent bits size
-    constexpr uint32_t f32_m_mask = 0x007fffff;  // f32 mantissa bits mask
-    constexpr uint32_t f32_m_size = 23;          // f32 mantissa bits size
+uint8_t f16_to_f8e4m3_bits(const float16 value) {
+    constexpr uint16_t f16_s_mask = 0x8000;  // f16 sign bit mask
+    constexpr uint16_t f16_e_mask = 0x7C00;  // f16 exponent bits mask
+    constexpr uint16_t f16_e_bias = 15;      // f16 exponent bias
+    constexpr uint16_t f16_e_size = 5;       // f16 exponent bits size
+    constexpr uint16_t f16_m_mask = 0x03ff;  // f16 mantissa bits mask
+    constexpr uint16_t f16_m_size = 10;      // f16 mantissa bits size
 
-    constexpr uint32_t f8_e_mask = f8e4m3_e_mask << three_bytes_shift;  // f8 exponent bits mask (on u32)
-    constexpr uint32_t f8_m_mask = f8e4m3_m_mask << three_bytes_shift;  // f8 mantissa bits mask (on u32)
-    constexpr uint32_t f8_m_hidden_one_mask = 0x08000000;               // f8 mantissa hidden one bits mask (on u32)
+    constexpr uint8_t byte_shift = 8;
 
-    constexpr uint32_t round_half = 0x01ffffff;  // value for half to even round for f8
-    constexpr uint32_t round_norm = 0x007fffff;  // value for normal round for f8
-    constexpr uint32_t round_even = 0x00800000;  // value for half to even round for f8
-    constexpr uint32_t round_odd = 0x01800000;   // value for an non-half to even round for f8
+    constexpr uint16_t f8_e_mask = f8e4m3_e_mask << byte_shift;  // f8 exponent bits mask (on u16)
+    constexpr uint16_t f8_m_mask = f8e4m3_m_mask << byte_shift;  // f8 mantissa bits mask (on u16)
+    constexpr uint16_t f8_m_hidden_one_mask = 0x0800;            // f8 mantissa hidden one bits mask (on u16)
 
-    const auto input = util::f32_to_u32_bits(value);
-    auto f8_bits = static_cast<uint8_t>((input & f32_s_mask) >> three_bytes_shift);
+    constexpr uint16_t round_half = 0x01ff;  // value for half to even round for f8
+    constexpr uint16_t round_norm = 0x007f;  // value for normal round for f8
+    constexpr uint16_t round_even = 0x0080;  // value for half to even round for f8
+    constexpr uint16_t round_odd = 0x0180;   // value for an non-half to even round for f8
 
-    uint32_t f32_e_field = input & f32_e_mask;
+    // f8 exponent min value for subnormal
+    // For f8_e less than -10, the hidden 1 is shifted beyond rounding bit.
+    // So the 3 bits in mantissa and rounding bit are all 0, the f8 value is always 0.
+    constexpr int16_t f8_e_subnormal_min = -10;
 
-    if (f32_e_field == f32_e_mask) {
+    const uint16_t input = value.to_bits();
+    uint8_t f8_bits = static_cast<uint8_t>((input & f16_s_mask) >> byte_shift);
+
+    uint16_t f16_e_field = input & f16_e_mask;
+
+    if (f16_e_field == f16_e_mask) {
         f8_bits |= (f8e4m3_e_mask | f8e4m3_m_mask);
-    } else if (f32_e_field != 0) {
-        int32_t f8_biased_exp = (f32_e_field >> f32_m_size) - (f32_e_bias - f8e4m3_e_bias);
-        uint32_t fractional = (input & f32_m_mask) << (f32_e_size - f8e4m3_e_size);
+    } else if (f16_e_field != 0) {
+        int16_t f8_biased_exp = (f16_e_field >> f16_m_size) - (f16_e_bias - f8e4m3_e_bias);
+        uint16_t fractional = (input & f16_m_mask) << (f16_e_size - f8e4m3_e_size);
 
         // for normalized values round apply rounding change f8 fractional and biased exponent
         if ((fractional & round_half) == round_odd || (fractional & round_norm) != 0) {
@@ -91,22 +99,24 @@ uint8_t f32_to_f8e4m3_bits(const float value) {
             // Use NAN as this type has no infinity
             f8_bits |= (f8e4m3_e_mask | f8e4m3_m_mask);
         } else if (f8_biased_exp > 0) {
-            f8_bits |= (f8_biased_exp << f8e4m3_m_size) | (fractional >> three_bytes_shift);
+            f8_bits |= (f8_biased_exp << f8e4m3_m_size) | (fractional >> byte_shift);
         } else {
             // Restore the hidden 1 in f8 mantissa for subnormal calculation
-            fractional = f8_m_hidden_one_mask | (input & f32_m_mask) << (f32_e_size - f8e4m3_e_size);
-            // Will any bits be shifted off?
-            int32_t shift = f8_biased_exp < -(f8e4m3_e_max) ? 0 : (1U << (1 - f8_biased_exp));
-            uint32_t sticky = (fractional & (shift - 1)) ? 1 : 0;
-
-            fractional = ((1 + f8_biased_exp) > f8e4m3_e_max) ? 0 : fractional >> (1 - f8_biased_exp);
-            fractional |= sticky;
+            fractional = f8_m_hidden_one_mask | (input & f16_m_mask) << (f16_e_size - f8e4m3_e_size);
+            int16_t f8_exp = f8_biased_exp - f8e4m3_e_bias;
+            int16_t shift = 1 - f8_exp;
+            int16_t sticky_mask = f8_exp < f8_e_subnormal_min ? 0 : ((1 << shift) - 1);
+            uint16_t sticky = (fractional & sticky_mask) ? 1 : 0;
+
+            // Subnormal mantissa has less significant bits for smaller exponent
+            fractional = f8_exp < f8_e_subnormal_min ? 0 : fractional >> (1 - f8_biased_exp);
             // apply rounding
-            if (((fractional & round_half) == round_odd) || ((fractional & round_norm) != 0)) {
+            if (((fractional & round_half) == round_odd && sticky == 0) || (fractional & round_norm) != 0 ||
+                sticky != 0) {
                 fractional += round_even;
             }
 
-            f8_bits |= fractional >> three_bytes_shift;
+            f8_bits |= fractional >> byte_shift;
         }
     }
 
@@ -118,7 +128,7 @@ float8_e4m3::float8_e4m3(const uint32_t sign, const uint32_t biased_exponent, co
     : m_value(((sign & 0x01U) << (f8e4m3_e_size + f8e4m3_m_size)) |
               (biased_exponent & (f8e4m3_e_mask >> f8e4m3_m_size)) << f8e4m3_m_size | (fraction & f8e4m3_m_mask)) {}
 
-float8_e4m3::float8_e4m3(const float value) : m_value{f32_to_f8e4m3_bits(value)} {}
+float8_e4m3::float8_e4m3(const float value) : m_value{f16_to_f8e4m3_bits(static_cast<float16>(value))} {}
 
 float8_e4m3::operator float() const {
     auto f32_bits = util::f32_to_u32_bits(f8_to_float_lut[m_value & (f8e4m3_e_mask | f8e4m3_m_mask)]);
diff --git a/src/core/tests/float8_e4m3.cpp b/src/core/tests/float8_e4m3.cpp
index e8e2b870f936b9..f81da2206b3a5f 100644
--- a/src/core/tests/float8_e4m3.cpp
+++ b/src/core/tests/float8_e4m3.cpp
@@ -162,9 +162,15 @@ TEST(F8E4M3Test, f32_gt_zero_le_f8_half_lowest_subnormal) {
     EXPECT_EQ(f8.to_bits(), 0x00);
 }
 
-TEST(F8E4M3Test, f32_gt_zero_gt_f8_half_lowest_subnormal) {
+TEST(F8E4M3Test, f32_in_f16_format_le_zero_gt_f8_half_lowest_subnormal) {
     const auto f8 = ov::float8_e4m3(0.00097656273283064365387f);
 
+    EXPECT_EQ(f8.to_bits(), 0x00);
+}
+
+TEST(F8E4M3Test, f32_in_f16_format_gt_zero_gt_f8_half_lowest_subnormal) {
+    const auto f8 = ov::float8_e4m3(0.00097751617431640625f);
+
     EXPECT_EQ(f8.to_bits(), 0x01);
 }
 
diff --git a/src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/conversion.cpp b/src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/conversion.cpp
index 295f7ed9d07cd9..510da1e26451c0 100644
--- a/src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/conversion.cpp
+++ b/src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/conversion.cpp
@@ -148,6 +148,11 @@ void ConvertCPULayerTest::SetUp() {
 }
 
 void ConvertCPULayerTest::generate_inputs(const std::vector<ov::Shape>& targetInputStaticShapes) {
+    if (outPrc != ov::element::nf4 && special_value == ov::test::SpecialValue::none) {
+        SubgraphBaseTest::generate_inputs(targetInputStaticShapes);
+        return;
+    }
+
     inputs.clear();
     const auto& funcInputs = function->inputs();
     for (size_t i = 0; i < funcInputs.size(); ++i) {
@@ -162,18 +167,17 @@ void ConvertCPULayerTest::generate_inputs(const std::vector<ov::Shape>& targetIn
         } else {
             tensor = ov::test::utils::create_and_fill_tensor(funcInput.get_element_type(), targetInputStaticShapes[i]);
         }
-        if (special_value != ov::test::SpecialValue::none) {
-            if (inPrc == ov::element::f32) {
-                modify_value<float>(tensor, special_value);
-            } else if (inPrc == ov::element::f16) {
-                modify_value<ov::float16>(tensor, special_value);
-            } else if (inPrc == ov::element::bf16) {
-                modify_value<ov::bfloat16>(tensor, special_value);
-            } else if (inPrc == ov::element::f8e4m3) {
-                modify_value<ov::float8_e4m3>(tensor, special_value);
-            } else if (inPrc == ov::element::f8e5m2) {
-                modify_value<ov::float8_e5m2>(tensor, special_value);
-            }
+
+        if (inPrc == ov::element::f32) {
+            modify_value<float>(tensor, special_value);
+        } else if (inPrc == ov::element::f16) {
+            modify_value<ov::float16>(tensor, special_value);
+        } else if (inPrc == ov::element::bf16) {
+            modify_value<ov::bfloat16>(tensor, special_value);
+        } else if (inPrc == ov::element::f8e4m3) {
+            modify_value<ov::float8_e4m3>(tensor, special_value);
+        } else if (inPrc == ov::element::f8e5m2) {
+            modify_value<ov::float8_e5m2>(tensor, special_value);
         }
 
         inputs.insert({funcInput.get_node_shared_ptr(), tensor});
diff --git a/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp b/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
index fa400a51ad2639..ca8a93e45e2f83 100644
--- a/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
+++ b/src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
@@ -173,8 +173,6 @@ std::vector<std::string> disabledTestPatterns() {
         R"(.*smoke_TopK/TopKLayerTest.Inference.*_k=21_.*_sort=value_modelType=f16_trgDev=CPU.*)",
         // Issue: 121812
         R"(.*ConvertCPULayerTest.*outFmts=(nhwc|nChw8c|nChw16c).*)",
-        // Issue: MFDNN-12917. The oneDNN emitter of conversion from fp32 to fp8 has rounding issue.
-        R"(.*ConvertCPULayerTest.*(\[1.1.1080.1920\]|\(2.17.5.4\))_.*_inputPRC=f32_targetPRC=f8e4m3_.*)",
         // Need to generate sequence exactly in the i64 data type. Enable in scope of i64 enabling.
         R"(.*RandomUniformLayerTestCPU.*OutPrc=i64.*)",
         // Issue: 123815 (Tests are sensintive to available thread count on testing machines)

From 047976e36904b3ce252a789fefdea2134751c7b1 Mon Sep 17 00:00:00 2001
From: Vatsala Shanubhag <vatsala.shanubhag@intel.com>
Date: Tue, 18 Feb 2025 19:07:44 +0530
Subject: [PATCH 12/20] [ONNX] Added FastGelu from com.microsoft domain
 (#28715)

Details:
Microsoft Contrib Operator "FastGelu" for ONNX RT

Tickets:
N/A

---------

Co-authored-by: Georgy Krivoruchko <georgy.krivoruchko@intel.com>
---
 .../src/op/com.microsoft/fast_gelu.cpp        | 52 +++++++++++++++
 .../models/com.microsoft/fast_gelu.prototxt   | 66 +++++++++++++++++++
 .../tests/onnx_import_com_microsoft.in.cpp    | 20 ++++++
 3 files changed, 138 insertions(+)
 create mode 100644 src/frontends/onnx/frontend/src/op/com.microsoft/fast_gelu.cpp
 create mode 100644 src/frontends/onnx/tests/models/com.microsoft/fast_gelu.prototxt

diff --git a/src/frontends/onnx/frontend/src/op/com.microsoft/fast_gelu.cpp b/src/frontends/onnx/frontend/src/op/com.microsoft/fast_gelu.cpp
new file mode 100644
index 00000000000000..d5f5a9049cadcd
--- /dev/null
+++ b/src/frontends/onnx/frontend/src/op/com.microsoft/fast_gelu.cpp
@@ -0,0 +1,52 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "core/operator_set.hpp"
+#include "exceptions.hpp"
+#include "openvino/frontend/exception.hpp"
+#include "openvino/op/add.hpp"
+#include "openvino/op/constant.hpp"
+#include "openvino/op/gelu.hpp"
+#include "utils/common.hpp"
+
+using namespace ov::op;
+
+namespace ov {
+namespace frontend {
+namespace onnx {
+namespace com_microsoft {
+namespace opset_1 {
+
+ov::OutputVector fast_gelu(const ov::frontend::onnx::Node& node) {
+    // Original documentation:
+    // https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#commicrosoftfastgelu
+    common::default_op_checks(node, 1);
+
+    const auto inputs = node.get_ov_inputs();
+    const auto& x = inputs[0];
+
+    CHECK_VALID_NODE(node,
+                     x.get_element_type() == ov::element::f16 || x.get_element_type() == ov::element::f32 ||
+                         x.get_element_type() == ov::element::bf16,
+                     "Unsupported input data type for X, expected FP16, FP32, or BF16 but got: ",
+                     x.get_element_type());
+
+    auto input_with_bias = x;
+
+    if (inputs.size() > 1) {
+        auto& bias = inputs[1];
+        input_with_bias = std::make_shared<v1::Add>(x, bias);
+    }
+
+    const auto approximation_mode = ov::op::GeluApproximationMode::TANH;
+    return {std::make_shared<v7::Gelu>(input_with_bias, approximation_mode)};
+}
+
+ONNX_OP("FastGelu", OPSET_SINCE(1), com_microsoft::opset_1::fast_gelu, MICROSOFT_DOMAIN);
+
+}  // namespace opset_1
+}  // namespace com_microsoft
+}  // namespace onnx
+}  // namespace frontend
+}  // namespace ov
diff --git a/src/frontends/onnx/tests/models/com.microsoft/fast_gelu.prototxt b/src/frontends/onnx/tests/models/com.microsoft/fast_gelu.prototxt
new file mode 100644
index 00000000000000..87938d9ebf3e1c
--- /dev/null
+++ b/src/frontends/onnx/tests/models/com.microsoft/fast_gelu.prototxt
@@ -0,0 +1,66 @@
+ir_version: 7
+producer_name: "OpenVINO ONNX Frontend"
+graph {
+  node {
+    input: "X"
+    input: "bias"
+    output: "Y"
+    op_type: "FastGelu"
+    domain: "com.microsoft"
+  }
+  name: "test_fast_gelu"
+  input {
+    name: "X"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 2
+          }
+          dim {
+            dim_value: 4
+          }
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+  input {
+    name: "bias"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+  output {
+    name: "Y"
+    type {
+      tensor_type {
+        elem_type: 1
+        shape {
+          dim {
+            dim_value: 2
+          }
+          dim {
+            dim_value: 4
+          }
+          dim {
+            dim_value: 3
+          }
+        }
+      }
+    }
+  }
+}
+opset_import {
+  version: 1
+}
diff --git a/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp b/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
index 1324c116804140..09a96ef3a1ee09 100644
--- a/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
+++ b/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
@@ -1683,6 +1683,26 @@ OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_qlinear_mul) {
     test_case.run();
 }
 
+OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_fast_gelu) {
+    const auto model = convert_model("com.microsoft/fast_gelu.onnx");
+    auto test_case = ov::test::TestCase(model, s_device);
+
+    const std::vector<float> X = {0.0f,  0.5f, 1.0f,  -0.5f, -1.0f, 2.0f, 1.5f,  -2.0f, 0.3f,  0.7f, -0.7f, 1.2f,
+                                  -0.3f, 0.8f, -1.5f, 1.1f,  -0.9f, 0.4f, -1.2f, 2.1f,  -0.4f, 0.6f, -1.1f, 1.3f};
+    const std::vector<float> bias = {0.1f, -0.1f, 0.2f};
+
+    const std::vector<float> expected_output = {
+        0.05398275f, 0.2621714f, 1.0615974f,  -0.1378286f, -0.1492447f, 2.1699832f, 1.51072f,     -0.0378f,
+        0.34569725f, 0.6304f,    -0.1696f,    1.2874f,     -0.0841f,    0.53025f,   -0.12675f,    1.0614f,
+        -0.159f,     0.4353f,    -0.1492447f, 1.954764f,   -0.0841f,    0.53025f,   -0.13829723f, 1.39957158f};
+
+    test_case.add_input<float>(Shape{2, 4, 3}, X);
+    test_case.add_input<float>(Shape{3}, bias);
+
+    test_case.add_expected_output<float>(Shape{2, 4, 3}, expected_output);
+    test_case.run_with_tolerance_as_fp(0.0055f);
+}
+
 OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_bias_add) {
     const auto model = convert_model("com.microsoft/bias_add.onnx");
     auto test_case = ov::test::TestCase(model, s_device);

From 68ecdfbd7ee02f12b26d597f70f7c8f7cb7f339a Mon Sep 17 00:00:00 2001
From: bopeng1234 <bo.peng@intel.com>
Date: Tue, 18 Feb 2025 21:38:52 +0800
Subject: [PATCH 13/20] optimize com.microsoft.MatMulNbits operator (#28504)

This PR is doing some optimization work on onnxfrontend
com.microsoft.MatMulNbits operators

with this changes:
1. it disabled const folding with use 75GB for phi3 INT4 model and
200+GB for llama3 INT4 model.
2. it trigger oneDNN matmul primitives, much benefits the GPU
performance

we tested this changes along with another PR #28163 , and confirmed
phi3/llama3 INT4 model run well in LNL.

---------

Co-authored-by: Yu, Zijun <zijun.yu@intel.com>
---
 .../src/op/com.microsoft/matmulnbits.cpp      | 183 +++++++-----------
 1 file changed, 71 insertions(+), 112 deletions(-)

diff --git a/src/frontends/onnx/frontend/src/op/com.microsoft/matmulnbits.cpp b/src/frontends/onnx/frontend/src/op/com.microsoft/matmulnbits.cpp
index 3c71f1c8985187..4b401bbd2f9037 100644
--- a/src/frontends/onnx/frontend/src/op/com.microsoft/matmulnbits.cpp
+++ b/src/frontends/onnx/frontend/src/op/com.microsoft/matmulnbits.cpp
@@ -7,15 +7,13 @@
 #include "exceptions.hpp"
 #include "openvino/frontend/exception.hpp"
 #include "openvino/op/add.hpp"
-#include "openvino/op/broadcast.hpp"
 #include "openvino/op/constant.hpp"
-#include "openvino/op/convert_like.hpp"
+#include "openvino/op/convert.hpp"
 #include "openvino/op/matmul.hpp"
 #include "openvino/op/multiply.hpp"
-#include "openvino/op/shape_of.hpp"
+#include "openvino/op/reshape.hpp"
 #include "openvino/op/slice.hpp"
 #include "openvino/op/subtract.hpp"
-#include "openvino/op/transpose.hpp"
 #include "utils/common.hpp"
 #include "utils/reshape.hpp"
 
@@ -111,6 +109,7 @@ ov::OutputVector matmulnbits(const ov::frontend::onnx::Node& node) {
                          bias.get_partial_shape());
     }
 
+    ov::Output<ov::Node> mm_output;
     {
         const auto b_const = ov::as_type_ptr<v0::Constant>(b_quantized.get_node_shared_ptr());
 
@@ -118,135 +117,95 @@ ov::OutputVector matmulnbits(const ov::frontend::onnx::Node& node) {
         ov::Shape casted_b_shape;
         ov::Output<ov::Node> default_zp;
         // Casting/converting data of source constant.
-        // For further calculations (sub and/or multiply) we need to reshape it from [N][n_blocks_per_col][blob_size *
-        // X] to [N * n_blocks_per_col][blob_size * X] (where X is amount of values in 1 byte) because scale and
-        // zero_point are represented as: ...with shape like: [N * n_blocks_per_col]...
+        // For further calculations (sub and/or multiply) we need to reshape
+        // b -> [N][n_blocks_per_col][block_size]
         switch (bits) {
         case 2:
-            casted_b_shape = ov::Shape{static_cast<size_t>(N * n_blocks_per_col), static_cast<size_t>(blob_size * 4)};
+            casted_b_shape = ov::Shape{static_cast<size_t>(N),
+                                       static_cast<size_t>(n_blocks_per_col),
+                                       static_cast<size_t>(blob_size * 4)};
             casted_b = std::make_shared<v0::Constant>(ov::element::u2, casted_b_shape, b_const->get_data_ptr());
-            if (a.get_element_type() != ov::element::dynamic) {
-                default_zp = std::make_shared<v0::Constant>(a.get_element_type(), Shape{}, 2);
-            } else {
-                default_zp =
-                    std::make_shared<v1::ConvertLike>(a,
-                                                      std::make_shared<v0::Constant>(ov::element::f32, Shape{}, 2.f));
-            }
+            default_zp = std::make_shared<v0::Constant>(ov::element::u2, Shape{1}, 2);
             break;
         case 4:
-            casted_b_shape = ov::Shape{static_cast<size_t>(N * n_blocks_per_col), static_cast<size_t>(blob_size * 2)};
+            casted_b_shape = ov::Shape{static_cast<size_t>(N),
+                                       static_cast<size_t>(n_blocks_per_col),
+                                       static_cast<size_t>(blob_size * 2)};
             casted_b = std::make_shared<v0::Constant>(ov::element::u4, casted_b_shape, b_const->get_data_ptr());
-            if (a.get_element_type() != ov::element::dynamic) {
-                default_zp = std::make_shared<v0::Constant>(a.get_element_type(), Shape{}, 8);
-            } else {
-                default_zp =
-                    std::make_shared<v1::ConvertLike>(a,
-                                                      std::make_shared<v0::Constant>(ov::element::f32, Shape{}, 8.f));
-            }
+            default_zp = std::make_shared<v0::Constant>(ov::element::u4, Shape{1}, 8);
             break;
         case 8:
-            casted_b_shape = ov::Shape{static_cast<size_t>(N * n_blocks_per_col), static_cast<size_t>(blob_size)};
-            casted_b = op::util::reshape(b_const, casted_b_shape);
-            if (a.get_element_type() != ov::element::dynamic) {
-                default_zp = std::make_shared<v0::Constant>(a.get_element_type(), Shape{}, 128);
-            } else {
-                default_zp =
-                    std::make_shared<v1::ConvertLike>(a,
-                                                      std::make_shared<v0::Constant>(ov::element::f32, Shape{}, 128.f));
-            }
+            casted_b_shape = ov::Shape{static_cast<size_t>(N),
+                                       static_cast<size_t>(n_blocks_per_col),
+                                       static_cast<size_t>(blob_size)};
+            casted_b = std::make_shared<v0::Constant>(ov::element::u8, casted_b_shape, b_const->get_data_ptr());
+            default_zp = std::make_shared<v0::Constant>(ov::element::u8, Shape{1}, 128);
             break;
         default:
             FRONT_END_THROW("Unsupported bits count");
             break;
         }
 
+        if (!zero_points.get_node_shared_ptr()) {
+            zero_points = default_zp;
+        } else {
+            // https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#com.microsoft.MatMulNBits
+            // according to the link, zero point are:
+            // Constrain quantized zero point types to uint8/int32/float16/float.
+            // Input zero_points is stored as uint8_t or same as type(A). It has the same packing method as input B
+            zero_points =
+                op::util::reshape(zero_points,
+                                  ov::Shape{static_cast<size_t>(N), static_cast<size_t>(n_blocks_per_col), 1});
+        }
+
         // Possible issue with slice implementation, had to move convertion before slice, instead of slicing uint4
         // TODO: Ticket
-        const auto converted_b = std::make_shared<v1::ConvertLike>(casted_b, a);
+        // Comments: it is still there, so need to convert b to fp16 first.
 
         // TODO: Need to collect performance data in case constant folding is applied. Possible some perf/mem-gap
-
-        // Simple case
-        if (n_blocks_per_col == 1) {
-            // Removing unused items in case block is bigger than column count
-            // For example, if data is (uint8)[1,2,3,4,5,6] then block will be (uint8)[1,2,3,4,5,6,0,0,0,0,0,0,0,0,0,0].
-            // And last zeros are unused.
-            const auto zero_const = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 0);
-            const auto one_const = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 1);
-            const auto elements_const =
-                std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, static_cast<int32_t>(K));
-            const auto axis_const = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 1);
-            const auto slice_b =
-                std::make_shared<v8::Slice>(converted_b, zero_const, elements_const, one_const, axis_const);
-
-            // Transpose matrix
-            const auto transposed_shape =
-                std::make_shared<v0::Constant>(ov::element::i64, Shape{2}, std::vector<int64_t>{1, 0});
-            const auto transposed_b = std::make_shared<v1::Transpose>(slice_b, transposed_shape);
-
-            // If no zero-points provided - we generate default, depends on data size
-            if (!zero_points.get_node_shared_ptr()) {
-                zero_points = default_zp;
-            }
-            const auto sub_b = std::make_shared<v1::Subtract>(transposed_b, zero_points);
-
-            // Scaling
-            const auto scaled_b = std::make_shared<v1::Multiply>(sub_b, scales);
-
-            // Adding bias if required
-            if (!bias.get_node_shared_ptr()) {
-                b = scaled_b;
-            } else {
-                b = std::make_shared<v1::Add>(scaled_b, bias);
-            }
+        // Comments: in this latest code, the const folding is gone, it trigle the oneDNN kernel
+        //           and use u2/u4/u8 weights as the kernel's input, won't do const folding anymore.
+
+        // use fp16 for compute
+
+        // convert b to fp16
+        auto converted_b = std::make_shared<v0::Convert>(casted_b, a.get_element_type());
+        auto converted_zero_points = std::make_shared<v0::Convert>(zero_points, a.get_element_type());
+
+        // sub and scale
+        const auto sub_b = std::make_shared<v1::Subtract>(converted_b, converted_zero_points);
+        const auto scales_fp16 = std::make_shared<v0::Convert>(scales, a.get_element_type());
+        const auto scales_reshaped =
+            op::util::reshape(scales_fp16, ov::Shape{static_cast<size_t>(N), static_cast<size_t>(n_blocks_per_col), 1});
+        const auto scaled_b = std::make_shared<v1::Multiply>(sub_b, scales_reshaped);
+
+        // reshape b to [N, K]
+        auto shape_b = v0::Constant::create(ov::element::i32, ov::Shape{2}, {0, -1});
+        auto reshaped_b = std::make_shared<v1::Reshape>(scaled_b, shape_b, true);
+
+        // if n_blocks_per_col*blob_size*X != K
+        // need slice it to K
+        // to produce b = [N, K]
+        const bool slice_needed = (K % block_size != 0);
+        if (slice_needed) {
+            const auto zero = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 0);
+            const auto one = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 1);
+            const auto elements = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, static_cast<int32_t>(K));
+            const auto axis = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 1);
+            b = std::make_shared<v8::Slice>(reshaped_b, zero, elements, one, axis);
         } else {
-            // Transpose matrix. Quantized B matrix is transposed and has a shape [N,K].
-            // To apply further operations on it which operand's shape is [N] we do this
-            // transpose to have a matrix [K,N]...
-            const auto transposed_shape =
-                std::make_shared<v0::Constant>(ov::element::i64, Shape{2}, std::vector<int64_t>{1, 0});
-            ov::Output<ov::Node> transposed_b = std::make_shared<v1::Transpose>(converted_b, transposed_shape);
-
-            // If no zero-points provided - we generate default, depends on data size
-            if (!zero_points.get_node_shared_ptr()) {
-                zero_points = default_zp;
-            }
-            const auto sub_b = std::make_shared<v1::Subtract>(transposed_b, zero_points);
-
-            // Scaling
-            const auto scaled_b = std::make_shared<v1::Multiply>(sub_b, scales);
-
-            // Transpose again to make reshaping and slicing
-            transposed_b = std::make_shared<v1::Transpose>(scaled_b, transposed_shape);
-
-            const auto reshaped_b =
-                op::util::reshape(transposed_b,
-                                  ov::Shape{static_cast<size_t>(casted_b_shape[0] / n_blocks_per_col),
-                                            static_cast<size_t>(casted_b_shape[1] * n_blocks_per_col)});
-
-            // Removing unused items in case block is bigger than column count (see description for
-            // Slice above)
-            const auto zero_const = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 0);
-            const auto one_const = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 1);
-            const auto elements_const =
-                std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, static_cast<int32_t>(K));
-            const auto axis_const = std::make_shared<v0::Constant>(ov::element::i32, Shape{1}, 1);
-            const auto slice_b =
-                std::make_shared<v8::Slice>(reshaped_b, zero_const, elements_const, one_const, axis_const);
-
-            // Adding bias if required
-            if (!bias.get_node_shared_ptr()) {
-                return {std::make_shared<v0::MatMul>(a, slice_b, false, true)};
-            } else {
-                // Transpose again
-                transposed_b = std::make_shared<v1::Transpose>(slice_b, transposed_shape);
-
-                b = std::make_shared<v1::Add>(transposed_b, bias);
-            }
+            b = reshaped_b;
         }
+
+        // mm = matmul(a,b)
+        mm_output = std::make_shared<v0::MatMul>(a, b, false, true);
     }
 
-    return {std::make_shared<v0::MatMul>(a, b)};
+    if (bias.get_node_shared_ptr()) {
+        return {std::make_shared<v1::Add>(mm_output, bias)};
+    } else {
+        return {mm_output};
+    }
 }
 
 ONNX_OP("MatMulNBits", OPSET_SINCE(1), com_microsoft::opset_1::matmulnbits, MICROSOFT_DOMAIN);
@@ -255,4 +214,4 @@ ONNX_OP("MatMulNBits", OPSET_SINCE(1), com_microsoft::opset_1::matmulnbits, MICR
 }  // namespace com_microsoft
 }  // namespace onnx
 }  // namespace frontend
-}  // namespace ov
+}  // namespace ov
\ No newline at end of file

From e58f38fac970986077e1961b41298fd79d6a7fb4 Mon Sep 17 00:00:00 2001
From: Vatsala Shanubhag <vatsala.shanubhag@intel.com>
Date: Tue, 18 Feb 2025 21:56:42 +0530
Subject: [PATCH 14/20] [ONNX] Added QLinearAveragePool from com.microsoft
 domain (#28799)

Details:
Microsoft Contrib Operator "QLinearAveragePool" for ONNX RT

Tickets:
N/A

---------

Co-authored-by: Georgy Krivoruchko <georgy.krivoruchko@intel.com>
---
 .../op/com.microsoft/qlinear_activation.cpp   |  50 ++++++--
 .../com.microsoft/qlinear_avg_pool.prototxt   | 117 ++++++++++++++++++
 .../tests/onnx_import_com_microsoft.in.cpp    |  17 +++
 3 files changed, 172 insertions(+), 12 deletions(-)
 create mode 100644 src/frontends/onnx/tests/models/com.microsoft/qlinear_avg_pool.prototxt

diff --git a/src/frontends/onnx/frontend/src/op/com.microsoft/qlinear_activation.cpp b/src/frontends/onnx/frontend/src/op/com.microsoft/qlinear_activation.cpp
index 3702d80c79e0ff..850c24fab2ccc6 100644
--- a/src/frontends/onnx/frontend/src/op/com.microsoft/qlinear_activation.cpp
+++ b/src/frontends/onnx/frontend/src/op/com.microsoft/qlinear_activation.cpp
@@ -6,6 +6,7 @@
 #include "exceptions.hpp"
 #include "openvino/frontend/exception.hpp"
 #include "openvino/op/add.hpp"
+#include "openvino/op/avg_pool.hpp"
 #include "openvino/op/constant.hpp"
 #include "openvino/op/convert.hpp"
 #include "openvino/op/divide.hpp"
@@ -57,21 +58,12 @@ ov::OutputVector qlinear_activation(const ov::frontend::onnx::Node& node, const
 }
 
 ov::OutputVector qlinear_sigmoid(const ov::frontend::onnx::Node& node) {
-    // Original documentation:
-    // https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#commicrosoftqlinearsigmoid
-    // f(x) = quantize(Sigmoid(dequantize(x)))
-
     return qlinear_activation(node, [](const std::shared_ptr<ov::Node>& input_dequantized) {
         return std::make_shared<v0::Sigmoid>(input_dequantized);
     });
 }
 
 ov::OutputVector qlinear_leaky_relu(const ov::frontend::onnx::Node& node) {
-    // Original documentation:
-    // https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#commicrosoftqlinearleakyrelu
-    // f(x) = quantize(alpha * dequantize(x)) for x < 0,
-    //        quantize(dequantize(x)) for x >= 0
-
     return qlinear_activation(node, [&](const std::shared_ptr<ov::Node>& input_dequantized) {
         auto alpha =
             v0::Constant::create(input_dequantized->get_element_type(), {}, {node.get_attribute_value<float>("alpha")});
@@ -80,10 +72,44 @@ ov::OutputVector qlinear_leaky_relu(const ov::frontend::onnx::Node& node) {
     });
 }
 
-namespace {
-ONNX_OP("QLinearSigmoid", OPSET_SINCE(1), com_microsoft::opset_1::qlinear_sigmoid, MICROSOFT_DOMAIN);
+ov::OutputVector qlinear_avg_pool(const ov::frontend::onnx::Node& node) {
+    return qlinear_activation(node, [&](const std::shared_ptr<ov::Node>& input_dequantized) {
+        const auto kernel_shape = node.get_attribute_value<std::vector<int64_t>>("kernel_shape");
+        auto strides = node.get_attribute_value<std::vector<int64_t>>("strides", std::vector<int64_t>{1});
+        auto pads = node.get_attribute_value<std::vector<int64_t>>("pads", std::vector<int64_t>{0});
+        const auto ceil_mode = node.get_attribute_value<int64_t>("ceil_mode", 0);
+        const auto count_include_pad = node.get_attribute_value<int64_t>("count_include_pad", 0);
+        const auto auto_pad = node.get_attribute_value<std::string>("auto_pad", "NOTSET");
+
+        const auto input_rank = input_dequantized->get_shape().size();
+        const size_t num_spatial_dims = input_rank - 2;
+
+        pads.resize(num_spatial_dims * 2, pads.size() == 1 ? pads[0] : 0);
+        strides.resize(num_spatial_dims, strides.size() == 1 ? strides[0] : 1);
+
+        auto avg_pool = std::make_shared<v1::AvgPool>(input_dequantized,
+                                                      Strides(strides.begin(), strides.end()),
+                                                      Shape(pads.begin(), pads.begin() + num_spatial_dims),
+                                                      Shape(pads.begin() + num_spatial_dims, pads.end()),
+                                                      Shape(kernel_shape.begin(), kernel_shape.end()),
+                                                      count_include_pad == 0,
+                                                      ceil_mode != 0 ? RoundingType::CEIL : RoundingType::FLOOR,
+                                                      auto_pad == "SAME_UPPER"   ? PadType::SAME_UPPER
+                                                      : auto_pad == "SAME_LOWER" ? PadType::SAME_LOWER
+                                                                                 : PadType::EXPLICIT);
+
+        return avg_pool;
+    });
 }
-ONNX_OP("QLinearLeakyRelu", OPSET_SINCE(1), com_microsoft::opset_1::qlinear_leaky_relu, MICROSOFT_DOMAIN);
+
+bool register_multiple_operators(void) {
+    ONNX_OP_M("QLinearSigmoid", OPSET_SINCE(1), com_microsoft::opset_1::qlinear_sigmoid, MICROSOFT_DOMAIN);
+    ONNX_OP_M("QLinearLeakyRelu", OPSET_SINCE(1), com_microsoft::opset_1::qlinear_leaky_relu, MICROSOFT_DOMAIN);
+    ONNX_OP_M("QLinearAveragePool", OPSET_SINCE(1), com_microsoft::opset_1::qlinear_avg_pool, MICROSOFT_DOMAIN);
+    return true;
+}
+
+static bool registered = register_multiple_operators();
 
 }  // namespace opset_1
 }  // namespace com_microsoft
diff --git a/src/frontends/onnx/tests/models/com.microsoft/qlinear_avg_pool.prototxt b/src/frontends/onnx/tests/models/com.microsoft/qlinear_avg_pool.prototxt
new file mode 100644
index 00000000000000..e8053b50dfa7d0
--- /dev/null
+++ b/src/frontends/onnx/tests/models/com.microsoft/qlinear_avg_pool.prototxt
@@ -0,0 +1,117 @@
+ir_version: 3
+producer_name: "OpenVINO ONNX Frontend"
+graph {
+  node {
+    input: "A"
+    input: "A_scale"
+    input: "A_zero"
+    input: "B_scale"
+    input: "B_zero"
+    output: "R"
+    name: "test_Qlinear_avg_pool"
+    domain: "com.microsoft"
+    op_type: "QLinearAveragePool"
+    attribute {
+      name: "auto_pad"
+      s: "NOTSET"
+      type: STRING
+    }
+    attribute {
+      name: "ceil_mode"
+      i: 0
+      type: INT
+    }
+    attribute {
+      name: "count_include_pad"
+      i: 0
+      type: INT
+    }
+    attribute {
+      name: "kernel_shape"
+      ints: 7
+      ints: 7
+      type: INTS
+    }
+    attribute {
+      name: "strides"
+      ints: 1
+      ints: 1
+      type: INTS
+    }
+  }
+
+  initializer {
+    data_type: 1
+    float_data: 0.023529412
+    name: "A_scale"
+  }
+
+ initializer {
+    data_type: 2
+    int32_data: 0
+    name: "A_zero"
+  }
+
+  initializer {
+    data_type: 1
+    float_data: 0.01812745
+    name: "B_scale"
+  }
+
+  initializer {
+    data_type: 2
+    int32_data: 0
+    name: "B_zero"
+  }
+
+
+   input {
+    name: "A"
+    type {
+      tensor_type {
+        elem_type: 2
+        shape {
+          dim {
+            dim_value: 1
+          }
+          dim {
+            dim_value: 1
+          }
+          dim {
+            dim_value: 7
+          }
+          dim {
+            dim_value: 7
+          }
+        }
+      }
+    }
+  }
+  
+    output {
+    name: "R"
+    type {
+      tensor_type {
+        elem_type: 2
+        shape {
+          dim {
+            dim_value: 1
+          }
+          dim {
+            dim_value: 1
+          }
+          dim {
+            dim_value: 1
+          }
+          dim {
+            dim_value: 1
+          }
+        }
+      }
+    }
+  }
+}
+opset_import {
+   domain: "com.microsoft"
+  version: 1
+}
\ No newline at end of file
diff --git a/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp b/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
index 09a96ef3a1ee09..170476aae05dd3 100644
--- a/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
+++ b/src/frontends/onnx/tests/onnx_import_com_microsoft.in.cpp
@@ -1577,6 +1577,23 @@ OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_matmul_integer_to_float) {
     test_case.run();
 }
 
+OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_qlinear_avg_pool) {
+    const auto model = convert_model("com.microsoft/qlinear_avg_pool.onnx");
+    auto test_case = ov::test::TestCase(model, s_device);
+
+    const std::vector<uint8_t> data_A = {140, 138, 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, 127,
+                                         126, 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, 115, 114,
+                                         113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103, 102, 101,
+                                         100, 99,  98,  97,  96,  95,  94,  93,  92,  91};
+
+    const std::vector<uint8_t> expected_output = {149};
+
+    test_case.add_input<uint8_t>(Shape{1, 1, 7, 7}, data_A);
+
+    test_case.add_expected_output<uint8_t>(Shape{1, 1, 1, 1}, expected_output);
+    test_case.run();
+}
+
 OPENVINO_TEST(${BACKEND_NAME}, onnx_com_microsoft_qlinearsigmoid) {
     const auto model = convert_model("com.microsoft/q_linear_sigmoid.onnx");
     auto test_case = ov::test::TestCase(model, s_device);

From 18e97b68bf715609d933e843651763bc53d73278 Mon Sep 17 00:00:00 2001
From: Przemyslaw Wysocki <przemyslaw.wysocki@intel.com>
Date: Tue, 18 Feb 2025 17:28:38 +0100
Subject: [PATCH 15/20] Add SegmentMax-16 reference implementation (#29047)

### Details:
- The original PR
(https://github.com/openvinotoolkit/openvino/pull/28788) has been
mistakenly force-merged due to a mistake in merge queue settings. It was
later reverted, so this is the "new" Ref PR.
 - Add reference implementation
 - Add tests

### Related PRs:
 - https://github.com/openvinotoolkit/openvino/pull/28103
 - https://github.com/openvinotoolkit/openvino/pull/28698
 - https://github.com/openvinotoolkit/openvino/pull/28979
 - https://github.com/openvinotoolkit/openvino/pull/28999

### Tickets:
 - CVS-158917

---------

Signed-off-by: p-wysocki <przemyslaw.wysocki@intel.com>
Co-authored-by: Roman Kazantsev <roman.kazantsev@intel.com>
Co-authored-by: Pawel Raasz <pawel.raasz@intel.com>
Co-authored-by: Katarzyna Mitrus <katarzyna.mitrus@intel.com>
---
 .../include/openvino/op/util/attr_types.hpp   |   2 +-
 .../include/openvino/opsets/opset16_tbl.hpp   |   1 +
 .../openvino/reference/segment_max.hpp        |  55 +++++
 .../include/segment_max_shape_inference.hpp   |   7 +-
 src/core/tests/opset.cpp                      |   2 +-
 src/core/tests/type_prop/segment_max.cpp      |  20 +-
 .../template/backend/ops/ops_evaluates.hpp    |   4 +
 .../template/backend/ops/segment_max.cpp      |  80 +++++++
 .../template/backend/opset_int_tbl.hpp        |   1 +
 .../functional/op_reference/segment_max.cpp   | 206 ++++++++++++++++++
 .../src/op_impl_check/single_op_graph.cpp     |   9 +
 11 files changed, 373 insertions(+), 14 deletions(-)
 create mode 100644 src/core/reference/include/openvino/reference/segment_max.hpp
 create mode 100644 src/plugins/template/backend/ops/segment_max.cpp
 create mode 100644 src/plugins/template/tests/functional/op_reference/segment_max.cpp

diff --git a/src/core/include/openvino/op/util/attr_types.hpp b/src/core/include/openvino/op/util/attr_types.hpp
index 5039cf25411dd7..2a33234e1fae3f 100644
--- a/src/core/include/openvino/op/util/attr_types.hpp
+++ b/src/core/include/openvino/op/util/attr_types.hpp
@@ -20,7 +20,7 @@ enum class PadMode { CONSTANT = 0, EDGE, REFLECT, SYMMETRIC };
 OPENVINO_API
 std::ostream& operator<<(std::ostream& s, const PadMode& type);
 
-/// \brief Fill modes for the `SegmentMax` operator.
+/// \brief Fill modes to set default value for operators like `SegmentMax`.
 enum class FillMode { ZERO = 0, LOWEST };
 
 OPENVINO_API
diff --git a/src/core/include/openvino/opsets/opset16_tbl.hpp b/src/core/include/openvino/opsets/opset16_tbl.hpp
index de0b3a9ed958f3..6c19ed12121f24 100644
--- a/src/core/include/openvino/opsets/opset16_tbl.hpp
+++ b/src/core/include/openvino/opsets/opset16_tbl.hpp
@@ -16,3 +16,4 @@ _OPENVINO_OP_REG(ShapeOf, ov::op::v3)
 // New operations added in opset16
 _OPENVINO_OP_REG(Identity, ov::op::v16)
 _OPENVINO_OP_REG(ISTFT, ov::op::v16)
+_OPENVINO_OP_REG(SegmentMax, ov::op::v16)
diff --git a/src/core/reference/include/openvino/reference/segment_max.hpp b/src/core/reference/include/openvino/reference/segment_max.hpp
new file mode 100644
index 00000000000000..3af1ff253c1c0c
--- /dev/null
+++ b/src/core/reference/include/openvino/reference/segment_max.hpp
@@ -0,0 +1,55 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include <algorithm>
+#include <limits>
+#include <vector>
+
+#include "openvino/core/shape.hpp"
+
+namespace ov::reference {
+
+template <typename T, typename T_idx, std::enable_if_t<std::is_same<std::decay_t<T_idx>, int64_t>::value>* = nullptr>
+void segment_max(const T* data,
+                 const Shape& data_shape,
+                 const T_idx* segment_ids,
+                 T* out,
+                 const Shape& output_shape,
+                 const T empty_segment_value) {
+    const T_idx num_segments = output_shape[0];
+    const auto inner_dim_size = shape_size(data_shape.begin() + 1, data_shape.end());
+
+    // Initialize output with empty_segment_value
+    std::fill(out, out + num_segments * inner_dim_size, empty_segment_value);
+
+    // Iterate over each element in the first dimension
+    for (size_t i = 0; i < data_shape[0]; ++i) {
+        const T_idx segment_id = segment_ids[i];
+        if (segment_id >= num_segments) {
+            continue;
+        }
+        // Iterate over each element in the inner dimensions
+        for (size_t j = 0; j < inner_dim_size; ++j) {
+            const size_t index = i * inner_dim_size + j;
+            const size_t out_index = segment_id * inner_dim_size + j;
+            // Update the maximum value for the current segment and inner dimension
+            out[out_index] = std::max(out[out_index], data[index]);
+        }
+    }
+}
+
+template <typename T, typename T_idx, std::enable_if_t<!std::is_same<std::decay_t<T_idx>, int64_t>::value>* = nullptr>
+void segment_max(const T* data,
+                 const Shape& data_shape,
+                 const T_idx* segment_ids,
+                 T* out,
+                 const Shape& output_shape,
+                 const T empty_segment_value) {
+    std::vector<int64_t> segment_ids_int64(segment_ids, segment_ids + data_shape[0]);
+    segment_max(data, data_shape, segment_ids_int64.data(), out, output_shape, empty_segment_value);
+}
+
+}  // namespace ov::reference
diff --git a/src/core/shape_inference/include/segment_max_shape_inference.hpp b/src/core/shape_inference/include/segment_max_shape_inference.hpp
index fac0c4b44599f9..3c365682b11f10 100644
--- a/src/core/shape_inference/include/segment_max_shape_inference.hpp
+++ b/src/core/shape_inference/include/segment_max_shape_inference.hpp
@@ -50,8 +50,11 @@ std::vector<TRShape> shape_infer(const SegmentMax* op,
 
     // validate num_segments input
     const auto num_segments_available = op->inputs().size() == 3;
-    const auto num_segments = num_segments_available ? get_input_const_data_as_shape<TRShape>(op, 2, tensor_accessor)
-                                                     : ov::optional<TRShape>{};
+    ov::optional<TRShape> num_segments;
+    if (num_segments_available) {
+        num_segments = get_input_const_data_as_shape<TRShape>(op, 2, tensor_accessor);
+    }
+
     if (num_segments_available) {
         const auto& num_segments_shape = input_shapes[2];
         NODE_SHAPE_INFER_CHECK(op,
diff --git a/src/core/tests/opset.cpp b/src/core/tests/opset.cpp
index dc24a832560464..3006e04a02f960 100644
--- a/src/core/tests/opset.cpp
+++ b/src/core/tests/opset.cpp
@@ -77,7 +77,7 @@ INSTANTIATE_TEST_SUITE_P(opset,
                                          OpsetTestParams{ov::get_opset13, 186},
                                          OpsetTestParams{ov::get_opset14, 188},
                                          OpsetTestParams{ov::get_opset15, 199},
-                                         OpsetTestParams{ov::get_opset16, 5}),
+                                         OpsetTestParams{ov::get_opset16, 6}),
                          OpsetTestNameGenerator{});
 
 class MyOpOld : public ov::op::Op {
diff --git a/src/core/tests/type_prop/segment_max.cpp b/src/core/tests/type_prop/segment_max.cpp
index a51ee7161e8f0d..cd039b3cfb61f4 100644
--- a/src/core/tests/type_prop/segment_max.cpp
+++ b/src/core/tests/type_prop/segment_max.cpp
@@ -16,6 +16,7 @@
 
 namespace ov::test {
 using op::v0::Constant, op::v0::Parameter, op::v1::Add, op::v1::ReduceMax, op::v1::StridedSlice, op::v3::ShapeOf;
+using testing::HasSubstr;
 
 class TypePropSegmentMaxTest : public TypePropOpTest<op::v16::SegmentMax> {};
 
@@ -69,45 +70,44 @@ TEST_F(TypePropSegmentMaxTest, incorrect_inputs) {
         const auto num_segments_f32 = std::make_shared<Parameter>(element::f32, PartialShape{});
         OV_EXPECT_THROW(std::ignore = make_op(data, segment_ids, num_segments_f32, op::FillMode::LOWEST),
                         ov::NodeValidationFailure,
-                        testing::HasSubstr("The element type of the num_segments input be i32 or i64."));
+                        HasSubstr("The element type of the num_segments input be i32 or i64."));
     }
     {
         const auto segment_ids_f32 = std::make_shared<Parameter>(element::f32, PartialShape{3});
         OV_EXPECT_THROW(std::ignore = make_op(data, segment_ids_f32, num_segments, op::FillMode::LOWEST),
                         ov::NodeValidationFailure,
-                        testing::HasSubstr("The element type of the segment_ids input be i32 or i64."));
+                        HasSubstr("The element type of the segment_ids input be i32 or i64."));
     }
     {
         const auto segment_ids_nd = std::make_shared<Parameter>(element::i32, PartialShape{2, 3});
         OV_EXPECT_THROW(std::ignore = make_op(data, segment_ids_nd, num_segments, op::FillMode::LOWEST),
                         ov::NodeValidationFailure,
-                        testing::HasSubstr("segment_ids must be a 1D input."));
+                        HasSubstr("segment_ids must be a 1D input."));
     }
     {
         const auto num_segments_nd = std::make_shared<Parameter>(element::i32, PartialShape{1});
         OV_EXPECT_THROW(std::ignore = make_op(data, segment_ids, num_segments_nd, op::FillMode::LOWEST),
                         ov::NodeValidationFailure,
-                        testing::HasSubstr("num_segments must be a scalar input."));
+                        HasSubstr("num_segments must be a scalar input."));
     }
     {
         const auto segment_ids_unsorted =
             std::make_shared<Constant>(element::i32, Shape{3}, std::vector<int64_t>{1, 0, 1});
         OV_EXPECT_THROW(std::ignore = make_op(data, segment_ids_unsorted, num_segments, op::FillMode::LOWEST),
                         ov::NodeValidationFailure,
-                        testing::HasSubstr("segment_ids must be sorted."));
+                        HasSubstr("segment_ids must be sorted."));
     }
     {
         const auto data_scalar = std::make_shared<Parameter>(element::i32, PartialShape{});
         OV_EXPECT_THROW(std::ignore = make_op(data_scalar, segment_ids, num_segments, op::FillMode::LOWEST),
                         ov::NodeValidationFailure,
-                        testing::HasSubstr("The data input cannot be a scalar."));
+                        HasSubstr("The data input cannot be a scalar."));
     }
     {
         const auto segment_ids_short = std::make_shared<Constant>(element::i32, Shape{2}, std::vector<int64_t>{1, 0});
-        OV_EXPECT_THROW(
-            std::ignore = make_op(data, segment_ids_short, num_segments, op::FillMode::LOWEST),
-            ov::NodeValidationFailure,
-            testing::HasSubstr("The number of elements in segment_ids must match the first dimension of data."));
+        OV_EXPECT_THROW(std::ignore = make_op(data, segment_ids_short, num_segments, op::FillMode::LOWEST),
+                        ov::NodeValidationFailure,
+                        HasSubstr("The number of elements in segment_ids must match the first dimension of data."));
     }
 }
 
diff --git a/src/plugins/template/backend/ops/ops_evaluates.hpp b/src/plugins/template/backend/ops/ops_evaluates.hpp
index 265967afbadc7b..e4383d08e4c35c 100644
--- a/src/plugins/template/backend/ops/ops_evaluates.hpp
+++ b/src/plugins/template/backend/ops/ops_evaluates.hpp
@@ -558,3 +558,7 @@ extern template bool evaluate_node<ov::op::v15::SearchSorted>(std::shared_ptr<ov
 extern template bool evaluate_node<ov::op::v16::Identity>(std::shared_ptr<ov::Node> node,
                                                           ov::TensorVector& outputs,
                                                           const ov::TensorVector& inputs);
+
+extern template bool evaluate_node<ov::op::v16::SegmentMax>(std::shared_ptr<ov::Node> node,
+                                                            ov::TensorVector& outputs,
+                                                            const ov::TensorVector& inputs);
diff --git a/src/plugins/template/backend/ops/segment_max.cpp b/src/plugins/template/backend/ops/segment_max.cpp
new file mode 100644
index 00000000000000..b286b718830d73
--- /dev/null
+++ b/src/plugins/template/backend/ops/segment_max.cpp
@@ -0,0 +1,80 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "openvino/reference/segment_max.hpp"
+
+#include "element_visitor.hpp"
+#include "evaluate_node.hpp"
+#include "segment_max_shape_inference.hpp"
+
+template <ov::element::Type_t ET_data, ov::element::Type_t ET_idx>
+bool evaluate_index_type(const std::shared_ptr<ov::op::v16::SegmentMax>& op,
+                         ov::TensorVector& outputs,
+                         const ov::TensorVector& inputs) {
+    using T_data = typename ov::element_type_traits<ET_data>::value_type;
+    using T_idx = typename ov::element_type_traits<ET_idx>::value_type;
+    auto input_shapes = std::vector<ov::PartialShape>{op->get_input_shape(0), op->get_input_shape(1)};
+    if (op->inputs().size() == 3) {
+        input_shapes.emplace_back(op->get_input_shape(2));
+    }
+    const auto output_shape =
+        ov::op::v16::shape_infer(op.get(), input_shapes, make_tensor_accessor(inputs)).front().to_shape();
+    outputs.front().set_shape(output_shape);
+    const auto empty_segment_value =
+        op->get_fill_mode() == ov::op::FillMode::ZERO ? T_data(0) : std::numeric_limits<T_data>::lowest();
+    ov::reference::segment_max(inputs[0].data<const T_data>(),
+                               inputs[0].get_shape(),
+                               inputs[1].data<const T_idx>(),
+                               outputs[0].data<T_data>(),
+                               outputs[0].get_shape(),
+                               empty_segment_value);
+    return true;
+}
+
+template <ov::element::Type_t ET_data>
+bool evaluate_data_type(const std::shared_ptr<ov::op::v16::SegmentMax>& op,
+                        ov::TensorVector& outputs,
+                        const ov::TensorVector& inputs) {
+    const auto& index_type = op->get_input_element_type(1);
+    using ov::op::v16::SegmentMax;
+    using namespace ov::element;
+    switch (index_type) {
+    case i32:
+        return evaluate_index_type<ET_data, i32>(ov::as_type_ptr<SegmentMax>(op), outputs, inputs);
+    case i64:
+        return evaluate_index_type<ET_data, i64>(ov::as_type_ptr<SegmentMax>(op), outputs, inputs);
+    default:
+        OPENVINO_THROW("Unhandled index type ", index_type, " in evaluate_node()");
+    }
+}
+
+template <>
+bool evaluate_node<ov::op::v16::SegmentMax>(std::shared_ptr<ov::Node> node,
+                                            ov::TensorVector& outputs,
+                                            const ov::TensorVector& inputs) {
+    const auto& element_type = node->get_output_element_type(0);
+
+    using ov::op::v16::SegmentMax;
+    using namespace ov::element;
+    switch (element_type) {
+    case i8:
+        return evaluate_data_type<i8>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case i32:
+        return evaluate_data_type<i32>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case i64:
+        return evaluate_data_type<i64>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case u8:
+        return evaluate_data_type<u8>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case u32:
+        return evaluate_data_type<u32>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case u64:
+        return evaluate_data_type<u64>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case f16:
+        return evaluate_data_type<f16>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    case f32:
+        return evaluate_data_type<f32>(ov::as_type_ptr<SegmentMax>(node), outputs, inputs);
+    default:
+        OPENVINO_THROW("Unhandled data type ", element_type, " in evaluate_node()");
+    }
+}
diff --git a/src/plugins/template/backend/opset_int_tbl.hpp b/src/plugins/template/backend/opset_int_tbl.hpp
index 4a9ad0b6af1f7a..7486421ba85d9b 100644
--- a/src/plugins/template/backend/opset_int_tbl.hpp
+++ b/src/plugins/template/backend/opset_int_tbl.hpp
@@ -177,6 +177,7 @@ _OPENVINO_OP_REG(SearchSorted, ov::op::v15)
 
 _OPENVINO_OP_REG(Identity, ov::op::v16)
 _OPENVINO_OP_REG(ISTFT, ov::op::v16)
+_OPENVINO_OP_REG(SegmentMax, ov::op::v16)
 
 _OPENVINO_OP_REG(AUGRUCell, ov::op::internal)
 _OPENVINO_OP_REG(AUGRUSequence, ov::op::internal)
diff --git a/src/plugins/template/tests/functional/op_reference/segment_max.cpp b/src/plugins/template/tests/functional/op_reference/segment_max.cpp
new file mode 100644
index 00000000000000..9cb8273c6bccad
--- /dev/null
+++ b/src/plugins/template/tests/functional/op_reference/segment_max.cpp
@@ -0,0 +1,206 @@
+// Copyright (C) 2018-2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "openvino/op/segment_max.hpp"
+
+#include <gtest/gtest.h>
+
+#include "base_reference_test.hpp"
+#include "openvino/core/type/element_type_traits.hpp"
+#include "openvino/op/constant.hpp"
+
+namespace {
+struct SegmentMaxParams {
+    SegmentMaxParams(const reference_tests::Tensor& dataTensor,
+                     const reference_tests::Tensor& segmentIdsTensor,
+                     const reference_tests::Tensor& numSegmentsTensor,
+                     const reference_tests::Tensor& expectedTensor,
+                     const reference_tests::Tensor& expectedTensorNumSegments,
+                     const ov::op::FillMode fillMode)
+        : dataTensor(dataTensor),
+          segmentIdsTensor(segmentIdsTensor),
+          numSegmentsTensor(numSegmentsTensor),
+          expectedTensor(expectedTensor),
+          expectedTensorNumSegments(expectedTensorNumSegments),
+          fillMode(fillMode) {}
+
+    reference_tests::Tensor dataTensor;
+    reference_tests::Tensor segmentIdsTensor;
+    reference_tests::Tensor numSegmentsTensor;
+    reference_tests::Tensor expectedTensor;
+    reference_tests::Tensor expectedTensorNumSegments;
+    ov::op::FillMode fillMode;
+};
+
+class ReferenceSegmentMaxV16LayerTest : public testing::TestWithParam<std::tuple<SegmentMaxParams, bool>>,
+                                        public reference_tests::CommonReferenceTest {
+protected:
+    void SetUp() override {
+        const auto& params = std::get<0>(GetParam());
+        const bool useNumSegments = std::get<1>(GetParam());
+        function = CreateFunction(params, useNumSegments);
+        inputData = {params.dataTensor.data, params.segmentIdsTensor.data};
+        if (useNumSegments) {
+            inputData.push_back(params.numSegmentsTensor.data);
+            refOutData.push_back(params.expectedTensorNumSegments.data);
+        } else {
+            refOutData = {params.expectedTensor.data};
+        }
+    }
+
+public:
+    static std::string getTestCaseName(const testing::TestParamInfo<std::tuple<SegmentMaxParams, bool>>& obj) {
+        auto param = std::get<0>(obj.param);
+        bool useNumSegments = std::get<1>(obj.param);
+        std::ostringstream result;
+        result << "dType=" << param.dataTensor.type;
+        result << "_dShape=" << param.dataTensor.shape;
+        result << "_segmentIdsType=" << param.segmentIdsTensor.type;
+        result << "_segmentIdsValues=" << testing::PrintToString(param.segmentIdsTensor.data);
+        result << "_segmentIdsShape=" << param.segmentIdsTensor.shape;
+        result << "_fillMode=" << param.fillMode;
+        result << "_useNumSegments=" << useNumSegments;
+        return result.str();
+    }
+
+private:
+    static std::shared_ptr<ov::Model> CreateFunction(const SegmentMaxParams& params, bool useNumSegments) {
+        using ov::op::v0::Parameter;
+        const auto data = std::make_shared<Parameter>(params.dataTensor.type, params.dataTensor.shape);
+        const auto segmentIds =
+            std::make_shared<Parameter>(params.segmentIdsTensor.type, params.segmentIdsTensor.shape);
+        std::shared_ptr<ov::op::v16::SegmentMax> segmentMax;
+        ov::ParameterVector parameters = {data, segmentIds};
+        if (useNumSegments) {
+            const auto numSegments =
+                std::make_shared<Parameter>(params.numSegmentsTensor.type, params.numSegmentsTensor.shape);
+            parameters.emplace_back(numSegments);
+            segmentMax = std::make_shared<ov::op::v16::SegmentMax>(data, segmentIds, numSegments, params.fillMode);
+        } else {
+            segmentMax = std::make_shared<ov::op::v16::SegmentMax>(data, segmentIds, params.fillMode);
+        }
+        return std::make_shared<ov::Model>(ov::NodeVector{segmentMax}, parameters);
+    }
+};
+
+TEST_P(ReferenceSegmentMaxV16LayerTest, CompareWithRefs) {
+    Exec();
+}
+
+template <ov::element::Type_t T, ov::element::Type_t T_idx>
+std::vector<SegmentMaxParams> generateSegmentMaxParams(ov::op::FillMode fillMode) {
+    using T_D = typename ov::element_type_traits<T>::value_type;
+    using T_I = typename ov::element_type_traits<T_idx>::value_type;
+    using reference_tests::Tensor;
+    const auto empty_segment_value = fillMode == ov::op::FillMode::ZERO ? T_D(0) : std::numeric_limits<T_D>::lowest();
+    std::vector<SegmentMaxParams> segmentMaxParams{
+        // 1D
+        SegmentMaxParams(Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),                 // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 0, 2, 2}),             // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{3}),                       // numSegments
+                         Tensor({3}, T, std::vector<T_D>{2, empty_segment_value, 4}),  // expectedResult
+                         Tensor({3}, T, std::vector<T_D>{2, empty_segment_value, 4}),  // expectedResultNumSegments
+                         fillMode),
+        // 2D
+        SegmentMaxParams(Tensor({4, 2}, T, std::vector<T_D>{8, 7, 6, 5, 4, 3, 2, 1}),  // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 0, 1, 1}),             // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{2}),                       // numSegments
+                         Tensor({2, 2}, T, std::vector<T_D>{8, 7, 4, 3}),              // expectedResult
+                         Tensor({2, 2}, T, std::vector<T_D>{8, 7, 4, 3}),              // expectedResultNumSegments
+                         fillMode),
+        // 3D
+        SegmentMaxParams(
+            Tensor({4, 2, 2}, T, std::vector<T_D>{1, 2, 3, 4, 5, 6, 7, 8, 16, 15, 14, 13, 12, 11, 10, 9}),  // data
+            Tensor({4}, T_idx, std::vector<T_I>{0, 0, 1, 1}),                    // segmentIds
+            Tensor({}, T_idx, std::vector<T_I>{2}),                              // numSegments
+            Tensor({2, 2, 2}, T, std::vector<T_D>{5, 6, 7, 8, 16, 15, 14, 13}),  // expectedResult
+            Tensor({2, 2, 2}, T, std::vector<T_D>{5, 6, 7, 8, 16, 15, 14, 13}),  // expectedResultNumSegments
+            fillMode),
+        // empty segments
+        SegmentMaxParams(Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),                 // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 0, 2, 2}),             // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{3}),                       // numSegments
+                         Tensor({3}, T, std::vector<T_D>{2, empty_segment_value, 4}),  // expectedResult
+                         Tensor({3}, T, std::vector<T_D>{2, empty_segment_value, 4}),  // expectedResultNumSegments
+                         fillMode),
+        // single element segments
+        SegmentMaxParams(Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 1, 2, 3}),  // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{4}),            // numSegments
+                         Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // expectedResult
+                         Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // expectedResultNumSegments
+                         fillMode),
+        // all elements in one segment
+        SegmentMaxParams(Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 0, 0, 0}),  // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{1}),            // numSegments
+                         Tensor({1}, T, std::vector<T_D>{4}),               // expectedResult
+                         Tensor({1}, T, std::vector<T_D>{4}),               // expectedResultNumSegments
+                         fillMode),
+        // numSegments < max(segmentIds) + 1
+        SegmentMaxParams(Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 1, 2, 3}),  // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{2}),            // numSegments
+                         Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // expectedResult
+                         Tensor({2}, T, std::vector<T_D>{1, 2}),            // expectedResultNumSegments
+                         fillMode),
+        // numSegments > max(segmentIds) + 1
+        SegmentMaxParams(Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // data
+                         Tensor({4}, T_idx, std::vector<T_I>{0, 1, 2, 3}),  // segmentIds
+                         Tensor({}, T_idx, std::vector<T_I>{6}),            // numSegments
+                         Tensor({4}, T, std::vector<T_D>{1, 2, 3, 4}),      // expectedResult
+                         Tensor(                                            // expectedResultNumSegments
+                             {6},
+                             T,
+                             std::vector<T_D>{1, 2, 3, 4, empty_segment_value, empty_segment_value}),
+                         fillMode),
+    };
+    return segmentMaxParams;
+}
+
+std::vector<std::tuple<SegmentMaxParams, bool>> generateSegmentMaxV16CombinedParams() {
+    using ov::element::Type_t;
+    const std::vector<std::vector<SegmentMaxParams>> SegmentMaxTypeParams{
+        generateSegmentMaxParams<Type_t::i32, Type_t::i32>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::i32, Type_t::i32>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::i64, Type_t::i32>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::i64, Type_t::i32>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::u32, Type_t::i32>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::u32, Type_t::i32>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::u64, Type_t::i32>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::u64, Type_t::i32>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::f16, Type_t::i32>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::f16, Type_t::i32>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::f32, Type_t::i32>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::f32, Type_t::i32>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::i32, Type_t::i64>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::i32, Type_t::i64>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::i64, Type_t::i64>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::i64, Type_t::i64>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::u32, Type_t::i64>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::u32, Type_t::i64>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::u64, Type_t::i64>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::u64, Type_t::i64>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::f16, Type_t::i64>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::f16, Type_t::i64>(ov::op::FillMode::LOWEST),
+        generateSegmentMaxParams<Type_t::f32, Type_t::i64>(ov::op::FillMode::ZERO),
+        generateSegmentMaxParams<Type_t::f32, Type_t::i64>(ov::op::FillMode::LOWEST),
+    };
+
+    // expand cases with useNumSegments bool
+    std::vector<std::tuple<SegmentMaxParams, bool>> combinedParams;
+    for (const auto& params : SegmentMaxTypeParams) {
+        for (const auto& param : params) {
+            combinedParams.emplace_back(param, true);
+            combinedParams.emplace_back(param, false);
+        }
+    }
+    return combinedParams;
+}
+
+INSTANTIATE_TEST_SUITE_P(smoke_SegmentMax_With_Hardcoded_Refs,
+                         ReferenceSegmentMaxV16LayerTest,
+                         testing::ValuesIn(generateSegmentMaxV16CombinedParams()),
+                         ReferenceSegmentMaxV16LayerTest::getTestCaseName);
+}  // namespace
diff --git a/src/tests/functional/plugin/conformance/test_runner/op_conformance_runner/src/op_impl_check/single_op_graph.cpp b/src/tests/functional/plugin/conformance/test_runner/op_conformance_runner/src/op_impl_check/single_op_graph.cpp
index cb29df89f5e3d8..5cd96e6c83a40c 100644
--- a/src/tests/functional/plugin/conformance/test_runner/op_conformance_runner/src/op_impl_check/single_op_graph.cpp
+++ b/src/tests/functional/plugin/conformance/test_runner/op_conformance_runner/src/op_impl_check/single_op_graph.cpp
@@ -532,6 +532,15 @@ std::shared_ptr<ov::Model> generate(const std::shared_ptr<ov::op::v16::Identity>
     return std::make_shared<ov::Model>(results, params, "Identity");
 }
 
+std::shared_ptr<ov::Model> generate(const std::shared_ptr<ov::op::v16::SegmentMax> &node) {
+    const auto data = std::make_shared<ov::op::v0::Parameter>(ov::element::f32, ov::PartialShape{2, 9});
+    const auto segment_ids = ov::op::v0::Constant::create<int32_t>(ov::element::i32, {2}, {4, 4});
+    const auto num_segments = ov::op::v0::Constant::create<int32_t>(ov::element::i32, {}, {5});
+    const auto SegmentMaxNode = std::make_shared<ov::op::v16::SegmentMax>(data, segment_ids, num_segments, ov::op::FillMode::ZERO);
+    ov::ResultVector results{std::make_shared<ov::op::v0::Result>(SegmentMaxNode)};
+    return std::make_shared<ov::Model>(results, ov::ParameterVector{data}, "SegmentMaxGraph");
+}
+
 std::shared_ptr<ov::Model> generate(const std::shared_ptr<ov::op::v4::Interpolate> &node) {
     using InterpolateAttrs = op::v4::Interpolate::InterpolateAttrs;
     using InterpolateMode = op::v4::Interpolate::InterpolateMode;

From c3ae4b03e5a2463a528bd76f3bbd61a6ee35b282 Mon Sep 17 00:00:00 2001
From: Taylor Yeonbok Lee <taylor.lee@intel.com>
Date: Wed, 19 Feb 2025 12:48:14 +0900
Subject: [PATCH 16/20] [GPU] update onednn with the latest 3.7 branch (#28986)

### Details:
- Update onednn for gpu with latest 3.7 branch which includes ARL-H perf
improvement

### Tickets:
 - *ticket-id*
---
 src/plugins/intel_gpu/thirdparty/onednn_gpu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/plugins/intel_gpu/thirdparty/onednn_gpu b/src/plugins/intel_gpu/thirdparty/onednn_gpu
index b6d57d81b5b9c5..1584b5a36b8512 160000
--- a/src/plugins/intel_gpu/thirdparty/onednn_gpu
+++ b/src/plugins/intel_gpu/thirdparty/onednn_gpu
@@ -1 +1 @@
-Subproject commit b6d57d81b5b9c5e5ee8d1b71a58c727392740e77
+Subproject commit 1584b5a36b851265d59bd723abc235e13759be2f

From 888cc14e6c1a529cdd401902d88fa39b0842ce87 Mon Sep 17 00:00:00 2001
From: Nikolay Shchegolev <nikolay.shchegolev@intel.com>
Date: Wed, 19 Feb 2025 10:00:49 +0400
Subject: [PATCH 17/20] [CORE][CACHE][HASH] DYNAMIC_CODE_POLICY check on
 Windows (#29006)

### Details:
- *Some customers can set policy ProcessDynamicCodePolicy to prohibit
dynamic code. So need to disable JIT in such cases.*

### Tickets:
 - *162440*
---
 .../include/openvino/util/common_util.hpp     |   8 ++
 src/common/util/src/common_util.cpp           |  13 ++
 src/core/reference/src/op/convert.cpp         |  28 ++--
 src/core/src/runtime/compute_hash.cpp         | 133 +++++++++---------
 4 files changed, 105 insertions(+), 77 deletions(-)

diff --git a/src/common/util/include/openvino/util/common_util.hpp b/src/common/util/include/openvino/util/common_util.hpp
index 15ec5d8f27d588..5d6f777d6937b8 100644
--- a/src/common/util/include/openvino/util/common_util.hpp
+++ b/src/common/util/include/openvino/util/common_util.hpp
@@ -180,5 +180,13 @@ constexpr std::array<std::conditional_t<std::is_void_v<T>, std::common_type_t<Ar
     return {std::forward<Args>(args)...};
 }
 
+#if defined(_WIN32)
+bool may_i_use_dynamic_code();
+#else
+constexpr bool may_i_use_dynamic_code() {
+    return true;
+}
+#endif
+
 }  // namespace util
 }  // namespace ov
diff --git a/src/common/util/src/common_util.cpp b/src/common/util/src/common_util.cpp
index ba6de2ed8937a3..2db9fa81af2ba3 100644
--- a/src/common/util/src/common_util.cpp
+++ b/src/common/util/src/common_util.cpp
@@ -6,6 +6,10 @@
 
 #include <algorithm>
 
+#if defined(_WIN32)
+#    include <windows.h>
+#endif
+
 std::string ov::util::to_lower(const std::string& s) {
     std::string rc = s;
     std::transform(rc.begin(), rc.end(), rc.begin(), ::tolower);
@@ -60,3 +64,12 @@ std::string ov::util::filter_lines_by_prefix(const std::string& str, const std::
     }
     return res.str();
 }
+
+#if defined(_WIN32)
+bool ov::util::may_i_use_dynamic_code() {
+    HANDLE handle = GetCurrentProcess();
+    PROCESS_MITIGATION_DYNAMIC_CODE_POLICY dynamic_code_policy = {0};
+    GetProcessMitigationPolicy(handle, ProcessDynamicCodePolicy, &dynamic_code_policy, sizeof(dynamic_code_policy));
+    return dynamic_code_policy.ProhibitDynamicCode != TRUE;
+}
+#endif
diff --git a/src/core/reference/src/op/convert.cpp b/src/core/reference/src/op/convert.cpp
index 0433444ec411f7..08420ff0fe6eff 100644
--- a/src/core/reference/src/op/convert.cpp
+++ b/src/core/reference/src/op/convert.cpp
@@ -8,6 +8,7 @@
 
 #ifdef OV_CORE_USE_XBYAK_JIT
 #    include "openvino/reference/utils/jit_generator.hpp"
+#    include "openvino/util/common_util.hpp"
 #endif
 
 #ifdef OV_CORE_USE_INTRINSICS
@@ -480,14 +481,15 @@ class jit_count_out_of_range : public jit::Generator {
 template <class Clamp, typename TI, typename TO>
 void convert_impl(const TI* arg, TO* out, size_t count) {
 #ifdef OV_CORE_USE_XBYAK_JIT
-    if (auto converter = jit_convert_array::get<TI, TO, Clamp::enabled>()) {
-        jit_convert_array::args_t args = {arg, out, count};
-        converter(&args);
-    } else
-#endif
-    {
-        Converter<TI, TO>::template apply<Clamp>(arg, out, count);
+    if (util::may_i_use_dynamic_code()) {
+        if (auto converter = jit_convert_array::get<TI, TO, Clamp::enabled>()) {
+            jit_convert_array::args_t args = {arg, out, count};
+            converter(&args);
+            return;
+        }
     }
+#endif  // OV_CORE_USE_XBYAK_JIT
+    Converter<TI, TO>::template apply<Clamp>(arg, out, count);
 }
 }  // namespace
 
@@ -544,11 +546,13 @@ void convert_from_bf16_to_f16_with_clamp(const bfloat16* arg, float16* out, size
 
 size_t count_out_of_f16_range(const float* arg, size_t count) {
 #ifdef OV_CORE_USE_XBYAK_JIT
-    if (auto converter = jit_count_out_of_range::get<float, float16>()) {
-        size_t num_out_of_range = 0;
-        jit_count_out_of_range::args_t args = {arg, &num_out_of_range, count};
-        converter(&args);
-        return num_out_of_range;
+    if (util::may_i_use_dynamic_code()) {
+        if (auto converter = jit_count_out_of_range::get<float, float16>()) {
+            size_t num_out_of_range = 0;
+            jit_count_out_of_range::args_t args = {arg, &num_out_of_range, count};
+            converter(&args);
+            return num_out_of_range;
+        }
     }
 #endif  // OV_CORE_USE_XBYAK_JIT
     const auto is_out_of_f16_range = [](const float v) {
diff --git a/src/core/src/runtime/compute_hash.cpp b/src/core/src/runtime/compute_hash.cpp
index f9d2aa9c7b14de..7c1d5bcc673a6e 100644
--- a/src/core/src/runtime/compute_hash.cpp
+++ b/src/core/src/runtime/compute_hash.cpp
@@ -21,6 +21,7 @@
 #ifdef OV_CORE_USE_XBYAK_JIT
 #    include "openvino/core/parallel.hpp"
 #    include "openvino/reference/utils/registers_pool.hpp"
+#    include "openvino/util/common_util.hpp"
 #endif  // OV_CORE_USE_XBYAK_JIT
 
 namespace ov {
@@ -822,77 +823,79 @@ void ComputeHash<isa>::fold_to_64(const Vmm& v_dst) {
 
 size_t compute_hash(const void* src, size_t size) {
 #ifdef OV_CORE_USE_XBYAK_JIT
-    if (Generator::mayiuse(avx2)) {
-        uint64_t result = 0lu;
-
-        // Parallel section
-        constexpr uint64_t min_wa_per_thread = 131072lu;  // 2^17
-        const uint64_t size_u64 = static_cast<uint64_t>(size);
-        if (size_u64 >= min_wa_per_thread * 2lu) {
-            static auto first_thr_kernel = Generator::mayiuse(avx512_core)
-                                               ? jit::ComputeHash<avx512_core>::create({jit::FIRST_THREAD})
-                                               : jit::ComputeHash<avx2>::create({jit::FIRST_THREAD});
-            static auto n_thr_kernel = Generator::mayiuse(avx512_core)
-                                           ? jit::ComputeHash<avx512_core>::create({jit::N_THREAD})
-                                           : jit::ComputeHash<avx2>::create({jit::N_THREAD});
-            static auto final_fold_kernel = Generator::mayiuse(avx512_core)
-                                                ? jit::ComputeHash<avx512_core>::create({jit::FINAL_FOLD})
-                                                : jit::ComputeHash<avx2>::create({jit::FINAL_FOLD});
-
-            static const uint64_t max_thr_num = 2lu;
-            uint64_t thr_num = std::min(size_u64 / min_wa_per_thread, max_thr_num);
-            const uint64_t el_per_thread =
-                first_thr_kernel->get_vlen() * ((size_u64 / thr_num) / first_thr_kernel->get_vlen());
-            std::vector<uint8_t> intermediate(thr_num * first_thr_kernel->get_vlen());
-
-            parallel_nt_static(static_cast<int>(thr_num), [&](const int ithr, const int nthr) {
-                uint64_t start = el_per_thread * ithr;
-                if (start >= size_u64) {
-                    return;
-                }
-                uint64_t work_amount = (el_per_thread + start > size_u64) ? size_u64 - start : el_per_thread;
+    if (util::may_i_use_dynamic_code()) {
+        if (Generator::mayiuse(avx2)) {
+            uint64_t result = 0lu;
+
+            // Parallel section
+            constexpr uint64_t min_wa_per_thread = 131072lu;  // 2^17
+            const uint64_t size_u64 = static_cast<uint64_t>(size);
+            if (size_u64 >= min_wa_per_thread * 2lu) {
+                static auto first_thr_kernel = Generator::mayiuse(avx512_core)
+                                                   ? jit::ComputeHash<avx512_core>::create({jit::FIRST_THREAD})
+                                                   : jit::ComputeHash<avx2>::create({jit::FIRST_THREAD});
+                static auto n_thr_kernel = Generator::mayiuse(avx512_core)
+                                               ? jit::ComputeHash<avx512_core>::create({jit::N_THREAD})
+                                               : jit::ComputeHash<avx2>::create({jit::N_THREAD});
+                static auto final_fold_kernel = Generator::mayiuse(avx512_core)
+                                                    ? jit::ComputeHash<avx512_core>::create({jit::FINAL_FOLD})
+                                                    : jit::ComputeHash<avx2>::create({jit::FINAL_FOLD});
+
+                static const uint64_t max_thr_num = 2lu;
+                uint64_t thr_num = std::min(size_u64 / min_wa_per_thread, max_thr_num);
+                const uint64_t el_per_thread =
+                    first_thr_kernel->get_vlen() * ((size_u64 / thr_num) / first_thr_kernel->get_vlen());
+                std::vector<uint8_t> intermediate(thr_num * first_thr_kernel->get_vlen());
+
+                parallel_nt_static(static_cast<int>(thr_num), [&](const int ithr, const int nthr) {
+                    uint64_t start = el_per_thread * ithr;
+                    if (start >= size_u64) {
+                        return;
+                    }
+                    uint64_t work_amount = (el_per_thread + start > size_u64) ? size_u64 - start : el_per_thread;
+
+                    jit::ComputeHashCallArgs args;
+
+                    args.src_ptr = reinterpret_cast<const uint8_t*>(src) + first_thr_kernel->get_vlen() * ithr;
+                    args.dst_ptr = &(intermediate[first_thr_kernel->get_vlen() * ithr]);
+                    args.k_ptr = jit::K_PULL;
+                    args.work_amount = work_amount;
+                    args.size = size_u64;
+                    args.threads_num = thr_num;
+
+                    if (ithr == 0) {
+                        (*first_thr_kernel)(&args);
+                    } else {
+                        (*n_thr_kernel)(&args);
+                    }
+                });
 
                 jit::ComputeHashCallArgs args;
+                args.work_amount = size_u64 - el_per_thread * thr_num;
+                args.src_ptr = reinterpret_cast<const uint8_t*>(src) + size_u64 - args.work_amount;
+                args.dst_ptr = &result;
+                args.k_ptr = jit::K_PULL;
+                args.size = size_u64;
+                args.intermediate_ptr = intermediate.data();
 
-                args.src_ptr = reinterpret_cast<const uint8_t*>(src) + first_thr_kernel->get_vlen() * ithr;
-                args.dst_ptr = &(intermediate[first_thr_kernel->get_vlen() * ithr]);
+                (*final_fold_kernel)(&args);
+            } else {
+                static auto single_thr_kernel = Generator::mayiuse(avx512_core)
+                                                    ? jit::ComputeHash<avx512_core>::create({jit::SINGLE_THREAD})
+                                                    : jit::ComputeHash<avx2>::create({jit::SINGLE_THREAD});
+
+                jit::ComputeHashCallArgs args;
+                args.src_ptr = src;
+                args.dst_ptr = &result;
                 args.k_ptr = jit::K_PULL;
-                args.work_amount = work_amount;
+                args.work_amount = size_u64;
                 args.size = size_u64;
-                args.threads_num = thr_num;
-
-                if (ithr == 0) {
-                    (*first_thr_kernel)(&args);
-                } else {
-                    (*n_thr_kernel)(&args);
-                }
-            });
-
-            jit::ComputeHashCallArgs args;
-            args.work_amount = size_u64 - el_per_thread * thr_num;
-            args.src_ptr = reinterpret_cast<const uint8_t*>(src) + size_u64 - args.work_amount;
-            args.dst_ptr = &result;
-            args.k_ptr = jit::K_PULL;
-            args.size = size_u64;
-            args.intermediate_ptr = intermediate.data();
-
-            (*final_fold_kernel)(&args);
-        } else {
-            static auto single_thr_kernel = Generator::mayiuse(avx512_core)
-                                                ? jit::ComputeHash<avx512_core>::create({jit::SINGLE_THREAD})
-                                                : jit::ComputeHash<avx2>::create({jit::SINGLE_THREAD});
-
-            jit::ComputeHashCallArgs args;
-            args.src_ptr = src;
-            args.dst_ptr = &result;
-            args.k_ptr = jit::K_PULL;
-            args.work_amount = size_u64;
-            args.size = size_u64;
-
-            (*single_thr_kernel)(&args);
-        }
 
-        return result;
+                (*single_thr_kernel)(&args);
+            }
+
+            return result;
+        }
     }
 
 #endif  // OV_CORE_USE_XBYAK_JIT

From b47c6076d302558ce78c732d9a8f8f0fa4eec43d Mon Sep 17 00:00:00 2001
From: yanlan song <bell.song@intel.com>
Date: Wed, 19 Feb 2025 15:26:25 +0800
Subject: [PATCH 18/20] [GPU] fix possible memory corruption with skippable
 nodes (#29042)

### Details:
- we have some nodes which is target to be optimized during runtime, the
memory status can be corrupted among iterations for these nodes

### Tickets:
 - CVS-161830

---------

Signed-off-by: fishbell <bell.song@intel.com>
---
 src/plugins/intel_gpu/src/graph/primitive_inst.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/plugins/intel_gpu/src/graph/primitive_inst.cpp b/src/plugins/intel_gpu/src/graph/primitive_inst.cpp
index 14a1072422f442..449c0d38aae95b 100644
--- a/src/plugins/intel_gpu/src/graph/primitive_inst.cpp
+++ b/src/plugins/intel_gpu/src/graph/primitive_inst.cpp
@@ -1460,6 +1460,11 @@ void primitive_inst::do_runtime_skip_gather() {
                 GPU_DEBUG_TRACE_DETAIL << "--- Cannot optimize because idx_data [" << i << "] (" << idx_data[i] << ") != " << i << std::endl;
                 if (_impl_params->output_layouts[0].data_padding.is_dynamic())
                     _impl_params->output_layouts[0].data_padding = padding();
+                // for runtime skippable nodes, if previous iter is skipped while this iter not, its output memory needs to be revalidate
+                // as memory opt/release may be applied for these nodes to reduce memory footprint in previous iters
+                if (can_be_optimized()) {
+                    set_flag(ExecutionFlags::SHAPE_CHANGED);
+                }
                 set_can_be_optimized(false);
                 return;
             }

From a84ae96991bdcc4dedbc5469d20920ce6bea871e Mon Sep 17 00:00:00 2001
From: barnasm1 <michal.barnas@intel.com>
Date: Wed, 19 Feb 2025 09:10:35 +0100
Subject: [PATCH 19/20] [CORE] Make an additional conversion from std::string
 to std::wstring (#29058)

Make an additional conversion from std::string to std::wstring at
uv::util::to_file_path function when
OPENVINO_ENABLE_UNICODE_PATH_SUPPORT was set

Tickets:
[162461](https://jira.devtools.intel.com/browse/CVS-162461)
[146659](https://jira.devtools.intel.com/browse/CVS-146659)
---
 src/common/util/include/openvino/util/file_util.hpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/common/util/include/openvino/util/file_util.hpp b/src/common/util/include/openvino/util/file_util.hpp
index ee6ea7a7e57b8a..0690d098d4e02c 100644
--- a/src/common/util/include/openvino/util/file_util.hpp
+++ b/src/common/util/include/openvino/util/file_util.hpp
@@ -239,7 +239,11 @@ inline std::string from_file_path(const ov::util::Path& path) {
 
 // TODO: remove this function after all calls use Path
 inline FilePath to_file_path(const ov::util::Path& path) {
+#if defined(_WIN32) && defined(OPENVINO_ENABLE_UNICODE_PATH_SUPPORT)
+    return ov::util::string_to_wstring(path.string());
+#else
     return path.native();
+#endif
 }
 
 #ifdef OPENVINO_ENABLE_UNICODE_PATH_SUPPORT

From 6d19e8b6887e096b3b84af892bbfadb355eb610c Mon Sep 17 00:00:00 2001
From: Pawel Raasz <pawel.raasz@intel.com>
Date: Wed, 19 Feb 2025 14:32:04 +0100
Subject: [PATCH 20/20] [clean-up ] Fix code style (#29064)

---
 src/core/src/type/float8_e4m3.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/core/src/type/float8_e4m3.cpp b/src/core/src/type/float8_e4m3.cpp
index 403a7e232c4196..6e6f3e1c774ead 100644
--- a/src/core/src/type/float8_e4m3.cpp
+++ b/src/core/src/type/float8_e4m3.cpp
@@ -8,8 +8,8 @@
 #include <cmath>
 #include <limits>
 
-#include "openvino/core/type/float_util.hpp"
 #include "openvino/core/type/float16.hpp"
+#include "openvino/core/type/float_util.hpp"
 
 namespace ov {