From 7a58a924f7c764ea576f52afc5fe7a430aedd8ad Mon Sep 17 00:00:00 2001 From: Manadher Kharroubi Date: Thu, 11 Jan 2024 16:46:00 -0800 Subject: [PATCH] Implementing RAM primitive transforms --- CMakeLists.txt | 4 + include/eblif_tranform/reconstruct_dsp38.h | 90 + include/eblif_tranform/reconstruct_ram18kx2.h | 464 +++ include/eblif_tranform/reconstruct_ram36k.h | 599 ++++ include/eblif_tranform/reconstruct_utils.h | 35 + include/eblif_tranform/transform_blif.h | 2830 ++--------------- 6 files changed, 1408 insertions(+), 2614 deletions(-) create mode 100644 include/eblif_tranform/reconstruct_dsp38.h create mode 100644 include/eblif_tranform/reconstruct_ram18kx2.h create mode 100644 include/eblif_tranform/reconstruct_ram36k.h create mode 100644 include/eblif_tranform/reconstruct_utils.h diff --git a/CMakeLists.txt b/CMakeLists.txt index a6f2d79c..9b2f2a9e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -109,6 +109,10 @@ endfunction(apply_patch) FILE(COPY ${EBLIF_TRANSFORM_SRC}/blifparse.cpp + ${EBLIF_TRANSFORM_SRC}/reconstruct_dsp38.h + ${EBLIF_TRANSFORM_SRC}/reconstruct_ram18kx2.h + ${EBLIF_TRANSFORM_SRC}/reconstruct_ram36k.h + ${EBLIF_TRANSFORM_SRC}/reconstruct_utils.h ${EBLIF_TRANSFORM_SRC}/transform_blif.h DESTINATION ${EBLIF_TRANSFORM_DEST}) diff --git a/include/eblif_tranform/reconstruct_dsp38.h b/include/eblif_tranform/reconstruct_dsp38.h new file mode 100644 index 00000000..41a50583 --- /dev/null +++ b/include/eblif_tranform/reconstruct_dsp38.h @@ -0,0 +1,90 @@ +#pragma once +/** + * @file reconstruct_dsp38.h + * @author Manadher Kharroubi (manadher@gmail.com) + * @brief + * @version 0.1 + * @date 2024-01- + * + * @copyright Copyright (c) 2024 +*/ +#include "reconstruct_utils.h" + +struct dsp38_instance { + std::unordered_map parameters = { + {"COEFF_0", "00000000000000000000"}, + {"COEFF_1", "00000000000000000000"}, + {"COEFF_2", "00000000000000000000"}, + {"COEFF_3", "00000000000000000000"}, + {"DSP_MODE", "MULTIPLY_ACCUMULATE"}, + {"OUTPUT_REG_EN", "FALSE"}, + {"INPUT_REG_EN", "FALSE"}, + {"accumulator", "0"}, + {"adder", "0"}, + {"output_reg", "0"}, + {"input_reg", "0"}}; + bool set_param(const std::string &par_name, std::string value) { + if (parameters.find(par_name) != end(parameters)) { + parameters[par_name] = value; + if (par_name == "DSP_MODE") { + if (value == "MULTIPLY_ACCUMULATE") + parameters["accumulator"] = "1"; + if (value == "MULTIPLY_ADD_SUB") + parameters["adder"] = "1"; + } else if (par_name == "OUTPUT_REG_EN") { + if (value == "TRUE") + parameters["output_reg"] = "1"; + } else if (par_name == "INPUT_REG_EN") { + if (value == "TRUE") + parameters["input_reg"] = "1"; + } + return true; + } + return false; + } + // DSP38 + std::unordered_map RS_DSP_Primitives{ + {"0000", "RS_DSP_MULT"}, + {"1111", "RS_DSP_MULT"}, + {"1110", "RS_DSP_MULT"}, + {"1101", "RS_DSP_MULT"}, + {"1100", "RS_DSP_MULT"}, + {"1011", "RS_DSP_MULTACC_REGIN_REGOUT"}, + {"1010", "RS_DSP_MULTACC_REGOUT"}, + {"1001", "RS_DSP_MULTACC_REGIN"}, + {"1000", "RS_DSP_MULTACC"}, + {"0111", "RS_DSP_MULTADD_REGIN_REGOUT"}, + {"0110", "RS_DSP_MULTADD_REGOUT"}, + {"0101", "RS_DSP_MULTADD_REGIN"}, + {"0100", "RS_DSP_MULTADD"}, + {"0011", "RS_DSP_MULT_REGIN_REGOUT"}, + {"0010", "RS_DSP_MULT_REGOUT"}, + {"0001", "RS_DSP_MULT_REGIN"}}; + std::string get_MODE_BITS() { + return parameters["COEFF_0"] + parameters["COEFF_1"] + + parameters["COEFF_2"] + parameters["COEFF_3"]; + } + std::string get_block_key() { + return parameters["accumulator"] + parameters["adder"] + + parameters["output_reg"] + parameters["input_reg"]; + } + void print(std::ostream &ofs) { + std::string rs_prim = RS_DSP_Primitives.at(get_block_key()); + ofs << ".subckt " << rs_prim << " "; + for (auto &cn : port_connections) { + std::string low_prim = cn.first; + std::transform(low_prim.begin(), low_prim.end(), low_prim.begin(), + ::tolower); + if (low_prim == std::string("saturate")) { + low_prim = "saturate_enable"; + } + if (low_prim == std::string("reset")) { + low_prim = "lreset"; + } + ofs << low_prim << "=" << cn.second << " "; + } + ofs << std::endl; + ofs << ".param MODE_BITS " << get_MODE_BITS() << std::endl; + } + std::unordered_map port_connections; +}; diff --git a/include/eblif_tranform/reconstruct_ram18kx2.h b/include/eblif_tranform/reconstruct_ram18kx2.h new file mode 100644 index 00000000..6cca7d09 --- /dev/null +++ b/include/eblif_tranform/reconstruct_ram18kx2.h @@ -0,0 +1,464 @@ +#pragma once +/** + * @file reconstruct_ram18kx2.h + * @author Manadher Kharroubi (manadher@gmail.com) + * @brief + * @version 0.1 + * @date 2024-01- + * + * @copyright Copyright (c) 2024 + * + */ +#include "reconstruct_utils.h" + +struct TDP_RAM18KX2_instance { + std::set TDP_RAM18KX2_internal_signals = { + "DATA_OUT_A1", "DATA_OUT_A2", "DATA_OUT_B1", "DATA_OUT_B2"}; + std::vector TDP_RAM18KX2_Assigns = { + ".names DATA_OUT_A1[15] RDATA_A1[15]", + ".names DATA_OUT_A1[14] RDATA_A1[14]", + ".names DATA_OUT_A1[13] RDATA_A1[13]", + ".names DATA_OUT_A1[12] RDATA_A1[12]", + ".names DATA_OUT_A1[11] RDATA_A1[11]", + ".names DATA_OUT_A1[10] RDATA_A1[10]", + ".names DATA_OUT_A1[9] RDATA_A1[9]", + ".names DATA_OUT_A1[8] RDATA_A1[8]", + ".names DATA_OUT_A1[7] RDATA_A1[7]", + ".names DATA_OUT_A1[6] RDATA_A1[6]", + ".names DATA_OUT_A1[5] RDATA_A1[5]", + ".names DATA_OUT_A1[4] RDATA_A1[4]", + ".names DATA_OUT_A1[3] RDATA_A1[3]", + ".names DATA_OUT_A1[2] RDATA_A1[2]", + ".names DATA_OUT_A1[1] RDATA_A1[1]", + ".names DATA_OUT_A1[0] RDATA_A1[0]", + ".names DATA_OUT_B1[15] RDATA_B1[15]", + ".names DATA_OUT_B1[14] RDATA_B1[14]", + ".names DATA_OUT_B1[13] RDATA_B1[13]", + ".names DATA_OUT_B1[12] RDATA_B1[12]", + ".names DATA_OUT_B1[11] RDATA_B1[11]", + ".names DATA_OUT_B1[10] RDATA_B1[10]", + ".names DATA_OUT_B1[9] RDATA_B1[9]", + ".names DATA_OUT_B1[8] RDATA_B1[8]", + ".names DATA_OUT_B1[7] RDATA_B1[7]", + ".names DATA_OUT_B1[6] RDATA_B1[6]", + ".names DATA_OUT_B1[5] RDATA_B1[5]", + ".names DATA_OUT_B1[4] RDATA_B1[4]", + ".names DATA_OUT_B1[3] RDATA_B1[3]", + ".names DATA_OUT_B1[2] RDATA_B1[2]", + ".names DATA_OUT_B1[1] RDATA_B1[1]", + ".names DATA_OUT_B1[0] RDATA_B1[0]", + ".names DATA_OUT_A1[17] RPARITY_A1[1]", + ".names DATA_OUT_A1[16] RPARITY_A1[0]", + ".names DATA_OUT_B1[17] RPARITY_B1[1]", + ".names DATA_OUT_B1[16] RPARITY_B1[0]", + ".names DATA_OUT_A2[15] RDATA_A2[15]", + ".names DATA_OUT_A2[14] RDATA_A2[14]", + ".names DATA_OUT_A2[13] RDATA_A2[13]", + ".names DATA_OUT_A2[12] RDATA_A2[12]", + ".names DATA_OUT_A2[11] RDATA_A2[11]", + ".names DATA_OUT_A2[10] RDATA_A2[10]", + ".names DATA_OUT_A2[9] RDATA_A2[9]", + ".names DATA_OUT_A2[8] RDATA_A2[8]", + ".names DATA_OUT_A2[7] RDATA_A2[7]", + ".names DATA_OUT_A2[6] RDATA_A2[6]", + ".names DATA_OUT_A2[5] RDATA_A2[5]", + ".names DATA_OUT_A2[4] RDATA_A2[4]", + ".names DATA_OUT_A2[3] RDATA_A2[3]", + ".names DATA_OUT_A2[2] RDATA_A2[2]", + ".names DATA_OUT_A2[1] RDATA_A2[1]", + ".names DATA_OUT_A2[0] RDATA_A2[0]", + ".names DATA_OUT_B2[15] RDATA_B2[15]", + ".names DATA_OUT_B2[14] RDATA_B2[14]", + ".names DATA_OUT_B2[13] RDATA_B2[13]", + ".names DATA_OUT_B2[12] RDATA_B2[12]", + ".names DATA_OUT_B2[11] RDATA_B2[11]", + ".names DATA_OUT_B2[10] RDATA_B2[10]", + ".names DATA_OUT_B2[9] RDATA_B2[9]", + ".names DATA_OUT_B2[8] RDATA_B2[8]", + ".names DATA_OUT_B2[7] RDATA_B2[7]", + ".names DATA_OUT_B2[6] RDATA_B2[6]", + ".names DATA_OUT_B2[5] RDATA_B2[5]", + ".names DATA_OUT_B2[4] RDATA_B2[4]", + ".names DATA_OUT_B2[3] RDATA_B2[3]", + ".names DATA_OUT_B2[2] RDATA_B2[2]", + ".names DATA_OUT_B2[1] RDATA_B2[1]", + ".names DATA_OUT_B2[0] RDATA_B2[0]", + ".names DATA_OUT_A2[17] RPARITY_A2[1]", + ".names DATA_OUT_A2[16] RPARITY_A2[0]", + ".names DATA_OUT_B2[17] RPARITY_B2[1]", + ".names DATA_OUT_B2[16] RPARITY_B2[0]"}; + std::unordered_map + TDP_RAM18KX2_to_RS_TDP36K_port_map = {{"WEN_A1", "WEN_A1"}, + {"WEN_B1", "WEN_B1"}, + {"REN_A1", "REN_A1"}, + {"REN_B1", "REN_B1"}, + {"CLK_A1", "CLK_A1"}, + {"CLK_B1", "CLK_B1"}, + {"BE_A1[0]", "BE_A1[0]"}, + {"BE_A1[1]", "BE_A1[1]"}, + {"BE_B1[0]", "BE_B1[0]"}, + {"BE_B1[1]", "BE_B1[1]"}, + {"ADDR_A1[0]", "ADDR_A1[0]"}, + {"ADDR_A1[1]", "ADDR_A1[1]"}, + {"ADDR_A1[2]", "ADDR_A1[2]"}, + {"ADDR_A1[3]", "ADDR_A1[3]"}, + {"ADDR_A1[4]", "ADDR_A1[4]"}, + {"ADDR_A1[5]", "ADDR_A1[5]"}, + {"ADDR_A1[6]", "ADDR_A1[6]"}, + {"ADDR_A1[7]", "ADDR_A1[7]"}, + {"ADDR_A1[8]", "ADDR_A1[8]"}, + {"ADDR_A1[9]", "ADDR_A1[9]"}, + {"ADDR_A1[10]", "ADDR_A1[10]"}, + {"ADDR_A1[11]", "ADDR_A1[11]"}, + {"ADDR_A1[12]", "ADDR_A1[12]"}, + {"ADDR_A1[13]", "ADDR_A1[13]"}, + {"ADDR_B1[0]", "ADDR_B1[0]"}, + {"ADDR_B1[1]", "ADDR_B1[1]"}, + {"ADDR_B1[2]", "ADDR_B1[2]"}, + {"ADDR_B1[3]", "ADDR_B1[3]"}, + {"ADDR_B1[4]", "ADDR_B1[4]"}, + {"ADDR_B1[5]", "ADDR_B1[5]"}, + {"ADDR_B1[6]", "ADDR_B1[6]"}, + {"ADDR_B1[7]", "ADDR_B1[7]"}, + {"ADDR_B1[8]", "ADDR_B1[8]"}, + {"ADDR_B1[9]", "ADDR_B1[9]"}, + {"ADDR_B1[10]", "ADDR_B1[10]"}, + {"ADDR_B1[11]", "ADDR_B1[11]"}, + {"ADDR_B1[12]", "ADDR_B1[12]"}, + {"ADDR_B1[13]", "ADDR_B1[13]"}, + {"WDATA_A1[0]", "WDATA_A1[0]"}, + {"WDATA_A1[1]", "WDATA_A1[1]"}, + {"WDATA_A1[2]", "WDATA_A1[2]"}, + {"WDATA_A1[3]", "WDATA_A1[3]"}, + {"WDATA_A1[4]", "WDATA_A1[4]"}, + {"WDATA_A1[5]", "WDATA_A1[5]"}, + {"WDATA_A1[6]", "WDATA_A1[6]"}, + {"WDATA_A1[7]", "WDATA_A1[7]"}, + {"WDATA_A1[8]", "WDATA_A1[8]"}, + {"WDATA_A1[9]", "WDATA_A1[9]"}, + {"WDATA_A1[10]", "WDATA_A1[10]"}, + {"WDATA_A1[11]", "WDATA_A1[11]"}, + {"WDATA_A1[12]", "WDATA_A1[12]"}, + {"WDATA_A1[13]", "WDATA_A1[13]"}, + {"WDATA_A1[14]", "WDATA_A1[14]"}, + {"WDATA_A1[15]", "WDATA_A1[15]"}, + {"WDATA_A1[16]", "WPARITY_A1[0]"}, + {"WDATA_A1[17]", "WPARITY_A1[1]"}, + {"WDATA_B1[0]", "WDATA_B1[0]"}, + {"WDATA_B1[1]", "WDATA_B1[1]"}, + {"WDATA_B1[2]", "WDATA_B1[2]"}, + {"WDATA_B1[3]", "WDATA_B1[3]"}, + {"WDATA_B1[4]", "WDATA_B1[4]"}, + {"WDATA_B1[5]", "WDATA_B1[5]"}, + {"WDATA_B1[6]", "WDATA_B1[6]"}, + {"WDATA_B1[7]", "WDATA_B1[7]"}, + {"WDATA_B1[8]", "WDATA_B1[8]"}, + {"WDATA_B1[9]", "WDATA_B1[9]"}, + {"WDATA_B1[10]", "WDATA_B1[10]"}, + {"WDATA_B1[11]", "WDATA_B1[11]"}, + {"WDATA_B1[12]", "WDATA_B1[12]"}, + {"WDATA_B1[13]", "WDATA_B1[13]"}, + {"WDATA_B1[14]", "WDATA_B1[14]"}, + {"WDATA_B1[15]", "WDATA_B1[15]"}, + {"WDATA_B1[16]", "WPARITY_B1[0]"}, + {"WDATA_B1[17]", "WPARITY_B1[1]"}, + {"RDATA_A1[0]", "DATA_OUT_A1[0]"}, + {"RDATA_A1[1]", "DATA_OUT_A1[1]"}, + {"RDATA_A1[2]", "DATA_OUT_A1[2]"}, + {"RDATA_A1[3]", "DATA_OUT_A1[3]"}, + {"RDATA_A1[4]", "DATA_OUT_A1[4]"}, + {"RDATA_A1[5]", "DATA_OUT_A1[5]"}, + {"RDATA_A1[6]", "DATA_OUT_A1[6]"}, + {"RDATA_A1[7]", "DATA_OUT_A1[7]"}, + {"RDATA_A1[8]", "DATA_OUT_A1[8]"}, + {"RDATA_A1[9]", "DATA_OUT_A1[9]"}, + {"RDATA_A1[10]", "DATA_OUT_A1[10]"}, + {"RDATA_A1[11]", "DATA_OUT_A1[11]"}, + {"RDATA_A1[12]", "DATA_OUT_A1[12]"}, + {"RDATA_A1[13]", "DATA_OUT_A1[13]"}, + {"RDATA_A1[14]", "DATA_OUT_A1[14]"}, + {"RDATA_A1[15]", "DATA_OUT_A1[15]"}, + {"RDATA_A1[16]", "DATA_OUT_A1[16]"}, + {"RDATA_A1[17]", "DATA_OUT_A1[17]"}, + {"RDATA_B1[0]", "DATA_OUT_B1[0]"}, + {"RDATA_B1[1]", "DATA_OUT_B1[1]"}, + {"RDATA_B1[2]", "DATA_OUT_B1[2]"}, + {"RDATA_B1[3]", "DATA_OUT_B1[3]"}, + {"RDATA_B1[4]", "DATA_OUT_B1[4]"}, + {"RDATA_B1[5]", "DATA_OUT_B1[5]"}, + {"RDATA_B1[6]", "DATA_OUT_B1[6]"}, + {"RDATA_B1[7]", "DATA_OUT_B1[7]"}, + {"RDATA_B1[8]", "DATA_OUT_B1[8]"}, + {"RDATA_B1[9]", "DATA_OUT_B1[9]"}, + {"RDATA_B1[10]", "DATA_OUT_B1[10]"}, + {"RDATA_B1[11]", "DATA_OUT_B1[11]"}, + {"RDATA_B1[12]", "DATA_OUT_B1[12]"}, + {"RDATA_B1[13]", "DATA_OUT_B1[13]"}, + {"RDATA_B1[14]", "DATA_OUT_B1[14]"}, + {"RDATA_B1[15]", "DATA_OUT_B1[15]"}, + {"RDATA_B1[16]", "DATA_OUT_B1[16]"}, + {"RDATA_B1[17]", "DATA_OUT_B1[17]"}, + {"FLUSH1", "$false"}, + {"WEN_A2", "WEN_A2"}, + {"WEN_B2", "WEN_B2"}, + {"REN_A2", "REN_A2"}, + {"REN_B2", "REN_B2"}, + {"CLK_A2", "CLK_A2"}, + {"CLK_B2", "CLK_B2"}, + {"BE_A2[0]", "BE_A2[0]"}, + {"BE_A2[1]", "BE_A2[1]"}, + {"BE_B2[0]", "BE_B2[0]"}, + {"BE_B2[1]", "BE_B2[1]"}, + {"ADDR_A2[0]", "ADDR_A2[0]"}, + {"ADDR_A2[1]", "ADDR_A2[1]"}, + {"ADDR_A2[2]", "ADDR_A2[2]"}, + {"ADDR_A2[3]", "ADDR_A2[3]"}, + {"ADDR_A2[4]", "ADDR_A2[4]"}, + {"ADDR_A2[5]", "ADDR_A2[5]"}, + {"ADDR_A2[6]", "ADDR_A2[6]"}, + {"ADDR_A2[7]", "ADDR_A2[7]"}, + {"ADDR_A2[8]", "ADDR_A2[8]"}, + {"ADDR_A2[9]", "ADDR_A2[9]"}, + {"ADDR_A2[10]", "ADDR_A2[10]"}, + {"ADDR_A2[11]", "ADDR_A2[11]"}, + {"ADDR_A2[12]", "ADDR_A2[12]"}, + {"ADDR_A2[13]", "ADDR_A2[13]"}, + {"ADDR_B2[0]", "ADDR_B2[0]"}, + {"ADDR_B2[1]", "ADDR_B2[1]"}, + {"ADDR_B2[2]", "ADDR_B2[2]"}, + {"ADDR_B2[3]", "ADDR_B2[3]"}, + {"ADDR_B2[4]", "ADDR_B2[4]"}, + {"ADDR_B2[5]", "ADDR_B2[5]"}, + {"ADDR_B2[6]", "ADDR_B2[6]"}, + {"ADDR_B2[7]", "ADDR_B2[7]"}, + {"ADDR_B2[8]", "ADDR_B2[8]"}, + {"ADDR_B2[9]", "ADDR_B2[9]"}, + {"ADDR_B2[10]", "ADDR_B2[10]"}, + {"ADDR_B2[11]", "ADDR_B2[11]"}, + {"ADDR_B2[12]", "ADDR_B2[12]"}, + {"ADDR_B2[13]", "ADDR_B2[13]"}, + {"WDATA_A2[0]", "WDATA_A2[0]"}, + {"WDATA_A2[1]", "WDATA_A2[1]"}, + {"WDATA_A2[2]", "WDATA_A2[2]"}, + {"WDATA_A2[3]", "WDATA_A2[3]"}, + {"WDATA_A2[4]", "WDATA_A2[4]"}, + {"WDATA_A2[5]", "WDATA_A2[5]"}, + {"WDATA_A2[6]", "WDATA_A2[6]"}, + {"WDATA_A2[7]", "WDATA_A2[7]"}, + {"WDATA_A2[8]", "WDATA_A2[8]"}, + {"WDATA_A2[9]", "WDATA_A2[9]"}, + {"WDATA_A2[10]", "WDATA_A2[10]"}, + {"WDATA_A2[11]", "WDATA_A2[11]"}, + {"WDATA_A2[12]", "WDATA_A2[12]"}, + {"WDATA_A2[13]", "WDATA_A2[13]"}, + {"WDATA_A2[14]", "WDATA_A2[14]"}, + {"WDATA_A2[15]", "WDATA_A2[15]"}, + {"WDATA_A2[16]", "WPARITY_A2[0]"}, + {"WDATA_A2[17]", "WPARITY_A2[1]"}, + {"WDATA_B2[0]", "WDATA_B2[0]"}, + {"WDATA_B2[1]", "WDATA_B2[1]"}, + {"WDATA_B2[2]", "WDATA_B2[2]"}, + {"WDATA_B2[3]", "WDATA_B2[3]"}, + {"WDATA_B2[4]", "WDATA_B2[4]"}, + {"WDATA_B2[5]", "WDATA_B2[5]"}, + {"WDATA_B2[6]", "WDATA_B2[6]"}, + {"WDATA_B2[7]", "WDATA_B2[7]"}, + {"WDATA_B2[8]", "WDATA_B2[8]"}, + {"WDATA_B2[9]", "WDATA_B2[9]"}, + {"WDATA_B2[10]", "WDATA_B2[10]"}, + {"WDATA_B2[11]", "WDATA_B2[11]"}, + {"WDATA_B2[12]", "WDATA_B2[12]"}, + {"WDATA_B2[13]", "WDATA_B2[13]"}, + {"WDATA_B2[14]", "WDATA_B2[14]"}, + {"WDATA_B2[15]", "WDATA_B2[15]"}, + {"WDATA_B2[16]", "WPARITY_B2[0]"}, + {"WDATA_B2[17]", "WPARITY_B2[1]"}, + {"RDATA_A2[0]", "DATA_OUT_A2[0]"}, + {"RDATA_A2[1]", "DATA_OUT_A2[1]"}, + {"RDATA_A2[2]", "DATA_OUT_A2[2]"}, + {"RDATA_A2[3]", "DATA_OUT_A2[3]"}, + {"RDATA_A2[4]", "DATA_OUT_A2[4]"}, + {"RDATA_A2[5]", "DATA_OUT_A2[5]"}, + {"RDATA_A2[6]", "DATA_OUT_A2[6]"}, + {"RDATA_A2[7]", "DATA_OUT_A2[7]"}, + {"RDATA_A2[8]", "DATA_OUT_A2[8]"}, + {"RDATA_A2[9]", "DATA_OUT_A2[9]"}, + {"RDATA_A2[10]", "DATA_OUT_A2[10]"}, + {"RDATA_A2[11]", "DATA_OUT_A2[11]"}, + {"RDATA_A2[12]", "DATA_OUT_A2[12]"}, + {"RDATA_A2[13]", "DATA_OUT_A2[13]"}, + {"RDATA_A2[14]", "DATA_OUT_A2[14]"}, + {"RDATA_A2[15]", "DATA_OUT_A2[15]"}, + {"RDATA_A2[16]", "DATA_OUT_A2[16]"}, + {"RDATA_A2[17]", "DATA_OUT_A2[17]"}, + {"RDATA_B2[0]", "DATA_OUT_B2[0]"}, + {"RDATA_B2[1]", "DATA_OUT_B2[1]"}, + {"RDATA_B2[2]", "DATA_OUT_B2[2]"}, + {"RDATA_B2[3]", "DATA_OUT_B2[3]"}, + {"RDATA_B2[4]", "DATA_OUT_B2[4]"}, + {"RDATA_B2[5]", "DATA_OUT_B2[5]"}, + {"RDATA_B2[6]", "DATA_OUT_B2[6]"}, + {"RDATA_B2[7]", "DATA_OUT_B2[7]"}, + {"RDATA_B2[8]", "DATA_OUT_B2[8]"}, + {"RDATA_B2[9]", "DATA_OUT_B2[9]"}, + {"RDATA_B2[10]", "DATA_OUT_B2[10]"}, + {"RDATA_B2[11]", "DATA_OUT_B2[11]"}, + {"RDATA_B2[12]", "DATA_OUT_B2[12]"}, + {"RDATA_B2[13]", "DATA_OUT_B2[13]"}, + {"RDATA_B2[14]", "DATA_OUT_B2[14]"}, + {"RDATA_B2[15]", "DATA_OUT_B2[15]"}, + {"RDATA_B2[16]", "DATA_OUT_B2[16]"}, + {"RDATA_B2[17]", "DATA_OUT_B2[17]"}, + {"FLUSH2", "$false"}}; + std::string per_instance_sig_name(std::string sn, int number) { + std::stringstream ss; + std::string num; + ss << number; + ss >> num; + for (auto &sg : TDP_RAM18KX2_internal_signals) { + if (sn.find(sg) == 0) { + return sn + std::string("_") + num; + } + } + return sn; + } + std::unordered_map parameters = { + {"INIT1", ""}, {"INIT1_PARITY", ""}, {"INIT2", ""}, + {"INIT2_PARITY", ""}, {"READ_WIDTH_A1", ""}, {"READ_WIDTH_A2", ""}, + {"READ_WIDTH_B1", ""}, {"READ_WIDTH_B2", ""}, {"WRITE_WIDTH_A1", ""}, + {"WRITE_WIDTH_A2", ""}, {"WRITE_WIDTH_B1", ""}, {"WRITE_WIDTH_B2", ""}}; + + std::unordered_map parameterSize = { + {"INIT1", 16384}, {"INIT1_PARITY", 2048}, {"INIT2", 16384}, + {"INIT2_PARITY", 2048}, {"READ_WIDTH_A1", 32}, {"READ_WIDTH_A2", 32}, + {"READ_WIDTH_B1", 32}, {"READ_WIDTH_B2", 32}, {"WRITE_WIDTH_A1", 32}, + {"WRITE_WIDTH_A2", 32}, {"WRITE_WIDTH_B1", 32}, {"WRITE_WIDTH_B2", 32}}; + + std::string str_2 = "00000000000000000000000000000010"; + std::string str_4 = "00000000000000000000000000000100"; + std::string str_9 = "00000000000000000000000000001001"; + std::string str_18 = "00000000000000000000000000010010"; + std::string str_36 = "00000000000000000000000000100100"; + std::string read_mode_A1; + std::string read_mode_B1; + std::string write_mode_A1; + std::string write_mode_B1; + std::string read_mode_A2; + std::string read_mode_B2; + std::string write_mode_A2; + std::string write_mode_B2; + std::string conf_code(std::string W) { + return W == str_36 ? "110" + : W == str_18 ? "010" + : W == str_9 ? "100" + : W == str_4 ? "001" + : W == str_2 ? "011" + : "101"; + } + std::string get_MODE_BITS() { + read_mode_A1 = conf_code(parameters["READ_WIDTH_A1"]); + read_mode_B1 = conf_code(parameters["WRITE_WIDTH_B1"]); + write_mode_A1 = conf_code(parameters["WRITE_WIDTH_A1"]); + write_mode_B1 = conf_code(parameters["WRITE_WIDTH_B1"]); + read_mode_A2 = conf_code(parameters["READ_WIDTH_A2"]); + read_mode_B2 = conf_code(parameters["READ_WIDTH_B2"]); + write_mode_A2 = conf_code(parameters["WRITE_WIDTH_A2"]); + write_mode_B2 = conf_code(parameters["WRITE_WIDTH_B2"]); + std::string MODE_BITS = + std::string("0") + read_mode_A1 + read_mode_B1 + write_mode_A1 + + write_mode_B1 + std::string(29, '0') + read_mode_A2 + read_mode_B2 + + write_mode_A2 + write_mode_B2 + std::string(26, '0') + std::string("1"); + return MODE_BITS; + }; + bool set_param(const std::string &par_name, std::string value) { + if (parameters.find(par_name) != end(parameters)) { + // Implementing expansion and truncation of parameters to their specified + // lengths + if (value.size() < parameterSize[par_name]) { + value = + std::string(parameterSize[par_name] - value.size(), '0') + value; + } else if (value.size() > parameterSize[par_name]) { + value = value.substr(parameterSize[par_name] - value.size()); + } + parameters[par_name] = value; + return true; + } + return false; + } + + std::string extract_sram1(const std::string &init, + const std::string &parity) { + std::string sram(18432, '0'); + + for (int i = 0; i < 1024; i++) { + sram.replace(i * 18, 16, init.substr(i * 16, 16)); + sram.replace((i + 1) * 16 + (2 * i), 2, parity.substr(i * 2, 2)); + } + + return sram; + } + + std::string extract_sram2(const std::string &init, + const std::string &parity) { + std::string sram(18432, '0'); + + for (int i = 0; i < 1024; i++) { + sram.replace(i * 18, 16, init.substr(i * 16, 16)); + sram.replace((i + 1) * 16 + (2 * i), 2, parity.substr(i * 2, 2)); + } + + return sram; + } + + std::string get_init_i1(const std::string &init1, const std::string &parity1, + const std::string &init2, + const std::string &parity2) { + + return extract_sram2(init2, parity2) + extract_sram1(init1, parity1); + } + void print(std::ostream &ofs) { + static unsigned cnt = 0; + cnt++; + std::string rs_prim = "RS_TDP36K"; + ofs << ".subckt " << rs_prim << " "; + for (auto &cn : TDP_RAM18KX2_to_RS_TDP36K_port_map) { + ofs << " " << cn.first; + if (port_connections.find(cn.second) != port_connections.end()) { + + ofs << "=" << port_connections[cn.second]; + } else { + ofs << "=" << per_instance_sig_name(cn.second, cnt); + } + } + ofs << std::endl; + ofs << ".param MODE_BITS " << get_MODE_BITS() << std::endl; + ofs << ".param INIT_i " + << get_init_i1(parameters["INIT1"], parameters["INIT1_PARITY"], + parameters["INIT2"], parameters["INIT2_PARITY"]) + << std::endl; + for (auto &assign : TDP_RAM18KX2_Assigns) { + bool connected = true; + std::vector tokens = split_on_space(assign); + std::string f_i_name = per_instance_sig_name(tokens[1], cnt); + std::string s_i_name = per_instance_sig_name(tokens[2], cnt); + if (f_i_name == tokens[1]) { + if (port_connections.find(f_i_name) != port_connections.end()) { + f_i_name = port_connections[f_i_name]; + } else { + connected = false; + } + } + if (s_i_name == tokens[2]) { + if (port_connections.find(s_i_name) != port_connections.end()) { + s_i_name = port_connections[s_i_name]; + } else { + connected = false; + } + } + if (connected) { + ofs << tokens[0] << " " << f_i_name << " " << s_i_name << "\n1 1\n"; + } + } + } + std::unordered_map port_connections; +}; diff --git a/include/eblif_tranform/reconstruct_ram36k.h b/include/eblif_tranform/reconstruct_ram36k.h new file mode 100644 index 00000000..636fe5a0 --- /dev/null +++ b/include/eblif_tranform/reconstruct_ram36k.h @@ -0,0 +1,599 @@ +#pragma once +/* + * @file reconstruct_ram36k.h + * @author Manadher Kharroubi (manadher@gmail.com) + * @brief + * @version 0.1 + * @date 2024-01- + * + * @copyright Copyright (c) 2024 + */ + +#include "reconstruct_utils.h" + +struct TDP_RAM36K_instance { + std::string str_1 = "00000000000000000000000000000001"; + std::string str_2 = "00000000000000000000000000000010"; + std::string str_4 = "00000000000000000000000000000100"; + std::string str_9 = "00000000000000000000000000001001"; + std::string str_18 = "00000000000000000000000000010010"; + std::string str_36 = "00000000000000000000000000100100"; + std::string str_26_zeroes = "00000000000000000000000000"; + std::string read_mode_A; + std::string read_mode_B; + std::string write_mode_A; + std::string write_mode_B; + std::set TDP_RAM36K_internal_signals = { + "DATA_OUT_A1", "DATA_OUT_A2", "DATA_OUT_B1", "DATA_OUT_B2", + "WDATA_A1", "WDATA_A2", "WDATA_B1", "WDATA_B2"}; + std::string per_instance_sig_name(std::string sn, int number) { + std::stringstream ss; + std::string num; + ss << number; + ss >> num; + for (auto &sg : TDP_RAM36K_internal_signals) { + if (sn.find(sg) == 0) { + return sn + std::string("_") + num; + } + } + return sn; + } + std::unordered_map parameterSize = { + {"INIT", 32768}, {"INIT_PARITY", 4096}, {"READ_WIDTH_A", 32}, + {"WRITE_WIDTH_A", 32}, {"READ_WIDTH_B", 32}, {"WRITE_WIDTH_B", 32}}; + std::unordered_map parameters = { + {"INIT", ""}, + {"INIT_PARITY", ""}, + {"READ_WIDTH_A", "00000000000000000000000000100100"}, + {"WRITE_WIDTH_A", "00000000000000000000000000100100"}, + {"READ_WIDTH_B", "00000000000000000000000000100100"}, + {"WRITE_WIDTH_B", "00000000000000000000000000100100"}}; + bool set_param(const std::string &par_name, std::string value) { + if (parameters.find(par_name) != end(parameters)) { + // Implementing expansion and truncation of parameters to their specified + // lengths + if (value.size() < parameterSize[par_name]) { + value = + std::string(parameterSize[par_name] - value.size(), '0') + value; + } else if (value.size() > parameterSize[par_name]) { + value = value.substr(parameterSize[par_name] - value.size()); + } + parameters[par_name] = value; + return true; + } + return false; + } + // The Keys are RS_TDP36K ports + std::unordered_map + TDP_RAM36K_to_RS_TDP36K_port_map = {{"WEN_A1", "WEN_A"}, + {"WEN_B1", "WEN_B"}, + {"REN_A1", "REN_A"}, + {"REN_B1", "REN_B"}, + {"CLK_A1", "CLK_A"}, + {"CLK_B1", "CLK_B"}, + {"BE_A1[0]", "BE_A[0]"}, + {"BE_A1[1]", "BE_A[1]"}, + {"BE_B1[0]", "BE_B[0]"}, + {"BE_B1[1]", "BE_B[1]"}, + {"ADDR_A1[0]", "ADDR_A[0]"}, + {"ADDR_A1[1]", "ADDR_A[1]"}, + {"ADDR_A1[2]", "ADDR_A[2]"}, + {"ADDR_A1[3]", "ADDR_A[3]"}, + {"ADDR_A1[4]", "ADDR_A[4]"}, + {"ADDR_A1[5]", "ADDR_A[5]"}, + {"ADDR_A1[6]", "ADDR_A[6]"}, + {"ADDR_A1[7]", "ADDR_A[7]"}, + {"ADDR_A1[8]", "ADDR_A[8]"}, + {"ADDR_A1[9]", "ADDR_A[9]"}, + {"ADDR_A1[10]", "ADDR_A[10]"}, + {"ADDR_A1[11]", "ADDR_A[11]"}, + {"ADDR_A1[12]", "ADDR_A[12]"}, + {"ADDR_A1[13]", "ADDR_A[13]"}, + {"ADDR_A1[14]", "ADDR_A[14]"}, + {"ADDR_B1[0]", "ADDR_B[0]"}, + {"ADDR_B1[1]", "ADDR_B[1]"}, + {"ADDR_B1[2]", "ADDR_B[2]"}, + {"ADDR_B1[3]", "ADDR_B[3]"}, + {"ADDR_B1[4]", "ADDR_B[4]"}, + {"ADDR_B1[5]", "ADDR_B[5]"}, + {"ADDR_B1[6]", "ADDR_B[6]"}, + {"ADDR_B1[7]", "ADDR_B[7]"}, + {"ADDR_B1[8]", "ADDR_B[8]"}, + {"ADDR_B1[9]", "ADDR_B[9]"}, + {"ADDR_B1[10]", "ADDR_B[10]"}, + {"ADDR_B1[11]", "ADDR_B[11]"}, + {"ADDR_B1[12]", "ADDR_B[12]"}, + {"ADDR_B1[13]", "ADDR_B[13]"}, + {"ADDR_B1[14]", "ADDR_B[14]"}, + {"WDATA_A1[0]", "WDATA_A1[0]"}, + {"WDATA_A1[1]", "WDATA_A1[1]"}, + {"WDATA_A1[2]", "WDATA_A1[2]"}, + {"WDATA_A1[3]", "WDATA_A1[3]"}, + {"WDATA_A1[4]", "WDATA_A1[4]"}, + {"WDATA_A1[5]", "WDATA_A1[5]"}, + {"WDATA_A1[6]", "WDATA_A1[6]"}, + {"WDATA_A1[7]", "WDATA_A1[7]"}, + {"WDATA_A1[8]", "WDATA_A1[8]"}, + {"WDATA_A1[9]", "WDATA_A1[9]"}, + {"WDATA_A1[10]", "WDATA_A1[10]"}, + {"WDATA_A1[11]", "WDATA_A1[11]"}, + {"WDATA_A1[12]", "WDATA_A1[12]"}, + {"WDATA_A1[13]", "WDATA_A1[13]"}, + {"WDATA_A1[14]", "WDATA_A1[14]"}, + {"WDATA_A1[15]", "WDATA_A1[15]"}, + {"WDATA_A1[16]", "WDATA_A1[16]"}, + {"WDATA_A1[17]", "WDATA_A1[17]"}, + {"WDATA_B1[0]", "WDATA_B1[0]"}, + {"WDATA_B1[1]", "WDATA_B1[1]"}, + {"WDATA_B1[2]", "WDATA_B1[2]"}, + {"WDATA_B1[3]", "WDATA_B1[3]"}, + {"WDATA_B1[4]", "WDATA_B1[4]"}, + {"WDATA_B1[5]", "WDATA_B1[5]"}, + {"WDATA_B1[6]", "WDATA_B1[6]"}, + {"WDATA_B1[7]", "WDATA_B1[7]"}, + {"WDATA_B1[8]", "WDATA_B1[8]"}, + {"WDATA_B1[9]", "WDATA_B1[9]"}, + {"WDATA_B1[10]", "WDATA_B1[10]"}, + {"WDATA_B1[11]", "WDATA_B1[11]"}, + {"WDATA_B1[12]", "WDATA_B1[12]"}, + {"WDATA_B1[13]", "WDATA_B1[13]"}, + {"WDATA_B1[14]", "WDATA_B1[14]"}, + {"WDATA_B1[15]", "WDATA_B1[15]"}, + {"WDATA_B1[16]", "WDATA_B1[16]"}, + {"WDATA_B1[17]", "WDATA_B1[17]"}, + {"RDATA_A1[0]", "DATA_OUT_A1[0]"}, + {"RDATA_A1[1]", "DATA_OUT_A1[1]"}, + {"RDATA_A1[2]", "DATA_OUT_A1[2]"}, + {"RDATA_A1[3]", "DATA_OUT_A1[3]"}, + {"RDATA_A1[4]", "DATA_OUT_A1[4]"}, + {"RDATA_A1[5]", "DATA_OUT_A1[5]"}, + {"RDATA_A1[6]", "DATA_OUT_A1[6]"}, + {"RDATA_A1[7]", "DATA_OUT_A1[7]"}, + {"RDATA_A1[8]", "DATA_OUT_A1[8]"}, + {"RDATA_A1[9]", "DATA_OUT_A1[9]"}, + {"RDATA_A1[10]", "DATA_OUT_A1[10]"}, + {"RDATA_A1[11]", "DATA_OUT_A1[11]"}, + {"RDATA_A1[12]", "DATA_OUT_A1[12]"}, + {"RDATA_A1[13]", "DATA_OUT_A1[13]"}, + {"RDATA_A1[14]", "DATA_OUT_A1[14]"}, + {"RDATA_A1[15]", "DATA_OUT_A1[15]"}, + {"RDATA_A1[16]", "DATA_OUT_A1[16]"}, + {"RDATA_A1[17]", "DATA_OUT_A1[17]"}, + {"RDATA_B1[0]", "DATA_OUT_B1[0]"}, + {"RDATA_B1[1]", "DATA_OUT_B1[1]"}, + {"RDATA_B1[2]", "DATA_OUT_B1[2]"}, + {"RDATA_B1[3]", "DATA_OUT_B1[3]"}, + {"RDATA_B1[4]", "DATA_OUT_B1[4]"}, + {"RDATA_B1[5]", "DATA_OUT_B1[5]"}, + {"RDATA_B1[6]", "DATA_OUT_B1[6]"}, + {"RDATA_B1[7]", "DATA_OUT_B1[7]"}, + {"RDATA_B1[8]", "DATA_OUT_B1[8]"}, + {"RDATA_B1[9]", "DATA_OUT_B1[9]"}, + {"RDATA_B1[10]", "DATA_OUT_B1[10]"}, + {"RDATA_B1[11]", "DATA_OUT_B1[11]"}, + {"RDATA_B1[12]", "DATA_OUT_B1[12]"}, + {"RDATA_B1[13]", "DATA_OUT_B1[13]"}, + {"RDATA_B1[14]", "DATA_OUT_B1[14]"}, + {"RDATA_B1[15]", "DATA_OUT_B1[15]"}, + {"RDATA_B1[16]", "DATA_OUT_B1[16]"}, + {"RDATA_B1[17]", "DATA_OUT_B1[17]"}, + {"FLUSH1", "$false"}, + {"WEN_A2", "WEN_A"}, + {"WEN_B2", "WEN_B"}, + {"REN_A2", "REN_A"}, + {"REN_B2", "REN_B"}, + {"CLK_A2", "CLK_A"}, + {"CLK_B2", "CLK_B"}, + {"BE_A2[0]", "BE_A[2]"}, + {"BE_A2[1]", "BE_A[3]"}, + {"BE_B2[0]", "BE_B[2]"}, + {"BE_B2[1]", "BE_B[3]"}, + {"ADDR_A2[0]", "ADDR_A[0]"}, + {"ADDR_A2[1]", "ADDR_A[1]"}, + {"ADDR_A2[2]", "ADDR_A[2]"}, + {"ADDR_A2[3]", "ADDR_A[3]"}, + {"ADDR_A2[4]", "ADDR_A[4]"}, + {"ADDR_A2[5]", "ADDR_A[5]"}, + {"ADDR_A2[6]", "ADDR_A[6]"}, + {"ADDR_A2[7]", "ADDR_A[7]"}, + {"ADDR_A2[8]", "ADDR_A[8]"}, + {"ADDR_A2[9]", "ADDR_A[9]"}, + {"ADDR_A2[10]", "ADDR_A[10]"}, + {"ADDR_A2[11]", "ADDR_A[11]"}, + {"ADDR_A2[12]", "ADDR_A[12]"}, + {"ADDR_A2[13]", "ADDR_A[13]"}, + {"ADDR_A2[14]", "ADDR_A[14]"}, + {"ADDR_B2[0]", "ADDR_B[0]"}, + {"ADDR_B2[1]", "ADDR_B[1]"}, + {"ADDR_B2[2]", "ADDR_B[2]"}, + {"ADDR_B2[3]", "ADDR_B[3]"}, + {"ADDR_B2[4]", "ADDR_B[4]"}, + {"ADDR_B2[5]", "ADDR_B[5]"}, + {"ADDR_B2[6]", "ADDR_B[6]"}, + {"ADDR_B2[7]", "ADDR_B[7]"}, + {"ADDR_B2[8]", "ADDR_B[8]"}, + {"ADDR_B2[9]", "ADDR_B[9]"}, + {"ADDR_B2[10]", "ADDR_B[10]"}, + {"ADDR_B2[11]", "ADDR_B[11]"}, + {"ADDR_B2[12]", "ADDR_B[12]"}, + {"ADDR_B2[13]", "ADDR_B[13]"}, + {"ADDR_B2[14]", "ADDR_B[14]"}, + {"WDATA_A2[0]", "WDATA_A2[0]"}, + {"WDATA_A2[1]", "WDATA_A2[1]"}, + {"WDATA_A2[2]", "WDATA_A2[2]"}, + {"WDATA_A2[3]", "WDATA_A2[3]"}, + {"WDATA_A2[4]", "WDATA_A2[4]"}, + {"WDATA_A2[5]", "WDATA_A2[5]"}, + {"WDATA_A2[6]", "WDATA_A2[6]"}, + {"WDATA_A2[7]", "WDATA_A2[7]"}, + {"WDATA_A2[8]", "WDATA_A2[8]"}, + {"WDATA_A2[9]", "WDATA_A2[9]"}, + {"WDATA_A2[10]", "WDATA_A2[10]"}, + {"WDATA_A2[11]", "WDATA_A2[11]"}, + {"WDATA_A2[12]", "WDATA_A2[12]"}, + {"WDATA_A2[13]", "WDATA_A2[13]"}, + {"WDATA_A2[14]", "WDATA_A2[14]"}, + {"WDATA_A2[15]", "WDATA_A2[15]"}, + {"WDATA_A2[16]", "WDATA_A2[16]"}, + {"WDATA_A2[17]", "WDATA_A2[17]"}, + {"WDATA_B2[0]", "WDATA_B2[0]"}, + {"WDATA_B2[1]", "WDATA_B2[1]"}, + {"WDATA_B2[2]", "WDATA_B2[2]"}, + {"WDATA_B2[3]", "WDATA_B2[3]"}, + {"WDATA_B2[4]", "WDATA_B2[4]"}, + {"WDATA_B2[5]", "WDATA_B2[5]"}, + {"WDATA_B2[6]", "WDATA_B2[6]"}, + {"WDATA_B2[7]", "WDATA_B2[7]"}, + {"WDATA_B2[8]", "WDATA_B2[8]"}, + {"WDATA_B2[9]", "WDATA_B2[9]"}, + {"WDATA_B2[10]", "WDATA_B2[10]"}, + {"WDATA_B2[11]", "WDATA_B2[11]"}, + {"WDATA_B2[12]", "WDATA_B2[12]"}, + {"WDATA_B2[13]", "WDATA_B2[13]"}, + {"WDATA_B2[14]", "WDATA_B2[14]"}, + {"WDATA_B2[15]", "WDATA_B2[15]"}, + {"WDATA_B2[16]", "WDATA_B2[16]"}, + {"WDATA_B2[17]", "WDATA_B2[17]"}, + {"RDATA_A2[0]", "DATA_OUT_A2[0]"}, + {"RDATA_A2[1]", "DATA_OUT_A2[1]"}, + {"RDATA_A2[2]", "DATA_OUT_A2[2]"}, + {"RDATA_A2[3]", "DATA_OUT_A2[3]"}, + {"RDATA_A2[4]", "DATA_OUT_A2[4]"}, + {"RDATA_A2[5]", "DATA_OUT_A2[5]"}, + {"RDATA_A2[6]", "DATA_OUT_A2[6]"}, + {"RDATA_A2[7]", "DATA_OUT_A2[7]"}, + {"RDATA_A2[8]", "DATA_OUT_A2[8]"}, + {"RDATA_A2[9]", "DATA_OUT_A2[9]"}, + {"RDATA_A2[10]", "DATA_OUT_A2[10]"}, + {"RDATA_A2[11]", "DATA_OUT_A2[11]"}, + {"RDATA_A2[12]", "DATA_OUT_A2[12]"}, + {"RDATA_A2[13]", "DATA_OUT_A2[13]"}, + {"RDATA_A2[14]", "DATA_OUT_A2[14]"}, + {"RDATA_A2[15]", "DATA_OUT_A2[15]"}, + {"RDATA_A2[16]", "DATA_OUT_A2[16]"}, + {"RDATA_A2[17]", "DATA_OUT_A2[17]"}, + {"RDATA_B2[0]", "DATA_OUT_B2[0]"}, + {"RDATA_B2[1]", "DATA_OUT_B2[1]"}, + {"RDATA_B2[2]", "DATA_OUT_B2[2]"}, + {"RDATA_B2[3]", "DATA_OUT_B2[3]"}, + {"RDATA_B2[4]", "DATA_OUT_B2[4]"}, + {"RDATA_B2[5]", "DATA_OUT_B2[5]"}, + {"RDATA_B2[6]", "DATA_OUT_B2[6]"}, + {"RDATA_B2[7]", "DATA_OUT_B2[7]"}, + {"RDATA_B2[8]", "DATA_OUT_B2[8]"}, + {"RDATA_B2[9]", "DATA_OUT_B2[9]"}, + {"RDATA_B2[10]", "DATA_OUT_B2[10]"}, + {"RDATA_B2[11]", "DATA_OUT_B2[11]"}, + {"RDATA_B2[12]", "DATA_OUT_B2[12]"}, + {"RDATA_B2[13]", "DATA_OUT_B2[13]"}, + {"RDATA_B2[14]", "DATA_OUT_B2[14]"}, + {"RDATA_B2[15]", "DATA_OUT_B2[15]"}, + {"RDATA_B2[16]", "DATA_OUT_B2[16]"}, + {"RDATA_B2[17]", "DATA_OUT_B2[17]"}, + {"FLUSH2", "$false"}}; + std::string conf_code(std::string W) { + return W == str_36 ? "110" + : W == str_18 ? "010" + : W == str_9 ? "100" + : W == str_4 ? "001" + : W == str_2 ? "011" + : "101"; + } + std::vector TDP_RAM36K_Assigns_params_WRITE_WIDTH_A_9_4_2_1 = { + ".names WPARITY_A[0] WDATA_A1[17]", ".names $false WDATA_A1[16]", + ".names $false WDATA_A1[15]", ".names $false WDATA_A1[14]", + ".names $false WDATA_A1[13]", ".names $false WDATA_A1[12]", + ".names $false WDATA_A1[11]", ".names $false WDATA_A1[10]", + ".names $false WDATA_A1[9]", ".names WDATA_A[7] WDATA_A1[8]", + ".names WDATA_A[6] WDATA_A1[7]", ".names WDATA_A[5] WDATA_A1[6]", + ".names WDATA_A[4] WDATA_A1[5]", ".names WDATA_A[3] WDATA_A1[4]", + ".names WDATA_A[2] WDATA_A1[3]", ".names WDATA_A[1] WDATA_A1[2]", + // ".names $undef WDATA_A2[17]", + // ".names $undef WDATA_A2[16]", + // ".names $undef WDATA_A2[15]", + // ".names $undef WDATA_A2[14]", + // ".names $undef WDATA_A2[13]", + // ".names $undef WDATA_A2[12]", + // ".names $undef WDATA_A2[11]", + // ".names $undef WDATA_A2[10]", + // ".names $undef WDATA_A2[9]", + // ".names $undef WDATA_A2[8]", + // ".names $undef WDATA_A2[7]", + // ".names $undef WDATA_A2[6]", + // ".names $undef WDATA_A2[5]", + // ".names $undef WDATA_A2[4]", + // ".names $undef WDATA_A2[3]", + // ".names $undef WDATA_A2[2]", + // ".names $undef WDATA_A2[1]", + // ".names $undef WDATA_A2[0]", + ".names WDATA_A[0] WDATA_A1[1]"}; + std::vector TDP_RAM36K_Assigns_params_WRITE_WIDTH_B_9_4_2_1 = { + ".names WPARITY_B[0] WDATA_B1[17]", ".names $false WDATA_B1[16]", + ".names $false WDATA_B1[15]", ".names $false WDATA_B1[14]", + ".names $false WDATA_B1[13]", ".names $false WDATA_B1[12]", + ".names $false WDATA_B1[11]", ".names $false WDATA_B1[10]", + ".names $false WDATA_B1[9]", ".names WDATA_B[7] WDATA_B1[8]", + ".names WDATA_B[6] WDATA_B1[7]", ".names WDATA_B[5] WDATA_B1[6]", + ".names WDATA_B[4] WDATA_B1[5]", ".names WDATA_B[3] WDATA_B1[4]", + ".names WDATA_B[2] WDATA_B1[3]", ".names WDATA_B[1] WDATA_B1[2]", + // ".names $undef WDATA_B2[17]", + // ".names $undef WDATA_B2[16]", + // ".names $undef WDATA_B2[15]", + // ".names $undef WDATA_B2[14]", + // ".names $undef WDATA_B2[13]", + // ".names $undef WDATA_B2[12]", + // ".names $undef WDATA_B2[11]", + // ".names $undef WDATA_B2[10]", + // ".names $undef WDATA_B2[9]", + // ".names $undef WDATA_B2[8]", + // ".names $undef WDATA_B2[7]", + // ".names $undef WDATA_B2[6]", + // ".names $undef WDATA_B2[5]", + // ".names $undef WDATA_B2[4]", + // ".names $undef WDATA_B2[3]", + // ".names $undef WDATA_B2[2]", + // ".names $undef WDATA_B2[1]", + // ".names $undef WDATA_B2[0]", + ".names WDATA_B[0] WDATA_B1[1]"}; + std::vector TDP_RAM36K_Assigns_params_READ_WIDTH_A_9_4_2_1 = { + ".names DATA_OUT_A1[7] RDATA_A[31]", ".names DATA_OUT_A1[6] RDATA_A[30]", + ".names DATA_OUT_A1[5] RDATA_A[29]", ".names DATA_OUT_A1[4] RDATA_A[28]", + ".names DATA_OUT_A1[3] RDATA_A[27]", ".names DATA_OUT_A1[2] RDATA_A[26]", + ".names DATA_OUT_A1[1] RDATA_A[25]", ".names DATA_OUT_A1[0] RDATA_A[24]", + ".names DATA_OUT_A1[16] RPARITY_A[3]"}; + std::vector TDP_RAM36K_Assigns_params_READ_WIDTH_B_9_4_2_1 = { + ".names DATA_OUT_B1[7] RDATA_B[31]", ".names DATA_OUT_B1[6] RDATA_B[30]", + ".names DATA_OUT_B1[5] RDATA_B[29]", ".names DATA_OUT_B1[4] RDATA_B[28]", + ".names DATA_OUT_B1[3] RDATA_B[27]", ".names DATA_OUT_B1[2] RDATA_B[26]", + ".names DATA_OUT_B1[1] RDATA_B[25]", ".names DATA_OUT_B1[0] RDATA_B[24]", + ".names DATA_OUT_B1[16] RPARITY_B[3]"}; + std::vector TDP_RAM36K_Assigns_params_WRITE_WIDTH_A_36_18 = { + ".names WPARITY_A[1] WDATA_A1[17]", ".names WPARITY_A[0] WDATA_A1[16]", + ".names WDATA_A[15] WDATA_A1[15]", ".names WDATA_A[14] WDATA_A1[14]", + ".names WDATA_A[13] WDATA_A1[13]", ".names WDATA_A[12] WDATA_A1[12]", + ".names WDATA_A[11] WDATA_A1[11]", ".names WDATA_A[10] WDATA_A1[10]", + ".names WDATA_A[9] WDATA_A1[9]", ".names WDATA_A[8] WDATA_A1[8]", + ".names WDATA_A[7] WDATA_A1[7]", ".names WDATA_A[6] WDATA_A1[6]", + ".names WDATA_A[5] WDATA_A1[5]", ".names WDATA_A[4] WDATA_A1[4]", + ".names WDATA_A[3] WDATA_A1[3]", ".names WDATA_A[2] WDATA_A1[2]", + ".names WDATA_A[1] WDATA_A1[1]", ".names WDATA_A[0] WDATA_A1[0]", + ".names WPARITY_A[3] WDATA_A2[17]", ".names WPARITY_A[2] WDATA_A2[16]", + ".names WDATA_A[31] WDATA_A2[15]", ".names WDATA_A[30] WDATA_A2[14]", + ".names WDATA_A[29] WDATA_A2[13]", ".names WDATA_A[28] WDATA_A2[12]", + ".names WDATA_A[27] WDATA_A2[11]", ".names WDATA_A[26] WDATA_A2[10]", + ".names WDATA_A[25] WDATA_A2[9]", ".names WDATA_A[24] WDATA_A2[8]", + ".names WDATA_A[23] WDATA_A2[7]", ".names WDATA_A[22] WDATA_A2[6]", + ".names WDATA_A[21] WDATA_A2[5]", ".names WDATA_A[20] WDATA_A2[4]", + ".names WDATA_A[19] WDATA_A2[3]", ".names WDATA_A[18] WDATA_A2[2]", + ".names WDATA_A[17] WDATA_A2[1]", ".names WDATA_A[16] WDATA_A2[0]"}; + std::vector TDP_RAM36K_Assigns_params_WRITE_WIDTH_B_36_18 = { + ".names WPARITY_B[1] WDATA_B1[17]", ".names WPARITY_B[0] WDATA_B1[16]", + ".names WDATA_B[15] WDATA_B1[15]", ".names WDATA_B[14] WDATA_B1[14]", + ".names WDATA_B[13] WDATA_B1[13]", ".names WDATA_B[12] WDATA_B1[12]", + ".names WDATA_B[11] WDATA_B1[11]", ".names WDATA_B[10] WDATA_B1[10]", + ".names WDATA_B[9] WDATA_B1[9]", ".names WDATA_B[8] WDATA_B1[8]", + ".names WDATA_B[7] WDATA_B1[7]", ".names WDATA_B[6] WDATA_B1[6]", + ".names WDATA_B[5] WDATA_B1[5]", ".names WDATA_B[4] WDATA_B1[4]", + ".names WDATA_B[3] WDATA_B1[3]", ".names WDATA_B[2] WDATA_B1[2]", + ".names WDATA_B[1] WDATA_B1[1]", ".names WDATA_B[0] WDATA_B1[0]", + ".names WPARITY_B[3] WDATA_B2[17]", ".names WPARITY_B[2] WDATA_B2[16]", + ".names WDATA_B[31] WDATA_B2[15]", ".names WDATA_B[30] WDATA_B2[14]", + ".names WDATA_B[29] WDATA_B2[13]", ".names WDATA_B[28] WDATA_B2[12]", + ".names WDATA_B[27] WDATA_B2[11]", ".names WDATA_B[26] WDATA_B2[10]", + ".names WDATA_B[25] WDATA_B2[9]", ".names WDATA_B[24] WDATA_B2[8]", + ".names WDATA_B[23] WDATA_B2[7]", ".names WDATA_B[22] WDATA_B2[6]", + ".names WDATA_B[21] WDATA_B2[5]", ".names WDATA_B[20] WDATA_B2[4]", + ".names WDATA_B[19] WDATA_B2[3]", ".names WDATA_B[18] WDATA_B2[2]", + ".names WDATA_B[17] WDATA_B2[1]", ".names WDATA_B[16] WDATA_B2[0]"}; + std::vector TDP_RAM36K_Assigns_params_READ_WIDTH_A_36_18 = { + ".names DATA_OUT_A2[15] RDATA_A[31]", + ".names DATA_OUT_A2[14] RDATA_A[30]", + ".names DATA_OUT_A2[13] RDATA_A[29]", + ".names DATA_OUT_A2[12] RDATA_A[28]", + ".names DATA_OUT_A2[11] RDATA_A[27]", + ".names DATA_OUT_A2[10] RDATA_A[26]", + ".names DATA_OUT_A2[9] RDATA_A[25]", + ".names DATA_OUT_A2[8] RDATA_A[24]", + ".names DATA_OUT_A2[7] RDATA_A[23]", + ".names DATA_OUT_A2[6] RDATA_A[22]", + ".names DATA_OUT_A2[5] RDATA_A[21]", + ".names DATA_OUT_A2[4] RDATA_A[20]", + ".names DATA_OUT_A2[3] RDATA_A[19]", + ".names DATA_OUT_A2[2] RDATA_A[18]", + ".names DATA_OUT_A2[1] RDATA_A[17]", + ".names DATA_OUT_A2[0] RDATA_A[16]", + ".names DATA_OUT_A1[15] RDATA_A[15]", + ".names DATA_OUT_A1[14] RDATA_A[14]", + ".names DATA_OUT_A1[13] RDATA_A[13]", + ".names DATA_OUT_A1[12] RDATA_A[12]", + ".names DATA_OUT_A1[11] RDATA_A[11]", + ".names DATA_OUT_A1[10] RDATA_A[10]", + ".names DATA_OUT_A1[9] RDATA_A[9]", + ".names DATA_OUT_A1[8] RDATA_A[8]", + ".names DATA_OUT_A1[7] RDATA_A[7]", + ".names DATA_OUT_A1[6] RDATA_A[6]", + ".names DATA_OUT_A1[5] RDATA_A[5]", + ".names DATA_OUT_A1[4] RDATA_A[4]", + ".names DATA_OUT_A1[3] RDATA_A[3]", + ".names DATA_OUT_A1[2] RDATA_A[2]", + ".names DATA_OUT_A1[1] RDATA_A[1]", + ".names DATA_OUT_A1[0] RDATA_A[0]", + ".names DATA_OUT_A2[17] RPARITY_A[3]", + ".names DATA_OUT_A2[16] RPARITY_A[2]", + ".names DATA_OUT_A1[17] RPARITY_A[1]", + ".names DATA_OUT_A1[16] RPARITY_A[0]"}; + std::vector TDP_RAM36K_Assigns_params_READ_WIDTH_B_36_18 = { + ".names DATA_OUT_B2[15] RDATA_B[31]", + ".names DATA_OUT_B2[14] RDATA_B[30]", + ".names DATA_OUT_B2[13] RDATA_B[29]", + ".names DATA_OUT_B2[12] RDATA_B[28]", + ".names DATA_OUT_B2[11] RDATA_B[27]", + ".names DATA_OUT_B2[10] RDATA_B[26]", + ".names DATA_OUT_B2[9] RDATA_B[25]", + ".names DATA_OUT_B2[8] RDATA_B[24]", + ".names DATA_OUT_B2[7] RDATA_B[23]", + ".names DATA_OUT_B2[6] RDATA_B[22]", + ".names DATA_OUT_B2[5] RDATA_B[21]", + ".names DATA_OUT_B2[4] RDATA_B[20]", + ".names DATA_OUT_B2[3] RDATA_B[19]", + ".names DATA_OUT_B2[2] RDATA_B[18]", + ".names DATA_OUT_B2[1] RDATA_B[17]", + ".names DATA_OUT_B2[0] RDATA_B[16]", + ".names DATA_OUT_B1[15] RDATA_B[15]", + ".names DATA_OUT_B1[14] RDATA_B[14]", + ".names DATA_OUT_B1[13] RDATA_B[13]", + ".names DATA_OUT_B1[12] RDATA_B[12]", + ".names DATA_OUT_B1[11] RDATA_B[11]", + ".names DATA_OUT_B1[10] RDATA_B[10]", + ".names DATA_OUT_B1[9] RDATA_B[9]", + ".names DATA_OUT_B1[8] RDATA_B[8]", + ".names DATA_OUT_B1[7] RDATA_B[7]", + ".names DATA_OUT_B1[6] RDATA_B[6]", + ".names DATA_OUT_B1[5] RDATA_B[5]", + ".names DATA_OUT_B1[4] RDATA_B[4]", + ".names DATA_OUT_B1[3] RDATA_B[3]", + ".names DATA_OUT_B1[2] RDATA_B[2]", + ".names DATA_OUT_B1[1] RDATA_B[1]", + ".names DATA_OUT_B1[0] RDATA_B[0]", + ".names DATA_OUT_B2[17] RPARITY_B[3]", + ".names DATA_OUT_B2[16] RPARITY_B[2]", + ".names DATA_OUT_B1[17] RPARITY_B[1]", + ".names DATA_OUT_B1[16] RPARITY_B[0]"}; + std::unordered_map> assign_map = { + {"WRITE_WIDTH_A_9_4_2_1", + TDP_RAM36K_Assigns_params_WRITE_WIDTH_A_9_4_2_1}, + {"WRITE_WIDTH_B_9_4_2_1", + TDP_RAM36K_Assigns_params_WRITE_WIDTH_B_9_4_2_1}, + {"READ_WIDTH_A_9_4_2_1", TDP_RAM36K_Assigns_params_READ_WIDTH_A_9_4_2_1}, + {"READ_WIDTH_B_9_4_2_1", TDP_RAM36K_Assigns_params_READ_WIDTH_B_9_4_2_1}, + {"WRITE_WIDTH_A_36_18", TDP_RAM36K_Assigns_params_WRITE_WIDTH_A_36_18}, + {"WRITE_WIDTH_B_36_18", TDP_RAM36K_Assigns_params_WRITE_WIDTH_B_36_18}, + {"READ_WIDTH_A_36_18", TDP_RAM36K_Assigns_params_READ_WIDTH_A_36_18}, + {"READ_WIDTH_B_36_18", TDP_RAM36K_Assigns_params_READ_WIDTH_B_36_18}, + {"DEFAULT", std::vector()}}; + std::vector &get_param_value_assigns(std::string p) { + if (parameters.find(p) == end(parameters)) + throw std::invalid_argument("Invalid TDP_RAM36K parameter name " + p); + std::unordered_set _9_4_2_1 = {str_1, str_2, str_4, str_9}; + std::unordered_set _36_18 = {str_18, str_36}; + if (_9_4_2_1.find(parameters[p]) != end(_9_4_2_1)) { + return assign_map[p + "_9_4_2_1"]; + }; + if (_36_18.find(parameters[p]) != end(_36_18)) { + return assign_map[p + "_36_18"]; + }; + return assign_map["DEFAULT"]; + } + std::string get_MODE_BITS() { + read_mode_A = conf_code(parameters["READ_WIDTH_A"]); + read_mode_B = conf_code(parameters["WRITE_WIDTH_B"]); + write_mode_A = conf_code(parameters["WRITE_WIDTH_A"]); + write_mode_B = conf_code(parameters["WRITE_WIDTH_B"]); + std::string MODE_BITS = std::string("0") + read_mode_A + read_mode_B + + write_mode_A + write_mode_B + std::string(29, '0') + + read_mode_A + read_mode_B + write_mode_A + + write_mode_B + std::string(27, '0'); + return MODE_BITS; + }; + + void print(std::ostream &ofs) { + static unsigned cnt = 0; + cnt++; + std::string rs_prim = "RS_TDP36K"; + ofs << ".subckt " << rs_prim << " "; + for (auto &cn : TDP_RAM36K_to_RS_TDP36K_port_map) { + ofs << " " << cn.first; + if (port_connections.find(cn.second) != port_connections.end()) { + + ofs << "=" << port_connections[cn.second]; + } else { + ofs << "=" << per_instance_sig_name(cn.second, cnt); + } + } + ofs << std::endl; + ofs << ".param MODE_BITS " << get_MODE_BITS() << std::endl; + ofs << ".param INIT_i " + << get_init_i1(parameters["INIT"], parameters["INIT_PARITY"]) + << std::endl; + for (auto &p : parameters) { + if (p.first.find("READ") == 0 || p.first.find("WRITE") == 0) { + for (auto &assign : get_param_value_assigns(p.first)) { + bool connected = true; + std::vector tokens = split_on_space(assign); + std::string f_i_name = per_instance_sig_name(tokens[1], cnt); + std::string s_i_name = per_instance_sig_name(tokens[2], cnt); + if (f_i_name == tokens[1]) { + if (port_connections.find(f_i_name) != port_connections.end()) { + f_i_name = port_connections[f_i_name]; + } else { + connected = false; + } + } + if (s_i_name == tokens[2]) { + if (port_connections.find(s_i_name) != port_connections.end()) { + s_i_name = port_connections[s_i_name]; + } else { + connected = false; + } + } + if (connected) { + ofs << tokens[0] << " " << f_i_name << " " << s_i_name << "\n1 1\n"; + } + } + } + } + } + std::string extract_sram1(const std::string &init, + const std::string &init_parity) { + if (init.size() < parameterSize["INIT"] || + init_parity.size() < parameterSize["INIT_PARITY"]) { + return ""; // Not enough init size + } + std::string sram1(18432, '0'); + + for (int i = 0; i < 2048; i += 2) { + sram1.replace((i * 9), 16, init.substr(i * 16, 16)); + sram1.replace(((i + 2) * 9) - 2, 2, init_parity.substr(i * 2, 2)); + } + + return sram1; + } + + std::string extract_sram2(const std::string &init, + const std::string &init_parity) { + std::string sram2(18432, '0'); + + for (int i = 1; i < 2048; i += 2) { + sram2.replace((i - 1) * 9, 16, init.substr(i * 16, 16)); + sram2.replace(((i + 1) * 9) - 2, 2, init_parity.substr(i * 2, 2)); + } + + return sram2; + } + + std::string get_init_i1(const std::string &init, + const std::string &init_parity) { + return extract_sram2(init, init_parity) + extract_sram1(init, init_parity); + } + std::unordered_map port_connections; +}; diff --git a/include/eblif_tranform/reconstruct_utils.h b/include/eblif_tranform/reconstruct_utils.h new file mode 100644 index 00000000..70b2386b --- /dev/null +++ b/include/eblif_tranform/reconstruct_utils.h @@ -0,0 +1,35 @@ +#pragma once +/** + * @file reconstruct_utils.h + * @author Manadher Kharroubi (manadher@gmail.com) + * @brief + * @version 0.1 + * @date 2024-01- + * + * @copyright Copyright (c) 2024 +*/ +#include "boost/multiprecision/cpp_int.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace boost::multiprecision; +using namespace std; +std::vector split_on_space(const std::string &line) { + std::vector tokens; + std::stringstream ss(line); + std::string token; + while (ss >> token) { + tokens.push_back(token); + } + return tokens; +} diff --git a/include/eblif_tranform/transform_blif.h b/include/eblif_tranform/transform_blif.h index 4f5e0147..af665973 100644 --- a/include/eblif_tranform/transform_blif.h +++ b/include/eblif_tranform/transform_blif.h @@ -1,80 +1,36 @@ +#pragma once /** * @file transforme_blif.h * @author Manadher Kharroubi (manadher@gmail.com) * @brief * @version 0.1 - * @date 2023-09-13 + * @date 2024-01- * - * @copyright Copyright (c) 2023 + * @copyright Copyright (c) 2024 * */ -#include "boost/multiprecision/cpp_int.hpp" -#include -#include -#include -#include // std::cout -#include -#include -#include -#include -#include -#include - -using namespace boost::multiprecision; - -using namespace std; +#include "reconstruct_dsp38.h" +#include "reconstruct_ram18kx2.h" +#include "reconstruct_ram36k.h" class Eblif_Transformer { - struct dsp38_instance { - - std::unordered_map parameters = { - {"COEFF_0", "00000000000000000000"}, - {"COEFF_1", "00000000000000000000"}, - {"COEFF_2", "00000000000000000000"}, - {"COEFF_3", "00000000000000000000"}, - {"DSP_MODE", "MULTIPLY_ACCUMULATE"}, - {"OUTPUT_REG_EN", "FALSE"}, - {"INPUT_REG_EN", "FALSE"}, - {"accumulator", "0"}, - {"adder", "0"}, - {"output_reg", "0"}, - {"input_reg", "0"}}; - - bool set_param(const std::string &par_name, std::string value) { - if (parameters.find(par_name) != end(parameters)) { - parameters[par_name] = value; - if (par_name == "DSP_MODE") { - if (value == "MULTIPLY_ACCUMULATE") - parameters["accumulator"] = "1"; - if (value == "MULTIPLY_ADD_SUB") - parameters["adder"] = "1"; - } else if (par_name == "OUTPUT_REG_EN") { - if (value == "TRUE") - parameters["output_reg"] = "1"; - } else if (par_name == "INPUT_REG_EN") { - if (value == "TRUE") - parameters["input_reg"] = "1"; - } - return true; - } - return false; - } - - std::string get_MODE_BITS() { - return parameters["COEFF_0"] + parameters["COEFF_1"] + - parameters["COEFF_2"] + parameters["COEFF_3"]; - } - - std::string get_block_key() { - return parameters["accumulator"] + parameters["adder"] + - parameters["output_reg"] + parameters["input_reg"]; + std::vector TDP_RAM18KX2_instances; + std::vector TDP_RAM36K_instances; + std::vector dsp38_instances; + unsigned uint_from_bits(std::string bits) { + if (!bits.size() || bits.size() > 31) + throw std::invalid_argument("Invalid 32 bit binary number "); + unsigned pw = 1, res = 0; + for (int i = bits.size() - 1; i + 1; --i) { + if (bits[i] == '1') + res += pw; + else if (bits[i] != '0') + throw std::invalid_argument("Invalid character in a binary number : " + + std::string(1, bits[i])); + pw <<= 1; } - - std::unordered_map port_connections; + return res; }; - std::vector dsp38_instances; - -public: std::unordered_map blifToCPlusPlusMap(const std::vector &tokens) { std::unordered_map res; @@ -116,7 +72,6 @@ class Eblif_Transformer { /* This is a binary word param */ return true; } - bool is_real_param_(const std::string ¶m) { /* Must be non-empty */ if (param.empty()) { @@ -161,7 +116,6 @@ class Eblif_Transformer { str = &dd[2]; return strtoull(str, &stops, bb); } - string bitsOfHexaDecimal(string &s) { if (!s.size()) { throw(std::invalid_argument( @@ -181,7 +135,6 @@ class Eblif_Transformer { } return res; } - int1024_t bigDecimalInteger(string &s) { if (!s.size()) { throw(std::invalid_argument( @@ -274,7 +227,6 @@ class Eblif_Transformer { vec_.push_back(vec[vIdx]); } } - std::vector entryTruth(unsigned long long e, unsigned long long w) { std::vector res(w, 0); unsigned p = 1; @@ -286,7 +238,6 @@ class Eblif_Transformer { } return res; } - void simpleTruthTable(std::string tr, std::string w, std::vector> &vec) { if (is_binary_param_(w)) @@ -306,14 +257,12 @@ class Eblif_Transformer { } } } - void vector_print(std::ostream &f, vector &vec) { for (auto n : vec) { f << " " << n; } f << std::endl; } - struct names_str { std::string Y = ""; std::vector A; @@ -333,24 +282,117 @@ class Eblif_Transformer { } } }; + // Latch flattening + std::unordered_map latch_lut_LUT_strs = { + {"LATCH", "10101100"}, + {"LATCHN", "10101100"}, + {"LATCHR", "0000101000001100"}, + {"LATCHS", "1111101011111100"}, + {"LATCHNR", "0000101000001100"}, + {"LATCHNS", "1111101011111100"}, + {"LATCHSRE", + "1011101111110011111100111111001100000000000000000000000000000000"}, + {"LATCHNSRE", + "1111001110111011111100111111001100000000000000000000000000000000"}}; + std::unordered_map latch_lut_WIDTH_strs = { + {"LATCH", "3"}, {"LATCHN", "3"}, {"LATCHR", "4"}, + {"LATCHS", "4"}, {"LATCHNR", "4"}, {"LATCHNS", "4"}, + {"LATCHSRE", "6"}, {"LATCHNSRE", "6"}}; + std::unordered_map latch_ports = { + {"LATCH", "DGQ"}, {"LATCHN", "DGQ"}, {"LATCHR", "DGRQ"}, + {"LATCHS", "DGRQ"}, {"LATCHNR", "DGRQ"}, {"LATCHNS", "DGRQ"}, + {"LATCHSRE", "QSRDGE"}, {"LATCHNSRE", "QSRDGE"}}; + std::unordered_map lut_A_port_connections = { + {"LATCH", "GQD"}, {"LATCHN", "GDQ"}, {"LATCHR", "GRQD"}, + {"LATCHS", "GRQD"}, {"LATCHNR", "GRDQ"}, {"LATCHNS", "GRDQ"}, + {"LATCHSRE", "RGEQSD"}, {"LATCHNSRE", "REGQSD"}}; + std::unordered_map lut_port_map_LATCH{ + {"G", "A[2]"}, {"Q", "A[1]"}, {"D", "A[0]"}}; + std::unordered_map lut_port_map_LATCHN{ + {"G", "A[2]"}, {"D", "A[1]"}, {"Q", "A[0]"}}; + std::unordered_map lut_port_map_LATCHR{ + {"G", "A[3]"}, {"R", "A[2]"}, {"Q", "A[1]"}, {"D", "A[0]"}}; + std::unordered_map lut_port_map_LATCHS{ + {"G", "A[3]"}, {"R", "A[2]"}, {"Q", "A[1]"}, {"D", "A[0]"}}; + std::unordered_map lut_port_map_LATCHNR{ + {"G", "A[3]"}, {"R", "A[2]"}, {"D", "A[1]"}, {"Q", "A[0]"}}; + std::unordered_map lut_port_map_LATCHNS{ + {"G", "A[3]"}, {"R", "A[2]"}, {"D", "A[1]"}, {"Q", "A[0]"}}; + std::unordered_map lut_port_map_LATCHSRE{ + {"R", "A[5]"}, {"G", "A[4]"}, {"E", "A[3]"}, + {"Q", "A[2]"}, {"S", "A[1]"}, {"D", "A[0]"}}; + std::unordered_map lut_port_map_LATCHNSRE{ + {"R", "A[5]"}, {"E", "A[4]"}, {"G", "A[3]"}, + {"Q", "A[2]"}, {"S", "A[1]"}, {"D", "A[0]"}}; + std::unordered_map> + latch_lut_port_conversion{{"LATCH", lut_port_map_LATCH}, + {"LATCHN", lut_port_map_LATCHN}, + {"LATCHR", lut_port_map_LATCHR}, + {"LATCHS", lut_port_map_LATCHS}, + {"LATCHNR", lut_port_map_LATCHNR}, + {"LATCHNS", lut_port_map_LATCHNS}, + {"LATCHSRE", lut_port_map_LATCHSRE}, + {"LATCHNSRE", lut_port_map_LATCHNSRE}}; + string mx = "179769313486231590772930519078902473361797697894230657273" + "43008115773267580" + "550096313270847732240753602112011387987139335765878976881" + "44166224928474306" + "394741243777678934248654852763022196012460941194530829520" + "85005768838150682" + "342462881473913110540827237163350510684586298239947245938" + "47971630483535632" + "9624224137215"; + std::map hexDecoder = { + {'0', "0000"}, {'1', "0001"}, {'2', "0010"}, {'3', "0011"}, {'4', "0100"}, + {'5', "0101"}, {'6', "0110"}, {'7', "0111"}, {'8', "1000"}, {'9', "1001"}, + {'A', "1010"}, {'B', "1011"}, {'C', "1100"}, {'D', "1101"}, {'E', "1110"}, + {'F', "1111"}, {'X', "xxxx"}, {'a', "1010"}, {'b', "1011"}, {'c', "1100"}, + {'d', "1101"}, {'e', "1110"}, {'f', "1111"}, {'x', "xxxx"}}; + std::unordered_map verilog_dsp_int_names = { + {"RS_DSP_MULT", + " DSP38 #(\n .DSP_MODE(\"MULTIPY\"),\n " + ".OUTPUT_REG_EN(\"FALSE\"),\n .INPUT_REG_EN(\"FALSE\")"}, + {"RS_DSP_MULT_REGIN", + " DSP38 #(\n .DSP_MODE(\"MULTIPY\"),\n " + ".OUTPUT_REG_EN(\"FALSE\"),\n .INPUT_REG_EN(\"TRUE\")"}, + {"RS_DSP_MULT_REGOUT", + " DSP38 #(\n .DSP_MODE(\"MULTIPY\"),\n " + ".OUTPUT_REG_EN(\"TRUE\"),\n .INPUT_REG_EN(\"FALSE\")"}, + {"RS_DSP_MULT_REGIN_REGOUT", + " DSP38 #(\n .DSP_MODE(\"MULTIPY\"),\n " + ".OUTPUT_REG_EN(\"TRUE\"),\n .INPUT_REG_EN(\"TRUE\")"}, + {"RS_DSP_MULTADD", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ADD_SUB\"),\n " + ".OUTPUT_REG_EN(\"FALSE\"),\n .INPUT_REG_EN(\"FALSE\")"}, + {"RS_DSP_MULTADD_REGIN", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ADD_SUB\"),\n " + ".OUTPUT_REG_EN(\"FALSE\"),\n .INPUT_REG_EN(\"TRUE\")"}, + {"RS_DSP_MULTADD_REGOUT", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ADD_SUB\"),\n " + ".OUTPUT_REG_EN(\"TRUE\"),\n .INPUT_REG_EN(\"FALSE\")"}, + {"RS_DSP_MULTADD_REGIN_REGOUT", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ADD_SUB\"),\n " + ".OUTPUT_REG_EN(\"TRUE\"),\n .INPUT_REG_EN(\"TRUE\")"}, + {"RS_DSP_MULTACC", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ACCUMULATE\"),\n " + ".OUTPUT_REG_EN(\"FALSE\"),\n .INPUT_REG_EN(\"FALSE\")"}, + {"RS_DSP_MULTACC_REGIN", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ACCUMULATE\"),\n " + ".OUTPUT_REG_EN(\"FALSE\"),\n .INPUT_REG_EN(\"TRUE\")"}, + {"RS_DSP_MULTACC_REGOUT", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ACCUMULATE\"),\n " + ".OUTPUT_REG_EN(\"TRUE\"),\n .INPUT_REG_EN(\"FALSE\")"}, + {"RS_DSP_MULTACC_REGIN_REGOUT", + " DSP38 #(\n .DSP_MODE(\"MULTIPLY_ACCUMULATE\"),\n " + ".OUTPUT_REG_EN(\"TRUE\"),\n .INPUT_REG_EN(\"TRUE\")"}}; - std::vector split_on_space(const std::string &line) { - std::vector tokens; - std::stringstream ss(line); - std::string token; - while (ss >> token) { - tokens.push_back(token); - } - return tokens; - } - +public: void rs_transform_eblif(std::istream &ifs, std::ostream &ofs) { - + // port_case_compare(); + // return; + std::string last_ckt = ""; std::string line; while (std::getline(ifs, line)) { - if (line.empty()) { - continue; - } std::string ln(line); while ('\\' == ln.back() && std::getline(ifs, line)) { ln.pop_back(); @@ -379,25 +421,27 @@ class Eblif_Transformer { par_value[idx] = par_value[idx + 1]; par_value.pop_back(); } - if (dsp38_instances.size() && + if (last_ckt == "dsp38" && dsp38_instances.size() && dsp38_instances.back().set_param(par_name, par_value)) { + } else if (last_ckt == "tdp_ram18kx2" && + TDP_RAM18KX2_instances.size() && + TDP_RAM18KX2_instances.back().set_param(par_name, + par_value)) { + } else if (last_ckt == "tdp_ram36k" && TDP_RAM36K_instances.size() && + TDP_RAM36K_instances.back().set_param(par_name, + par_value)) { } else { ofs << ln << "\n"; } } else if (tokens[0] == ".end") { for (auto &ds : dsp38_instances) { - std::string rs_prim = RS_DSP_Primitives.at(ds.get_block_key()); - ofs << ".subckt " << rs_prim << " "; - for (auto &cn : ds.port_connections) { - if (prim_io_maps_dsp_to_rs_prim[rs_prim].find(cn.first) != - end(prim_io_maps_dsp_to_rs_prim[rs_prim])) { - std::string at_prim = - prim_io_maps_dsp_to_rs_prim[rs_prim][cn.first]; - ofs << at_prim << "=" << cn.second << " "; - } - } - ofs << std::endl; - ofs << ".param MODE_BITS " << ds.get_MODE_BITS() << std::endl; + ds.print(ofs); + } + for (auto &rm : TDP_RAM18KX2_instances) { + rm.print(ofs); + } + for (auto &rm : TDP_RAM36K_instances) { + rm.print(ofs); } ofs << ln << "\n"; @@ -407,6 +451,7 @@ class Eblif_Transformer { continue; } if (tokens[0] == ".subckt") { + last_ckt = ""; std::string name = tokens[1]; std::transform(name.begin(), name.end(), name.begin(), ::tolower); if (name.find("dff") != std::string::npos || @@ -414,13 +459,15 @@ class Eblif_Transformer { name == std::string("carry")) { if (name == std::string("carry")) { name = std::string("adder_carry"); - for(int i =2; i < tokens.size(); ++i){ + for (int i = 2; i < tokens.size(); ++i) { auto itr = tokens[i].find('='); - if(std::string::npos == itr){ + if (std::string::npos == itr) { continue; } - std::transform(tokens[i].begin(),tokens[i].begin() + itr, tokens[i].begin(), ::tolower); - if(tokens[i].size() > 2 && tokens[i][0] == 'o' && tokens[i][1] == '='){ + std::transform(tokens[i].begin(), tokens[i].begin() + itr, + tokens[i].begin(), ::tolower); + if (tokens[i].size() > 2 && tokens[i][0] == 'o' && + tokens[i][1] == '=') { tokens[i] = std::string("sumout=") + tokens[i].substr(2); } } @@ -533,8 +580,19 @@ class Eblif_Transformer { ofs << "\n"; } } else if (name.find("dsp38") == 0) { + last_ckt = "dsp38"; dsp38_instances.push_back(dsp38_instance()); dsp38_instances.back().port_connections = blifToCPlusPlusMap(tokens); + } else if (name.find("tdp_ram18kx2") == 0) { + last_ckt = "tdp_ram18kx2"; + TDP_RAM18KX2_instances.push_back(TDP_RAM18KX2_instance()); + TDP_RAM18KX2_instances.back().port_connections = + blifToCPlusPlusMap(tokens); + } else if (name.find("tdp_ram36k") == 0) { + last_ckt = "tdp_ram36k"; + TDP_RAM36K_instances.push_back(TDP_RAM36K_instance()); + TDP_RAM36K_instances.back().port_connections = + blifToCPlusPlusMap(tokens); } else { for (auto &t : tokens) { ofs << t << " "; @@ -546,18 +604,66 @@ class Eblif_Transformer { } } } - - void transform_files(std::string in_file, std::string out_file) { + void rs_transform_verilog(std::istream &ifs, std::ostream &ofs) { + std::string line; + bool within_rs_dsp = false; + while (std::getline(ifs, line)) { + std::string ln(line); + while ('\\' == ln.back() && std::getline(ifs, line)) { + ln.pop_back(); + ln += " " + line; + } + auto tokens = split_on_space(ln); + if (!tokens.size()) { + // If failed to tokenize, Write the line as is and get the next line + ofs << line << "\n"; + continue; + } + if (verilog_dsp_int_names.find(tokens[0]) != end(verilog_dsp_int_names)) { + within_rs_dsp = true, ofs << verilog_dsp_int_names[tokens[0]] << ",\n"; + } else if (tokens[0] == ");") { + within_rs_dsp = false; + ofs << line << "\n"; + } else if (within_rs_dsp && '.' == tokens[0][0]) { + auto par_pos = tokens[0].find('('); + // Error if not found + transform(tokens[0].begin(), tokens[0].begin() + par_pos, + tokens[0].begin(), ::toupper); + + ofs << " "; + if (tokens[0].find(std::string(".LRESET")) == 0) { + ofs << ".RESET" << tokens[0].substr(par_pos); + for (int idx = 1; idx < tokens.size(); ++idx) { + ofs << tokens[idx]; + } + } else if (tokens[0].find(std::string(".SATURATE_ENABLE")) == 0) { + ofs << ".SATURATE" << tokens[0].substr(par_pos); + for (int idx = 1; idx < tokens.size(); ++idx) { + ofs << tokens[idx]; + } + } else + for (auto &a : tokens) { + ofs << a << " "; + } + ofs << "\n"; + } else { + ofs << line << "\n"; + } + } + } + void transform_files(std::string in_file, std::string out_file, + bool isblif = true) { std::ifstream ifs(in_file); std::ofstream ofs(out_file); - - rs_transform_eblif(ifs, ofs); - + if (isblif) { + rs_transform_eblif(ifs, ofs); + } else { + rs_transform_verilog(ifs, ofs); + } ifs.close(); ofs.close(); } - void printFileContents(FILE *pf, FILE *pfout = nullptr, bool close = false) { if (!pf) { std::cerr << "Invalid file pointer!" << std::endl; @@ -582,7 +688,6 @@ class Eblif_Transformer { if (close) fclose(pf); // Close the memory stream. } - inline FILE *open_and_transform_eblif(const char *filename) { // FILE* infile = std::fopen(filename, "r"); // int fd = fileno(infile); @@ -592,2513 +697,10 @@ class Eblif_Transformer { ss << ""; // Call transform function rs_transform_eblif(fstr, ss); - // std::cout << ss.str() << std::endl << std::endl; std::string data = ss.str(); - // std::cout << data << std::endl << std::endl; FILE *infile = fmemopen((void *)data.c_str(), data.size(), "r"); printFileContents(infile); return infile; } - -private: - // DSP38 - std::unordered_map RS_DSP_Primitives{ - {"0000", "RS_DSP_MULT"}, - {"1111", "RS_DSP_MULT"}, - {"1110", "RS_DSP_MULT"}, - {"1101", "RS_DSP_MULT"}, - {"1100", "RS_DSP_MULT"}, - {"1011", "RS_DSP_MULTACC_REGIN_REGOUT"}, - {"1010", "RS_DSP_MULTACC_REGOUT"}, - {"1001", "RS_DSP_MULTACC_REGIN"}, - {"1000", "RS_DSP_MULTACC"}, - {"0111", "RS_DSP_MULTADD_REGIN_REGOUT"}, - {"0110", "RS_DSP_MULTADD_REGOUT"}, - {"0101", "RS_DSP_MULTADD_REGIN"}, - {"0100", "RS_DSP_MULTADD"}, - {"0011", "RS_DSP_MULT_REGIN_REGOUT"}, - {"0010", "RS_DSP_MULT_REGOUT"}, - {"0001", "RS_DSP_MULT_REGIN"}}; - std::unordered_map RS_DSP_MULT_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}}; - std::unordered_map - RS_DSP_MULTACC_REGIN_REGOUT_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULTACC_REGOUT_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULTACC_REGIN_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULTACC_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map - RS_DSP_MULTADD_REGIN_REGOUT_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"dly_b[0]", "DLY_B[0]"}, - {"dly_b[1]", "DLY_B[1]"}, - {"dly_b[2]", "DLY_B[2]"}, - {"dly_b[3]", "DLY_B[3]"}, - {"dly_b[4]", "DLY_B[4]"}, - {"dly_b[5]", "DLY_B[5]"}, - {"dly_b[6]", "DLY_B[6]"}, - {"dly_b[7]", "DLY_B[7]"}, - {"dly_b[8]", "DLY_B[8]"}, - {"dly_b[9]", "DLY_B[9]"}, - {"dly_b[10]", "DLY_B[10]"}, - {"dly_b[11]", "DLY_B[11]"}, - {"dly_b[12]", "DLY_B[12]"}, - {"dly_b[13]", "DLY_B[13]"}, - {"dly_b[14]", "DLY_B[14]"}, - {"dly_b[15]", "DLY_B[15]"}, - {"dly_b[16]", "DLY_B[16]"}, - {"dly_b[17]", "DLY_B[17]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"acc_fir[0]", "ACC_FIR[0]"}, - {"acc_fir[1]", "ACC_FIR[1]"}, - {"acc_fir[2]", "ACC_FIR[2]"}, - {"acc_fir[3]", "ACC_FIR[3]"}, - {"acc_fir[4]", "ACC_FIR[4]"}, - {"acc_fir[5]", "ACC_FIR[5]"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULTADD_REGOUT_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"dly_b[0]", "DLY_B[0]"}, - {"dly_b[1]", "DLY_B[1]"}, - {"dly_b[2]", "DLY_B[2]"}, - {"dly_b[3]", "DLY_B[3]"}, - {"dly_b[4]", "DLY_B[4]"}, - {"dly_b[5]", "DLY_B[5]"}, - {"dly_b[6]", "DLY_B[6]"}, - {"dly_b[7]", "DLY_B[7]"}, - {"dly_b[8]", "DLY_B[8]"}, - {"dly_b[9]", "DLY_B[9]"}, - {"dly_b[10]", "DLY_B[10]"}, - {"dly_b[11]", "DLY_B[11]"}, - {"dly_b[12]", "DLY_B[12]"}, - {"dly_b[13]", "DLY_B[13]"}, - {"dly_b[14]", "DLY_B[14]"}, - {"dly_b[15]", "DLY_B[15]"}, - {"dly_b[16]", "DLY_B[16]"}, - {"dly_b[17]", "DLY_B[17]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"acc_fir[0]", "ACC_FIR[0]"}, - {"acc_fir[1]", "ACC_FIR[1]"}, - {"acc_fir[2]", "ACC_FIR[2]"}, - {"acc_fir[3]", "ACC_FIR[3]"}, - {"acc_fir[4]", "ACC_FIR[4]"}, - {"acc_fir[5]", "ACC_FIR[5]"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULTADD_REGIN_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"dly_b[0]", "DLY_B[0]"}, - {"dly_b[1]", "DLY_B[1]"}, - {"dly_b[2]", "DLY_B[2]"}, - {"dly_b[3]", "DLY_B[3]"}, - {"dly_b[4]", "DLY_B[4]"}, - {"dly_b[5]", "DLY_B[5]"}, - {"dly_b[6]", "DLY_B[6]"}, - {"dly_b[7]", "DLY_B[7]"}, - {"dly_b[8]", "DLY_B[8]"}, - {"dly_b[9]", "DLY_B[9]"}, - {"dly_b[10]", "DLY_B[10]"}, - {"dly_b[11]", "DLY_B[11]"}, - {"dly_b[12]", "DLY_B[12]"}, - {"dly_b[13]", "DLY_B[13]"}, - {"dly_b[14]", "DLY_B[14]"}, - {"dly_b[15]", "DLY_B[15]"}, - {"dly_b[16]", "DLY_B[16]"}, - {"dly_b[17]", "DLY_B[17]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"acc_fir[0]", "ACC_FIR[0]"}, - {"acc_fir[1]", "ACC_FIR[1]"}, - {"acc_fir[2]", "ACC_FIR[2]"}, - {"acc_fir[3]", "ACC_FIR[3]"}, - {"acc_fir[4]", "ACC_FIR[4]"}, - {"acc_fir[5]", "ACC_FIR[5]"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULTADD_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"dly_b[0]", "DLY_B[0]"}, - {"dly_b[1]", "DLY_B[1]"}, - {"dly_b[2]", "DLY_B[2]"}, - {"dly_b[3]", "DLY_B[3]"}, - {"dly_b[4]", "DLY_B[4]"}, - {"dly_b[5]", "DLY_B[5]"}, - {"dly_b[6]", "DLY_B[6]"}, - {"dly_b[7]", "DLY_B[7]"}, - {"dly_b[8]", "DLY_B[8]"}, - {"dly_b[9]", "DLY_B[9]"}, - {"dly_b[10]", "DLY_B[10]"}, - {"dly_b[11]", "DLY_B[11]"}, - {"dly_b[12]", "DLY_B[12]"}, - {"dly_b[13]", "DLY_B[13]"}, - {"dly_b[14]", "DLY_B[14]"}, - {"dly_b[15]", "DLY_B[15]"}, - {"dly_b[16]", "DLY_B[16]"}, - {"dly_b[17]", "DLY_B[17]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}, - {"acc_fir[0]", "ACC_FIR[0]"}, - {"acc_fir[1]", "ACC_FIR[1]"}, - {"acc_fir[2]", "ACC_FIR[2]"}, - {"acc_fir[3]", "ACC_FIR[3]"}, - {"acc_fir[4]", "ACC_FIR[4]"}, - {"acc_fir[5]", "ACC_FIR[5]"}, - {"load_acc", "LOAD_ACC"}, - {"saturate_enable", "SATURATE"}, - {"shift_right[0]", "SHIFT_RIGHT[0]"}, - {"shift_right[1]", "SHIFT_RIGHT[1]"}, - {"shift_right[2]", "SHIFT_RIGHT[2]"}, - {"shift_right[3]", "SHIFT_RIGHT[3]"}, - {"shift_right[4]", "SHIFT_RIGHT[4]"}, - {"shift_right[5]", "SHIFT_RIGHT[5]"}, - {"round", "ROUND"}, - {"subtract", "SUBTRACT"}}; - std::unordered_map RS_DSP_MULT_REGIN_REGOUT_io_map = - {{"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}}; - std::unordered_map RS_DSP_MULT_REGOUT_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}}; - std::unordered_map RS_DSP_MULT_REGIN_io_map = { - {"a[0]", "A[0]"}, - {"a[1]", "A[1]"}, - {"a[2]", "A[2]"}, - {"a[3]", "A[3]"}, - {"a[4]", "A[4]"}, - {"a[5]", "A[5]"}, - {"a[6]", "A[6]"}, - {"a[7]", "A[7]"}, - {"a[8]", "A[8]"}, - {"a[9]", "A[9]"}, - {"a[10]", "A[10]"}, - {"a[11]", "A[11]"}, - {"a[12]", "A[12]"}, - {"a[13]", "A[13]"}, - {"a[14]", "A[14]"}, - {"a[15]", "A[15]"}, - {"a[16]", "A[16]"}, - {"a[17]", "A[17]"}, - {"a[18]", "A[18]"}, - {"a[19]", "A[19]"}, - {"b[0]", "B[0]"}, - {"b[1]", "B[1]"}, - {"b[2]", "B[2]"}, - {"b[3]", "B[3]"}, - {"b[4]", "B[4]"}, - {"b[5]", "B[5]"}, - {"b[6]", "B[6]"}, - {"b[7]", "B[7]"}, - {"b[8]", "B[8]"}, - {"b[9]", "B[9]"}, - {"b[10]", "B[10]"}, - {"b[11]", "B[11]"}, - {"b[12]", "B[12]"}, - {"b[13]", "B[13]"}, - {"b[14]", "B[14]"}, - {"b[15]", "B[15]"}, - {"b[16]", "B[16]"}, - {"b[17]", "B[17]"}, - {"z[0]", "Z[0]"}, - {"z[1]", "Z[1]"}, - {"z[2]", "Z[2]"}, - {"z[3]", "Z[3]"}, - {"z[4]", "Z[4]"}, - {"z[5]", "Z[5]"}, - {"z[6]", "Z[6]"}, - {"z[7]", "Z[7]"}, - {"z[8]", "Z[8]"}, - {"z[9]", "Z[9]"}, - {"z[10]", "Z[10]"}, - {"z[11]", "Z[11]"}, - {"z[12]", "Z[12]"}, - {"z[13]", "Z[13]"}, - {"z[14]", "Z[14]"}, - {"z[15]", "Z[15]"}, - {"z[16]", "Z[16]"}, - {"z[17]", "Z[17]"}, - {"z[18]", "Z[18]"}, - {"z[19]", "Z[19]"}, - {"z[20]", "Z[20]"}, - {"z[21]", "Z[21]"}, - {"z[22]", "Z[22]"}, - {"z[23]", "Z[23]"}, - {"z[24]", "Z[24]"}, - {"z[25]", "Z[25]"}, - {"z[26]", "Z[26]"}, - {"z[27]", "Z[27]"}, - {"z[28]", "Z[28]"}, - {"z[29]", "Z[29]"}, - {"z[30]", "Z[30]"}, - {"z[31]", "Z[31]"}, - {"z[32]", "Z[32]"}, - {"z[33]", "Z[33]"}, - {"z[34]", "Z[34]"}, - {"z[35]", "Z[35]"}, - {"z[36]", "Z[36]"}, - {"z[37]", "Z[37]"}, - {"feedback[0]", "FEEDBACK[0]"}, - {"feedback[1]", "FEEDBACK[1]"}, - {"feedback[2]", "FEEDBACK[2]"}, - {"unsigned_a", "UNSIGNED_A"}, - {"unsigned_b", "UNSIGNED_B"}, - {"clk", "CLK"}, - {"lreset", "RESET"}}; - - std::unordered_map> - prim_io_maps = { - {"RS_DSP_MULT", RS_DSP_MULT_io_map}, - {"RS_DSP_MULTACC_REGIN_REGOUT", RS_DSP_MULTACC_REGIN_REGOUT_io_map}, - {"RS_DSP_MULTACC_REGOUT", RS_DSP_MULTACC_REGOUT_io_map}, - {"RS_DSP_MULTACC_REGIN", RS_DSP_MULTACC_REGIN_io_map}, - {"RS_DSP_MULTACC", RS_DSP_MULTACC_io_map}, - {"RS_DSP_MULTADD_REGIN_REGOUT", RS_DSP_MULTADD_REGIN_REGOUT_io_map}, - {"RS_DSP_MULTADD_REGOUT", RS_DSP_MULTADD_REGOUT_io_map}, - {"RS_DSP_MULTADD_REGIN", RS_DSP_MULTADD_REGIN_io_map}, - {"RS_DSP_MULTADD", RS_DSP_MULTADD_io_map}, - {"RS_DSP_MULT_REGIN_REGOUT", RS_DSP_MULT_REGIN_REGOUT_io_map}, - {"RS_DSP_MULT_REGOUT", RS_DSP_MULT_REGOUT_io_map}, - {"RS_DSP_MULT_REGIN", RS_DSP_MULT_REGIN_io_map}}; - - std::unordered_map RS_DSP_MULT_REGIN_DSP_to_RS = { - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULT_REGOUT_DSP_to_RS = { - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map - RS_DSP_MULT_REGIN_REGOUT_DSP_to_RS = {{"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULTADD_DSP_to_RS = { - {"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"ACC_FIR[5]", "acc_fir[5]"}, - {"ACC_FIR[2]", "acc_fir[2]"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"ACC_FIR[3]", "acc_fir[3]"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"DLY_B[17]", "dly_b[17]"}, - {"DLY_B[16]", "dly_b[16]"}, - {"DLY_B[15]", "dly_b[15]"}, - {"DLY_B[14]", "dly_b[14]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"DLY_B[13]", "dly_b[13]"}, - {"UNSIGNED_A", "unsigned_a"}, - {"DLY_B[12]", "dly_b[12]"}, - {"DLY_B[10]", "dly_b[10]"}, - {"DLY_B[9]", "dly_b[9]"}, - {"DLY_B[8]", "dly_b[8]"}, - {"DLY_B[7]", "dly_b[7]"}, - {"DLY_B[6]", "dly_b[6]"}, - {"DLY_B[3]", "dly_b[3]"}, - {"DLY_B[2]", "dly_b[2]"}, - {"DLY_B[0]", "dly_b[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"DLY_B[1]", "dly_b[1]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"DLY_B[5]", "dly_b[5]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"ACC_FIR[1]", "acc_fir[1]"}, - {"A[14]", "a[14]"}, - {"ACC_FIR[4]", "acc_fir[4]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"ACC_FIR[0]", "acc_fir[0]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"DLY_B[4]", "dly_b[4]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"DLY_B[11]", "dly_b[11]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULTADD_REGIN_DSP_to_RS = - {{"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"ACC_FIR[5]", "acc_fir[5]"}, - {"ACC_FIR[2]", "acc_fir[2]"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"ACC_FIR[3]", "acc_fir[3]"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"DLY_B[17]", "dly_b[17]"}, - {"DLY_B[16]", "dly_b[16]"}, - {"DLY_B[15]", "dly_b[15]"}, - {"DLY_B[14]", "dly_b[14]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"DLY_B[13]", "dly_b[13]"}, - {"UNSIGNED_A", "unsigned_a"}, - {"DLY_B[12]", "dly_b[12]"}, - {"DLY_B[10]", "dly_b[10]"}, - {"DLY_B[9]", "dly_b[9]"}, - {"DLY_B[8]", "dly_b[8]"}, - {"DLY_B[7]", "dly_b[7]"}, - {"DLY_B[6]", "dly_b[6]"}, - {"DLY_B[3]", "dly_b[3]"}, - {"DLY_B[2]", "dly_b[2]"}, - {"DLY_B[0]", "dly_b[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"DLY_B[1]", "dly_b[1]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"DLY_B[5]", "dly_b[5]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"ACC_FIR[1]", "acc_fir[1]"}, - {"A[14]", "a[14]"}, - {"ACC_FIR[4]", "acc_fir[4]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"ACC_FIR[0]", "acc_fir[0]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"DLY_B[4]", "dly_b[4]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"DLY_B[11]", "dly_b[11]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map - RS_DSP_MULTADD_REGIN_REGOUT_DSP_to_RS = { - {"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"ACC_FIR[5]", "acc_fir[5]"}, - {"ACC_FIR[2]", "acc_fir[2]"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"ACC_FIR[3]", "acc_fir[3]"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"DLY_B[17]", "dly_b[17]"}, - {"DLY_B[16]", "dly_b[16]"}, - {"DLY_B[15]", "dly_b[15]"}, - {"DLY_B[14]", "dly_b[14]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"DLY_B[13]", "dly_b[13]"}, - {"UNSIGNED_A", "unsigned_a"}, - {"DLY_B[12]", "dly_b[12]"}, - {"DLY_B[10]", "dly_b[10]"}, - {"DLY_B[9]", "dly_b[9]"}, - {"DLY_B[8]", "dly_b[8]"}, - {"DLY_B[7]", "dly_b[7]"}, - {"DLY_B[6]", "dly_b[6]"}, - {"DLY_B[3]", "dly_b[3]"}, - {"DLY_B[2]", "dly_b[2]"}, - {"DLY_B[0]", "dly_b[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"DLY_B[1]", "dly_b[1]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"DLY_B[5]", "dly_b[5]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"ACC_FIR[1]", "acc_fir[1]"}, - {"A[14]", "a[14]"}, - {"ACC_FIR[4]", "acc_fir[4]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"ACC_FIR[0]", "acc_fir[0]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"DLY_B[4]", "dly_b[4]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"DLY_B[11]", "dly_b[11]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULTACC_DSP_to_RS = { - {"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULTACC_REGIN_DSP_to_RS = - {{"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULTACC_REGOUT_DSP_to_RS = - {{"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULTADD_REGOUT_DSP_to_RS = - {{"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"ACC_FIR[5]", "acc_fir[5]"}, - {"ACC_FIR[2]", "acc_fir[2]"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"ACC_FIR[3]", "acc_fir[3]"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"DLY_B[17]", "dly_b[17]"}, - {"DLY_B[16]", "dly_b[16]"}, - {"DLY_B[15]", "dly_b[15]"}, - {"DLY_B[14]", "dly_b[14]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"DLY_B[13]", "dly_b[13]"}, - {"UNSIGNED_A", "unsigned_a"}, - {"DLY_B[12]", "dly_b[12]"}, - {"DLY_B[10]", "dly_b[10]"}, - {"DLY_B[9]", "dly_b[9]"}, - {"DLY_B[8]", "dly_b[8]"}, - {"DLY_B[7]", "dly_b[7]"}, - {"DLY_B[6]", "dly_b[6]"}, - {"DLY_B[3]", "dly_b[3]"}, - {"DLY_B[2]", "dly_b[2]"}, - {"DLY_B[0]", "dly_b[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"DLY_B[1]", "dly_b[1]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"DLY_B[5]", "dly_b[5]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"ACC_FIR[1]", "acc_fir[1]"}, - {"A[14]", "a[14]"}, - {"ACC_FIR[4]", "acc_fir[4]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"ACC_FIR[0]", "acc_fir[0]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"DLY_B[4]", "dly_b[4]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"DLY_B[11]", "dly_b[11]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map - RS_DSP_MULTACC_REGIN_REGOUT_DSP_to_RS = { - {"SUBTRACT", "subtract"}, - {"SHIFT_RIGHT[4]", "shift_right[4]"}, - {"SHIFT_RIGHT[3]", "shift_right[3]"}, - {"SHIFT_RIGHT[2]", "shift_right[2]"}, - {"SATURATE", "saturate_enable"}, - {"RESET", "lreset"}, - {"CLK", "clk"}, - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"SHIFT_RIGHT[0]", "shift_right[0]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"SHIFT_RIGHT[5]", "shift_right[5]"}, - {"LOAD_ACC", "load_acc"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"SHIFT_RIGHT[1]", "shift_right[1]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"ROUND", "round"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - - std::unordered_map RS_DSP_MULT_DSP_to_RS = { - {"UNSIGNED_A", "unsigned_a"}, - {"FEEDBACK[1]", "feedback[1]"}, - {"FEEDBACK[0]", "feedback[0]"}, - {"Z[37]", "z[37]"}, - {"Z[36]", "z[36]"}, - {"Z[34]", "z[34]"}, - {"Z[33]", "z[33]"}, - {"FEEDBACK[2]", "feedback[2]"}, - {"Z[30]", "z[30]"}, - {"Z[28]", "z[28]"}, - {"Z[27]", "z[27]"}, - {"Z[25]", "z[25]"}, - {"UNSIGNED_B", "unsigned_b"}, - {"Z[24]", "z[24]"}, - {"Z[23]", "z[23]"}, - {"Z[22]", "z[22]"}, - {"Z[21]", "z[21]"}, - {"B[5]", "b[5]"}, - {"B[8]", "b[8]"}, - {"B[3]", "b[3]"}, - {"Z[10]", "z[10]"}, - {"Z[31]", "z[31]"}, - {"A[18]", "a[18]"}, - {"B[2]", "b[2]"}, - {"A[16]", "a[16]"}, - {"A[13]", "a[13]"}, - {"Z[2]", "z[2]"}, - {"B[10]", "b[10]"}, - {"B[0]", "b[0]"}, - {"B[14]", "b[14]"}, - {"A[0]", "a[0]"}, - {"A[1]", "a[1]"}, - {"A[14]", "a[14]"}, - {"A[2]", "a[2]"}, - {"A[9]", "a[9]"}, - {"A[17]", "a[17]"}, - {"Z[32]", "z[32]"}, - {"Z[9]", "z[9]"}, - {"Z[26]", "z[26]"}, - {"B[4]", "b[4]"}, - {"Z[12]", "z[12]"}, - {"A[5]", "a[5]"}, - {"B[1]", "b[1]"}, - {"Z[8]", "z[8]"}, - {"A[11]", "a[11]"}, - {"B[12]", "b[12]"}, - {"Z[0]", "z[0]"}, - {"B[6]", "b[6]"}, - {"Z[18]", "z[18]"}, - {"B[16]", "b[16]"}, - {"A[6]", "a[6]"}, - {"Z[7]", "z[7]"}, - {"A[7]", "a[7]"}, - {"A[8]", "a[8]"}, - {"B[7]", "b[7]"}, - {"B[9]", "b[9]"}, - {"Z[19]", "z[19]"}, - {"A[10]", "a[10]"}, - {"A[12]", "a[12]"}, - {"Z[4]", "z[4]"}, - {"Z[29]", "z[29]"}, - {"A[3]", "a[3]"}, - {"B[11]", "b[11]"}, - {"B[13]", "b[13]"}, - {"Z[35]", "z[35]"}, - {"B[15]", "b[15]"}, - {"Z[1]", "z[1]"}, - {"B[17]", "b[17]"}, - {"Z[3]", "z[3]"}, - {"A[4]", "a[4]"}, - {"Z[5]", "z[5]"}, - {"A[19]", "a[19]"}, - {"Z[6]", "z[6]"}, - {"Z[14]", "z[14]"}, - {"Z[13]", "z[13]"}, - {"Z[15]", "z[15]"}, - {"A[15]", "a[15]"}, - {"Z[16]", "z[16]"}, - {"Z[17]", "z[17]"}, - {"Z[11]", "z[11]"}, - {"Z[20]", "z[20]"}}; - std::unordered_map> - prim_io_maps_dsp_to_rs_prim = { - {"RS_DSP_MULT", RS_DSP_MULT_DSP_to_RS}, - {"RS_DSP_MULTACC_REGIN_REGOUT", - RS_DSP_MULTACC_REGIN_REGOUT_DSP_to_RS}, - {"RS_DSP_MULTADD_REGOUT", RS_DSP_MULTADD_REGOUT_DSP_to_RS}, - {"RS_DSP_MULTACC_REGOUT", RS_DSP_MULTACC_REGOUT_DSP_to_RS}, - {"RS_DSP_MULTACC_REGIN", RS_DSP_MULTACC_REGIN_DSP_to_RS}, - {"RS_DSP_MULTACC", RS_DSP_MULTACC_DSP_to_RS}, - {"RS_DSP_MULTADD_REGIN_REGOUT", - RS_DSP_MULTADD_REGIN_REGOUT_DSP_to_RS}, - {"RS_DSP_MULTADD_REGIN", RS_DSP_MULTADD_REGIN_DSP_to_RS}, - {"RS_DSP_MULTADD", RS_DSP_MULTADD_DSP_to_RS}, - {"RS_DSP_MULT_REGIN_REGOUT", RS_DSP_MULT_REGIN_REGOUT_DSP_to_RS}, - {"RS_DSP_MULT_REGOUT", RS_DSP_MULT_REGOUT_DSP_to_RS}, - {"RS_DSP_MULT_REGIN", RS_DSP_MULT_REGIN_DSP_to_RS}}; - - // Latch flattening - std::unordered_map latch_lut_LUT_strs = { - {"LATCH", "10101100"}, - {"LATCHN", "10101100"}, - {"LATCHR", "0000101000001100"}, - {"LATCHS", "1111101011111100"}, - {"LATCHNR", "0000101000001100"}, - {"LATCHNS", "1111101011111100"}, - {"LATCHSRE", - "1011101111110011111100111111001100000000000000000000000000000000"}, - {"LATCHNSRE", - "1111001110111011111100111111001100000000000000000000000000000000"}}; - - std::unordered_map latch_lut_WIDTH_strs = { - {"LATCH", "3"}, {"LATCHN", "3"}, {"LATCHR", "4"}, - {"LATCHS", "4"}, {"LATCHNR", "4"}, {"LATCHNS", "4"}, - {"LATCHSRE", "6"}, {"LATCHNSRE", "6"}}; - std::unordered_map latch_ports = { - {"LATCH", "DGQ"}, {"LATCHN", "DGQ"}, {"LATCHR", "DGRQ"}, - {"LATCHS", "DGRQ"}, {"LATCHNR", "DGRQ"}, {"LATCHNS", "DGRQ"}, - {"LATCHSRE", "QSRDGE"}, {"LATCHNSRE", "QSRDGE"}}; - - std::unordered_map lut_A_port_connections = { - {"LATCH", "GQD"}, {"LATCHN", "GDQ"}, {"LATCHR", "GRQD"}, - {"LATCHS", "GRQD"}, {"LATCHNR", "GRDQ"}, {"LATCHNS", "GRDQ"}, - {"LATCHSRE", "RGEQSD"}, {"LATCHNSRE", "REGQSD"}}; - - std::unordered_map lut_port_map_LATCH{ - {"G", "A[2]"}, {"Q", "A[1]"}, {"D", "A[0]"}}; - std::unordered_map lut_port_map_LATCHN{ - {"G", "A[2]"}, {"D", "A[1]"}, {"Q", "A[0]"}}; - std::unordered_map lut_port_map_LATCHR{ - {"G", "A[3]"}, {"R", "A[2]"}, {"Q", "A[1]"}, {"D", "A[0]"}}; - std::unordered_map lut_port_map_LATCHS{ - {"G", "A[3]"}, {"R", "A[2]"}, {"Q", "A[1]"}, {"D", "A[0]"}}; - std::unordered_map lut_port_map_LATCHNR{ - {"G", "A[3]"}, {"R", "A[2]"}, {"D", "A[1]"}, {"Q", "A[0]"}}; - std::unordered_map lut_port_map_LATCHNS{ - {"G", "A[3]"}, {"R", "A[2]"}, {"D", "A[1]"}, {"Q", "A[0]"}}; - std::unordered_map lut_port_map_LATCHSRE{ - {"R", "A[5]"}, {"G", "A[4]"}, {"E", "A[3]"}, - {"Q", "A[2]"}, {"S", "A[1]"}, {"D", "A[0]"}}; - std::unordered_map lut_port_map_LATCHNSRE{ - {"R", "A[5]"}, {"E", "A[4]"}, {"G", "A[3]"}, - {"Q", "A[2]"}, {"S", "A[1]"}, {"D", "A[0]"}}; - - std::unordered_map> - latch_lut_port_conversion{{"LATCH", lut_port_map_LATCH}, - {"LATCHN", lut_port_map_LATCHN}, - {"LATCHR", lut_port_map_LATCHR}, - {"LATCHS", lut_port_map_LATCHS}, - {"LATCHNR", lut_port_map_LATCHNR}, - {"LATCHNS", lut_port_map_LATCHNS}, - {"LATCHSRE", lut_port_map_LATCHSRE}, - {"LATCHNSRE", lut_port_map_LATCHNSRE}}; - string mx = "179769313486231590772930519078902473361797697894230657273" - "43008115773267580" - "550096313270847732240753602112011387987139335765878976881" - "44166224928474306" - "394741243777678934248654852763022196012460941194530829520" - "85005768838150682" - "342462881473913110540827237163350510684586298239947245938" - "47971630483535632" - "9624224137215"; - std::map hexDecoder = { - {'0', "0000"}, {'1', "0001"}, {'2', "0010"}, {'3', "0011"}, {'4', "0100"}, - {'5', "0101"}, {'6', "0110"}, {'7', "0111"}, {'8', "1000"}, {'9', "1001"}, - {'A', "1010"}, {'B', "1011"}, {'C', "1100"}, {'D', "1101"}, {'E', "1110"}, - {'F', "1111"}, {'X', "xxxx"}, {'a', "1010"}, {'b', "1011"}, {'c', "1100"}, - {'d', "1101"}, {'e', "1110"}, {'f', "1111"}, {'x', "xxxx"}}; }; +