NOT An ISSUE - How can I give you some new information to add?

[shawty]

The "Digital" logic simulator, right here on Github : https://github.com/hneemann/Digital

Can directly produce JED files for burning into a PAL/GAL chip.

You can use the Analysis->Synthesis menu to open the truth table designer:

Then add/remove input and output columns, and design your truth table states.

Once you have designed your circuit, you can then click "create->circuit"

This will build you a logic circuit according to your table

Once you have a circuit you need to edit the input/output pins by right clicking on each in turn and using the advanced properties, so assign a pin number to each I/O line

You may also want to set up any circuit specific settings.

Once you have set up your circuit and pin numbers, you then save your circuit.

and go back to the Analysis circuit, this time Analyzing the circuit, rather than synthesizing it.

This will re-build your truth table and logic rules, but this time the code in the app is now aware of how to run them

If you click on "Create->Device->devtype->...." you'll now find that you have menu items that will directly produce either a CUPL file to be compiled with the CUPL/WINCUPL compilers and/or a JED file that you can directly burn to a GAL using a suitable programmer.

If you need any further details please do feel free to ask.

I'm NOT the author of Digital, but I am an avid user of the program, it's java so will run on all major platforms, it has an extension API, so you can write your own JAVA based electronics modules/plugins, it has the ability to turn any circuits you synthesize, into sub circuits that can be added to your own libraries and used in larger circuits, it can also run test cases to test logic designs and interact with standard SPICE & FPGA tools.

[AlyssonRowan]

Ah. Most useful. Thankyou.

[shawty]

I figured this might be useful, it means that it's now possible to use fully modern tooling that runs great on modern OS's (I'm using this on Win 10 x64 without a hitch) and I can build, design and test my circuits 100% virtually.

Not only that, but the JED files can also be loaded into Proteus and 100% simulated with Analog circuitry using it's built in spice simulation layer.

[shawty]

@AlyssonRowan PS: I too have a habit of recycling old parts, the whole reason I started playing with PLD's & GALs again was because I got my hands on an old custom ethernet concentrator and when I started to take it apart, there was about 20 cards inside, each with it's own 186 based stand alone system on it, and 20 to 30 GAL's on each board :-)

I now have about 60+ of the things to muck about with.

One of these days, I might actually get some content created for my "Shawty's Workshop" YouTube channel and start making use of all this stuff I salvage :-D

[peterzieba]

Hi,

I do have a section in the main README.md page that briefly covers Digital and mentions this functionality, though not in the detail you have posted.

It is admittedly a dense page and poorly organized so it is hard to find buried in there.

My personal experience with Digital is that I could not get it to do what I wanted it to do with Hi-Z / Bidirectional pins, however, that was a very long time ago.

If you like Digital, you might also like Logisim and Logisim-Evolution:
https://cburch.com/logisim/
https://github.com/logisim-evolution/logisim-evolution

The direction I am currently heading in for simulation, however, is to leverage CUPL's simulator (CSIM.EXE) and turn a bunch of test-vectors into a graphical representation using WaveDrom as an output. This would allow one to avoid WinSIM entirely, which seems to have some weird glitch when updating the screen.

The workflow is basically that I currently feed a bunch of test vectors into a spreadsheet and get a WaveDrom output.

I'll need to clean it up a bit when a get some time and add it to the repository.