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portsorch.cpp
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#include "portsorch.h"
#include "intfsorch.h"
#include "bufferorch.h"
#include "neighorch.h"
#include "gearboxutils.h"
#include "vxlanorch.h"
#include "directory.h"
#include "subintf.h"
#include "notifications.h"
#include <inttypes.h>
#include <cassert>
#include <fstream>
#include <sstream>
#include <set>
#include <algorithm>
#include <tuple>
#include <sstream>
#include <unordered_set>
#include <netinet/if_ether.h>
#include "net/if.h"
#include "logger.h"
#include "schema.h"
#include "redisapi.h"
#include "converter.h"
#include "sai_serialize.h"
#include "crmorch.h"
#include "countercheckorch.h"
#include "notifier.h"
#include "fdborch.h"
#include "switchorch.h"
#include "stringutility.h"
#include "subscriberstatetable.h"
extern sai_switch_api_t *sai_switch_api;
extern sai_bridge_api_t *sai_bridge_api;
extern sai_port_api_t *sai_port_api;
extern sai_vlan_api_t *sai_vlan_api;
extern sai_lag_api_t *sai_lag_api;
extern sai_hostif_api_t* sai_hostif_api;
extern sai_acl_api_t* sai_acl_api;
extern sai_queue_api_t *sai_queue_api;
extern sai_object_id_t gSwitchId;
extern sai_fdb_api_t *sai_fdb_api;
extern sai_l2mc_group_api_t *sai_l2mc_group_api;
extern IntfsOrch *gIntfsOrch;
extern NeighOrch *gNeighOrch;
extern CrmOrch *gCrmOrch;
extern BufferOrch *gBufferOrch;
extern FdbOrch *gFdbOrch;
extern SwitchOrch *gSwitchOrch;
extern Directory<Orch*> gDirectory;
extern sai_system_port_api_t *sai_system_port_api;
extern string gMySwitchType;
extern int32_t gVoqMySwitchId;
extern string gMyHostName;
extern string gMyAsicName;
extern event_handle_t g_events_handle;
// defines ------------------------------------------------------------------------------------------------------------
#define DEFAULT_SYSTEM_PORT_MTU 9100
#define VLAN_PREFIX "Vlan"
#define DEFAULT_VLAN_ID 1
#define MAX_VALID_VLAN_ID 4094
#define DEFAULT_HOSTIF_TX_QUEUE 7
#define PORT_SPEED_LIST_DEFAULT_SIZE 16
#define PORT_STATE_POLLING_SEC 5
#define PORT_STAT_FLEX_COUNTER_POLLING_INTERVAL_MS 1000
#define PORT_BUFFER_DROP_STAT_POLLING_INTERVAL_MS 60000
#define QUEUE_STAT_FLEX_COUNTER_POLLING_INTERVAL_MS 10000
#define QUEUE_WATERMARK_FLEX_STAT_COUNTER_POLL_MSECS "60000"
#define PG_WATERMARK_FLEX_STAT_COUNTER_POLL_MSECS "60000"
#define PG_DROP_FLEX_STAT_COUNTER_POLL_MSECS "10000"
#define PORT_RATE_FLEX_COUNTER_POLLING_INTERVAL_MS "1000"
// types --------------------------------------------------------------------------------------------------------------
struct PortAttrValue
{
std::vector<std::uint32_t> lanes;
};
typedef PortAttrValue PortAttrValue_t;
typedef std::map<sai_port_serdes_attr_t, std::vector<std::uint32_t>> PortSerdesAttrMap_t;
// constants ----------------------------------------------------------------------------------------------------------
static map<string, sai_bridge_port_fdb_learning_mode_t> learn_mode_map =
{
{ "drop", SAI_BRIDGE_PORT_FDB_LEARNING_MODE_DROP },
{ "disable", SAI_BRIDGE_PORT_FDB_LEARNING_MODE_DISABLE },
{ "hardware", SAI_BRIDGE_PORT_FDB_LEARNING_MODE_HW },
{ "cpu_trap", SAI_BRIDGE_PORT_FDB_LEARNING_MODE_CPU_TRAP},
{ "cpu_log", SAI_BRIDGE_PORT_FDB_LEARNING_MODE_CPU_LOG},
{ "notification", SAI_BRIDGE_PORT_FDB_LEARNING_MODE_FDB_NOTIFICATION}
};
static map<string, sai_port_media_type_t> media_type_map =
{
{ "fiber", SAI_PORT_MEDIA_TYPE_FIBER },
{ "copper", SAI_PORT_MEDIA_TYPE_COPPER }
};
static map<string, sai_port_internal_loopback_mode_t> loopback_mode_map =
{
{ "none", SAI_PORT_INTERNAL_LOOPBACK_MODE_NONE },
{ "phy", SAI_PORT_INTERNAL_LOOPBACK_MODE_PHY },
{ "mac", SAI_PORT_INTERNAL_LOOPBACK_MODE_MAC }
};
static map<string, int> autoneg_mode_map =
{
{ "on", 1 },
{ "off", 0 }
};
static map<sai_port_link_training_failure_status_t, string> link_training_failure_map =
{
{ SAI_PORT_LINK_TRAINING_FAILURE_STATUS_NO_ERROR, "none" },
{ SAI_PORT_LINK_TRAINING_FAILURE_STATUS_FRAME_LOCK_ERROR, "frame_lock"},
{ SAI_PORT_LINK_TRAINING_FAILURE_STATUS_SNR_LOWER_THRESHOLD, "snr_low"},
{ SAI_PORT_LINK_TRAINING_FAILURE_STATUS_TIME_OUT, "timeout"}
};
static map<sai_port_link_training_rx_status_t, string> link_training_rx_status_map =
{
{ SAI_PORT_LINK_TRAINING_RX_STATUS_NOT_TRAINED, "not_trained" },
{ SAI_PORT_LINK_TRAINING_RX_STATUS_TRAINED, "trained"}
};
// Interface type map used for gearbox
static map<string, sai_port_interface_type_t> interface_type_map =
{
{ "none", SAI_PORT_INTERFACE_TYPE_NONE },
{ "cr", SAI_PORT_INTERFACE_TYPE_CR },
{ "cr4", SAI_PORT_INTERFACE_TYPE_CR4 },
{ "cr8", SAI_PORT_INTERFACE_TYPE_CR8 },
{ "sr", SAI_PORT_INTERFACE_TYPE_SR },
{ "sr4", SAI_PORT_INTERFACE_TYPE_SR4 },
{ "sr8", SAI_PORT_INTERFACE_TYPE_SR8 },
{ "lr", SAI_PORT_INTERFACE_TYPE_LR },
{ "lr4", SAI_PORT_INTERFACE_TYPE_LR4 },
{ "lr8", SAI_PORT_INTERFACE_TYPE_LR8 },
{ "kr", SAI_PORT_INTERFACE_TYPE_KR },
{ "kr4", SAI_PORT_INTERFACE_TYPE_KR4 },
{ "kr8", SAI_PORT_INTERFACE_TYPE_KR8 }
};
const vector<sai_port_stat_t> port_stat_ids =
{
SAI_PORT_STAT_IF_IN_OCTETS,
SAI_PORT_STAT_IF_IN_UCAST_PKTS,
SAI_PORT_STAT_IF_IN_NON_UCAST_PKTS,
SAI_PORT_STAT_IF_IN_DISCARDS,
SAI_PORT_STAT_IF_IN_ERRORS,
SAI_PORT_STAT_IF_IN_UNKNOWN_PROTOS,
SAI_PORT_STAT_IF_OUT_OCTETS,
SAI_PORT_STAT_IF_OUT_UCAST_PKTS,
SAI_PORT_STAT_IF_OUT_NON_UCAST_PKTS,
SAI_PORT_STAT_IF_OUT_DISCARDS,
SAI_PORT_STAT_IF_OUT_ERRORS,
SAI_PORT_STAT_IF_OUT_QLEN,
SAI_PORT_STAT_IF_IN_MULTICAST_PKTS,
SAI_PORT_STAT_IF_IN_BROADCAST_PKTS,
SAI_PORT_STAT_IF_OUT_MULTICAST_PKTS,
SAI_PORT_STAT_IF_OUT_BROADCAST_PKTS,
SAI_PORT_STAT_ETHER_RX_OVERSIZE_PKTS,
SAI_PORT_STAT_ETHER_TX_OVERSIZE_PKTS,
SAI_PORT_STAT_ETHER_IN_PKTS_64_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_65_TO_127_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_128_TO_255_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_256_TO_511_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_512_TO_1023_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_1024_TO_1518_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_1519_TO_2047_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_2048_TO_4095_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_4096_TO_9216_OCTETS,
SAI_PORT_STAT_ETHER_IN_PKTS_9217_TO_16383_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_64_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_65_TO_127_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_128_TO_255_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_256_TO_511_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_512_TO_1023_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_1024_TO_1518_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_1519_TO_2047_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_2048_TO_4095_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_4096_TO_9216_OCTETS,
SAI_PORT_STAT_ETHER_OUT_PKTS_9217_TO_16383_OCTETS,
SAI_PORT_STAT_PFC_0_TX_PKTS,
SAI_PORT_STAT_PFC_1_TX_PKTS,
SAI_PORT_STAT_PFC_2_TX_PKTS,
SAI_PORT_STAT_PFC_3_TX_PKTS,
SAI_PORT_STAT_PFC_4_TX_PKTS,
SAI_PORT_STAT_PFC_5_TX_PKTS,
SAI_PORT_STAT_PFC_6_TX_PKTS,
SAI_PORT_STAT_PFC_7_TX_PKTS,
SAI_PORT_STAT_PFC_0_RX_PKTS,
SAI_PORT_STAT_PFC_1_RX_PKTS,
SAI_PORT_STAT_PFC_2_RX_PKTS,
SAI_PORT_STAT_PFC_3_RX_PKTS,
SAI_PORT_STAT_PFC_4_RX_PKTS,
SAI_PORT_STAT_PFC_5_RX_PKTS,
SAI_PORT_STAT_PFC_6_RX_PKTS,
SAI_PORT_STAT_PFC_7_RX_PKTS,
SAI_PORT_STAT_PAUSE_RX_PKTS,
SAI_PORT_STAT_PAUSE_TX_PKTS,
SAI_PORT_STAT_ETHER_STATS_TX_NO_ERRORS,
SAI_PORT_STAT_IP_IN_UCAST_PKTS,
SAI_PORT_STAT_ETHER_STATS_JABBERS,
SAI_PORT_STAT_ETHER_STATS_FRAGMENTS,
SAI_PORT_STAT_ETHER_STATS_UNDERSIZE_PKTS,
SAI_PORT_STAT_IP_IN_RECEIVES,
SAI_PORT_STAT_IF_IN_FEC_CORRECTABLE_FRAMES,
SAI_PORT_STAT_IF_IN_FEC_NOT_CORRECTABLE_FRAMES,
SAI_PORT_STAT_IF_IN_FEC_SYMBOL_ERRORS,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S0,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S1,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S2,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S3,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S4,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S5,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S6,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S7,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S8,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S9,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S10,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S11,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S12,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S13,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S14,
SAI_PORT_STAT_IF_IN_FEC_CODEWORD_ERRORS_S15
};
const vector<sai_port_stat_t> gbport_stat_ids =
{
SAI_PORT_STAT_IF_IN_OCTETS,
SAI_PORT_STAT_IF_IN_UCAST_PKTS,
SAI_PORT_STAT_IF_IN_NON_UCAST_PKTS,
SAI_PORT_STAT_IF_OUT_OCTETS,
SAI_PORT_STAT_IF_OUT_UCAST_PKTS,
SAI_PORT_STAT_IF_OUT_NON_UCAST_PKTS,
SAI_PORT_STAT_IF_IN_DISCARDS,
SAI_PORT_STAT_IF_OUT_DISCARDS,
SAI_PORT_STAT_IF_IN_ERRORS,
SAI_PORT_STAT_IF_OUT_ERRORS,
SAI_PORT_STAT_ETHER_RX_OVERSIZE_PKTS,
SAI_PORT_STAT_ETHER_TX_OVERSIZE_PKTS,
SAI_PORT_STAT_ETHER_STATS_UNDERSIZE_PKTS,
SAI_PORT_STAT_ETHER_STATS_JABBERS,
SAI_PORT_STAT_ETHER_STATS_FRAGMENTS,
SAI_PORT_STAT_IF_IN_FEC_CORRECTABLE_FRAMES,
SAI_PORT_STAT_IF_IN_FEC_NOT_CORRECTABLE_FRAMES,
SAI_PORT_STAT_IF_IN_FEC_SYMBOL_ERRORS
};
const vector<sai_port_stat_t> port_buffer_drop_stat_ids =
{
SAI_PORT_STAT_IN_DROPPED_PKTS,
SAI_PORT_STAT_OUT_DROPPED_PKTS
};
static const vector<sai_queue_stat_t> queue_stat_ids =
{
SAI_QUEUE_STAT_PACKETS,
SAI_QUEUE_STAT_BYTES,
SAI_QUEUE_STAT_DROPPED_PACKETS,
SAI_QUEUE_STAT_DROPPED_BYTES,
};
static const vector<sai_queue_stat_t> queueWatermarkStatIds =
{
SAI_QUEUE_STAT_SHARED_WATERMARK_BYTES,
};
static const vector<sai_ingress_priority_group_stat_t> ingressPriorityGroupWatermarkStatIds =
{
SAI_INGRESS_PRIORITY_GROUP_STAT_XOFF_ROOM_WATERMARK_BYTES,
SAI_INGRESS_PRIORITY_GROUP_STAT_SHARED_WATERMARK_BYTES,
};
static const vector<sai_ingress_priority_group_stat_t> ingressPriorityGroupDropStatIds =
{
SAI_INGRESS_PRIORITY_GROUP_STAT_DROPPED_PACKETS
};
static char* hostif_vlan_tag[] = {
[SAI_HOSTIF_VLAN_TAG_STRIP] = "SAI_HOSTIF_VLAN_TAG_STRIP",
[SAI_HOSTIF_VLAN_TAG_KEEP] = "SAI_HOSTIF_VLAN_TAG_KEEP",
[SAI_HOSTIF_VLAN_TAG_ORIGINAL] = "SAI_HOSTIF_VLAN_TAG_ORIGINAL"
};
// functions ----------------------------------------------------------------------------------------------------------
static bool isValidPortTypeForLagMember(const Port& port)
{
return (port.m_type == Port::Type::PHY || port.m_type == Port::Type::SYSTEM);
}
static void getPortSerdesAttr(PortSerdesAttrMap_t &map, const PortConfig &port)
{
if (port.serdes.preemphasis.is_set)
{
map[SAI_PORT_SERDES_ATTR_PREEMPHASIS] = port.serdes.preemphasis.value;
}
if (port.serdes.idriver.is_set)
{
map[SAI_PORT_SERDES_ATTR_IDRIVER] = port.serdes.idriver.value;
}
if (port.serdes.ipredriver.is_set)
{
map[SAI_PORT_SERDES_ATTR_IPREDRIVER] = port.serdes.ipredriver.value;
}
if (port.serdes.pre1.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_PRE1] = port.serdes.pre1.value;
}
if (port.serdes.pre2.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_PRE2] = port.serdes.pre2.value;
}
if (port.serdes.pre3.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_PRE3] = port.serdes.pre3.value;
}
if (port.serdes.main.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_MAIN] = port.serdes.main.value;
}
if (port.serdes.post1.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_POST1] = port.serdes.post1.value;
}
if (port.serdes.post2.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_POST2] = port.serdes.post2.value;
}
if (port.serdes.post3.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_POST3] = port.serdes.post3.value;
}
if (port.serdes.attn.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_FIR_ATTN] = port.serdes.attn.value;
}
if (port.serdes.ob_m2lp.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_PAM4_RATIO] = port.serdes.ob_m2lp.value;
}
if (port.serdes.ob_alev_out.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_OUT_COMMON_MODE] = port.serdes.ob_alev_out.value;
}
if (port.serdes.obplev.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_PMOS_COMMON_MODE] = port.serdes.obplev.value;
}
if (port.serdes.obnlev.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_NMOS_COMMON_MODE] = port.serdes.obnlev.value;
}
if (port.serdes.regn_bfm1p.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_PMOS_VLTG_REG] = port.serdes.regn_bfm1p.value;
}
if (port.serdes.regn_bfm1n.is_set)
{
map[SAI_PORT_SERDES_ATTR_TX_NMOS_VLTG_REG] = port.serdes.regn_bfm1n.value;
}
}
// Port OA ------------------------------------------------------------------------------------------------------------
/*
* Initialize PortsOrch
* 0) If Gearbox is enabled, then initialize the external PHYs as defined in
* the GEARBOX_TABLE.
* 1) By default, a switch has one CPU port, one 802.1Q bridge, and one default
* VLAN. All ports are in .1Q bridge as bridge ports, and all bridge ports
* are in default VLAN as VLAN members.
* 2) Query switch CPU port.
* 3) Query ports associated with lane mappings
* 4) Query switch .1Q bridge and all its bridge ports.
* 5) Query switch default VLAN and all its VLAN members.
* 6) Remove each VLAN member from default VLAN and each bridge port from .1Q
* bridge. By design, SONiC switch starts with all bridge ports removed from
* default VLAN and all ports removed from .1Q bridge.
*/
PortsOrch::PortsOrch(DBConnector *db, DBConnector *stateDb, vector<table_name_with_pri_t> &tableNames, DBConnector *chassisAppDb) :
Orch(db, tableNames),
m_portStateTable(stateDb, STATE_PORT_TABLE_NAME),
port_stat_manager(PORT_STAT_COUNTER_FLEX_COUNTER_GROUP, StatsMode::READ, PORT_STAT_FLEX_COUNTER_POLLING_INTERVAL_MS, false),
gb_port_stat_manager("GB_FLEX_COUNTER_DB",
PORT_STAT_COUNTER_FLEX_COUNTER_GROUP, StatsMode::READ,
PORT_STAT_FLEX_COUNTER_POLLING_INTERVAL_MS, false),
port_buffer_drop_stat_manager(PORT_BUFFER_DROP_STAT_FLEX_COUNTER_GROUP, StatsMode::READ, PORT_BUFFER_DROP_STAT_POLLING_INTERVAL_MS, false),
queue_stat_manager(QUEUE_STAT_COUNTER_FLEX_COUNTER_GROUP, StatsMode::READ, QUEUE_STAT_FLEX_COUNTER_POLLING_INTERVAL_MS, false),
m_port_state_poller(new SelectableTimer(timespec { .tv_sec = PORT_STATE_POLLING_SEC, .tv_nsec = 0 }))
{
SWSS_LOG_ENTER();
/* Initialize counter table */
m_counter_db = shared_ptr<DBConnector>(new DBConnector("COUNTERS_DB", 0));
m_counterTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_PORT_NAME_MAP));
m_counterSysPortTable = unique_ptr<Table>(
new Table(m_counter_db.get(), COUNTERS_SYSTEM_PORT_NAME_MAP));
m_counterLagTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_LAG_NAME_MAP));
FieldValueTuple tuple("", "");
vector<FieldValueTuple> defaultLagFv;
defaultLagFv.push_back(tuple);
m_counterLagTable->set("", defaultLagFv);
/* Initialize port and vlan table */
m_portTable = unique_ptr<Table>(new Table(db, APP_PORT_TABLE_NAME));
m_sendToIngressPortTable = unique_ptr<Table>(new Table(db, APP_SEND_TO_INGRESS_PORT_TABLE_NAME));
/* Initialize gearbox */
m_gearboxTable = unique_ptr<Table>(new Table(db, "_GEARBOX_TABLE"));
/* Initialize queue tables */
m_queueTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_QUEUE_NAME_MAP));
m_voqTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_VOQ_NAME_MAP));
m_queuePortTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_QUEUE_PORT_MAP));
m_queueIndexTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_QUEUE_INDEX_MAP));
m_queueTypeTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_QUEUE_TYPE_MAP));
/* Initialize ingress priority group tables */
m_pgTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_PG_NAME_MAP));
m_pgPortTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_PG_PORT_MAP));
m_pgIndexTable = unique_ptr<Table>(new Table(m_counter_db.get(), COUNTERS_PG_INDEX_MAP));
m_flex_db = shared_ptr<DBConnector>(new DBConnector("FLEX_COUNTER_DB", 0));
m_flexCounterTable = unique_ptr<ProducerTable>(new ProducerTable(m_flex_db.get(), FLEX_COUNTER_TABLE));
m_flexCounterGroupTable = unique_ptr<ProducerTable>(new ProducerTable(m_flex_db.get(), FLEX_COUNTER_GROUP_TABLE));
m_state_db = shared_ptr<DBConnector>(new DBConnector("STATE_DB", 0));
m_stateBufferMaximumValueTable = unique_ptr<Table>(new Table(m_state_db.get(), STATE_BUFFER_MAXIMUM_VALUE_TABLE));
initGearbox();
string queueWmSha, pgWmSha;
string queueWmPluginName = "watermark_queue.lua";
string pgWmPluginName = "watermark_pg.lua";
string portRatePluginName = "port_rates.lua";
try
{
string queueLuaScript = swss::loadLuaScript(queueWmPluginName);
queueWmSha = swss::loadRedisScript(m_counter_db.get(), queueLuaScript);
string pgLuaScript = swss::loadLuaScript(pgWmPluginName);
pgWmSha = swss::loadRedisScript(m_counter_db.get(), pgLuaScript);
string portRateLuaScript = swss::loadLuaScript(portRatePluginName);
string portRateSha = swss::loadRedisScript(m_counter_db.get(), portRateLuaScript);
vector<FieldValueTuple> fieldValues;
fieldValues.emplace_back(QUEUE_PLUGIN_FIELD, queueWmSha);
fieldValues.emplace_back(POLL_INTERVAL_FIELD, QUEUE_WATERMARK_FLEX_STAT_COUNTER_POLL_MSECS);
fieldValues.emplace_back(STATS_MODE_FIELD, STATS_MODE_READ_AND_CLEAR);
m_flexCounterGroupTable->set(QUEUE_WATERMARK_STAT_COUNTER_FLEX_COUNTER_GROUP, fieldValues);
fieldValues.clear();
fieldValues.emplace_back(PG_PLUGIN_FIELD, pgWmSha);
fieldValues.emplace_back(POLL_INTERVAL_FIELD, PG_WATERMARK_FLEX_STAT_COUNTER_POLL_MSECS);
fieldValues.emplace_back(STATS_MODE_FIELD, STATS_MODE_READ_AND_CLEAR);
m_flexCounterGroupTable->set(PG_WATERMARK_STAT_COUNTER_FLEX_COUNTER_GROUP, fieldValues);
fieldValues.clear();
fieldValues.emplace_back(PORT_PLUGIN_FIELD, portRateSha);
fieldValues.emplace_back(POLL_INTERVAL_FIELD, PORT_RATE_FLEX_COUNTER_POLLING_INTERVAL_MS);
fieldValues.emplace_back(STATS_MODE_FIELD, STATS_MODE_READ);
m_flexCounterGroupTable->set(PORT_STAT_COUNTER_FLEX_COUNTER_GROUP, fieldValues);
fieldValues.clear();
fieldValues.emplace_back(POLL_INTERVAL_FIELD, PG_DROP_FLEX_STAT_COUNTER_POLL_MSECS);
fieldValues.emplace_back(STATS_MODE_FIELD, STATS_MODE_READ);
m_flexCounterGroupTable->set(PG_DROP_STAT_COUNTER_FLEX_COUNTER_GROUP, fieldValues);
}
catch (const runtime_error &e)
{
SWSS_LOG_ERROR("Port flex counter groups were not set successfully: %s", e.what());
}
/* Get CPU port */
this->initializeCpuPort();
/* Get ports */
this->initializePorts();
/* Get the flood control types and check if combined mode is supported */
vector<int32_t> supported_flood_control_types(max_flood_control_types, 0);
sai_s32_list_t values;
values.count = max_flood_control_types;
values.list = supported_flood_control_types.data();
if (sai_query_attribute_enum_values_capability(gSwitchId, SAI_OBJECT_TYPE_VLAN,
SAI_VLAN_ATTR_UNKNOWN_UNICAST_FLOOD_CONTROL_TYPE,
&values) != SAI_STATUS_SUCCESS)
{
SWSS_LOG_NOTICE("This device does not support unknown unicast flood control types");
}
else
{
for (uint32_t idx = 0; idx < values.count; idx++)
{
uuc_sup_flood_control_type.insert(static_cast<sai_vlan_flood_control_type_t>(values.list[idx]));
}
}
supported_flood_control_types.assign(max_flood_control_types, 0);
values.count = max_flood_control_types;
values.list = supported_flood_control_types.data();
if (sai_query_attribute_enum_values_capability(gSwitchId, SAI_OBJECT_TYPE_VLAN,
SAI_VLAN_ATTR_BROADCAST_FLOOD_CONTROL_TYPE,
&values) != SAI_STATUS_SUCCESS)
{
SWSS_LOG_NOTICE("This device does not support broadcast flood control types");
}
else
{
for (uint32_t idx = 0; idx < values.count; idx++)
{
bc_sup_flood_control_type.insert(static_cast<sai_vlan_flood_control_type_t>(values.list[idx]));
}
}
// Query whether SAI supports Host Tx Signal and Host Tx Notification
sai_attr_capability_t capability;
bool saiHwTxSignalSupported = false;
bool saiTxReadyNotifySupported = false;
if (sai_query_attribute_capability(gSwitchId, SAI_OBJECT_TYPE_PORT,
SAI_PORT_ATTR_HOST_TX_SIGNAL_ENABLE,
&capability) == SAI_STATUS_SUCCESS)
{
if (capability.create_implemented == true)
{
SWSS_LOG_DEBUG("SAI_PORT_ATTR_HOST_TX_SIGNAL_ENABLE is true");
saiHwTxSignalSupported = true;
}
}
if (sai_query_attribute_capability(gSwitchId, SAI_OBJECT_TYPE_SWITCH,
SAI_SWITCH_ATTR_PORT_HOST_TX_READY_NOTIFY,
&capability) == SAI_STATUS_SUCCESS)
{
if (capability.create_implemented == true)
{
SWSS_LOG_DEBUG("SAI_SWITCH_ATTR_PORT_HOST_TX_READY_NOTIFY is true");
saiTxReadyNotifySupported = true;
}
}
if (saiHwTxSignalSupported && saiTxReadyNotifySupported)
{
SWSS_LOG_DEBUG("m_cmisModuleAsicSyncSupported is true");
m_cmisModuleAsicSyncSupported = true;
// set HOST_TX_READY callback function attribute to SAI, only if the feature is enabled
sai_attribute_t attr;
attr.id = SAI_SWITCH_ATTR_PORT_HOST_TX_READY_NOTIFY;
attr.value.ptr = (void *)on_port_host_tx_ready;
if (sai_switch_api->set_switch_attribute(gSwitchId, &attr) != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("PortsOrch failed to set SAI_SWITCH_ATTR_PORT_HOST_TX_READY_NOTIFY attribute");
}
Orch::addExecutor(new Consumer(new SubscriberStateTable(stateDb, STATE_TRANSCEIVER_INFO_TABLE_NAME, TableConsumable::DEFAULT_POP_BATCH_SIZE, 0), this, STATE_TRANSCEIVER_INFO_TABLE_NAME));
}
if (gMySwitchType != "dpu")
{
sai_attr_capability_t attr_cap;
if (sai_query_attribute_capability(gSwitchId, SAI_OBJECT_TYPE_PORT,
SAI_PORT_ATTR_AUTO_NEG_FEC_MODE_OVERRIDE,
&attr_cap) != SAI_STATUS_SUCCESS)
{
SWSS_LOG_NOTICE("Unable to query autoneg fec mode override");
}
else if (attr_cap.set_implemented && attr_cap.create_implemented)
{
fec_override_sup = true;
}
sai_attr_capability_t oper_fec_cap;
if (sai_query_attribute_capability(gSwitchId, SAI_OBJECT_TYPE_PORT,
SAI_PORT_ATTR_OPER_PORT_FEC_MODE, &oper_fec_cap)
!= SAI_STATUS_SUCCESS)
{
SWSS_LOG_NOTICE("Unable to query capability support for oper fec mode");
}
else if (oper_fec_cap.get_implemented)
{
oper_fec_sup = true;
}
/* Get default 1Q bridge and default VLAN */
sai_status_t status;
sai_attribute_t attr;
vector<sai_attribute_t> attrs;
attr.id = SAI_SWITCH_ATTR_DEFAULT_1Q_BRIDGE_ID;
attrs.push_back(attr);
attr.id = SAI_SWITCH_ATTR_DEFAULT_VLAN_ID;
attrs.push_back(attr);
status = sai_switch_api->get_switch_attribute(gSwitchId, (uint32_t)attrs.size(), attrs.data());
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to get default 1Q bridge and/or default VLAN, rv:%d", status);
task_process_status handle_status = handleSaiGetStatus(SAI_API_SWITCH, status);
if (handle_status != task_process_status::task_success)
{
throw runtime_error("PortsOrch initialization failure");
}
}
m_default1QBridge = attrs[0].value.oid;
m_defaultVlan = attrs[1].value.oid;
}
/* Get System ports */
getSystemPorts();
if (gMySwitchType != "dpu")
{
removeDefaultVlanMembers();
removeDefaultBridgePorts();
}
/* Add port oper status notification support */
m_notificationsDb = make_shared<DBConnector>("ASIC_DB", 0);
m_portStatusNotificationConsumer = new swss::NotificationConsumer(m_notificationsDb.get(), "NOTIFICATIONS");
auto portStatusNotificatier = new Notifier(m_portStatusNotificationConsumer, this, "PORT_STATUS_NOTIFICATIONS");
Orch::addExecutor(portStatusNotificatier);
if (m_cmisModuleAsicSyncSupported)
{
m_portHostTxReadyNotificationConsumer = new swss::NotificationConsumer(m_notificationsDb.get(), "NOTIFICATIONS");
auto portHostTxReadyNotificatier = new Notifier(m_portHostTxReadyNotificationConsumer, this, "PORT_HOST_TX_NOTIFICATIONS");
Orch::addExecutor(portHostTxReadyNotificatier);
}
if (gMySwitchType == "voq")
{
string tableName;
//Add subscriber to process system LAG (System PortChannel) table
tableName = CHASSIS_APP_LAG_TABLE_NAME;
Orch::addExecutor(new Consumer(new SubscriberStateTable(chassisAppDb, tableName, TableConsumable::DEFAULT_POP_BATCH_SIZE, 0), this, tableName));
m_tableVoqSystemLagTable = unique_ptr<Table>(new Table(chassisAppDb, CHASSIS_APP_LAG_TABLE_NAME));
//Add subscriber to process system LAG member (System PortChannelMember) table
tableName = CHASSIS_APP_LAG_MEMBER_TABLE_NAME;
Orch::addExecutor(new Consumer(new SubscriberStateTable(chassisAppDb, tableName, TableConsumable::DEFAULT_POP_BATCH_SIZE, 0), this, tableName));
m_tableVoqSystemLagMemberTable = unique_ptr<Table>(new Table(chassisAppDb, CHASSIS_APP_LAG_MEMBER_TABLE_NAME));
m_lagIdAllocator = unique_ptr<LagIdAllocator> (new LagIdAllocator(chassisAppDb));
}
auto executor = new ExecutableTimer(m_port_state_poller, this, "PORT_STATE_POLLER");
Orch::addExecutor(executor);
}
void PortsOrch::initializeCpuPort()
{
SWSS_LOG_ENTER();
sai_attribute_t attr;
attr.id = SAI_SWITCH_ATTR_CPU_PORT;
auto status = sai_switch_api->get_switch_attribute(gSwitchId, 1, &attr);
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to get CPU port, rv:%d", status);
auto handle_status = handleSaiGetStatus(SAI_API_SWITCH, status);
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch initialization failure");
}
}
this->m_cpuPort = Port("CPU", Port::CPU);
this->m_cpuPort.m_port_id = attr.value.oid;
this->m_portList[m_cpuPort.m_alias] = m_cpuPort;
this->m_port_ref_count[m_cpuPort.m_alias] = 0;
SWSS_LOG_NOTICE("Get CPU port pid:%" PRIx64, this->m_cpuPort.m_port_id);
}
void PortsOrch::initializePorts()
{
SWSS_LOG_ENTER();
sai_status_t status;
sai_attribute_t attr;
// Get port number
attr.id = SAI_SWITCH_ATTR_PORT_NUMBER;
status = sai_switch_api->get_switch_attribute(gSwitchId, 1, &attr);
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to get port number, rv:%d", status);
auto handle_status = handleSaiGetStatus(SAI_API_SWITCH, status);
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch initialization failure");
}
}
this->m_portCount = attr.value.u32;
SWSS_LOG_NOTICE("Get %d ports", this->m_portCount);
// Get port list
std::vector<sai_object_id_t> portList(this->m_portCount, SAI_NULL_OBJECT_ID);
attr.id = SAI_SWITCH_ATTR_PORT_LIST;
attr.value.objlist.count = static_cast<sai_uint32_t>(portList.size());
attr.value.objlist.list = portList.data();
status = sai_switch_api->get_switch_attribute(gSwitchId, 1, &attr);
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to get port list, rv:%d", status);
auto handle_status = handleSaiGetStatus(SAI_API_SWITCH, status);
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch initialization failure");
}
}
// Get port hardware lane info
for (const auto &portId : portList)
{
std::vector<sai_uint32_t> laneList(Port::max_lanes, 0);
attr.id = SAI_PORT_ATTR_HW_LANE_LIST;
attr.value.u32list.count = static_cast<sai_uint32_t>(laneList.size());
attr.value.u32list.list = laneList.data();
status = sai_port_api->get_port_attribute(portId, 1, &attr);
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to get hardware lane list pid:%" PRIx64, portId);
auto handle_status = handleSaiGetStatus(SAI_API_PORT, status);
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch initialization failure");
}
}
std::set<std::uint32_t> laneSet;
for (sai_uint32_t i = 0; i < attr.value.u32list.count; i++)
{
laneSet.insert(attr.value.u32list.list[i]);
}
this->m_portListLaneMap[laneSet] = portId;
SWSS_LOG_NOTICE(
"Get port with lanes pid:%" PRIx64 " lanes:%s",
portId, swss::join(" ", laneSet.cbegin(), laneSet.cend()).c_str()
);
}
}
auto PortsOrch::getPortConfigState() const -> port_config_state_t
{
return this->m_portConfigState;
}
void PortsOrch::setPortConfigState(port_config_state_t value)
{
this->m_portConfigState = value;
}
bool PortsOrch::addPortBulk(const std::vector<PortConfig> &portList)
{
// The method is used to create ports in a bulk mode.
// The action takes place when:
// 1. Ports are being initialized at system start
// 2. Ports are being added/removed by a user at runtime
SWSS_LOG_ENTER();
if (portList.empty())
{
return true;
}
std::vector<PortAttrValue_t> attrValueList;
std::vector<std::vector<sai_attribute_t>> attrDataList;
std::vector<std::uint32_t> attrCountList;
std::vector<const sai_attribute_t*> attrPtrList;
auto portCount = static_cast<std::uint32_t>(portList.size());
std::vector<sai_object_id_t> oidList(portCount, SAI_NULL_OBJECT_ID);
std::vector<sai_status_t> statusList(portCount, SAI_STATUS_SUCCESS);
for (const auto &cit : portList)
{
sai_attribute_t attr;
std::vector<sai_attribute_t> attrList;
if (cit.lanes.is_set)
{
PortAttrValue_t attrValue;
auto &outList = attrValue.lanes;
auto &inList = cit.lanes.value;
outList.insert(outList.begin(), inList.begin(), inList.end());
attrValueList.push_back(attrValue);
attr.id = SAI_PORT_ATTR_HW_LANE_LIST;
attr.value.u32list.count = static_cast<std::uint32_t>(attrValueList.back().lanes.size());
attr.value.u32list.list = attrValueList.back().lanes.data();
attrList.push_back(attr);
}
if (cit.speed.is_set)
{
attr.id = SAI_PORT_ATTR_SPEED;
attr.value.u32 = cit.speed.value;
attrList.push_back(attr);
}
if (cit.autoneg.is_set)
{
attr.id = SAI_PORT_ATTR_AUTO_NEG_MODE;
attr.value.booldata = cit.autoneg.value;
attrList.push_back(attr);
}
if (cit.fec.is_set)
{
attr.id = SAI_PORT_ATTR_FEC_MODE;
attr.value.s32 = cit.fec.value;
attrList.push_back(attr);
}
if (m_cmisModuleAsicSyncSupported)
{
attr.id = SAI_PORT_ATTR_HOST_TX_SIGNAL_ENABLE;
attr.value.booldata = false;
attrList.push_back(attr);
}
attrDataList.push_back(attrList);
attrCountList.push_back(static_cast<std::uint32_t>(attrDataList.back().size()));
attrPtrList.push_back(attrDataList.back().data());
}
auto status = sai_port_api->create_ports(
gSwitchId, portCount, attrCountList.data(), attrPtrList.data(),
SAI_BULK_OP_ERROR_MODE_IGNORE_ERROR,
oidList.data(), statusList.data()
);
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to create ports with bulk operation, rv:%d", status);
auto handle_status = handleSaiCreateStatus(SAI_API_PORT, status);
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch bulk create failure");
}
return false;
}
for (std::uint32_t i = 0; i < portCount; i++)
{
if (statusList.at(i) != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR(
"Failed to create port %s with bulk operation, rv:%d",
portList.at(i).key.c_str(), statusList.at(i)
);
auto handle_status = handleSaiCreateStatus(SAI_API_PORT, statusList.at(i));
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch bulk create failure");
}
return false;
}
m_portListLaneMap[portList.at(i).lanes.value] = oidList.at(i);
m_portCount++;
}
// newly created ports might be put in the default vlan so remove all ports from
// the default vlan.
if (gMySwitchType == "voq") {
removeDefaultVlanMembers();
removeDefaultBridgePorts();
}
SWSS_LOG_NOTICE("Created ports: %s", swss::join(',', oidList.begin(), oidList.end()).c_str());
return true;
}
bool PortsOrch::removePortBulk(const std::vector<sai_object_id_t> &portList)
{
SWSS_LOG_ENTER();
if (portList.empty())
{
return true;
}
for (const auto &cit : portList)
{
Port p;
// Make sure to bring down admin state
if (getPort(cit, p))
{
setPortAdminStatus(p, false);
}
// else : port is in default state or not yet created
// Remove port serdes (if exists) before removing port since this reference is dependency
removePortSerdesAttribute(cit);
}
auto portCount = static_cast<std::uint32_t>(portList.size());
std::vector<sai_status_t> statusList(portCount, SAI_STATUS_SUCCESS);
auto status = sai_port_api->remove_ports(
portCount, portList.data(),
SAI_BULK_OP_ERROR_MODE_IGNORE_ERROR,
statusList.data()
);
if (status != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR("Failed to remove ports with bulk operation, rv:%d", status);
auto handle_status = handleSaiRemoveStatus(SAI_API_PORT, status);
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch bulk remove failure");
}
return false;
}
for (std::uint32_t i = 0; i < portCount; i++)
{
if (statusList.at(i) != SAI_STATUS_SUCCESS)
{
SWSS_LOG_ERROR(
"Failed to remove port %" PRIx64 " with bulk operation, rv:%d",
portList.at(i), statusList.at(i)
);
auto handle_status = handleSaiRemoveStatus(SAI_API_PORT, statusList.at(i));
if (handle_status != task_process_status::task_success)
{
SWSS_LOG_THROW("PortsOrch bulk remove failure");
}
return false;
}
m_portSupportedSpeeds.erase(portList.at(i));
m_portCount--;
}
SWSS_LOG_NOTICE("Removed ports: %s", swss::join(',', portList.begin(), portList.end()).c_str());