gpio: Enable all GPIO for all targets #66
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Seems I broke something on the stm32l0x2. I'll check it out tomorrow. |
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It looks like even GPIOE and GPIOH are present on the bigger L0x1 chips, so maybe all the |
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Ah, you're right, I missed that! |
According to the reference manuals for the 0x1¹, 0x2² and 0x3³ series, the GPIO A/B/C/D/E as well as H[0:1][9:10] are available on all devices (given a class 5 device). ¹ Reference manual RM0377 ² Reference manual RM0376 ³ Reference manual RM0367
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It wasn't in my code, but I fixed it anyways.
Verified against the reference manuals and fixed. Do you plan to limit the availability of GPIO pins depending on the package in the future? |
I can't speak to anyone's plans, but I'd like to note there's precedent for going full bananas with packages: https://github.com/stm32-rs/stm32l0xx-hal/blob/68eeba6cd8c71a22b365d15dfe4ae9c4bb62888a/src/adc.rs#L223-#L299 |
This is technically true, but I think there is no released L0x1 chip that actually has those ports, so maybe it doesn't make sense to expose them? |
Hm? There's the STM32L071V8 with an LQFP100 package.
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Oh, never mind then. I was confused by ST's product selector. |
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Good catch! Thanks for fixing the serial dma async bug as well. Not sure how that one slipped through the cracks. |
For some reason, GPIOC and GPIOD were disabled for the stm32l0x1, but these GPIO banks are present in the PAC (and in the datasheet).