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Update K64 sdk drivers #3194

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merged 3 commits into from
Nov 10, 2016
Merged

Update K64 sdk drivers #3194

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931da51
K64F: Update to the latest SDK drivers
mmahadevan108 Oct 31, 2016
177eaff
K64F ENET: Update to remove unused variable. This is no longer availa…
mmahadevan108 Oct 31, 2016
1c2a7d8
Added the commit: Access MCG and SIM through secure access
salkinium Nov 4, 2016
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2 changes: 0 additions & 2 deletions features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/k64f_emac.c
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Original file line number Diff line number Diff line change
Expand Up @@ -86,10 +86,8 @@ static void update_read_buffer(uint8_t *buf)
/* Increases the buffer descriptor to the next one. */
if (g_handle.rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) {
g_handle.rxBdCurrent = g_handle.rxBdBase;
g_handle.rxBdDirty = g_handle.rxBdBase;
} else {
g_handle.rxBdCurrent++;
g_handle.rxBdDirty++;
}

/* Actives the receive buffer descriptor. */
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82 changes: 43 additions & 39 deletions targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/device/MK64F12.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*
** ###################################################################
** Processors: MK64FN1M0VDC12
** Processors: MK64FN1M0CAJ12
** MK64FN1M0VDC12
** MK64FN1M0VLL12
** MK64FN1M0VLQ12
** MK64FN1M0VMD12
Expand All @@ -15,13 +16,13 @@
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
** Version: rev. 2.8, 2015-02-19
** Build: b151218
** Version: rev. 2.9, 2016-03-21
** Build: b160321
**
** Abstract:
** CMSIS Peripheral Access Layer for MK64F12
**
** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without modification,
Expand Down Expand Up @@ -84,14 +85,17 @@
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
** - rev. 2.8 (2015-02-19)
** Renamed interrupt vector LLW to LLWU.
** - rev. 2.9 (2016-03-21)
** Added MK64FN1M0CAJ12 part.
** GPIO - renamed port instances: PTx -> GPIOx.
**
** ###################################################################
*/

/*!
* @file MK64F12.h
* @version 2.8
* @date 2015-02-19
* @version 2.9
* @date 2016-03-21
* @brief CMSIS Peripheral Access Layer for MK64F12
*
* CMSIS Peripheral Access Layer for MK64F12
Expand All @@ -104,7 +108,7 @@
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0200U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0008U
#define MCU_MEM_MAP_VERSION_MINOR 0x0009U

/**
* @brief Macro to calculate address of an aliased word in the peripheral
Expand Down Expand Up @@ -6926,30 +6930,30 @@ typedef struct {


/* GPIO - Peripheral instance base addresses */
/** Peripheral PTA base address */
#define PTA_BASE (0x400FF000u)
/** Peripheral PTA base pointer */
#define PTA ((GPIO_Type *)PTA_BASE)
/** Peripheral PTB base address */
#define PTB_BASE (0x400FF040u)
/** Peripheral PTB base pointer */
#define PTB ((GPIO_Type *)PTB_BASE)
/** Peripheral PTC base address */
#define PTC_BASE (0x400FF080u)
/** Peripheral PTC base pointer */
#define PTC ((GPIO_Type *)PTC_BASE)
/** Peripheral PTD base address */
#define PTD_BASE (0x400FF0C0u)
/** Peripheral PTD base pointer */
#define PTD ((GPIO_Type *)PTD_BASE)
/** Peripheral PTE base address */
#define PTE_BASE (0x400FF100u)
/** Peripheral PTE base pointer */
#define PTE ((GPIO_Type *)PTE_BASE)
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x400FF000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x400FF040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
/** Peripheral GPIOC base address */
#define GPIOC_BASE (0x400FF080u)
/** Peripheral GPIOC base pointer */
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
/** Peripheral GPIOD base address */
#define GPIOD_BASE (0x400FF0C0u)
/** Peripheral GPIOD base pointer */
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
/** Peripheral GPIOE base address */
#define GPIOE_BASE (0x400FF100u)
/** Peripheral GPIOE base pointer */
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }

/*!
* @}
Expand Down Expand Up @@ -12677,16 +12681,16 @@ typedef struct {
#define DSPI1 SPI1
#define DSPI2 SPI2
#define FLEXCAN0 CAN0
#define GPIOA_BASE PTA_BASE
#define GPIOA PTA
#define GPIOB_BASE PTB_BASE
#define GPIOB PTB
#define GPIOC_BASE PTC_BASE
#define GPIOC PTC
#define GPIOD_BASE PTD_BASE
#define GPIOD PTD
#define GPIOE_BASE PTE_BASE
#define GPIOE PTE
#define PTA_BASE GPIOA_BASE
#define PTA GPIOA
#define PTB_BASE GPIOB_BASE
#define PTB GPIOB
#define PTC_BASE GPIOC_BASE
#define PTC GPIOC
#define PTD_BASE GPIOD_BASE
#define PTD GPIOD
#define PTE_BASE GPIOE_BASE
#define PTE GPIOE
#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
Expand Down
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