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feat: Make all core types serializable (#850)
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Implements serialization on some core types that where missing it
(Incoming/Outgoing ports, Wires, ...)

Required for CQCL/tket2#220
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aborgna-q authored Feb 28, 2024
1 parent 8ade90c commit ff5f117
Showing 1 changed file with 12 additions and 4 deletions.
16 changes: 12 additions & 4 deletions src/core.rs
Original file line number Diff line number Diff line change
Expand Up @@ -50,21 +50,27 @@ pub trait NodeIndex {
}

/// A port in the incoming direction.
#[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord, Hash, Default)]
#[derive(
Clone, Copy, PartialEq, PartialOrd, Eq, Ord, Hash, Default, serde::Serialize, serde::Deserialize,
)]
pub struct IncomingPort {
index: u16,
}

/// A port in the outgoing direction.
#[derive(Clone, Copy, PartialEq, PartialOrd, Eq, Ord, Hash, Default)]
#[derive(
Clone, Copy, PartialEq, PartialOrd, Eq, Ord, Hash, Default, serde::Serialize, serde::Deserialize,
)]
pub struct OutgoingPort {
index: u16,
}

/// The direction of a port.
pub type Direction = portgraph::Direction;

#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
#[derive(
Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
)]
/// A DataFlow wire, defined by a Value-kind output port of a node
// Stores node and offset to output port
pub struct Wire(Node, OutgoingPort);
Expand Down Expand Up @@ -223,7 +229,9 @@ impl Wire {
///
/// Falls back to [`Wire`] if the wire is not linear or if it's not possible to
/// track the origin.
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
#[derive(
Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
)]
pub enum CircuitUnit {
/// Arbitrary input wire.
Wire(Wire),
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