Remove litex dontCareGenAsZero/init all reg

SpinalHDL · Jan 30, 2025 · 084181b · 084181b
1 parent a834f9f
commit 084181b
Showing 1 changed file with 0 additions and 9 deletions.
diff --git a/src/main/scala/vexiiriscv/soc/litex/Soc.scala b/src/main/scala/vexiiriscv/soc/litex/Soc.scala
@@ -469,15 +469,6 @@ object SocGen extends App{
   val spinalConfig = SpinalConfig(inlineRom = true, targetDirectory = netlistDirectory)
   spinalConfig.addTransformationPhase(new MultiPortWritesSymplifier)
   spinalConfig.addStandardMemBlackboxing(blackboxPolicy)
-  spinalConfig.dontCareGenAsZero = true
-  spinalConfig.addTransformationPhase(new PhaseNetlist {
-    override def impl(pc: PhaseContext) = {
-      pc.walkDeclarations{
-        case bt : BaseType if bt.isReg && !bt.hasInit && bt.clockDomain.canInit => bt.component.rework(bt.init(bt.getZero))
-        case _ =>
-      }
-    }
-  })
 //  spinalConfig.addTransformationPhase(new EnforceSyncRamPhase)
 
   val report = spinalConfig.generateVerilog {