Add --stressed-fpu

src/main/scala/vexiiriscv/Param.scala

@@ -12,6 +12,7 @@ import vexiiriscv._
 import vexiiriscv.decode.DecoderPlugin
 import vexiiriscv.execute._
 import vexiiriscv.execute.cfu.{CfuBusParameter, CfuPlugin, CfuPluginEncoding}
+import vexiiriscv.execute.fpu.{FpuAddSharedParam, FpuMulParam}
 import vexiiriscv.execute.lsu._
 import vexiiriscv.fetch.{FetchCachelessPlugin, FetchL1Plugin, PrefetcherNextLinePlugin}
 import vexiiriscv.memory.{MmuPortParameter, MmuSpec, MmuStorageLevel, MmuStorageParameter, PmpParam, PmpPlugin, PmpPortParameter}
@@ -107,9 +108,10 @@ class ParamSimple(){
   var withRva = false
   var withRvf = false
   var btbDualPortRam = true
-  var skipFma = false
-  var fpuFmaFullAccuracy = true
   var fpuIgnoreSubnormal = false
+  var fpuWbAt = 2
+  var fpuMulParam = FpuMulParam()
+  var fpuAddSharedParam = FpuAddSharedParam()
   var withRvd = false
   var withRvZb = false
   var withWhiteboxerOutputs = false
@@ -511,6 +513,17 @@ class ParamSimple(){
     opt[Unit]("stressed-branch") action { (v, c) => relaxedBranch = false }
     opt[Unit]("stressed-shift") action { (v, c) => relaxedShift = false }
     opt[Unit]("stressed-src") action { (v, c) => relaxedSrc = false }
+    opt[Unit]("stressed-fpu") action { (v, c) =>
+      fpuMulParam.expAt = 0
+      fpuMulParam.normAt = 2
+      fpuMulParam.packAt = 2
+      fpuAddSharedParam.preShiftStage = 0
+      fpuAddSharedParam.shifterStage = 0
+      fpuAddSharedParam.mathStage = 1
+      fpuAddSharedParam.normStage = 2
+      fpuAddSharedParam.packAt = 2
+      fpuWbAt = 1
+    }
     opt[Unit]("with-mul") unbounded() action { (v, c) => withMul = true }
     opt[Unit]("with-div") unbounded() action { (v, c) => withDiv = true }
     opt[Unit]("with-rvm") action { (v, c) => withMul = true; withDiv = true }
@@ -521,7 +534,7 @@ class ParamSimple(){
     opt[Unit]("with-rvZb") action { (v, c) => withRvZb = true }
     opt[Unit]("with-whiteboxer-outputs") action { (v, c) => withWhiteboxerOutputs = true }
     opt[Unit]("with-hart-id-input") action { (v, c) => withHartIdInput = true }
-    opt[Unit]("fma-reduced-accuracy") action { (v, c) => fpuFmaFullAccuracy = false }
+    opt[Unit]("fma-reduced-accuracy") action { (v, c) => fpuMulParam.fmaFullAccuracy = false }
     opt[Unit]("fpu-ignore-subnormal") action { (v, c) => fpuIgnoreSubnormal = true }
     opt[Unit]("with-aligner-buffer") unbounded() action { (v, c) => withAlignerBuffer = true }
     opt[Unit]("with-dispatcher-buffer") action { (v, c) => withDispatcherBuffer = true }
@@ -959,17 +972,17 @@ class ParamSimple(){
       plugins += new execute.fpu.FpuFlagsWritebackPlugin(lane0, pipTo = intWritebackAt)
       plugins += new execute.fpu.FpuCsrPlugin(List(lane0), intWritebackAt)
       plugins += new execute.fpu.FpuUnpackerPlugin(early0, ignoreSubnormal = fpuIgnoreSubnormal)
-      plugins += new execute.fpu.FpuAddSharedPlugin(lane0)
+      plugins += new execute.fpu.FpuAddSharedPlugin(lane0, p = fpuAddSharedParam)
       plugins += new execute.fpu.FpuAddPlugin(early0)
-      plugins += new execute.fpu.FpuMulPlugin(early0, withFma = !skipFma, fmaFullAccuracy = fpuFmaFullAccuracy)
+      plugins += new execute.fpu.FpuMulPlugin(early0, p = fpuMulParam)
       plugins += new execute.fpu.FpuSqrtPlugin(early0)
       plugins += new execute.fpu.FpuClassPlugin(early0)
       plugins += new execute.fpu.FpuCmpPlugin(early0)
       plugins += new execute.fpu.FpuF2iPlugin(early0)
       plugins += new execute.fpu.FpuMvPlugin(early0, floatWbAt = 2)
       if(withRvd) plugins += new execute.fpu.FpuXxPlugin(early0)
       plugins += new execute.fpu.FpuDivPlugin(early0)
-      plugins += new execute.fpu.FpuPackerPlugin(lane0, ignoreSubnormal = fpuIgnoreSubnormal)
+      plugins += new execute.fpu.FpuPackerPlugin(lane0, ignoreSubnormal = fpuIgnoreSubnormal, wbAt = fpuWbAt)
     }
 
     plugins += new WhiteboxerPlugin(

src/main/scala/vexiiriscv/execute/fpu/FpuAddSharedPlugin.scala

@@ -31,18 +31,21 @@ class FpuAddSharedPort(_cmd : FpuAddSharedCmd) extends Area{
   val cmd = _cmd
 }
 
+case class FpuAddSharedParam(var preShiftStage : Int = 0,
+                             var shifterStage : Int = 1,
+                             var mathStage : Int = 2,
+                             var normStage : Int = 3,
+                             var packAt : Int = 4)
+
 /**
  * This plugin implements an shared hardware floating point adder and provide an API for other plugins to time share it.
  * In practice, the RISC-V fadd and fma instruction use it.
  * The actual adder hadware is provided by the FpuAdd plugin.
  */
 class FpuAddSharedPlugin(lane: ExecuteLanePlugin,
-                         preShiftStage : Int = 0,
-                         shifterStage : Int = 1,
-                         mathStage : Int = 2,
-                         normStage : Int = 3,
-                         packAt : Int = 4) extends FiberPlugin {
-  val p = FpuUtils
+                         p : FpuAddSharedParam) extends FiberPlugin {
+  import p._
+  val fu = FpuUtils
 
   val elaborationLock = Retainer()
 

src/main/scala/vexiiriscv/execute/fpu/FpuMulPlugin.scala

@@ -10,17 +10,19 @@ import vexiiriscv.execute.fpu.FpuUtils.FORMAT
 import vexiiriscv.riscv.Riscv.XLEN
 import vexiiriscv.riscv._
 
+case class FpuMulParam( var withFma : Boolean = true,
+                        var fmaFullAccuracy : Boolean = true,
+                        var expAt : Int = 0,
+                        var normAt: Int = 3,
+                        var packAt : Int = 3)
+
 /**
  * Add the floating point mul instruction the CPU.
  * The mantissa multiplier is implemented by reusing the hardware from the integer multiplier
  */
-class FpuMulPlugin(val layer : LaneLayer,
-                   withFma : Boolean = true,
-                   fmaFullAccuracy : Boolean = true,
-                   var expAt : Int = 0,
-                   var normAt: Int = 3,
-                   var packAt : Int = 3) extends FiberPlugin{
-  val p = FpuUtils
+class FpuMulPlugin(val layer : LaneLayer, p : FpuMulParam) extends FiberPlugin{
+  import p._
+  val fu = FpuUtils
 
   val SEL = Payload(Bool())
   val FMA = Payload(Bool())
@@ -35,18 +37,18 @@ class FpuMulPlugin(val layer : LaneLayer,
     val buildBefore = retains(layer.lane.pipelineLock)
     val uopLock = retains(layer.lane.uopLock, fup.elaborationLock, fpp.elaborationLock, mp.mulLock)
     awaitBuild()
-    mp.injectWidth(p.unpackedConfig.mantissaWidth + 2, p.unpackedConfig.mantissaWidth + 2, 2 * (p.unpackedConfig.mantissaWidth + 2))
+    mp.injectWidth(fu.unpackedConfig.mantissaWidth + 2, fu.unpackedConfig.mantissaWidth + 2, 2 * (fu.unpackedConfig.mantissaWidth + 2))
 
     val packParam = FloatUnpackedParam(
-      exponentMax   = p.unpackedConfig.exponentMax * 2 + 1,
-      exponentMin   = p.unpackedConfig.exponentMin * 2,
-      mantissaWidth = p.unpackedConfig.mantissaWidth + 2
+      exponentMax   = fu.unpackedConfig.exponentMax * 2 + 1,
+      exponentMin   = fu.unpackedConfig.exponentMin * 2,
+      mantissaWidth = fu.unpackedConfig.mantissaWidth + 2
     )
 
     val addParam = FloatUnpackedParam(
-      exponentMax = p.unpackedConfig.exponentMax * 2 + 1,
-      exponentMin = p.unpackedConfig.exponentMin * 2,
-      mantissaWidth = fmaFullAccuracy.mux(p.unpackedConfig.mantissaWidth * 2 + 1, packParam.mantissaWidth)
+      exponentMax = fu.unpackedConfig.exponentMax * 2 + 1,
+      exponentMin = fu.unpackedConfig.exponentMin * 2,
+      mantissaWidth = fmaFullAccuracy.mux(fu.unpackedConfig.mantissaWidth * 2 + 1, packParam.mantissaWidth)
     )
 
     val packPort = fpp.createPort(List(packAt), packParam)

src/test/scala/vexiiriscv/scratchpad/Synt.scala

@@ -787,7 +787,7 @@ object IntegrationSynthBench extends App{
 
     withRvf = true
     withRvd = true
-    fpuFmaFullAccuracy = false
+    fpuMulParam.fmaFullAccuracy = false
     fpuIgnoreSubnormal = false
   }
 

src/test/scala/vexiiriscv/tester/Regression.scala

@@ -106,6 +106,7 @@ class Regression extends MultithreadedFunSuite(sys.env.getOrElse("VEXIIRISCV_REG
       return List("", "--with-rvf", "--with-rvf --with-rvd").randomPick(random)
     }
   }
+  addDim("fpuStressed", List("", "--stressed-fpu"))
   addDim("pmp", List("", "--pmp-size=8"))
   dimensions += new Dimensions[ParamSimple]("btbRelaxed") {
     override def getRandomPosition(state : ParamSimple, random: Random): String = {