Pattern matching for indirect register addressing #87
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chbessonova
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chbessonova
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This is another implementation for emitting instructions in indirect register addressing mode (just note that indirect register addressing has 2 bytes less encoding than indexed one).
First one was in #66. It provides an MI-level pass which rewrites mm|mr instructions where displacement == 0 to their nm|nr counterpart.
This one is more straightforward. It allows matching correct instruction form on ISel phase. The only drawback it has is that it doesn't work with SP base register.
Will appreciate any feedback for this or/and #66 implementation.