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Add support for AD4052 ADC Family #2642
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Here it goes first round of review...
I think this one can be upstreamed without the offload bits
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Change log v0 -> v1 Review changes:
New:
Design changes:
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drivers/iio/adc/Kconfig
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tristate "Analog Devices AD4052 Driver" | ||
depends on SPI | ||
depends on PWM | ||
depends on GPIOLIB |
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I'm also not sure if gpio is something you should depend on or just select it. I think the single shot reading could be something useful to have even more to make this driver more upstreamable without offload support (we can still some questions about it though).
drivers/iio/adc/Kconfig
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tristate "Analog Devices AD4052 Driver" | ||
depends on SPI | ||
depends on PWM | ||
depends on GPIOLIB |
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Also one not on the commit message. Style is iio: adc: ...
. Drop the drivers:
if (val == 0) { | ||
st->mode = AD4052_SAMPLE_MODE; | ||
} else { | ||
st->mode = AD4052_BURST_AVERAGING_MODE; |
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I would double check other examples of oversampling. To me this is a 1 or 0 thing. Either it's enabled it not. Your mode variable also just seems to have two states here so the way you're handling val
raises some questions.
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The device supports from 2 to 4096 in powers of 2 samples for avg mode.
Decided to reserve 0 and 1 to disable the feature (return to sample mode)
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Change log v1 -> v2 Review changes:
Changes:
Extra force push to resolve merge conflict |
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Change log v2 -> v3
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This is not forgotten... I'll try to check it Monday |
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Force pushed to resolve merge conflicts due to main rebase. |
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@nunojsa is this version good enough to consider finished? |
Sorry for the slow approach on this one...
Definitely... But I would even say to maybe wait a few more weeks. We can be close to land spi offload support upstream.
I'll take a look. Note that CI is failing - maybe due to conflicts with 6.6 merge |
drivers/iio/adc/ad4052.c
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/* Single sample read should be used only for oversampling and | ||
* sampling frequency pairs that take less than 1 sec. | ||
*/ | ||
if (st->gp1_irq.enabled) { |
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can we do raw reads without the IRQ?
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Without oversampling enabled the raw read may be slower than the gpio CNV to spi transfer,
allowing to do raw reads without the IRQ.
But I will remove this option/use case.
Note: CNV and GP0 (threshold) are still optional.
Note 2: Since CNV is optional, if cnv not present I will yield an empty spi transfer to trigger a conversion (considering the user had shorten CNV to CS)
return PTR_ERR(gpio); | ||
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if (gpio) { | ||
irq = gpiod_to_irq(gpio); |
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Directly use devm_request_threaded_irq()... i see one the IRQs is for completion but what's the purpose of the other one? We need some comments here I guess
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One is for the threshold IIO event (ad4052_irq_handler_thresh).
The other is drdy for raw read (completion).
I didn't get the comment to directly use devm_request_threaded_irq.
Do you want me to change from a soft interrupt from the GPIO (like ad9081,c) to a hard interrupt (like ad7280a.c)?
} else { | ||
val = ilog2(val); | ||
st->mode = AD4052_BURST_AVERAGING_MODE; | ||
ret = regmap_write(st->regmap, AD4052_REG_AVG_CONFIG, val - 1); |
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We should still make sure val is valid right?
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It already bounds the value at AD4052_CHECK_OVERSAMPLING.
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V2 -> V3
Tested on HW at fsclk 31.25MHz (could not achieve datasheet 62.5MHz). TODO: Solve buffer/sample_freq hack . Wait upstream offload? |
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V4:
In practice:
Sorry for forgetting to track #2640, this could have been done earlier. Note: waiting hw test to push V5, that resolves the hackish:
By using samp_freq for the pwm freq (like pulsar.c), and moving the sample_rate device register to an ext_info attribute. |
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V5
V4..V5
Wait V6 due to #2713? |
This was merged... Sorry for missing this one for a long time. Ping me when you have a new version for review |
Add dt-bindings for AD4052 family, devices AD4050/AD4052/AD4056/AD4058, low-power with monitor capabilities SAR ADCs. Contain selectable oversampling and sample rate, the latter for both oversampling and monitor mode. The monitor capability is exposed as an IIO threshold either direction event. Signed-off-by: Jorge Marques <[email protected]>
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The AD4052 CNV pin is driven by a GPIO for single shot readings and by a PWM for buffer readings. The functional-mode entry allows to set Sample Mode (0) or Burst Averaging Mode (1). During runtime, it is possible to enter Trigger Mode through IIO Events. Signed-off-by: Jorge Marques <[email protected]>
This adds a new page to document how to use the ad4052 ADC driver. Signed-off-by: Jorge Marques <[email protected]>
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V6
I decided to not fallback to a triggered buffer to not have to mux the RDY signal for triggered buffer and raw read.
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I'll wait until you fix the build issues in CI |
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The AD4052/AD4058/AD4050/AD4056 are versatile, 16-bit/12-bit, successive approximation register (SAR) analog-to-digital converter (ADC) that enables low-power, high-density data acquisition solutions without sacrificing precision. This ADC offers a unique balance of performance and power efficiency, plus innovative features for seamlessly switching between high-resolution and low-power modes tailored to the immediate needs of the system. The AD4052/AD4058/AD4050/AD4056 are ideal for battery-powered, compact data acquisition and edge sensing applications. Signed-off-by: Jorge Marques <[email protected]>
Add entry for the AD4052 ADC family driver. Signed-off-by: Jorge Marques <[email protected]>
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@nunojsa Sorry, fixed the warnings.
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PR Description
Add:
Optional:
Features:
Overall, the highlight of this device is the monitor capability, leveraged by the autonomous trigger mode and exposed as IIO Event.
Linux driver doc:
HDL: analogdevicesinc/hdl#1504
Datasheet: www.analog.com/ad4052
Tested on Coraz7s
PR Type
PR Checklist