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Fix RISC-V Debug Functional Test Errors #489

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merged 2 commits into from
Mar 14, 2023
Merged

Fix RISC-V Debug Functional Test Errors #489

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1ee175d
Use MXC_NVIC_SetVector for AI87 imagenet-riscv
Jake-Carter Mar 14, 2023
2e04b03
Signal M4 before entering while(1)
Jake-Carter Mar 14, 2023
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6 changes: 3 additions & 3 deletions Examples/MAX32655/Hello_World-riscv/main_riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,9 @@ int main(void)
Debug_Init(); // Set up RISCV JTAG
MXC_ICC_Enable(MXC_ICC1); // Enable cache

// Signal the Cortex-M4
MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;

printf("Hello World!\n");
while (1) {
LED_On(0);
Expand All @@ -56,8 +59,5 @@ int main(void)
printf("count = %d\n", cnt++);
}

// Signal the Cortex-M4
MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;

return 0;
}
6 changes: 3 additions & 3 deletions Examples/MAX32680/Hello_World-riscv/main_riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,9 @@ int main(void)
Debug_Init(); // Set up RISCV JTAG
MXC_ICC_Enable(MXC_ICC1); // Enable cache

// Signal the Cortex-M4
MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;

printf("Hello World!\n");
while (1) {
LED_On(0);
Expand All @@ -56,8 +59,5 @@ int main(void)
printf("count = %d\n", cnt++);
}

// Signal the Cortex-M4
MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;

return 0;
}
2 changes: 1 addition & 1 deletion Examples/MAX78002/CNN/imagenet-riscv/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ int main(void)

MXC_FCR->urvbootaddr = (uint32_t)&__FlashStart_; // Set RISC-V boot address
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SMPHR); // Enable Sempahore clock
NVIC_SetVector(RISCV_IRQn, WakeISR); // Set wakeup ISR
MXC_NVIC_SetVector(RISCV_IRQn, WakeISR); // Set wakeup ISR

// DO NOT DELETE THIS LINE:
MXC_Delay(SEC(2)); // Let debugger interrupt if needed
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