GitHub - bdshaffer73/ComputerDesign: A 32-bit computer designed in Verilog to run on Altera DE2 FPGAs.

bdshaffer73 / ComputerDesign Public

A 32-bit computer designed in Verilog to run on Altera DE2 FPGAs.

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
db		db
greybox_tmp		greybox_tmp
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
CONTROL.v		CONTROL.v
CONTROL.v.bak		CONTROL.v.bak
CONTROL.v~		CONTROL.v~
MEM.v		MEM.v
MEM.v.bak		MEM.v.bak
MEMORY.qip		MEMORY.qip
MEMORY.v		MEMORY.v
MEMORY_bb.v		MEMORY_bb.v
PC.v		PC.v
PC.v~		PC.v~
REG.v		REG.v
REGFILE.v		REGFILE.v
REGFILE.v.bak		REGFILE.v.bak
ReadMe.txt		ReadMe.txt
SevenSeg.v		SevenSeg.v
SevenSeg.v.bak		SevenSeg.v.bak
VM.mif		VM.mif
VM.pti_db_list.ddb		VM.pti_db_list.ddb
VM.qpf		VM.qpf
VM.qsf		VM.qsf
VM.qws		VM.qws
VM.tis_db_list.ddb		VM.tis_db_list.ddb
VM.v		VM.v
VM.v.bak		VM.v.bak
VM.v~		VM.v~

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This code is meant to be compiled in Altera Quartus and run on a DE2-115 FPGA.

A 32-bit computer designed in Verilog to run on Altera DE2 FPGAs.

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