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x64: rework new assembler rule priorities, remove old emission rules #10260

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merged 5 commits into from
Feb 22, 2025
Merged

x64: rework new assembler rule priorities, remove old emission rules #10260

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1f844b4
x64: Use priority overlap in new instruction lowerings
alexcrichton Feb 17, 2025
e6a97ad
x64: ensure 8-bit sign extensions have higher priorities
abrown Feb 20, 2025
7c2f6bd
x64: remove old emission replaced by new assembler
abrown Feb 20, 2025
62136d7
x64: re-prioritize based review, add line breaks
abrown Feb 22, 2025
c912ab0
review: remove `is_mem` extractor for now
abrown Feb 22, 2025
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135 changes: 55 additions & 80 deletions cranelift/codegen/src/isa/x64/inst.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -2747,23 +2747,18 @@

;; Helper for emitting `add` instructions.
(decl x64_add (Type Gpr GprMemImm) Gpr)
(rule 12 (x64_add $I8 src1 (is_imm8 src2)) (x64_addb_mi src1 src2))
(rule 11 (x64_add $I16 src1 (is_imm16 src2)) (x64_addw_mi src1 src2))
(rule 10 (x64_add $I32 src1 (is_simm8 src2)) (x64_addl_mi_sxb src1 src2))
(rule 9 (x64_add $I32 src1 (is_imm32 src2)) (x64_addl_mi src1 src2))
(rule 8 (x64_add $I64 src1 (is_simm8 src2)) (x64_addq_mi_sxb src1 src2))
(rule 7 (x64_add $I64 src1 (is_simm32 src2)) (x64_addq_mi_sxl src1 src2))
(rule 6 (x64_add $I8 src1 (is_gpr src2)) (x64_addl_rm src1 src2))
(rule 5 (x64_add $I8 src1 (is_mem src2)) (x64_addb_rm src1 src2))
(rule 4 (x64_add $I16 src1 (is_gpr src2)) (x64_addl_rm src1 src2))
(rule 1 (x64_add $I8 src1 (is_imm8 src2)) (x64_addb_mi src1 src2))
(rule 2 (x64_add $I8 src1 (is_gpr src2)) (x64_addl_rm src1 src2))
(rule 3 (x64_add $I8 src1 (is_mem src2)) (x64_addb_rm src1 src2))
(rule 1 (x64_add $I16 src1 (is_imm16 src2)) (x64_addw_mi src1 src2))
(rule 2 (x64_add $I16 src1 (is_gpr src2)) (x64_addl_rm src1 src2))
(rule 3 (x64_add $I16 src1 (is_mem src2)) (x64_addw_rm src1 src2))
(rule 2 (x64_add $I32 src1 (is_gpr_mem src2)) (x64_addl_rm src1 src2))
(rule 1 (x64_add $I64 src1 (is_gpr_mem src2)) (x64_addq_rm src1 src2))
(rule 0 (x64_add ty src1 src2)
(alu_rmi_r ty
(AluRmiROpcode.Add)
src1
src2))
(rule 1 (x64_add $I32 src1 (is_imm32 src2)) (x64_addl_mi src1 src2))
(rule 2 (x64_add $I32 src1 (is_simm8 src2)) (x64_addl_mi_sxb src1 src2))
(rule 3 (x64_add $I32 src1 (is_gpr_mem src2)) (x64_addl_rm src1 src2))
(rule 1 (x64_add $I64 src1 (is_simm32 src2)) (x64_addq_mi_sxl src1 src2))
(rule 2 (x64_add $I64 src1 (is_simm8 src2)) (x64_addq_mi_sxb src1 src2))
(rule 3 (x64_add $I64 src1 (is_gpr_mem src2)) (x64_addq_rm src1 src2))

;; Helper for creating `add` instructions whose flags are also used.
(decl x64_add_with_flags_paired (Type Gpr GprMemImm) ProducesFlags)
Expand Down Expand Up @@ -2823,23 +2818,18 @@

;; Helper for emitting `sub` instructions.
(decl x64_sub (Type Gpr GprMemImm) Gpr)
(rule 12 (x64_sub $I8 src1 (is_imm8 src2)) (x64_subb_mi src1 src2))
(rule 11 (x64_sub $I16 src1 (is_imm16 src2)) (x64_subw_mi src1 src2))
(rule 10 (x64_sub $I32 src1 (is_simm8 src2)) (x64_subl_mi_sxb src1 src2))
(rule 9 (x64_sub $I32 src1 (is_imm32 src2)) (x64_subl_mi src1 src2))
(rule 8 (x64_sub $I64 src1 (is_simm8 src2)) (x64_subq_mi_sxb src1 src2))
(rule 7 (x64_sub $I64 src1 (is_simm32 src2)) (x64_subq_mi_sxl src1 src2))
(rule 6 (x64_sub $I8 src1 (is_gpr src2)) (x64_subl_rm src1 src2))
(rule 5 (x64_sub $I8 src1 (is_mem src2)) (x64_subb_rm src1 src2))
(rule 4 (x64_sub $I16 src1 (is_gpr src2)) (x64_subl_rm src1 src2))
(rule 1 (x64_sub $I8 src1 (is_imm8 src2)) (x64_subb_mi src1 src2))
(rule 2 (x64_sub $I8 src1 (is_gpr src2)) (x64_subl_rm src1 src2))
(rule 3 (x64_sub $I8 src1 (is_mem src2)) (x64_subb_rm src1 src2))
(rule 1 (x64_sub $I16 src1 (is_imm16 src2)) (x64_subw_mi src1 src2))
(rule 2 (x64_sub $I16 src1 (is_gpr src2)) (x64_subl_rm src1 src2))
(rule 3 (x64_sub $I16 src1 (is_mem src2)) (x64_subw_rm src1 src2))
(rule 2 (x64_sub $I32 src1 (is_gpr_mem src2)) (x64_subl_rm src1 src2))
(rule 1 (x64_sub $I64 src1 (is_gpr_mem src2)) (x64_subq_rm src1 src2))
(rule 0 (x64_sub ty src1 src2)
(alu_rmi_r ty
(AluRmiROpcode.Sub)
src1
src2))
(rule 1 (x64_sub $I32 src1 (is_imm32 src2)) (x64_subl_mi src1 src2))
(rule 2 (x64_sub $I32 src1 (is_simm8 src2)) (x64_subl_mi_sxb src1 src2))
(rule 3 (x64_sub $I32 src1 (is_gpr_mem src2)) (x64_subl_rm src1 src2))
(rule 1 (x64_sub $I64 src1 (is_simm32 src2)) (x64_subq_mi_sxl src1 src2))
(rule 2 (x64_sub $I64 src1 (is_simm8 src2)) (x64_subq_mi_sxb src1 src2))
(rule 3 (x64_sub $I64 src1 (is_gpr_mem src2)) (x64_subq_rm src1 src2))

;; Helper for creating `sub` instructions whose flags are also used.
(decl x64_sub_with_flags_paired (Type Gpr GprMemImm) ProducesFlags)
Expand Down Expand Up @@ -3029,23 +3019,18 @@
;; Note that, to avoid potential partial-register stalls, we use the 32-bit-wide
;; instruction when we know the 8-bit or 16-bit values are both in registers.
(decl x64_and (Type Gpr GprMemImm) Gpr)
(rule 12 (x64_and $I8 src1 (is_imm8 src2)) (x64_andb_mi src1 src2))
(rule 11 (x64_and $I16 src1 (is_imm16 src2)) (x64_andw_mi src1 src2))
(rule 10 (x64_and $I32 src1 (is_simm8 src2)) (x64_andl_mi_sxb src1 src2))
(rule 9 (x64_and $I32 src1 (is_imm32 src2)) (x64_andl_mi src1 src2))
(rule 8 (x64_and $I64 src1 (is_simm8 src2)) (x64_andq_mi_sxb src1 src2))
(rule 7 (x64_and $I64 src1 (is_simm32 src2)) (x64_andq_mi_sxl src1 src2))
(rule 6 (x64_and $I8 src1 (is_gpr src2)) (x64_andl_rm src1 src2))
(rule 5 (x64_and $I8 src1 (is_mem src2)) (x64_andb_rm src1 src2))
(rule 4 (x64_and $I16 src1 (is_gpr src2)) (x64_andl_rm src1 src2))
(rule 1 (x64_and $I8 src1 (is_imm8 src2)) (x64_andb_mi src1 src2))
(rule 2 (x64_and $I8 src1 (is_gpr src2)) (x64_andl_rm src1 src2))
(rule 3 (x64_and $I8 src1 (is_mem src2)) (x64_andb_rm src1 src2))
(rule 1 (x64_and $I16 src1 (is_imm16 src2)) (x64_andw_mi src1 src2))
(rule 2 (x64_and $I16 src1 (is_gpr src2)) (x64_andl_rm src1 src2))
(rule 3 (x64_and $I16 src1 (is_mem src2)) (x64_andw_rm src1 src2))
(rule 2 (x64_and $I32 src1 (is_gpr_mem src2)) (x64_andl_rm src1 src2))
(rule 1 (x64_and $I64 src1 (is_gpr_mem src2)) (x64_andq_rm src1 src2))
(rule 0 (x64_and ty src1 src2)
(alu_rmi_r ty
(AluRmiROpcode.And)
src1
src2))
(rule 1 (x64_and $I32 src1 (is_imm32 src2)) (x64_andl_mi src1 src2))
(rule 2 (x64_and $I32 src1 (is_simm8 src2)) (x64_andl_mi_sxb src1 src2))
(rule 3 (x64_and $I32 src1 (is_gpr_mem src2)) (x64_andl_rm src1 src2))
(rule 1 (x64_and $I64 src1 (is_simm32 src2)) (x64_andq_mi_sxl src1 src2))
(rule 2 (x64_and $I64 src1 (is_simm8 src2)) (x64_andq_mi_sxb src1 src2))
(rule 3 (x64_and $I64 src1 (is_gpr_mem src2)) (x64_andq_rm src1 src2))

(decl x64_and_with_flags_paired (Type Gpr GprMemImm) ProducesFlags)
(rule (x64_and_with_flags_paired ty src1 src2)
Expand All @@ -3059,43 +3044,33 @@

;; Helper for emitting `or` instructions.
(decl x64_or (Type Gpr GprMemImm) Gpr)
(rule 12 (x64_or $I8 src1 (is_imm8 src2)) (x64_orb_mi src1 src2))
(rule 11 (x64_or $I16 src1 (is_imm16 src2)) (x64_orw_mi src1 src2))
(rule 10 (x64_or $I32 src1 (is_simm8 src2)) (x64_orl_mi_sxb src1 src2))
(rule 9 (x64_or $I32 src1 (is_imm32 src2)) (x64_orl_mi src1 src2))
(rule 8 (x64_or $I64 src1 (is_simm8 src2)) (x64_orq_mi_sxb src1 src2))
(rule 7 (x64_or $I64 src1 (is_simm32 src2)) (x64_orq_mi_sxl src1 src2))
(rule 6 (x64_or $I8 src1 (is_gpr src2)) (x64_orl_rm src1 src2))
(rule 5 (x64_or $I8 src1 (is_mem src2)) (x64_orb_rm src1 src2))
(rule 4 (x64_or $I16 src1 (is_gpr src2)) (x64_orl_rm src1 src2))
(rule 1 (x64_or $I8 src1 (is_imm8 src2)) (x64_orb_mi src1 src2))
(rule 2 (x64_or $I8 src1 (is_gpr src2)) (x64_orl_rm src1 src2))
(rule 3 (x64_or $I8 src1 (is_mem src2)) (x64_orb_rm src1 src2))
(rule 1 (x64_or $I16 src1 (is_imm16 src2)) (x64_orw_mi src1 src2))
(rule 2 (x64_or $I16 src1 (is_gpr src2)) (x64_orl_rm src1 src2))
(rule 3 (x64_or $I16 src1 (is_mem src2)) (x64_orw_rm src1 src2))
(rule 2 (x64_or $I32 src1 (is_gpr_mem src2)) (x64_orl_rm src1 src2))
(rule 1 (x64_or $I64 src1 (is_gpr_mem src2)) (x64_orq_rm src1 src2))
(rule 0 (x64_or ty src1 src2)
(alu_rmi_r ty
(AluRmiROpcode.Or)
src1
src2))
(rule 1 (x64_or $I32 src1 (is_imm32 src2)) (x64_orl_mi src1 src2))
(rule 2 (x64_or $I32 src1 (is_simm8 src2)) (x64_orl_mi_sxb src1 src2))
(rule 3 (x64_or $I32 src1 (is_gpr_mem src2)) (x64_orl_rm src1 src2))
(rule 1 (x64_or $I64 src1 (is_simm32 src2)) (x64_orq_mi_sxl src1 src2))
(rule 2 (x64_or $I64 src1 (is_simm8 src2)) (x64_orq_mi_sxb src1 src2))
(rule 3 (x64_or $I64 src1 (is_gpr_mem src2)) (x64_orq_rm src1 src2))

;; Helper for emitting `xor` instructions.
(decl x64_xor (Type Gpr GprMemImm) Gpr)
(rule 12 (x64_xor $I8 src1 (is_imm8 src2)) (x64_xorb_mi src1 src2))
(rule 11 (x64_xor $I16 src1 (is_imm16 src2)) (x64_xorw_mi src1 src2))
(rule 10 (x64_xor $I32 src1 (is_simm8 src2)) (x64_xorl_mi_sxb src1 src2))
(rule 9 (x64_xor $I32 src1 (is_imm32 src2)) (x64_xorl_mi src1 src2))
(rule 8 (x64_xor $I64 src1 (is_simm8 src2)) (x64_xorq_mi_sxb src1 src2))
(rule 7 (x64_xor $I64 src1 (is_simm32 src2)) (x64_xorq_mi_sxl src1 src2))
(rule 6 (x64_xor $I8 src1 (is_gpr src2)) (x64_xorl_rm src1 src2))
(rule 5 (x64_xor $I8 src1 (is_mem src2)) (x64_xorb_rm src1 src2))
(rule 4 (x64_xor $I16 src1 (is_gpr src2)) (x64_xorl_rm src1 src2))
(rule 1 (x64_xor $I8 src1 (is_imm8 src2)) (x64_xorb_mi src1 src2))
(rule 2 (x64_xor $I8 src1 (is_gpr src2)) (x64_xorl_rm src1 src2))
(rule 3 (x64_xor $I8 src1 (is_mem src2)) (x64_xorb_rm src1 src2))
(rule 1 (x64_xor $I16 src1 (is_imm16 src2)) (x64_xorw_mi src1 src2))
(rule 2 (x64_xor $I16 src1 (is_gpr src2)) (x64_xorl_rm src1 src2))
(rule 3 (x64_xor $I16 src1 (is_mem src2)) (x64_xorw_rm src1 src2))
(rule 2 (x64_xor $I32 src1 (is_gpr_mem src2)) (x64_xorl_rm src1 src2))
(rule 1 (x64_xor $I64 src1 (is_gpr_mem src2)) (x64_xorq_rm src1 src2))
(rule 0 (x64_xor ty src1 src2)
(alu_rmi_r ty
(AluRmiROpcode.Xor)
src1
src2))
(rule 1 (x64_xor $I32 src1 (is_imm32 src2)) (x64_xorl_mi src1 src2))
(rule 2 (x64_xor $I32 src1 (is_simm8 src2)) (x64_xorl_mi_sxb src1 src2))
(rule 3 (x64_xor $I32 src1 (is_gpr_mem src2)) (x64_xorl_rm src1 src2))
(rule 1 (x64_xor $I64 src1 (is_simm32 src2)) (x64_xorq_mi_sxl src1 src2))
(rule 2 (x64_xor $I64 src1 (is_simm8 src2)) (x64_xorq_mi_sxb src1 src2))
(rule 3 (x64_xor $I64 src1 (is_gpr_mem src2)) (x64_xorq_rm src1 src2))

(decl x64_andn (Type Gpr GprMem) Gpr)
(rule (x64_andn ty src1 src2)
Expand Down
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