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Modify FPGA creation for Versal and for 2.0 (#1950)
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* Updated hw/latest/rtl to fc2ec4574c8662d0d208c8cfd916ea5dcc312ef7

* FPGA Versal support for 2.0

- Migrate to Versal
- Add Adam's Bridge
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jlmahowa-amd authored Feb 25, 2025
1 parent 3ba3f6a commit daa42ff
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Showing 48 changed files with 2,311 additions and 1,169 deletions.
2 changes: 1 addition & 1 deletion ci-tools/fpga-image/boot.scr
Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
setenv bootargs "earlycon root=/dev/mmcblk0p3 rootwait console=ttyPS0,115200 console=tty1 uio_pdrv_genirq.of_id=generic-uio cma=700M overlayroot=tmpfs modprobe.blacklist=zynqmp_dpsub,i2c_mux_pca954x,i2c_cadence,ahci_ceva,raid10,raid1,raid0,raid456"
load mmc 0:1 0x10000000 image.fit
bootm 0x10000000 0x10000000 $fdtcontroladdr
bootm 0x10000000 0x10000000 $fdtcontroladdr
2 changes: 1 addition & 1 deletion drivers/src/soc_ifc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -515,7 +515,7 @@ impl SocIfc {
.regs()
.cptra_hw_config()
.read()
.active_mode_en()
.subsystem_mode_en()
}

pub fn uds_fuse_row_granularity_64(&self) -> bool {
Expand Down
2 changes: 1 addition & 1 deletion hw-model/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -625,7 +625,7 @@ pub trait HwModel: SocManager {
}
writeln!(self.output().logger(), "ready_for_fw is high")?;
self.cover_fw_mage(fw_image);
let active_mode = self.soc_ifc().cptra_hw_config().read().active_mode_en();
let active_mode = self.soc_ifc().cptra_hw_config().read().subsystem_mode_en();
writeln!(
self.output().logger(),
"mode {}",
Expand Down
18 changes: 9 additions & 9 deletions hw-model/src/model_fpga_realtime.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ use std::process::{Child, Command, Stdio};
use std::sync::atomic::{AtomicBool, Ordering};
use std::sync::Arc;
use std::thread;
use std::{env, str::FromStr};
use std::{env, slice, str::FromStr};

use bitfield::bitfield;
use caliptra_emu_bus::{Bus, BusError, BusMmio};
Expand All @@ -32,6 +32,7 @@ pub enum OpenOcdError {
// UIO mapping indices
const FPGA_WRAPPER_MAPPING: usize = 0;
const CALIPTRA_MAPPING: usize = 1;
const ROM_MAPPING: usize = 2;

// Set to core_clk cycles per ITRNG sample.
const ITRNG_DIVISOR: u32 = 400;
Expand Down Expand Up @@ -151,7 +152,7 @@ impl ModelFpgaRealtime {
};
if trngfifosts.trng_fifo_full() == 0 {
let mut itrng_dw = 0;
for i in (0..8).rev() {
for i in 0..8 {
match itrng_nibbles.next() {
Some(nibble) => itrng_dw += u32::from(nibble) << (4 * i),
None => return,
Expand Down Expand Up @@ -367,6 +368,7 @@ impl HwModel for ModelFpgaRealtime {
.map_mapping(FPGA_WRAPPER_MAPPING)
.map_err(fmt_uio_error)? as *mut u32;
let mmio = dev.map_mapping(CALIPTRA_MAPPING).map_err(fmt_uio_error)? as *mut u32;
let rom = dev.map_mapping(ROM_MAPPING).map_err(fmt_uio_error)? as *mut u8;

let realtime_thread_exit_flag = Arc::new(AtomicBool::new(false));
let realtime_thread_exit_flag2 = realtime_thread_exit_flag.clone();
Expand Down Expand Up @@ -436,12 +438,9 @@ impl HwModel for ModelFpgaRealtime {
}

// Write ROM image over backdoor
let mut rom_driver = std::fs::OpenOptions::new()
.write(true)
.open("/dev/caliptra-rom-backdoor")
.unwrap();
rom_driver.write_all(params.rom)?;
rom_driver.sync_all()?;
writeln!(m.output().logger(), "Writing ROM")?;
let rom_slice = unsafe { slice::from_raw_parts_mut(rom, params.rom.len()) };
rom_slice.copy_from_slice(params.rom);

// Sometimes there's garbage in here; clean it out
m.clear_log_fifo();
Expand Down Expand Up @@ -590,6 +589,7 @@ impl Drop for ModelFpgaRealtime {
// Unmap UIO memory space so that the file lock is released
self.unmap_mapping(self.wrapper, FPGA_WRAPPER_MAPPING);
self.unmap_mapping(self.mmio, CALIPTRA_MAPPING);
self.unmap_mapping(self.mmio, ROM_MAPPING);

// Close openocd
match &mut self.openocd {
Expand All @@ -608,7 +608,7 @@ impl<'a> FpgaRealtimeBus<'a> {
let addr = addr as usize;
unsafe {
match addr {
0x3002_0000..=0x3003_ffff => Some(self.mmio.add((addr - 0x3002_0000) / 4)),
0x3002_0000..=0x3003_ffff => Some(self.mmio.add((addr - 0x3000_0000) / 4)),
_ => None,
}
}
Expand Down
134 changes: 66 additions & 68 deletions hw/fpga/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -15,28 +15,42 @@ limitations under the License.*_<BR>

# **Caliptra FPGA Guide** #
FPGA provides a fast environment for software development and testing that uses Caliptra RTL.
The Zynq's Programmable Logic is programmed with the Caliptra RTL and FPGA specific SoC wrapper logic including a connection to the Processing System AXI bus.
The FPGA's Programmable Logic is programmed with the Caliptra RTL and FPGA specific SoC wrapper logic including a connection to the Processing System AXI bus.
The Processing System ARM cores then act as the SoC Security Processor with memory mapped access to Caliptra's public register space.

![](./images/fpga_module_diagram.svg)

### Requirements: ###
- Vivado
- Version v2022.2
- Version v2022.2 or 2024.2
- PetaLinux Tools
- Version must match Vivado
- FPGA
- [ZCU104 Development Board](https://www.xilinx.com/products/boards-and-kits/zcu104.html)
- [VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html)
- VMK180 will be supported soon.

### ZCU104 ###
### Versal ###
#### Processing system one time setup: ####
1. Install ZCU104 SD card image
1. Download VCK190 SD card image and install to a microSD card.
- Insert the SD card into the slot on top of the board. The slot below the board is for the System Controller.
- https://ubuntu.com/download/amd-xilinx
1. Configure SW6 to boot from SD1.
- Mode SW6[4:1]: OFF, OFF, OFF, ON
![](./images/zynq_boot_switch.jpg)
1. Install rustup using Unix directions: https://rustup.rs/#
1. Configure SW1 to boot from SD1: [Image](./images/versal_boot_switch.jpg)
- Mode SW1[4:1]: OFF, OFF, OFF, ON
1. Boot from the SD card. (Suggest using the serial port for initial setup)
- Initial credentials
- User: ubuntu Pass: ubuntu
- Install software dependencies - *Do not update the system*
```shell
sudo apt update
sudo apt install make gcc
```
- Install rustup using Unix directions: https://rustup.rs/#
- Consider assigning a hostname for SSH access.

#### Serial port configuration: ####
Serial port settings for connection over USB.
The USB Type-C connecter J207 provides UART and JTAG access to the board. The first UART connection should be for the PS.

Serial port settings:
- Speed: 115200
- Data bits: 8
- Stop bits: 1
Expand All @@ -47,14 +61,15 @@ Serial port settings for connection over USB.
The FPGA build process uses Vivado's batch mode to procedurally create the Vivado project using fpga_configuration.tcl.
This script provides a number of configuration options for features that can be enabled using "-tclargs OPTION=VALUE OPTION=VALUE"
| Option | Purpose
| ------ | -------
| BUILD | Automatically start building the FPGA.
| GUI | Open the Vivado GUI.
| JTAG | Assign JTAG signals to Zynq PS GPIO.
| ITRNG | Enable Caliptra's ITRNG.
| CG_EN | Removes FPGA optimizations and allows clock gating.
| HW_LATEST | Use hw/latest instead of hw/1.0.
| Option | Purpose
| ------ | -------
| BUILD | Automatically start building the FPGA.
| GUI | Open the Vivado GUI.
| JTAG | Assign JTAG signals to PS GPIO.
| ITRNG | Enable Caliptra's ITRNG.
| CG_EN | Removes FPGA optimizations and allows clock gating.
| RTL_VERSION | RTL directory under hw/. latest or 1.0.
| BOARD | VCK190 or VMK180 (TODO: VMK180 not fully enabled)

- Build FPGA image without GUI
- `vivado -mode batch -source fpga_configuration.tcl -tclargs BUILD=TRUE`
Expand All @@ -67,60 +82,43 @@ This script provides a number of configuration options for features that can be
- Run Synthesis: `launch_runs synth_1`
- [Optional] Set Up Debug signals on Synthesized Design
- Run Implementation: `launch_runs impl_1`
- Generate Bitstream: `write_bitstream -bin_file \tmp\caliptra_fpga`

### Loading and execution Steps: ###
[setup_fpga.sh](setup_fpga.sh) performs platform setup that is needed after each boot.
- Disables CPU IDLE. Vivado HW Manager access during IDLE causes crashes.
- Reduces fan speed by setting the GPIO pin connected to the fan controller FULLSPD pin to output.
- https://support.xilinx.com/s/question/0D52E00006iHuopSAC/zcu104-fan-running-at-max-speed?language=en_US
- Builds and installs the rom_backdoor and io_module kernel modules.
- Sets the clock for the FPGA logic.
- Installs the provided FPGA image.

- Generate Device Image: `write_device_image $outputDir/caliptra_fpga`
- Export hardware: `write_hw_platform -fixed -include_bit -force -file $outputDir/caliptra_fpga.xsa`

### Build boot.bin: ###
- Source PetaLinux tools from the PetaLinux installation directory.
`source settings.sh`
- Run steps from [create_boot_bin.sh](create_boot_bin.sh) to create a BOOT.BIN
- `./create_boot_bin.sh /path/to/caliptra_fpga_project_bd_wrapper.xsa`
- Copy petalinux_project/images/linux/BOOT.BIN to the boot partition as boot1900.bin
- If the Ubuntu image is booted, it will mount the boot partition at /boot/firmware/
- If boot1900.bin fails to boot the system will fallback to the default boot1901.bin

### Running Caliptra tests from the FPGA: ###
```shell
sudo ./hw/fpga/setup_fpga.sh caliptra_fpga.bin

CPTRA_UIO_NUM=4 cargo test --features=fpga_realtime,itrng -p caliptra-test smoke_test::smoke_test
# Install dependencies
sudo apt update
sudo apt install make gcc
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
# Clone this repo
git clone https://github.com/chipsalliance/caliptra-sw.git
git submodule init
git submodule update
# Compile and install the kernel module
sudo ./hw/fpga/setup_fpga.sh
CPTRA_UIO_NUM=0 cargo test --features=fpga_realtime,itrng -p caliptra-test smoke_test::smoke_test
```

### Processing System - Programmable Logic interfaces ###
#### AXI Memory Map ####
- SoC adapter for driving caliptra-top signals
- 0x80000000 - Generic Input Wires
- 0x80000008 - Generic Output Wires
- 0x80000010-0x8000002C - Deobfuscation key (256 bit)
- 0x80000030 - Control
- `[0] -> cptra_pwrgood`
- `[1] -> cptra_rst_b`
- `[3:2] -> device_lifecycle`
- `[4] -> debug_locked`
- 0x80000034 - Status
- `[0] <- cptra_error_fatal`
- `[1] <- cptra_error_non_fatal`
- `[2] <- ready_for_fuses`
- `[3] <- ready_for_fw`
- `[4] <- ready_for_runtime`
- 0x80000038 - PAUSER
- `[31:0] -> PAUSER to Caliptra APB`
- 0x80001000 - Log FIFO data. Reads pop data from FIFO.
- `[7:0] -> Next log character`
- `[8] -> Log character valid`
- 0x80001004 - Log FIFO register
- `[0] -> Log FIFO empty`
- `[1] -> Log FIFO full (probably overrun)`
- 0x80001008 - ITRNG FIFO data. Write loads data to FIFO.
- `[31:0] -> 32 bits of random data to be fed to itrng_data 4 bits at a time`
- 0x8000100C - ITRNG FIFO status.
- `[0] -> ITRNG FIFO empty`
- `[1] -> ITRNG FIFO full`
- `[2] -> ITRNG FIFO reset`
- ROM Backdoor - 32K
- `0x82000000 - 0x82007FFF`
- Caliptra SoC register interface
- `0x90000000`
#### Interrupts ####
- 89 - Log FIFO half full.
[FPGA Wrapper Registers](fpga_wrapper_regs.md)

#### Versal Memory Map ####
| IP/Peripheral | Address size | Start address | End address |
| :---------------------------------- | :----------- | :------------ | :---------- |
| ROM Backdoor | 96 KiB | 0xB000_0000 | 0xB001_7FFF |
| FPGA Wrapper Registers | 8 KiB | 0xA401_0000 | 0xA401_1FFF |
| Caliptra | 1 MiB | 0xA410_0000 | 0xA41F_FFFF |

### JTAG debug
Requirements:
Expand Down
119 changes: 119 additions & 0 deletions hw/fpga/adams-bridge-files.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,119 @@

set adbDir $fpgaDir/../$RTL_VERSION/rtl/submodules/adams-bridge

if { [file exists $adbDir/src/abr_prim/rtl/abr_prim_flop_macros.sv] == 0 } {
puts "ERROR: $adbDir/src/abr_prim/rtl/abr_prim_flop_macros.sv not found"
puts "Adam's bridge submodule may not be initialized"
puts "Try: git submodule update --init --recursive"
exit
}

add_files $adbDir/src/abr_prim/rtl/abr_prim_flop_macros.sv

# Initial list from mldsa_top_tb.vf
add_files $adbDir/src/mldsa_top/rtl/mldsa_config_defines.svh
add_files $adbDir/src/mldsa_top/rtl/mldsa_params_pkg.sv
add_files $adbDir/src/mldsa_top/rtl/mldsa_reg_pkg.sv

add_files $adbDir/src/abr_libs/rtl/abr_sva.svh
add_files $adbDir/src/abr_libs/rtl/abr_macros.svh

add_files [ glob $adbDir/src/abr_libs/rtl/*.sv ]

add_files $adbDir/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv
add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball_pkg.sv
add_files $adbDir/src/sample_in_ball/rtl/sib_mem.sv

add_files [ glob $adbDir/src/abr_prim/rtl/*.sv ]
add_files [ glob $adbDir/src/abr_prim/rtl/*.svh ]

add_files [ glob $adbDir/src/ntt_top/rtl/*.sv ]
add_files $adbDir/src/ntt_top/tb/ntt_ram_tdp_file.sv
add_files $adbDir/src/ntt_top/tb/ntt_wrapper.sv
add_files $adbDir/src/norm_check/rtl/norm_check_defines_pkg.sv
add_files $adbDir/src/mldsa_top/tb/mldsa_top_tb.sv
add_files $adbDir/src/rej_bounded/rtl/rej_bounded_ctrl.sv
add_files $adbDir/src/rej_bounded/rtl/rej_bounded2.sv
add_files $adbDir/src/rej_sampler/rtl/rej_sampler_ctrl.sv
add_files $adbDir/src/rej_sampler/rtl/rej_sampler.sv
add_files $adbDir/src/exp_mask/rtl/exp_mask_ctrl.sv
add_files $adbDir/src/exp_mask/rtl/exp_mask.sv
add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv
add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv
add_files $adbDir/src/sample_in_ball/rtl/sample_in_ball.sv
add_files $adbDir/src/abr_sha3/rtl/abr_sha3_pkg.sv
add_files $adbDir/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv
add_files $adbDir/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv
add_files $adbDir/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_flop_en.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_flop_2sync.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_lfsr.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_mubi4_sync.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_diff_decode.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_slicer.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_count.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_dom_and_2share.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_reg_we_check.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_packer_fifo.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_max_tree.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_subreg_arb.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_subreg.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_intr_hw.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_onehot_check.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_mubi8_sync.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_buf.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_alert_receiver.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_flop.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_alert_sender.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_fifo_sync.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_sum_tree.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_subreg_ext.sv
add_files $adbDir/src/abr_prim/rtl/abr_prim_edge_detector.sv
add_files $adbDir/src/abr_sha3/rtl/abr_keccak_round.sv
add_files $adbDir/src/abr_sha3/rtl/abr_keccak_2share.sv
add_files $adbDir/src/abr_sha3/rtl/abr_sha3pad.sv
add_files $adbDir/src/abr_sha3/rtl/abr_sha3.sv
add_files $adbDir/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv
add_files $adbDir/src/decompose/rtl/decompose_defines_pkg.sv
add_files $adbDir/src/decompose/rtl/decompose.sv
add_files $adbDir/src/decompose/rtl/decompose_r1_lut.sv
add_files $adbDir/src/decompose/rtl/decompose_w1_mem.sv
add_files $adbDir/src/decompose/rtl/decompose_mod_2gamma2.sv
add_files $adbDir/src/decompose/rtl/decompose_ctrl.sv
add_files $adbDir/src/decompose/rtl/decompose_w1_encode.sv
add_files $adbDir/src/decompose/rtl/decompose_usehint.sv
add_files $adbDir/src/sk_decode/rtl/skdecode_defines_pkg.sv
add_files $adbDir/src/sk_encode/rtl/skencode.sv
add_files $adbDir/src/sk_decode/rtl/skdecode_top.sv
add_files $adbDir/src/sk_decode/rtl/skdecode_ctrl.sv
add_files $adbDir/src/sk_decode/rtl/skdecode_s1s2_unpack.sv
add_files $adbDir/src/sk_decode/rtl/skdecode_t0_unpack.sv
add_files $adbDir/src/makehint/rtl/makehint_defines_pkg.sv
add_files $adbDir/src/makehint/rtl/hintgen.sv
add_files $adbDir/src/makehint/rtl/makehint.sv
add_files $adbDir/src/norm_check/rtl/norm_check.sv
add_files $adbDir/src/norm_check/rtl/norm_check_ctrl.sv
add_files $adbDir/src/norm_check/rtl/norm_check_top.sv
add_files $adbDir/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv
add_files $adbDir/src/sig_encode_z/rtl/sigencode_z_top.sv
add_files $adbDir/src/sig_encode_z/rtl/sigencode_z_unit.sv
add_files $adbDir/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv
add_files $adbDir/src/sigdecode_h/rtl/sigdecode_h.sv
add_files $adbDir/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv
add_files $adbDir/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv
add_files $adbDir/src/sig_decode_z/rtl/sigdecode_z_top.sv
add_files $adbDir/src/sig_decode_z/rtl/sigdecode_z_unit.sv
add_files $adbDir/src/pk_decode/rtl/pkdecode.sv
add_files $adbDir/src/power2round/rtl/power2round_defines_pkg.sv
add_files $adbDir/src/power2round/rtl/power2round_top.sv
add_files $adbDir/src/power2round/rtl/power2round_ctrl.sv
add_files $adbDir/src/power2round/rtl/power2round_core.sv
add_files $adbDir/src/power2round/rtl/power2round_skencode.sv

add_files [ glob $adbDir/src/mldsa_top/rtl/*.sv ]
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