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[LoongArch64] Fix some bugs in the test sets 'System.Runtime.Tests' and 'System.Linq.Expressions.Tests' for loongarch64. #86435

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merged 3 commits into from
May 22, 2023
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[LoongArch64] Fix some bugs in the test sets 'System.Runtime.Tests' and 'System.Linq.Expressions.Tests' for loongarch64. #86435

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d6658d3
Fix the error of the Truncate/Saturate convert from Float/Double NAN …
LuckyXu-HF May 18, 2023
ccad980
Merge branch 'main' into main-temp
LuckyXu-HF May 22, 2023
7897367
Update codegenloongarch64.cpp
LuckyXu-HF May 22, 2023
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2 changes: 1 addition & 1 deletion src/coreclr/jit/codegencommon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5827,7 +5827,7 @@ void CodeGen::genFnProlog()
//
extraFrameSize = compiler->compCalleeRegsPushed * REGSIZE_BYTES;
}
#endif // TARGET_ARM64
#endif // TARGET_AMD64

if (doubleAlignOrFramePointerUsed())
{
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29 changes: 23 additions & 6 deletions src/coreclr/jit/codegenloongarch64.cpp
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Expand Up @@ -3877,17 +3877,24 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
}

if (srcType == TYP_DOUBLE)
{
GetEmitter()->emitIns_R_R_I(INS_lu52i_d, EA_8BYTE, REG_R21, REG_R0, imm >> 8);
}
else
{
GetEmitter()->emitIns_R_I(INS_lu12i_w, EA_PTRSIZE, REG_R21, imm);
}

GetEmitter()->emitIns_R_R(srcType == TYP_DOUBLE ? INS_movgr2fr_d : INS_movgr2fr_w, EA_8BYTE, tmpReg, REG_R21);

GetEmitter()->emitIns_R_R_I(srcType == TYP_DOUBLE ? INS_fcmp_clt_d : INS_fcmp_clt_s, EA_8BYTE, op1->GetRegNum(),
tmpReg, 2);
tmpReg, 2); // cc=2

GetEmitter()->emitIns_R_R_I(srcType == TYP_DOUBLE ? INS_fcmp_ceq_d : INS_fcmp_ceq_s, EA_8BYTE, op1->GetRegNum(),
tmpReg, 3); // cc=3

GetEmitter()->emitIns_R_R_I(INS_ori, EA_PTRSIZE, REG_R21, REG_R0, 0);
GetEmitter()->emitIns_I_I(INS_bcnez, EA_PTRSIZE, 2, 4 << 2);
GetEmitter()->emitIns_I_I(INS_bcnez, EA_PTRSIZE, 2, 4 << 2); // cc=2

GetEmitter()->emitIns_R_R_R(srcType == TYP_DOUBLE ? INS_fsub_d : INS_fsub_s, EA_8BYTE, tmpReg, op1->GetRegNum(),
tmpReg);
Expand All @@ -3901,6 +3908,9 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
GetEmitter()->emitIns_R_R(ins1, dstSize, tmpReg, tmpReg);
GetEmitter()->emitIns_R_R(ins2, dstSize, treeNode->GetRegNum(), tmpReg);

GetEmitter()->emitIns_I_I(INS_bcnez, EA_PTRSIZE, 3, 2 << 2); // cc=3
GetEmitter()->emitIns_R_I(INS_beqz, EA_PTRSIZE, treeNode->GetRegNum(), 2 << 2);

GetEmitter()->emitIns_R_R_R(INS_or, dstSize, treeNode->GetRegNum(), REG_R21, treeNode->GetRegNum());
}
else
Expand Down Expand Up @@ -4104,20 +4114,22 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
switch (cmpSize)
{
case EA_4BYTE:
{
regNumber tmpRegOp1 = REG_R21;
assert(regOp1 != tmpRegOp1);
if (IsUnsigned)
{
imm = static_cast<uint32_t>(imm);

regNumber tmpRegOp1 = REG_R21;
assert(regOp1 != tmpRegOp1);
emit->emitIns_R_R_I_I(INS_bstrpick_d, EA_8BYTE, tmpRegOp1, regOp1, 31, 0);
regOp1 = tmpRegOp1;
}
else
{
imm = static_cast<int32_t>(imm);
emit->emitIns_R_R_I(INS_slli_w, EA_8BYTE, tmpRegOp1, regOp1, 0);
}
regOp1 = tmpRegOp1;
break;
}
case EA_8BYTE:
break;
case EA_1BYTE:
Expand Down Expand Up @@ -5932,6 +5944,11 @@ void CodeGen::genRangeCheck(GenTree* oper)
}
else
{
if (genActualType(src1->TypeGet()) == TYP_INT)
{
GetEmitter()->emitIns_R_R_I(INS_slli_w, EA_4BYTE, REG_R21, reg1, 0);
reg1 = REG_R21;
}
reg2 = src2->GetRegNum();
}
}
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