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Add Arm64 encodings for IF_SVE_AH_3A #95864

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Dec 11, 2023
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Add Arm64 encodings for IF_SVE_AH_3A #95864

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18 changes: 18 additions & 0 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10165,6 +10165,24 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_sve_umulh, EA_SCALABLE, REG_V12, REG_P2, REG_V24,
INS_OPTS_SCALABLE_B); /* UMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */

// IF_SVE_AH_3A
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V13, REG_P0, REG_V31,
INS_OPTS_SCALABLE_B); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V14, REG_P1, REG_V0,
INS_OPTS_SCALABLE_H); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V13, REG_P2, REG_V1,
INS_OPTS_SCALABLE_S); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V15, REG_P3, REG_V2,
INS_OPTS_SCALABLE_D); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V16, REG_P4, REG_V3,
INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V17, REG_P5, REG_V12,
INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V0, REG_P6, REG_V13,
INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V31, REG_P7, REG_V22,
INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE); // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>

// IF_SVE_AN_3A
theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V5, REG_P0, REG_V21,
INS_OPTS_SCALABLE_S); /* ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> */
Expand Down
114 changes: 81 additions & 33 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -974,6 +974,16 @@ void emitter::emitInsSanityCheck(instrDesc* id)
assert(isScalableVectorSize(elemsize));
break;

// Scalable, Merge or Zero predicate.
case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated)
elemsize = id->idOpSize();
assert(insOptsScalableSimple(id->idInsOpt()) || insOptsScalableWithPredicateMerge(id->idInsOpt()));
assert(isVectorRegister(id->idReg1())); // nnnnn
assert(isLowPredicateRegister(id->idReg2())); // ggg
assert(isVectorRegister(id->idReg3())); // ddddd
assert(isScalableVectorSize(elemsize));
break;

// Scalable Wide.
case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
elemsize = id->idOpSize();
Expand Down Expand Up @@ -5279,26 +5289,30 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt)
case INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_B_WITH_SCALAR:
case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE:
return EA_1BYTE;

case INS_OPTS_SCALABLE_H:
case INS_OPTS_SCALABLE_WIDE_H:
case INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_H_WITH_SCALAR:
case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE:
return EA_2BYTE;

case INS_OPTS_SCALABLE_S:
case INS_OPTS_SCALABLE_WIDE_S:
case INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_S_WITH_SCALAR:
case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE:
return EA_4BYTE;

case INS_OPTS_SCALABLE_D:
case INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_D_WITH_SCALAR:
case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE:
return EA_8BYTE;

default:
Expand Down Expand Up @@ -8501,6 +8515,14 @@ void emitter::emitIns_R_R_R(
fmt = IF_SVE_AG_3A;
break;

case INS_sve_movprfx:
assert(isVectorRegister(reg1));
assert(isLowPredicateRegister(reg2));
assert(isVectorRegister(reg3));
assert(insOptsScalableSimple(opt) || insOptsScalableWithPredicateMerge(opt));
fmt = IF_SVE_AH_3A;
break;

case INS_sve_saddv:
case INS_sve_uaddv:
assert(isFloatReg(reg1));
Expand Down Expand Up @@ -11694,6 +11716,16 @@ void emitter::emitIns_Call(EmitCallType callType,
return ureg << 0;
}

/*****************************************************************************
*
* Return an encoding for the specified predicate type used in '16' position.
*/

/*static*/ emitter::code_t emitter::insEncodePredQualifier_16(bool merge)
{
return merge ? 1 << 16 : 0;
}

/*****************************************************************************
*
* Return an encoding for the specified 'V' register used in '19' thru '17' position.
Expand Down Expand Up @@ -12547,35 +12579,20 @@ void emitter::emitIns_Call(EmitCallType callType,
* Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 Sve vector instruction
*/

/*static*/ emitter::code_t emitter::insEncodeSveElemsize(insOpts opt)
/*static*/ emitter::code_t emitter::insEncodeSveElemsize(emitAttr size)
{
switch (opt)
switch (size)
{
case INS_OPTS_SCALABLE_B:
case INS_OPTS_SCALABLE_WIDE_B:
case INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_B_WITH_SCALAR:
case EA_1BYTE:
return 0x00000000;

case INS_OPTS_SCALABLE_H:
case INS_OPTS_SCALABLE_WIDE_H:
case INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_H_WITH_SCALAR:
case EA_2BYTE:
return 0x00400000; // set the bit at location 22

case INS_OPTS_SCALABLE_S:
case INS_OPTS_SCALABLE_WIDE_S:
case INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_S_WITH_SCALAR:
case EA_4BYTE:
return 0x00800000; // set the bit at location 23

case INS_OPTS_SCALABLE_D:
case INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR:
case INS_OPTS_SCALABLE_D_WITH_SCALAR:
case EA_8BYTE:
return 0x00C00000; // set the bit at location 23 and 22

default:
Expand Down Expand Up @@ -14594,31 +14611,42 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
case IF_SVE_HQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point round to integral value
case IF_SVE_HR_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point unary operations
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_V_9_to_5(id->idReg3()); // mmmmm or nnnnn
code |= insEncodeSveElemsize(id->idInsOpt()); // xx
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_V_9_to_5(id->idReg3()); // mmmmm or nnnnn
code |= insEncodeSveElemsize(optGetSveElemsize(id->idInsOpt())); // xx
dst += emitOutput_Instr(dst, code);
break;

// Scalable with Merge or Zero predicate
case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated)
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_V_4_to_0(id->idReg1()); // nnnnn
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_V_9_to_5(id->idReg3()); // ddddd
code |= insEncodePredQualifier_16(insOptsScalableWithPredicateMerge(id->idInsOpt())); // M
code |= insEncodeSveElemsize(optGetSveElemsize(id->idInsOpt())); // xx
dst += emitOutput_Instr(dst, code);
break;

// Scalable to general register.
case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register
case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_Rd(id->idReg1()); // ddddd
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_V_9_to_5(id->idReg3()); // mmmmm
code |= insEncodeSveElemsize(id->idInsOpt()); // xx
code |= insEncodeReg_Rd(id->idReg1()); // ddddd
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_V_9_to_5(id->idReg3()); // mmmmm
code |= insEncodeSveElemsize(optGetSveElemsize(id->idInsOpt())); // xx
dst += emitOutput_Instr(dst, code);
break;

// Scalable from general register.
case IF_SVE_CQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated)
code = emitInsCodeSve(ins, fmt);
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_Rn(id->idReg3()); // mmmmm
code |= insEncodeSveElemsize(id->idInsOpt()); // xx
code |= insEncodeReg_V_4_to_0(id->idReg1()); // ddddd
code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg
code |= insEncodeReg_Rn(id->idReg3()); // mmmmm
code |= insEncodeSveElemsize(optGetSveElemsize(id->idInsOpt())); // xx
dst += emitOutput_Instr(dst, code);
break;

Expand Down Expand Up @@ -15283,6 +15311,7 @@ void emitter::emitDispArrangement(insOpts opt)
case INS_OPTS_SCALABLE_WIDE_B:
case INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_B_WITH_SCALAR:
case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE:
str = "b";
break;
case INS_OPTS_4H:
Expand All @@ -15296,6 +15325,7 @@ void emitter::emitDispArrangement(insOpts opt)
case INS_OPTS_SCALABLE_WIDE_H:
case INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_H_WITH_SCALAR:
case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE:
str = "h";
break;
case INS_OPTS_2S:
Expand All @@ -15309,6 +15339,7 @@ void emitter::emitDispArrangement(insOpts opt)
case INS_OPTS_SCALABLE_WIDE_S:
case INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_S_WITH_SCALAR:
case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE:
str = "s";
break;
case INS_OPTS_1D:
Expand All @@ -15321,6 +15352,7 @@ void emitter::emitDispArrangement(insOpts opt)
case INS_OPTS_SCALABLE_D:
case INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR:
case INS_OPTS_SCALABLE_D_WITH_SCALAR:
case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE:
str = "d";
break;

Expand Down Expand Up @@ -16905,6 +16937,17 @@ void emitter::emitDispInsHelp(
emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm
break;

// <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated)
{
PredicateType ptype =
(insOptsScalableWithPredicateMerge(id->idInsOpt())) ? PREDICATE_MERGE : PREDICATE_ZERO;
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // nnnnn
emitDispLowPredicateReg(id->idReg2(), ptype, true); // ggg
emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // ddddd
break;
}

// <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated)
emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd
Expand Down Expand Up @@ -19243,6 +19286,11 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
break;

case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated)
result.insThroughput = PERFSCORE_THROUGHPUT_2C;
result.insLatency = PERFSCORE_LATENCY_2C;
break;

// Reduction, arithmetic, D form (worse for B, S and H)
case IF_SVE_AI_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (predicated)
// Reduction, arithmetic, D form (worse for B, S and H)
Expand Down
15 changes: 13 additions & 2 deletions src/coreclr/jit/emitarm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -370,6 +370,9 @@ static code_t insEncodeReg_P_3_to_1(regNumber reg);
// Return an encoding for the specified 'P' register used in '2' thru '0' position.
static code_t insEncodeReg_P_2_to_0(regNumber reg);

// Return an encoding for the specified predicate type used in '16' position.
static code_t insEncodePredQualifier_16(bool merge);

// Return an encoding for the specified 'V' register used in '19' thru '17' position.
static code_t insEncodeReg_V_19_to_17(regNumber reg);

Expand Down Expand Up @@ -466,7 +469,7 @@ static code_t insEncodeExtendScale(ssize_t imm);
static code_t insEncodeReg3Scale(bool isScaled);

// Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 SVE vector instruction
static code_t insEncodeSveElemsize(insOpts opt);
static code_t insEncodeSveElemsize(emitAttr size);

// Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 SVE vector instruction
// This specifically encodes the field 'tszh:tszl' at bit locations '22:20-19'.
Expand Down Expand Up @@ -879,7 +882,8 @@ inline static bool insOptsScalable(insOpts opt)
{
// Opt is any of the scalable types.
return ((insOptsScalableSimple(opt)) || (insOptsScalableWide(opt)) || (insOptsScalableWithSimdScalar(opt)) ||
(insOptsScalableWithScalar(opt)) || (insOptsScalableWithSimdVector(opt)));
(insOptsScalableWithScalar(opt)) || (insOptsScalableWithSimdVector(opt)) ||
insOptsScalableWithPredicateMerge(opt));
}

inline static bool insOptsScalableSimple(insOpts opt)
Expand Down Expand Up @@ -949,6 +953,13 @@ inline static bool insOptsScalableWithScalar(insOpts opt)
(opt == INS_OPTS_SCALABLE_S_WITH_SCALAR) || (opt == INS_OPTS_SCALABLE_D_WITH_SCALAR));
}

inline static bool insOptsScalableWithPredicateMerge(insOpts opt)
{
// `opt` is any of the SIMD scalable types that are valid for use with a merge predicate.
return ((opt == INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE) || (opt == INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE) ||
(opt == INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE) || (opt == INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE));
}

static bool isValidImmCond(ssize_t imm);
static bool isValidImmCondFlags(ssize_t imm);
static bool isValidImmCondFlagsImm5(ssize_t imm);
Expand Down
5 changes: 5 additions & 0 deletions src/coreclr/jit/instr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -294,6 +294,11 @@ enum insOpts : unsigned
INS_OPTS_SCALABLE_S_WITH_SCALAR,
INS_OPTS_SCALABLE_D_WITH_SCALAR,

INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE,
INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE,
INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE,
INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE,

INS_OPTS_MSL, // Vector Immediate (shifting ones variant)

INS_OPTS_S_TO_4BYTE, // Single to INT32
Expand Down