Initial support for RISC-V 32 I M #781

clebreto · 2024-04-08T08:18:16Z

…s (ADD / ADDI). (#706) * Provides RISCV initial architecture description and first instructions (ADD / ADDI). Co-authored-by: Benjamin Gregoire <[email protected]> Co-authored-by: Jean-Christophe Léchenet <[email protected]> --------- Co-authored-by: Benjamin Gregoire <[email protected]> Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Co-authored-by: LE BRETON Come <[email protected]>

Co-authored-by: Santiago Arranz Olmos <[email protected]>

Add XOR and OR to compiler/riscv_instr_decl.v --------- Co-authored-by: Julian Wälde <[email protected]> Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Renames registers. Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Riscv compiler skeleton

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Co-authored-by: Jean-Christophe Léchenet<[email protected]>

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

+ Fix push / pop ra to stack

It looks like gp may be used to access globals. I don't know for tp, but to be safe I added both of them into the list of callee-saved registers.

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Taking into account that division by 0 returns -1 for signed and 2ˆL-1 for unsigned.

bgregoir · 2024-12-11T06:12:30Z

Did we still have work to do before merging?
Or we can resolve conflict and merge?

vbgl · 2024-12-11T06:49:45Z

My comments above still need to be addressed.

This reverts commit 0be66c6.

Let's be generous!

The pass used to systematically introduce an auxiliary register, even for the case of constant 0, while in this case we can use register x0 directly.

+ small fix in error message in pretyping

On RISC-V, sp can be manipulated like any other register, so we can use fewer instructions than on ARM. We use the same code as on x86, except that we have to take special care of large immediates.

vbgl

Can I squash all these commits into a single one?

clebreto · 2025-01-13T13:05:36Z

Can I squash all these commits into a single one?

Fine with me.

vbgl · 2025-01-13T13:13:37Z

This needs a bit of work to adapt to current main… I’m on it.

rtetley and others added 27 commits February 5, 2024 09:14

Add dependencies to build vscoq-language-server (temp fix).

0be66c6

Adds SUB, AND, MV

bfafb60

Co-authored-by: LE BRETON Come <[email protected]>

Adds LOAD and STORE

881bfc8

Co-authored-by: LE BRETON Come <[email protected]>

Refactor cond

121aad6

Co-authored-by: Santiago Arranz Olmos <[email protected]>

Add XOR and OR to compiler/riscv_instr_decl.v (#747)

65371a0

Add XOR and OR to compiler/riscv_instr_decl.v --------- Co-authored-by: Julian Wälde <[email protected]> Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Adds the very minimal bits for dummy compilation.

35faf94

Renames registers. Co-authored-by: Jean-Christophe Léchenet <[email protected]>

WIP : bug-499.

602bee6

Adds li to implement more functionalities.

8055c6d

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Merge pull request #754 from jasmin-lang/riscv-compiler-skeleton

254fd06

Riscv compiler skeleton

Merge branch 'main' into risc-v

218dc38

Adds XOR lowering.

b0b4453

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Fix adressing assembly syntax.

3a80c10

Intrepret "subi" as ADDI.

f9fc5db

Factorize instructions by encodings.

9778be6

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Adds swap and subi as extra ops.

7a00b90

Co-authored-by: Jean-Christophe Léchenet<[email protected]>

Condition lowering implementation.

84b5d1b

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Provides JAL instruction to match calling convention

12e88bc

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Provides tests for branching conditions.

9309743

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Hack to compare with imm.

2f9c8c8

+ Fix push / pop ra to stack

X1 -> X2

ff7977e

X1 -> X2 again

33f5b14

Push and pop ok

50e48b8

assemble_cond: correctly detects 0

6f1cc0e

Fixes program crash

6d84586

It looks like gp may be used to access globals. I don't know for tp, but to be safe I added both of them into the list of callee-saved registers.

Allows to execute at least once each test.

8e2aa91

Merge branch 'main' into risc-v

922c98c

eponier force-pushed the risc-v branch from abaad88 to 922c98c Compare April 10, 2024 09:10

clebreto added 2 commits April 10, 2024 11:35

Check execution of tests.

ff82fa2

Co-authored-by: Jean-Christophe Léchenet <[email protected]>

Adds MUL MULH instructions declaration.

7de90ac

clebreto added 2 commits November 18, 2024 17:35

EC extraction for DIV DIVU REM and REMU.

ed9621d

Update EC for DIV.

deadb01

Taking into account that division by 0 returns -1 for signed and 2ˆL-1 for unsigned.

bgregoir and others added 7 commits December 12, 2024 06:51

small clean-up

f19825b

Merge branch 'main' into risc-v

3947b6a

Merge branch 'main' into risc-v

30efff8

Revert "Add dependencies to build vscoq-language-server (temp fix)."

3abb899

This reverts commit 0be66c6.

polishing

322cd15

Add new authors

2510cfc

Let's be generous!

Load constants in cond: disable for constant 0

73054f7

The pass used to systematically introduce an auxiliary register, even for the case of constant 0, while in this case we can use register x0 directly.

This was referenced Dec 17, 2024

RISC-V : Test every instructions in a same fashion as it was done for ARM #789

Open

Basic description of RISC-V32 I + M + ZIFENCEI ISA #698

Closed

eponier added 7 commits December 17, 2024 14:55

Add changelog

95c9407

RISC-V is no longer "really" experimental

bfc61ed

-help-intrinsics: clearer message

0163280

+ small fix in error message in pretyping

Better set_up_sp_register

1428d18

On RISC-V, sp can be manipulated like any other register, so we can use fewer instructions than on ARM. We use the same code as on x86, except that we have to take special care of large immediates.

Merge branch 'main' into risc-v

71ec917

Fix SAR -> SRA

f54fc8f

RISC-V spelling more uniform, I hope

d780d5b

eponier force-pushed the risc-v branch from 30c65ba to d780d5b Compare January 6, 2025 17:04

vbgl previously approved these changes Jan 13, 2025

View reviewed changes

Merge remote-tracking branch 'origin/main' into risc-v

8038bee

Fix after PR 991

06f84dd

vbgl dismissed their stale review via 06f84dd January 13, 2025 13:20

vbgl approved these changes Jan 13, 2025

View reviewed changes

vbgl merged commit 41068bc into main Jan 13, 2025
1 check passed

vbgl deleted the risc-v branch January 13, 2025 14:21

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Initial support for RISC-V 32 I M #781

Initial support for RISC-V 32 I M #781

clebreto commented Apr 8, 2024 •

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bgregoir commented Dec 11, 2024

vbgl commented Dec 11, 2024

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clebreto commented Jan 13, 2025

vbgl commented Jan 13, 2025

Initial support for RISC-V 32 I M #781

Initial support for RISC-V 32 I M #781

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clebreto commented Apr 8, 2024 • edited Loading

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clebreto commented Jan 13, 2025

vbgl commented Jan 13, 2025

clebreto commented Apr 8, 2024 •

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