Rename RISCVFoldMasks -> RISCVVectorPeephole

llvm · Jul 6, 2024 · 82e8c8b · 82e8c8b
1 parent f25dd71
commit 82e8c8b
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Showing 5 changed files with 31 additions and 23 deletions.
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -34,7 +34,6 @@ add_llvm_target(RISCVCodeGen
   RISCVMakeCompressible.cpp
   RISCVExpandAtomicPseudoInsts.cpp
   RISCVExpandPseudoInsts.cpp
-  RISCVFoldMasks.cpp
   RISCVFrameLowering.cpp
   RISCVGatherScatterLowering.cpp
   RISCVInsertVSETVLI.cpp
@@ -55,6 +54,7 @@ add_llvm_target(RISCVCodeGen
   RISCVTargetMachine.cpp
   RISCVTargetObjectFile.cpp
   RISCVTargetTransformInfo.cpp
+  RISCVVectorPeephole.cpp
   GISel/RISCVCallLowering.cpp
   GISel/RISCVInstructionSelector.cpp
   GISel/RISCVLegalizerInfo.cpp

diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
@@ -40,8 +40,8 @@ void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
 FunctionPass *createRISCVGatherScatterLoweringPass();
 void initializeRISCVGatherScatterLoweringPass(PassRegistry &);
 
-FunctionPass *createRISCVFoldMasksPass();
-void initializeRISCVFoldMasksPass(PassRegistry &);
+FunctionPass *createRISCVVectorPeepholePass();
+void initializeRISCVVectorPeepholePass(PassRegistry &);
 
 FunctionPass *createRISCVOptWInstrsPass();
 void initializeRISCVOptWInstrsPass(PassRegistry &);

diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -121,7 +121,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   initializeRISCVOptWInstrsPass(*PR);
   initializeRISCVPreRAExpandPseudoPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
-  initializeRISCVFoldMasksPass(*PR);
+  initializeRISCVVectorPeepholePass(*PR);
   initializeRISCVInsertVSETVLIPass(*PR);
   initializeRISCVInsertReadWriteCSRPass(*PR);
   initializeRISCVInsertWriteVXRMPass(*PR);
@@ -532,7 +532,7 @@ void RISCVPassConfig::addPreEmitPass2() {
 }
 
 void RISCVPassConfig::addMachineSSAOptimization() {
-  addPass(createRISCVFoldMasksPass());
+  addPass(createRISCVVectorPeepholePass());
 
   TargetPassConfig::addMachineSSAOptimization();
 

diff --git a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp → .../lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp → .../lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -1,24 +1,29 @@
-//===- RISCVFoldMasks.cpp - MI Vector Pseudo Mask Peepholes ---------------===//
+//===- RISCVVectorPeephole.cpp - MI Vector Pseudo Peepholes --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===---------------------------------------------------------------------===//
 //
-// This pass performs various peephole optimisations that fold masks into vector
-// pseudo instructions after instruction selection.
+// This pass performs various vector pseudo peephole optimisations after
+// instruction selection.
 //
-// Currently it converts
+// Currently it converts vmerge.vvm to vmv.v.v
 // PseudoVMERGE_VVM %false, %false, %true, %allonesmask, %vl, %sew
 // ->
 // PseudoVMV_V_V %false, %true, %vl, %sew
 //
+// And masked pseudos to unmasked pseudos
+// PseudoVADD_V_V_MASK %passthru, %a, %b, %allonesmask, %vl, sew, policy
+// ->
+// PseudoVADD_V_V %passthru %a, %b, %vl, sew, policy
+//
 // It also converts AVLs to VLMAX where possible
 // %vl = VLENB * something
-// PseudoVADD_V_V %a, %b, %vl
+// PseudoVADD_V_V %passthru, %a, %b, %vl, sew, policy
 // ->
-// PseudoVADD_V_V %a, %b, -1
+// PseudoVADD_V_V %passthru, %a, %b, -1, sew, policy
 //
 //===---------------------------------------------------------------------===//
 
@@ -32,17 +37,17 @@
 
 using namespace llvm;
 
-#define DEBUG_TYPE "riscv-fold-masks"
+#define DEBUG_TYPE "riscv-vector-peephole"
 
 namespace {
 
-class RISCVFoldMasks : public MachineFunctionPass {
+class RISCVVectorPeephole : public MachineFunctionPass {
 public:
   static char ID;
   const TargetInstrInfo *TII;
   MachineRegisterInfo *MRI;
   const TargetRegisterInfo *TRI;
-  RISCVFoldMasks() : MachineFunctionPass(ID) {}
+  RISCVVectorPeephole() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override;
   MachineFunctionProperties getRequiredProperties() const override {
@@ -65,13 +70,14 @@ class RISCVFoldMasks : public MachineFunctionPass {
 
 } // namespace
 
-char RISCVFoldMasks::ID = 0;
+char RISCVVectorPeephole::ID = 0;
 
-INITIALIZE_PASS(RISCVFoldMasks, DEBUG_TYPE, "RISC-V Fold Masks", false, false)
+INITIALIZE_PASS(RISCVVectorPeephole, DEBUG_TYPE, "RISC-V Fold Masks", false,
+                false)
 
 // If an AVL is a VLENB that's possibly scaled to be equal to VLMAX, convert it
 // to the VLMAX sentinel value.
-bool RISCVFoldMasks::convertToVLMAX(MachineInstr &MI) const {
+bool RISCVVectorPeephole::convertToVLMAX(MachineInstr &MI) const {
   if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) ||
       !RISCVII::hasSEWOp(MI.getDesc().TSFlags))
     return false;
@@ -119,7 +125,7 @@ bool RISCVFoldMasks::convertToVLMAX(MachineInstr &MI) const {
   return true;
 }
 
-bool RISCVFoldMasks::isAllOnesMask(const MachineInstr *MaskDef) const {
+bool RISCVVectorPeephole::isAllOnesMask(const MachineInstr *MaskDef) const {
   assert(MaskDef && MaskDef->isCopy() &&
          MaskDef->getOperand(0).getReg() == RISCV::V0);
   Register SrcReg = TRI->lookThruCopyLike(MaskDef->getOperand(1).getReg(), MRI);
@@ -148,7 +154,7 @@ bool RISCVFoldMasks::isAllOnesMask(const MachineInstr *MaskDef) const {
 
 // Transform (VMERGE_VVM_<LMUL> false, false, true, allones, vl, sew) to
 // (VMV_V_V_<LMUL> false, true, vl, sew). It may decrease uses of VMSET.
-bool RISCVFoldMasks::convertVMergeToVMv(MachineInstr &MI) const {
+bool RISCVVectorPeephole::convertVMergeToVMv(MachineInstr &MI) const {
 #define CASE_VMERGE_TO_VMV(lmul)                                               \
   case RISCV::PseudoVMERGE_VVM_##lmul:                                         \
     NewOpc = RISCV::PseudoVMV_V_V_##lmul;                                      \
@@ -191,7 +197,7 @@ bool RISCVFoldMasks::convertVMergeToVMv(MachineInstr &MI) const {
   return true;
 }
 
-bool RISCVFoldMasks::convertToUnmasked(MachineInstr &MI) const {
+bool RISCVVectorPeephole::convertToUnmasked(MachineInstr &MI) const {
   const RISCV::RISCVMaskedPseudoInfo *I =
       RISCV::getMaskedPseudoInfo(MI.getOpcode());
   if (!I)
@@ -235,7 +241,7 @@ bool RISCVFoldMasks::convertToUnmasked(MachineInstr &MI) const {
   return true;
 }
 
-bool RISCVFoldMasks::runOnMachineFunction(MachineFunction &MF) {
+bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
     return false;
 
@@ -279,4 +285,6 @@ bool RISCVFoldMasks::runOnMachineFunction(MachineFunction &MF) {
   return Changed;
 }
 
-FunctionPass *llvm::createRISCVFoldMasksPass() { return new RISCVFoldMasks(); }
+FunctionPass *llvm::createRISCVVectorPeepholePass() {
+  return new RISCVVectorPeephole();
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-fold-masks \
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
 # RUN:     -verify-machineinstrs | FileCheck %s
 
 ---