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Linker Warning: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi) #69780

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hiraditya opened this issue Oct 20, 2023 · 7 comments
Open

Linker Warning: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi) #69780

hiraditya opened this issue Oct 20, 2023 · 7 comments
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ipo Interprocedural optimizations LTO Link time optimization (regular/full LTO or ThinLTO)

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@hiraditya
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hiraditya commented Oct 20, 2023 •
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This happens while building aosp with lto. A reduced case of building libziparchive also gives this warning. Here is the linker invocation.

"clang/host/linux-x86/clang-r498229b/bin/ld.lld" -z now -z relro --hash-style=gnu --eh-frame-hdr -m elf64lriscv -X -shared -o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_shared_cfi/unstripped/libziparchive.so -Lclang/host/linux-x86/clang-r498229b/lib/clang/17/lib/linux/riscv64 -L/lib/../lib64 -L/usr/lib/../lib64 -L/lib -L/usr/lib -plugin-opt=mcpu=generic-rv64 --no-demangle --export-dynamic-symbol=__cfi_check out/soong/.intermediates/bionic/libc/crtbegin_so/android_vendor_ramdisk_riscv64/crtbegin_so.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_archive.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_archive_stream_entry.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_cd_entry_map.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_error.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_writer.o out/soong/.intermediates/external/libcxxabi/libc++demangle/android_vendor_ramdisk_riscv64_static_lto-none/libc++demangle.a prebuilts/clang/host/linux-x86/clang-r498229b/lib/clang/17/lib/linux/libclang_rt.ubsan_minimal-riscv64-android.a prebuilts/clang/host/linux-x86/clang-r498229b/lib/clang/17/lib/linux/libclang_rt.builtins-riscv64-android.a out/soong/.intermediates/system/logging/liblog/liblog/android_vendor_ramdisk_riscv64_shared/liblog.so out/soong/.intermediates/system/libbase/libbase/android_vendor_ramdisk_riscv64_shared/libbase.so out/soong/.intermediates/external/zlib/libz/android_vendor_ramdisk_riscv64_shared/libz.so out/soong/.intermediates/external/libcxx/libc++/android_vendor_ramdisk_riscv64_shared/libc++.so out/soong/.intermediates/bionic/libc/libc/android_vendor_ramdisk_riscv64_shared/libc.so out/soong/.intermediates/bionic/libm/libm/android_vendor_ramdisk_riscv64_shared/libm.so out/soong/.intermediates/bionic/libdl/libdl/android_vendor_ramdisk_riscv64_shared/libdl.so out/soong/.intermediates/bionic/libc/crtend_so/android_vendor_ramdisk_riscv64/crtend_so.o -z noexecstack -z relro -z now --build-id=md5 --fatal-warnings --no-undefined-version --exclude-libs libgcc.a --exclude-libs libgcc_stripped.a --exclude-libs libunwind_llvm.a --exclude-libs libunwind.a -mllvm -regalloc-enable-advisor=release --icf=safe --pack-dyn-relocs=android+relr --no-undefined --hash-style=gnu -z max-page-size=4096 -plugin-opt -emulated-tls=0 --gc-sections -soname libziparchive.so -plugin-opt O1 --exclude-libs=libclang_rt.builtins-riscv64-android.a --exclude-libs=libclang_rt.ubsan_minimal-riscv64-android.a

All the binary files (including the ones in .a) have 'double-float ABI'. it could be that the bitcode files 'out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/*.o' are not getting compiled with the double-float flag?

Repro steps if you one can download aosp.

$ lunch aosp_riscv64-userdebug
$ cd system/libziparchive
$ mm

Related discussions/PRs/issues:
@hiraditya hiraditya added backend:RISC-V LTO Link time optimization (regular/full LTO or ThinLTO) labels Oct 20, 2023
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llvmbot commented Oct 20, 2023

@llvm/issue-subscribers-backend-risc-v

Author: AdityaK (hiraditya)

This happens while building aosp with lto. A reduced case of building libziparchive also gives this warning. Here is the linker invocation.

> "clang/host/linux-x86/clang-r498229b/bin/ld.lld" -z now -z relro --hash-style=gnu --eh-frame-hdr -m elf64lriscv -X -shared -o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_shared_cfi/unstripped/libziparchive.so -Lclang/host/linux-x86/clang-r498229b/lib/clang/17/lib/linux/riscv64 -L/lib/../lib64 -L/usr/lib/../lib64 -L/lib -L/usr/lib -plugin-opt=mcpu=generic-rv64 --no-demangle --export-dynamic-symbol=__cfi_check out/soong/.intermediates/bionic/libc/crtbegin_so/android_vendor_ramdisk_riscv64/crtbegin_so.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_archive.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_archive_stream_entry.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_cd_entry_map.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_error.o out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/zip_writer.o out/soong/.intermediates/external/libcxxabi/libc++demangle/android_vendor_ramdisk_riscv64_static_lto-none/libc++demangle.a prebuilts/clang/host/linux-x86/clang-r498229b/lib/clang/17/lib/linux/libclang_rt.ubsan_minimal-riscv64-android.a prebuilts/clang/host/linux-x86/clang-r498229b/lib/clang/17/lib/linux/libclang_rt.builtins-riscv64-android.a out/soong/.intermediates/system/logging/liblog/liblog/android_vendor_ramdisk_riscv64_shared/liblog.so out/soong/.intermediates/system/libbase/libbase/android_vendor_ramdisk_riscv64_shared/libbase.so out/soong/.intermediates/external/zlib/libz/android_vendor_ramdisk_riscv64_shared/libz.so out/soong/.intermediates/external/libcxx/libc++/android_vendor_ramdisk_riscv64_shared/libc++.so out/soong/.intermediates/bionic/libc/libc/android_vendor_ramdisk_riscv64_shared/libc.so out/soong/.intermediates/bionic/libm/libm/android_vendor_ramdisk_riscv64_shared/libm.so out/soong/.intermediates/bionic/libdl/libdl/android_vendor_ramdisk_riscv64_shared/libdl.so out/soong/.intermediates/bionic/libc/crtend_so/android_vendor_ramdisk_riscv64/crtend_so.o -z noexecstack -z relro -z now --build-id=md5 --fatal-warnings --no-undefined-version --exclude-libs libgcc.a --exclude-libs libgcc_stripped.a --exclude-libs libunwind_llvm.a --exclude-libs libunwind.a -mllvm -regalloc-enable-advisor=release --icf=safe --pack-dyn-relocs=android+relr --no-undefined --hash-style=gnu -z max-page-size=4096 -plugin-opt -emulated-tls=0 --gc-sections -soname libziparchive.so -plugin-opt O1 --exclude-libs=libclang_rt.builtins-riscv64-android.a --exclude-libs=libclang_rt.ubsan_minimal-riscv64-android.a

All the binary files (including the ones in .a) have 'double-float ABI'. it could be that the bitcode files 'out/soong/.intermediates/system/libziparchive/libziparchive/android_vendor_ramdisk_riscv64_static_cfi_lto-none/obj/system/libziparchive/*.o' are not getting compiled with the double-float flag?

Related discussions/PR:

@hiraditya hiraditya changed the title Linker Warning: "Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)" Linker Warning: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi) Oct 20, 2023
@hiraditya
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cc: @topperc @teresajohnson

@hiraditya
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Maybe we should also improve the warning to include the offending file that is causing the issue?

The warning comes from:

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -92,7 +92,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
   } else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) &&
              !Subtarget.hasStdExtD()) {

@ilovepi ilovepi mentioned this issue Nov 28, 2023
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@hiraditya
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hiraditya commented Jul 25, 2024 •
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The warning is only emitted from (IIUC) compiler generated functions like

define void @__cfi_check(i64 %0, ptr %1, ptr %2) align 4096
define private void @.cfi.jumptable() #46 align 8

Seems like the bug is in functions like CrossDSOCFI::buildCFICheck(Module &M) where the compiler doesn't provide desired target attributes for generated functions.

Currently arm has a hacky way of adding target-feature when generating __cfi_check (

llvm-project/llvm/lib/Transforms/IPO/CrossDSOCFI.cpp

Lines 94 to 100 in 4ed543d

Triple T(M.getTargetTriple());
if (T.isARM() || T.isThumb())
F->addFnAttr("target-features", "+thumb-mode");
auto args = F->arg_begin();
Value &CallSiteTypeId = *(args++);
) but it is likely other places were missed.

Seems like we are missing something like a 'target-feature-unification' pass as the final binary can only support a specific ABI.

@hiraditya hiraditya mentioned this issue Jul 25, 2024
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@hiraditya
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hiraditya commented Jul 25, 2024 •
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Related patch #98673

@hiraditya hiraditya mentioned this issue Jul 26, 2024
Closed
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Jul 26, 2024
@hiraditya
[Draft] Use Module to get Triple in getDefaultSubtargetFeatures
6052288 
Module can be used to query target-abi (follow up patch) which
can be used to populate default subtarget features.
It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Jul 31, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
04a4523 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Aug 31, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
a882c96 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 4, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
fb822ab 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 5, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
3e4125b 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 5, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
f9307a0 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 5, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
6fbcafd 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 5, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
45e232d 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 6, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
09c2dde 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 6, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
06d0e15 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 9, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
a65c4f5 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Sep 10, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
cc43666 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
@hiraditya hiraditya mentioned this issue Nov 12, 2024
Open
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Dec 18, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
2430ee2 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Dec 18, 2024
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
999b9b9 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
hiraditya added a commit to hiraditya/llvm-project that referenced this issue Feb 5, 2025
@hiraditya
Use TargetABI to assign default-target features in getDefaultSubtarge…
11d6bf5 
…tFeatures

It is currently not possible to provide any reasonable
target-features for compiler generated functions (See: llvm#69780)
Having a target-abi will provide a way to add minimal
requirements for target-features like `+d` for RISC-V.
@asb asb mentioned this issue Feb 17, 2025
Open
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asb commented Feb 18, 2025

I've been seeing this warning with some llvm-test-suite compiles, and believe I have a case where it occurs that's not addressed by any of the in-flight patches. I've narrowed it down to the GlobalOpt pass:

tc.ll:

; ModuleID = 'ld-temp.o'
source_filename = "ld-temp.o"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

@__const.main.s = private unnamed_addr constant [14 x i8] c"abcedfg012345\00", align 1

; Function Attrs: nofree norecurse nosync nounwind memory(none) uwtable
define dso_local noundef signext i32 @main() #0 {
  %1 = alloca [14 x i8], align 1
  call void @llvm.lifetime.start.p0(i64 14, ptr nonnull %1) #3
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(14) %1, ptr noundef nonnull align 1 dereferenceable(14) @__const.main.s, i64 14, i1 false)
  br label %2

2:                                                ; preds = %2, %0
  %3 = phi ptr [ %1, %0 ], [ %4, %2 ]
  %4 = getelementptr inbounds i8, ptr %3, i64 -1
  %5 = load i8, ptr %4, align 1, !tbaa !11
  %6 = icmp eq i8 %5, 0
  br i1 %6, label %7, label %2, !llvm.loop !14

7:                                                ; preds = %2
  store i16 88, ptr %4, align 1
  call void @llvm.lifetime.end.p0(i64 14, ptr nonnull %1) #3
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg %0, ptr captures(none) %1) #1

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none) %0, ptr noalias readonly captures(none) %1, i64 %2, i1 immarg %3) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg %0, ptr captures(none) %1) #1

attributes #0 = { nofree norecurse nosync nounwind memory(none) uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.ident = !{!0}
!llvm.module.flags = !{!1, !2, !3, !5, !6, !7, !8, !9, !10}

!0 = !{!"clang version 21.0.0git"}
!1 = !{i32 1, !"wchar_size", i32 4}
!2 = !{i32 1, !"target-abi", !"lp64d"}
!3 = !{i32 6, !"riscv-isa", !4}
!4 = !{!"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"}
!5 = !{i32 8, !"PIC Level", i32 2}
!6 = !{i32 7, !"PIE Level", i32 2}
!7 = !{i32 7, !"uwtable", i32 2}
!8 = !{i32 8, !"SmallDataLimit", i32 0}
!9 = !{i32 1, !"ThinLTO", i32 0}
!10 = !{i32 1, !"EnableSplitLTOUnit", i32 1}
!11 = !{!12, !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C/C++ TBAA"}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}

./bin/opt < tc2.ll -S -passes=globalopt >/dev/null
Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)

@frederick-vs-ja frederick-vs-ja mentioned this issue Feb 18, 2025
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@topperc
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topperc commented Feb 19, 2025

I've been seeing this warning with some llvm-test-suite compiles, and believe I have a case where it occurs that's not addressed by any of the in-flight patches. I've narrowed it down to the GlobalOpt pass:

tc.ll:

; ModuleID = 'ld-temp.o'
source_filename = "ld-temp.o"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

@__const.main.s = private unnamed_addr constant [14 x i8] c"abcedfg012345\00", align 1

; Function Attrs: nofree norecurse nosync nounwind memory(none) uwtable
define dso_local noundef signext i32 @main() #0 {
  %1 = alloca [14 x i8], align 1
  call void @llvm.lifetime.start.p0(i64 14, ptr nonnull %1) #3
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(14) %1, ptr noundef nonnull align 1 dereferenceable(14) @__const.main.s, i64 14, i1 false)
  br label %2

2:                                                ; preds = %2, %0
  %3 = phi ptr [ %1, %0 ], [ %4, %2 ]
  %4 = getelementptr inbounds i8, ptr %3, i64 -1
  %5 = load i8, ptr %4, align 1, !tbaa !11
  %6 = icmp eq i8 %5, 0
  br i1 %6, label %7, label %2, !llvm.loop !14

7:                                                ; preds = %2
  store i16 88, ptr %4, align 1
  call void @llvm.lifetime.end.p0(i64 14, ptr nonnull %1) #3
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg %0, ptr captures(none) %1) #1

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none) %0, ptr noalias readonly captures(none) %1, i64 %2, i1 immarg %3) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg %0, ptr captures(none) %1) #1

attributes #0 = { nofree norecurse nosync nounwind memory(none) uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.ident = !{!0}
!llvm.module.flags = !{!1, !2, !3, !5, !6, !7, !8, !9, !10}

!0 = !{!"clang version 21.0.0git"}
!1 = !{i32 1, !"wchar_size", i32 4}
!2 = !{i32 1, !"target-abi", !"lp64d"}
!3 = !{i32 6, !"riscv-isa", !4}
!4 = !{!"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"}
!5 = !{i32 8, !"PIC Level", i32 2}
!6 = !{i32 7, !"PIE Level", i32 2}
!7 = !{i32 7, !"uwtable", i32 2}
!8 = !{i32 8, !"SmallDataLimit", i32 0}
!9 = !{i32 1, !"ThinLTO", i32 0}
!10 = !{i32 1, !"EnableSplitLTOUnit", i32 1}
!11 = !{!12, !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C/C++ TBAA"}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}

./bin/opt < tc2.ll -S -passes=globalopt >/dev/null
Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)

It appears we're trying to get the TTI for an llvm.memcpy declaration. We should probably get TTI for the caller instead.

diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 9586fc97a39f..32a2632fee36 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -2186,7 +2186,7 @@ static bool tryWidenGlobalArraysUsedByMemcpy(
     if (NumElementsToCopy != DZSize || DZSize != SZSize)
       continue;
 
-    unsigned NumBytesToPad = GetTTI(*F).getNumBytesToPadGlobalArray(
+    unsigned NumBytesToPad = GetTTI(*CI->getFunction()).getNumBytesToPadGlobalArray(
         NumBytesToCopy, SourceDataArray->getType());
     if (NumBytesToPad) {
       return tryWidenGlobalArrayAndDests(F, GV, NumBytesToPad, NumBytesToCopy,

@topperc topperc mentioned this issue Feb 19, 2025
Merged
@EugeneZelenko EugeneZelenko added ipo Interprocedural optimizations and removed backend:RISC-V labels Feb 19, 2025
topperc added a commit that referenced this issue Feb 19, 2025
@topperc
[GlobalOpt] Don't query TTI on a llvm.memcpy declaration. (#127760)
2bf473b 
Querying TTI creates a Subtarget object, but an llvm.memcpy declaration
doesn't have target-cpu and target-feature attributes like functions
with definitions. This can cause a warning to be printed on RISC-V
because the target-abi in the Module requires floating point, but the
subtarget features don't enable floating point. So far we've only seen
this in LTO when an -mcpu is not supplied for the TargetMachine.

To fix this, get TTI for the calling function instead.

Fixes the issue reported here
#69780 (comment)
llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this issue Feb 19, 2025
@topperc @github-actions
Automerge: [GlobalOpt] Don't query TTI on a llvm.memcpy declaration. …
195157b 
…(#127760)

Querying TTI creates a Subtarget object, but an llvm.memcpy declaration
doesn't have target-cpu and target-feature attributes like functions
with definitions. This can cause a warning to be printed on RISC-V
because the target-abi in the Module requires floating point, but the
subtarget features don't enable floating point. So far we've only seen
this in LTO when an -mcpu is not supplied for the TargetMachine.

To fix this, get TTI for the calling function instead.

Fixes the issue reported here
llvm/llvm-project#69780 (comment)
@joaosaffran joaosaffran mentioned this issue Feb 26, 2025
Closed
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ipo Interprocedural optimizations LTO Link time optimization (regular/full LTO or ThinLTO)
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