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Bump verif/core-v-verif from 60e5724 to 868d630
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@ASintzoff
ASintzoff committed Feb 21, 2025
1 parent dc0a848 commit ae96389
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion verif/core-v-verif
Submodule core-v-verif updated 27 files
+4 −0 lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv
+1 −0 lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv
+3 −2 lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_utils.sv
+14 −4 lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_drv.sv
+5 −5 lib/uvm_agents/uvma_cvxif/src/obj/uvma_cvxif_cfg.sv
+0 −13 lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_assert.sv
+4 −2 lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv
+2 −1 lib/uvm_agents/uvma_isacov/uvma_isacov_macros.sv
+3 −3 lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv
+2 −2 lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv
+33 −0 vendor/patches/riscv/riscv-isa-sim/0037-make-zifencei-optional.patch
+298 −46 vendor/riscv/riscv-isa-sim/customext/cvxif.cc
+10 −0 vendor/riscv/riscv-isa-sim/disasm/disasm.cc
+12 −3 vendor/riscv/riscv-isa-sim/disasm/isa_parser.cc
+1 −1 vendor/riscv/riscv-isa-sim/fesvr/SimDTM.cc
+2 −2 vendor/riscv/riscv-isa-sim/fesvr/fesvr_dpi.cc
+15 −4 vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+6 −0 vendor/riscv/riscv-isa-sim/riscv/Proc.h
+34 −7 vendor/riscv/riscv-isa-sim/riscv/cvxif.h
+4 −6 vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc
+26 −0 vendor/riscv/riscv-isa-sim/riscv/encoding.h
+3 −0 vendor/riscv/riscv-isa-sim/riscv/extension.h
+1 −0 vendor/riscv/riscv-isa-sim/riscv/insns/fence_i.h
+2 −0 vendor/riscv/riscv-isa-sim/riscv/isa_parser.h
+7 −0 vendor/riscv/riscv-isa-sim/riscv/overlap_list.h
+6 −2 vendor/riscv/riscv-isa-sim/riscv/processor.cc
+5 −0 vendor/riscv/riscv-isa-sim/spike_main/spike.cc

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