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Merge branch 'verilog' of https://github.com/vhda/ctags into fishman/…
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	verilog.c
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@vhda
vhda committed Nov 6, 2014
2 parents e83b58e + 7e847bb commit 5ecd391
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Showing 7 changed files with 316 additions and 72 deletions.
1 change: 1 addition & 0 deletions Units/verilog-2001.d/args.ctags
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--extra=+q
42 changes: 40 additions & 2 deletions Units/verilog-2001.d/expected.tags
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DEFINE Units/verilog-2001.d/input.v /^`define DEFINE$/;" c
PARAM Units/verilog-2001.d/input.v /^parameter PARAM = 1;$/;" c module:mod
DEF_VALUE Units/verilog-2001.d/input.v /^`define DEF_VALUE 1'd100$/;" c
LOCALPARAM Units/verilog-2001.d/input.v /^localparam LOCALPARAM = 2**2;$/;" c module:mod
PARAM1 Units/verilog-2001.d/input.v /^ parameter PARAM1 = 10,$/;" c module:mod
PARAM2 Units/verilog-2001.d/input.v /^ parameter PARAM2 = 2.0$/;" c module:mod
STATE1 Units/verilog-2001.d/input.v /^localparam STATE1 = 4'h0,$/;" c module:mod
STATE2 Units/verilog-2001.d/input.v /^ STATE2 = 4'h1,$/;" c module:mod
STATE3 Units/verilog-2001.d/input.v /^ STATE3 = 4'h2,$/;" c module:mod
STATE4 Units/verilog-2001.d/input.v /^ STATE4 = 4'h5 ,$/;" c module:mod
STATE5 Units/verilog-2001.d/input.v /^ STATE5 = 4'h6 ,$/;" c module:mod
STATE6 Units/verilog-2001.d/input.v /^ STATE6 = 4'h7 ,$/;" c module:mod
STATE7 Units/verilog-2001.d/input.v /^ STATE7 = 4'h8;$/;" c module:mod
a Units/verilog-2001.d/input.v /^ input wire a,$/;" p module:mod
add Units/verilog-2001.d/input.v /^task add ($/;" t module:mod
b Units/verilog-2001.d/input.v /^ b,c,$/;" p module:mod
Expand All @@ -10,8 +20,36 @@ f Units/verilog-2001.d/input.v /^ output reg f,$/;" p module:mod
g Units/verilog-2001.d/input.v /^ inout wire g$/;" p module:mod
k Units/verilog-2001.d/input.v /^real k;$/;" r module:mod
l Units/verilog-2001.d/input.v /^integer l;$/;" r module:mod
mod Units/verilog-2001.d/input.v /^module mod ($/;" m
mod Units/verilog-2001.d/input.v /^module mod#($/;" m
mod.LOCALPARAM Units/verilog-2001.d/input.v /^localparam LOCALPARAM = 2**2;$/;" c module:mod
mod.PARAM1 Units/verilog-2001.d/input.v /^ parameter PARAM1 = 10,$/;" c module:mod
mod.PARAM2 Units/verilog-2001.d/input.v /^ parameter PARAM2 = 2.0$/;" c module:mod
mod.STATE1 Units/verilog-2001.d/input.v /^localparam STATE1 = 4'h0,$/;" c module:mod
mod.STATE2 Units/verilog-2001.d/input.v /^ STATE2 = 4'h1,$/;" c module:mod
mod.STATE3 Units/verilog-2001.d/input.v /^ STATE3 = 4'h2,$/;" c module:mod
mod.STATE4 Units/verilog-2001.d/input.v /^ STATE4 = 4'h5 ,$/;" c module:mod
mod.STATE5 Units/verilog-2001.d/input.v /^ STATE5 = 4'h6 ,$/;" c module:mod
mod.STATE6 Units/verilog-2001.d/input.v /^ STATE6 = 4'h7 ,$/;" c module:mod
mod.STATE7 Units/verilog-2001.d/input.v /^ STATE7 = 4'h8;$/;" c module:mod
mod.a Units/verilog-2001.d/input.v /^ input wire a,$/;" p module:mod
mod.add Units/verilog-2001.d/input.v /^task add ($/;" t module:mod
mod.add.x Units/verilog-2001.d/input.v /^ input x, y,$/;" p task:mod.add
mod.add.y Units/verilog-2001.d/input.v /^ input x, y,$/;" p task:mod.add
mod.add.z Units/verilog-2001.d/input.v /^ output z$/;" p task:mod.add
mod.b Units/verilog-2001.d/input.v /^ b,c,$/;" p module:mod
mod.c Units/verilog-2001.d/input.v /^ b,c,$/;" p module:mod
mod.d Units/verilog-2001.d/input.v /^ d ,$/;" p module:mod
mod.e Units/verilog-2001.d/input.v /^ output wire e ,$/;" p module:mod
mod.f Units/verilog-2001.d/input.v /^ output reg f,$/;" p module:mod
mod.g Units/verilog-2001.d/input.v /^ inout wire g$/;" p module:mod
mod.k Units/verilog-2001.d/input.v /^real k;$/;" r module:mod
mod.l Units/verilog-2001.d/input.v /^integer l;$/;" r module:mod
mod.mult Units/verilog-2001.d/input.v /^function mult ($/;" f module:mod
mod.mult.x Units/verilog-2001.d/input.v /^ input x,$/;" p function:mod.mult
mod.mult.y Units/verilog-2001.d/input.v /^ input y);$/;" p function:mod.mult
mod.scounter Units/verilog-2001.d/input.v /^reg signed [3:0] scounter;$/;" r module:mod
mult Units/verilog-2001.d/input.v /^function mult ($/;" f module:mod
scounter Units/verilog-2001.d/input.v /^reg signed [3:0] scounter;$/;" r module:mod
x Units/verilog-2001.d/input.v /^ input x, y,$/;" p task:mod.add
x Units/verilog-2001.d/input.v /^ input x,$/;" p function:mod.mult
y Units/verilog-2001.d/input.v /^ input x, y,$/;" p task:mod.add
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17 changes: 15 additions & 2 deletions Units/verilog-2001.d/input.v
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Expand Up @@ -2,8 +2,12 @@
// module wrong;
// endmodule
`define DEFINE
`define DEF_VALUE 1'd100

module mod (
module mod#(
parameter PARAM1 = 10,
parameter PARAM2 = 2.0
) (
input wire a,
b,c,
d ,
Expand All @@ -12,10 +16,19 @@ module mod (
inout wire g
);

parameter PARAM = 1;
localparam LOCALPARAM = 2**2;

localparam STATE1 = 4'h0,
STATE2 = 4'h1,
STATE3 = 4'h2,
STATE4 = 4'h5 ,
STATE5 = 4'h6 ,
STATE6 = 4'h7 ,
STATE7 = 4'h8;

real k;
integer l;
reg signed [3:0] scounter;

task add (
input x, y,
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1 change: 1 addition & 0 deletions Units/verilog-basic.d/args.ctags
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--extra=+q
39 changes: 39 additions & 0 deletions Units/verilog-basic.d/expected.tags
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@@ -1,5 +1,13 @@
DEFINE Units/verilog-basic.d/input.v /^`define DEFINE$/;" c
DEF_VALUE Units/verilog-basic.d/input.v /^`define DEF_VALUE 1'd100$/;" c
PARAM Units/verilog-basic.d/input.v /^parameter PARAM = 1;$/;" c module:mod
STATE1 Units/verilog-basic.d/input.v /^parameter STATE1 = 4'h0,$/;" c module:mod
STATE2 Units/verilog-basic.d/input.v /^ STATE2 = 4'h1,$/;" c module:mod
STATE3 Units/verilog-basic.d/input.v /^ STATE3 = 4'h2,$/;" c module:mod
STATE4 Units/verilog-basic.d/input.v /^ STATE4 = 4'h5 ,$/;" c module:mod
STATE5 Units/verilog-basic.d/input.v /^ STATE5 = 4'h6 ,$/;" c module:mod
STATE6 Units/verilog-basic.d/input.v /^ STATE6 = 4'h7 ,$/;" c module:mod
STATE7 Units/verilog-basic.d/input.v /^ STATE7 = 4'h8;$/;" c module:mod
a Units/verilog-basic.d/input.v /^input a,b, c, d ;$/;" p module:mod
a Units/verilog-basic.d/input.v /^wire a,b,c,d,e;$/;" n module:mod
add Units/verilog-basic.d/input.v /^task add;$/;" t module:mod
Expand All @@ -18,6 +26,37 @@ g Units/verilog-basic.d/input.v /^wire g;$/;" n module:mod
k Units/verilog-basic.d/input.v /^real k;$/;" r module:mod
l Units/verilog-basic.d/input.v /^integer l;$/;" r module:mod
mod Units/verilog-basic.d/input.v /^module mod ($/;" m
mod.PARAM Units/verilog-basic.d/input.v /^parameter PARAM = 1;$/;" c module:mod
mod.STATE1 Units/verilog-basic.d/input.v /^parameter STATE1 = 4'h0,$/;" c module:mod
mod.STATE2 Units/verilog-basic.d/input.v /^ STATE2 = 4'h1,$/;" c module:mod
mod.STATE3 Units/verilog-basic.d/input.v /^ STATE3 = 4'h2,$/;" c module:mod
mod.STATE4 Units/verilog-basic.d/input.v /^ STATE4 = 4'h5 ,$/;" c module:mod
mod.STATE5 Units/verilog-basic.d/input.v /^ STATE5 = 4'h6 ,$/;" c module:mod
mod.STATE6 Units/verilog-basic.d/input.v /^ STATE6 = 4'h7 ,$/;" c module:mod
mod.STATE7 Units/verilog-basic.d/input.v /^ STATE7 = 4'h8;$/;" c module:mod
mod.a Units/verilog-basic.d/input.v /^input a,b, c, d ;$/;" p module:mod
mod.a Units/verilog-basic.d/input.v /^wire a,b,c,d,e;$/;" n module:mod
mod.add Units/verilog-basic.d/input.v /^task add;$/;" t module:mod
mod.add.x Units/verilog-basic.d/input.v /^ input x, y;$/;" p task:mod.add
mod.add.y Units/verilog-basic.d/input.v /^ input x, y;$/;" p task:mod.add
mod.add.z Units/verilog-basic.d/input.v /^ output z;$/;" p task:mod.add
mod.b Units/verilog-basic.d/input.v /^input a,b, c, d ;$/;" p module:mod
mod.b Units/verilog-basic.d/input.v /^wire a,b,c,d,e;$/;" n module:mod
mod.c Units/verilog-basic.d/input.v /^input a,b, c, d ;$/;" p module:mod
mod.c Units/verilog-basic.d/input.v /^wire a,b,c,d,e;$/;" n module:mod
mod.d Units/verilog-basic.d/input.v /^input a,b, c, d ;$/;" p module:mod
mod.d Units/verilog-basic.d/input.v /^wire a,b,c,d,e;$/;" n module:mod
mod.e Units/verilog-basic.d/input.v /^output e;$/;" p module:mod
mod.e Units/verilog-basic.d/input.v /^wire a,b,c,d,e;$/;" n module:mod
mod.f Units/verilog-basic.d/input.v /^output f;$/;" p module:mod
mod.f Units/verilog-basic.d/input.v /^reg f;$/;" r module:mod
mod.g Units/verilog-basic.d/input.v /^inout g;$/;" p module:mod
mod.g Units/verilog-basic.d/input.v /^wire g;$/;" n module:mod
mod.k Units/verilog-basic.d/input.v /^real k;$/;" r module:mod
mod.l Units/verilog-basic.d/input.v /^integer l;$/;" r module:mod
mod.mult Units/verilog-basic.d/input.v /^function mult;$/;" f module:mod
mod.mult.x Units/verilog-basic.d/input.v /^ input x;$/;" p function:mod.mult
mod.mult.y Units/verilog-basic.d/input.v /^ input y;$/;" p function:mod.mult
mult Units/verilog-basic.d/input.v /^function mult;$/;" f module:mod
x Units/verilog-basic.d/input.v /^ input x, y;$/;" p task:mod.add
x Units/verilog-basic.d/input.v /^ input x;$/;" p function:mod.mult
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9 changes: 9 additions & 0 deletions Units/verilog-basic.d/input.v
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Expand Up @@ -2,6 +2,7 @@
// module wrong;
// endmodule
`define DEFINE
`define DEF_VALUE 1'd100

module mod (
a,
Expand All @@ -13,6 +14,14 @@ module mod (

parameter PARAM = 1;

parameter STATE1 = 4'h0,
STATE2 = 4'h1,
STATE3 = 4'h2,
STATE4 = 4'h5 ,
STATE5 = 4'h6 ,
STATE6 = 4'h7 ,
STATE7 = 4'h8;

input a,b, c, d ;
output e;
output f;
Expand Down
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2 comments on commit 5ecd391

@ffes
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@ffes ffes commented on 5ecd391 Nov 6, 2014

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@vhda I don't know Verilog, but are all these changes to this parser worth mentioning in f-news.rst "Heavily improved parsers" section?

@vhda
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@vhda vhda commented on 5ecd391 Nov 6, 2014

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Yes, it would probably make sense to do that.
The original parser was very basic and I'm trying to improve it to at least accommodate my day-to-day use.
Next step is to include SystemVerilog support.

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