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Adopt sdkng to hal_nxp #501

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@ZhaoxiangJin ZhaoxiangJin commented Jan 23, 2025

Hello reviewers, please see the Zephyr side PR descriptions. Thanks.

@ZhaoxiangJin ZhaoxiangJin changed the title Feature/mcux ng glue upstream no kconfig Adopt sdkng to hal_nxp Jan 23, 2025
@zejiang0jason zejiang0jason force-pushed the feature/mcux_ng_glue_upstream_no_kconfig branch 2 times, most recently from c707f91 to 571f2f4 Compare February 4, 2025 14:41
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dbaluta commented Feb 4, 2025

@ZhaoxiangJin I think we should a proper description of this PR here explaining why we need sdkng.

@zejiang0jason zejiang0jason force-pushed the feature/mcux_ng_glue_upstream_no_kconfig branch from 571f2f4 to a9f2516 Compare February 5, 2025 07:37
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@ZhaoxiangJin I think we should a proper description of this PR here explaining why we need sdkng.

The sdkng uses cmake to organize files and kconfig to resolve dependencies. Integrating sdkng into hal_nxp will improve the efficiency of NXP SoC/drivers/components/middleware support in Zephyr.

@ZhaoxiangJin ZhaoxiangJin force-pushed the feature/mcux_ng_glue_upstream_no_kconfig branch 5 times, most recently from cd06bf6 to 06ed137 Compare February 15, 2025 05:57
@ZhaoxiangJin ZhaoxiangJin marked this pull request as ready for review February 15, 2025 05:57
ZhaoxiangJin and others added 17 commits February 15, 2025 14:15
 - Remove the unused cmake which depends on Kconfig.

Signed-off-by: Jason Yu <[email protected]>
 - When SDK NG used, use the file in mcu-sdk-ng folder

Signed-off-by: Jason Yu <[email protected]>
Moves CAAM initialization and RNG related job descriptors to
a non-cacheable region instead of being on the write-back stack.
Currently the CAAM and cores are accessing these descriptors incoherently.

Signed-off-by: Declan Snyder <[email protected]>
BIT macro is defined in util_macro.h in zephyr, let's rename this macro to avoid
conflicts.

Signed-off-by: Lucien Zhao <[email protected]>
Add missing guards to avoid compilation warnings when building with SDK
clock control driver disabled.

Signed-off-by: Marcin Wierzbicki <[email protected]>
For IRQ_STEER, lower CHn_MASK register indexes are used
to mask higher interrupt IDs. For instance, in the case
of i.MX8MP, the mapping is as follows:

	CHn_MASK4 => masks interrupts [31:0]
	CHn_MASK3 => masks interrupts [63:32]
	CHn_MASK2 => masks interrupts [95:64]
	CHn_MASK1 => masks interrupts [127:96]
	CHn_MASK0 => masks interrupts [159:128]

The `IRQSTEER_GetRegIndex()` function is used to fetch
the CHn_MASK register index based on a given slice. The term
"slice" is used to refer to an index of a CHn_MASK register in
the set of CHn_MASK registers assigned to a certain master. Assuming
the following partition scheme (i.MX8MP):

	{ CHn_MASK4 } is assigned to MASTER0
	{ CHn_MASK3, CHn_MASK2 } is assigned to MASTER1
	{ CHn_MASK1, CHn_MASK0 } is assiged to MASTER2

CHn_MASK3 would be at slice (index) 0, CHn_MASK2 would be at
slice 1, CHn_MASK1 would be at slice 0 and so on.

To compute the CHn_MASK register index found at a given slice,
`IRQSTEER_GetRegIndex()` uses a base index, which is either
the lowest or the highest CHn_MASK register index in a master's
partition (for instance, for MASTER1 the higher would be 3 and
the lowest would be 2).

For IRQ_STEER instances with an uneven number of CHn_MASK registers
the base is the lowest index, while in the case of instances with
an even number of CHn_MASK registers it's exactly the opposite. This
is an issue because the software using this function might expect
the base to either be the lowest or the highest index ALL THE TIME
(since this affects the order in which the CHn_MASK register indexes
are returned).

As such, fix this problem by making the base the highest CHn_MASK
register index.

Signed-off-by: Laurentiu Mihalcea <[email protected]>
Allow the flexio driver to pass a parameter to the GPIO
callback functions.

Signed-off-by: Mahesh Mahadevan <[email protected]>
Flexio IP functions in mcux and S32 SoCs are quite similar
This commit enables the existing flexio driver to support
Flexio IP on S32 SoCs by adding PIN Operations and NO DOZE mode.

Signed-off-by: Sumit Batra <[email protected]>
Add missing variable soc_series

Signed-off-by: Jason Yu <[email protected]>
zejiang0jason and others added 8 commits February 15, 2025 14:15
The code uses hal_clock, which causes build fail

Signed-off-by: Jason Yu <[email protected]>
According the RM document, RT1170 58.3.3 (should be same for other MCU
which has a similiar SAI IP):
"A valid frame sync is also ignored (slave mode) or not generated (master
mode) for the first four bit clock cycles after enabling the transmitter
or receiver."
but in fact, we found master side send out a valid frame sync at the 3rd
bit clock cycles which cause this frame sync is ignored by the slave
side and frame data lost.
To workaround this issue, bit clock is enabled before TE/RE.

Signed-off-by: Raymond Lei <[email protected]>
The script sync the MCUX SDK code to folder mcux/mcux-sdk-ng

Signed-off-by: Jason Yu <[email protected]>
@ZhaoxiangJin ZhaoxiangJin force-pushed the feature/mcux_ng_glue_upstream_no_kconfig branch from 06ed137 to daab227 Compare February 15, 2025 10:26
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10 participants