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Merge pull request #40 from SpinalHDL/cleanup
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Cleanup
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Dolu1990 authored Feb 1, 2025
2 parents 9906238 + 084181b commit 5b09686
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34 changes: 34 additions & 0 deletions .github/workflows/push-docs.yml
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name: "Push scaladoc on gh-pages"

on:
push:
branches:
- dev
release:
types:
- published

jobs:
push-docs:
runs-on: ubuntu-22.04
timeout-minutes: 30

steps:
- name: Checkout
uses: actions/checkout@v4
with:
submodules: recursive
- name: Setup JDK
uses: actions/setup-java@v3
with:
distribution: temurin
java-version: 17
cache: sbt
- name: Build scaladoc
run: sbt clean doc
- name: Deploy 🚀
uses: JamesIves/github-pages-deploy-action@v4
with:
folder: target/scala-2.12/api
target-folder: ${{ github.ref_name }}
single-commit: true
16 changes: 12 additions & 4 deletions README.md
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VexiiRiscv (Vex2Risc5) is the successor of VexRiscv. Work in progress, here are its currently implemented features :

- RV32/64 I[M][A][F][D][C][S][U][B]
- Up to 5.24 coremark/Mhz 2.50 dhystone/Mhz (WIP)
- Up to 5.24 coremark/Mhz 2.50 dhystone/Mhz
- In-order execution
- early [late-alu]
- single/dual issue (can be asymmetric)
- BTB, GShare, RAS branch prediction
- cacheless fetch/load/store, I$, D$ (WIP)
- optional SV32/SV39 MMU
- Can run linux / buildroot
- cacheless fetch/load/store
- Optional I$, D$
- Optional SV32/SV39 MMU
- Can run linux / buildroot / Debian
- Pipeline visualisation in simulation via Konata
- Lock step simulation via RVLS and Spike
- ... and many other things

Here is a demonstration of a quad core VexiiRiscv running debian on FPGA : https://youtu.be/dR_jqS13D2c?t=112

Overall the goal is to have a design which can stretch (through configuration) from Cortex M0 up to a Cortex A53 and potentialy beyond.

Expand All @@ -21,6 +25,10 @@ Here is the online documentation :
- https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Introduction/#
- https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/HowToUse/index.html

Here is the VexiiRiscv's scala doc (auto-generated from the source code) :

- https://spinalhdl.github.io/VexiiRiscv/doc/vexiiriscv/index.html

A roadmap is available here :

- https://github.com/SpinalHDL/VexiiRiscv/issues/1
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23 changes: 19 additions & 4 deletions doc/litex/alpine/README.md
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https://blog.ari.lt/b/how-to-manually-install-alpine-linux-on-any-linux-distribution/
https://wiki.gentoo.org/wiki/OpenRC_to_systemd_Cheatsheet
# Getting Alpine linux to run on RISC-V

So this README compile a set of command lines which were used to get it up on running on the VexiiRiscv RV64GC litex SoC.
You can find most of the fundamental informations on the links bellow :

- https://blog.ari.lt/b/how-to-manually-install-alpine-linux-on-any-linux-distribution/
- https://wiki.gentoo.org/wiki/OpenRC_to_systemd_Cheatsheet

Overall, if you have a system which can run Debian, then it should be able to run Alpine without issues.
The one tricky thing with alpine linux is that the image you can download generaly need a few tweeks using chroot to be functional.

## Image setup

```bash
cd /media/rawrr/rootfs
sudo rm -rf *
sudo tar xpvf /media/data2/download/alpine-minirootfs-3.20.1-riscv64.tar.gz --xattrs-include='*.*' --numeric-owner
Expand All @@ -15,18 +26,22 @@ rc-update add loadkeys boot
rc-update add chronyd boot

apk add xf86-video-fbdev xterm
```

setup-keymap ch fr
## Scrap commands

```bash
setup-keymap ch fr
XKBMODEL="pc105"
XKBLAYOUT="ch"
XKBVARIANT="fr"
XKBOPTIONS=""

mount -o remount,rw /

kbd-bkeymaps

loadkeys ch-fr

apk add chocolate-doom --repository=https://dl-cdn.alpinelinux.org/alpine/edge/testing

```
5 changes: 5 additions & 0 deletions doc/litex/buildroot/README.md
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This readme document (from scratch) how to generate all the images to run buildroot Litex + VexiiRiscv.

The hardware requirements are to have :
- RV32IMA CPU
- Some RAM (64 MB)
- SDCARD support

## Setup environnement variables

```shell
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5 changes: 5 additions & 0 deletions doc/litex/debian/README.md
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This readme document (from scratch) how to generate all the images to run debian Litex + VexiiRiscv.

The hardware requirements are to have :
- RV64IMAFDC CPU
- A good amount of RAM (128 MB)
- SDCARD support

## Setup environnement variables

```shell
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2 changes: 1 addition & 1 deletion ext/NaxSoftware
2 changes: 1 addition & 1 deletion ext/SpinalHDL
Submodule SpinalHDL updated 47 files
+0 −2 build.sbt
+1 −1 core/src/main/scala/spinal/core/ClockDomain.scala
+13 −7 core/src/main/scala/spinal/core/Mem.scala
+12 −7 core/src/main/scala/spinal/core/MemBlackBox.scala
+2 −1 core/src/main/scala/spinal/core/Misc.scala
+1 −1 core/src/main/scala/spinal/core/ScopeProperty.scala
+12 −0 core/src/main/scala/spinal/core/Vec.scala
+2 −0 core/src/main/scala/spinal/core/fiber/Misc.scala
+1 −2 core/src/main/scala/spinal/core/internals/ComponentEmitter.scala
+13 −11 core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala
+6 −9 core/src/main/scala/spinal/core/internals/ComponentEmitterVhdl.scala
+143 −23 core/src/main/scala/spinal/core/internals/Phase.scala
+3 −2 core/src/main/scala/spinal/core/internals/Statement.scala
+4 −0 core/src/main/scala/spinal/core/sim/package.scala
+2 −0 lib/src/main/scala/spinal/lib/CrossClock.scala
+0 −3 lib/src/main/scala/spinal/lib/Mem.scala
+12 −8 lib/src/main/scala/spinal/lib/Stream.scala
+42 −13 lib/src/main/scala/spinal/lib/Utils.scala
+6 −7 lib/src/main/scala/spinal/lib/bus/amba3/apb/APB3.scala
+2 −2 lib/src/main/scala/spinal/lib/bus/amba4/axi/Axi4ToTilelink.scala
+2 −2 lib/src/main/scala/spinal/lib/bus/bmb/Bmb.scala
+37 −3 lib/src/main/scala/spinal/lib/bus/bmb/BmbDecoder.scala
+1 −1 lib/src/main/scala/spinal/lib/bus/misc/BusSlaveFactory.scala
+58 −46 lib/src/main/scala/spinal/lib/bus/regif/BusIf.scala
+1 −1 lib/src/main/scala/spinal/lib/bus/regif/BusInterface.scala
+32 −7 lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala
+2 −2 lib/src/main/scala/spinal/lib/com/usb/phy/UsbHubLsFs.scala
+3 −2 lib/src/main/scala/spinal/lib/cpu/riscv/debug/DebugModuleFiber.scala
+3 −2 lib/src/main/scala/spinal/lib/cpu/riscv/debug/DebugTransportModuleJtag.scala
+221 −0 lib/src/main/scala/spinal/lib/eda/TimingExtractor.scala
+7 −1 lib/src/main/scala/spinal/lib/misc/plugin/Host.scala
+0 −631 lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala
+0 −108 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022AbstractionDefinitionGenerator.scala
+0 −53 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022BusDefinitionGenerator.scala
+0 −262 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022ComponentGenerator.scala
+0 −55 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022DesignConfigXMLGenerator.scala
+0 −422 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022DesignXMLGenerator.scala
+0 −206 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACT2022LogicalPart.scala
+0 −43 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACTGenerator.scala
+0 −427 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACTVivadoBusReference.scala
+0 −360 lib/src/main/scala/spinal/lib/tools/IPXACTGenerator/IPXACTVivadoComponentGenerator.scala
+95 −0 tester/src/test/scala/spinal/core/Apb3ConnectionTester.scala
+1 −0 tester/src/test/scala/spinal/lib/bus/regif/RegIfBasicAccessTester.scala
+29 −0 tester/src/test/scala/spinal/lib/bus/regif/RegIfDefaultErrorStateTester.scala
+55 −38 tester/src/test/scala/spinal/lib/bus/tilelink/CacheTester.scala
+0 −85 tester/src/test/scala/spinal/lib/tools/HDElkDiagramGenTester.scala
+0 −114 tester/src/test/scala/spinal/lib/tools/IPXACTGeneratorDemo.scala
2 changes: 1 addition & 1 deletion ext/riscv-isa-sim
2 changes: 1 addition & 1 deletion ext/rvls
Submodule rvls updated 2 files
+11 −11 README.md
+3 −4 src/hart.cpp
224 changes: 0 additions & 224 deletions src/main/scala/spinal/core/MultiDataRaw.scala

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