Fix FPGA build; add to build and test

We don't do the verilator build since that requires additional tools to
be installed.

.github/workflows/build-test.yml

@@ -119,6 +119,13 @@ jobs:
             cargo build -p $proj --locked --no-default-features --features rustcrypto
           done
 
+      - name: Build hw-model with fpga_realtime, itrng, coverage
+        run: |
+          for feature in fpga_realtime itrng coverage; do
+            echo "Building with $feature"
+            cargo build --locked --features $feature
+          done
+
       # Clippy needs to build crates as part of the check, so do it after the
       # build.
       - name: Clippy lint check
@@ -167,8 +174,8 @@ jobs:
 
       - name: ROM Makefile
         run: |
-          (cd rom/dev && make run)         
-         
+          (cd rom/dev && make run)
+
       - name: Caliptra HW-Model C Binding Smoke Test
         run: |
           git submodule update --init
@@ -180,4 +187,3 @@ jobs:
       - name: DPE Verification Tests
         run: |
           (cd test/dpe_verification && make run)
-          

hw-model/src/bin/fpga_realtime_mbox_pauser.rs

@@ -71,25 +71,25 @@ fn main() {
         // Set up the PAUSER as valid for the mailbox (using index 0)
         model
             .soc_ifc()
-            .cptra_mbox_valid_pauser()
+            .cptra_mbox_valid_axi_user()
             .at(0)
             .write(|_| 0x1);
         model
             .soc_ifc()
-            .cptra_mbox_pauser_lock()
+            .cptra_mbox_axi_user_lock()
             .at(0)
             .write(|w| w.lock(true));
 
         // Set the PAUSER to something invalid
-        model.set_apb_pauser(0x2);
+        model.set_axi_user(0x2);
 
         // The accesses below trigger sigbus
         assert!(!model.soc_mbox().lock().read().lock());
         // Should continue to read 0 because the reads are being blocked by valid PAUSER
         assert!(!model.soc_mbox().lock().read().lock());
 
         // Set the PAUSER back to valid
-        model.set_apb_pauser(0x1);
+        model.set_axi_user(0x1);
 
         // Should read 0 the first time still for lock available
         assert!(!model.soc_mbox().lock().read().lock());

hw-model/src/model_fpga_realtime.rs

@@ -529,7 +529,7 @@ impl HwModel for ModelFpgaRealtime {
         }
     }
 
-    fn put_firmware_in_rri(&mut self, firmware: &[u8]) -> Result<(), ModelError> {
+    fn put_firmware_in_rri(&mut self, _firmware: &[u8]) -> Result<(), ModelError> {
         todo!()
     }
 }