Verilog #23

vhda · 2014-04-11T23:07:12Z

Hi!

Please do not pull this in yet, I'm just looking for code review and feedback from you.

Thanks,
Vitor

fishman · 2014-04-14T14:21:57Z

@masatake can you take a look at this too by any chance?

fishman · 2014-04-14T18:27:32Z

also @vhda do you have a test for this by any chance?

vhda · 2014-04-14T19:26:15Z

No really. I've used some SV examples I found online during the development
of these updates.
I'm now reviewing ctags within my projects at work.
I'll create some test cases later (in fact, I already found an issue where
a `endif is being identified as a port).

On Mon, Apr 14, 2014 at 7:27 PM, Reza Jelveh [email protected]:

also @vhda https://github.com/vhda do you have a test for this by any
chance?

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masatake · 2014-04-17T01:18:34Z

I'll take a look.

2014-04-14 23:21 GMT+09:00 Reza Jelveh [email protected]:

@masatake https://github.com/masatake can you take a look at this too
by any chance?

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masatake · 2014-04-20T16:39:25Z

Hi, sorry to be late.
I did cherry-pick "96831e68eef9f627ac4b73e40f0babb6c478ed13".
About other patch, the knowledges for verilog and SystemVerilog are needed.
I need test cases to merge.
The problem is the test facility of ctags; it seems that the facility has not been maintained well.
I'm working on this area. Please, wait me for fixing the facility.

masatake · 2014-04-29T07:42:08Z

Hi, again.

I've fixed the test facility. I did much more.
Could you send a pull request https://github.com/masatake/ctags/tree/next.
I'll merge and the I send a pull request for ctags/fishman to Reza.
To fix the test facility to many changes are needed. Reza is busy now. So I decided to use masatake/ctags/tree/next for patch buffering:)

In addition I need example and expected output of ctags.
Based on your information I will extend the test facility more language oriented.
Thank you.

masatake · 2014-05-01T07:55:04Z

Related topic was discussed at:

http://sourceforge.net/p/ctags/support-requests/17/

masatake · 2014-05-01T15:37:15Z

Finally I introduced unit test facility in my next tree.
Could you read https://github.com/masatake/ctags/blob/next/Units/README
and write a test case?
I need testes for the unit test facility:)

vhda · 2014-05-02T09:40:59Z

I'll try to create some test cases during the weekend :)

On Thu, May 1, 2014 at 4:37 PM, Masatake YAMATO [email protected]:

Finally I introduced unit test facility in my next tree.
Could you read https://github.com/masatake/ctags/blob/next/Units/README
and write a test case?
I need testes for the unit test facility:)

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vhda · 2014-05-05T22:23:06Z

Please check my testcase branch.
There's nothing fancy there, as I did not have much free time this weekend.

masatake · 2014-05-07T02:20:04Z

Thank you for preparing test cases.

After applying all your patch to my next tree, I run tests and got a coredump.
By git-bisect I found your a885e73 introduces the coredump.
Could you take a look?

$ PATH=/usr/bin make -f testing.mak test
Testing tag inclusion...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/bug2888482.js
make: *** [test.include] Segmentation fault (core dumped)
$ gdb ctags --core ./core.4031
...
Core was generated by ./ctags -R -nu --c-kinds=+lpx --format=1 -o tags.test Test'. Program terminated with signal SIGSEGV, Segmentation fault. #0 0x0000000000425786 in findTag (name=0x193b990) at verilog.c:365 365 vStringCatS (endTokenName, VerilogKinds[currentContext->kind].name); warning: File "/home/yamato/var/ctags-github/.gdbinit" auto-loading has been declined by yourauto-load safe-path' set to "$debugdir:$datadir/auto-load:/usr/bin/mono-gdb.py".
(gdb) p File.source.name.buffer
$1 = 0x193b8c0 "Test/bug2747828.v"
(gdb) where
#0 0x0000000000425786 in findTag (name=0x193b990) at verilog.c:365
#1 findVerilogTags () at verilog.c:435
#2 0x000000000041bc10 in createTagsForFile (passCount=, language=40, fileName=0x18e6810 "Test/bug2747828.v") at parse.c:617
#3 createTagsWithFallback (language=40, fileName=0x18e6810 "Test/bug2747828.v") at parse.c:640
#4 parseFile (fileName=fileName@entry=0x18e6810 "Test/bug2747828.v") at parse.c:677
#5 0x0000000000414c85 in createTagsForEntry (entryName=0x18e6810 "Test/bug2747828.v") at main.c:303
#6 0x0000000000414b5a in recurseUsingOpendir (dirName=0x7ffffecbc3bf "Test") at main.c:161
#7 recurseIntoDirectory (dirName=0x7ffffecbc3bf "Test") at main.c:258
#8 0x0000000000414ce0 in createTagsForEntry (entryName=0x7ffffecbc3bf "Test") at main.c:299
#9 0x0000000000402ab0 in createTagsForArgs (args=0x18b2120) at main.c:348
#10 makeTags (args=0x18b2120) at main.c:494
#11 main (argc=, argv=) at main.c:562
(gdb)

vhda · 2014-05-07T15:49:20Z

Hi Masatake,

I'm unable to replicate this segmentation fault on my side :(
Could you please share all the compilation steps you followed?

Thanks!

On Wed, May 7, 2014 at 3:20 AM, Masatake YAMATO [email protected]:

Thank you for preparing test cases.

After applying all your patch to my next tree, I run tests and got a
coredump.
By git-bisect I found your a885e73a885e73introduces the coredump.
Could you take a look?

$ PATH=/usr/bin make -f testing.mak test

Testing tag inclusion...ctags.ref: Warning: ignoring null tag in
Test/1878155.js
ctags: Warning: ignoring null tag in Test/bug2888482.js
make: *** [test.include] Segmentation fault (core dumped)
$ gdb ctags --core ./core.4031
...
Core was generated by ./ctags -R -nu --c-kinds=+lpx --format=1 -o
tags.test Test'.
Program terminated with signal SIGSEGV, Segmentation fault.
#0 0x0000000000425786 in findTag (name=0x193b990) at verilog.c:365
365 vStringCatS (endTokenName, VerilogKinds[currentContext->kind].name);
warning: File "/home/yamato/var/ctags-github/.gdbinit" auto-loading has
been declined by yourauto-load safe-path' set to
"$debugdir:$datadir/auto-load:/usr/bin/mono-gdb.py".
(gdb) p File.source.name.buffer
$1 = 0x193b8c0 "Test/bug2747828.v"
(gdb) where
#0 0x0000000000425786 in findTag (name=0x193b990) at verilog.c:365
#1 #1 findVerilogTags () at
verilog.c:435
#2 #2 0x000000000041bc10 in
createTagsForFile (passCount=, language=40, fileName=0x18e6810
"Test/bug2747828.v") at parse.c:617
#3 #3 createTagsWithFallback
(language=40, fileName=0x18e6810 "Test/bug2747828.v") at parse.c:640
#4 #4 parseFile
(fileName=fileName@entry=0x18e6810 "Test/bug2747828.v") at parse.c:677
#5 #5 0x0000000000414c85 in
createTagsForEntry (entryName=0x18e6810 "Test/bug2747828.v") at main.c:303
#6 #6 0x0000000000414b5a in
recurseUsingOpendir (dirName=0x7ffffecbc3bf "Test") at main.c:161
#7 #7 recurseIntoDirectory
(dirName=0x7ffffecbc3bf "Test") at main.c:258
#8 #8 0x0000000000414ce0 in
createTagsForEntry (entryName=0x7ffffecbc3bf "Test") at main.c:299
#9 #9 0x0000000000402ab0 in
createTagsForArgs (args=0x18b2120) at main.c:348
#10 #10 makeTags (args=0x18b2120)
at main.c:494
#11 #11 main (argc=, argv=) at
main.c:562
(gdb)

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masatake · 2014-05-08T03:00:08Z

I put the working tree for merging your patch to github. Could you see following command line session?

How to reproduce

$ cd /tmp
$ git clone https://github.com/masatake/ctags.git
$ cd ctags
$ git checkout tmp-review-SystemVerilog
$ autoconf
$ ./configure
$ make
$ cp ctags ctags.ref
$ make  -f testing.mak 
Testing tag inclusion...ctags.ref: Warning: ignoring null tag in Test/1878155.js
make: *** [test.include] Segmentation fault (core dumped)

My fix

This may be not enough.

$ cat tmp.patch 
diff --git a/verilog.c b/verilog.c
index 3783efc..4650479 100644
--- a/verilog.c
+++ b/verilog.c
@@ -496,6 +496,7 @@ static void findVerilogTags (void)
        }
    }
    deleteToken (currentContext);
+   currentContext = NULL;
 }

 extern parserDefinition* VerilogParser (void)

Re run the test

Unit test reports unexpected output.

$ patch < tmp.patch
$ make
$ cp ctags ctags.ref
$ make  -f testing.mak
Testing tag inclusion...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing extension fields...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing extra tags...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing line directives...Passed
Testing TAGS output...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
No Eiffel library source found for testing
No Linux kernel source found for testing
Testing Units/cpp-type-alias-with-using-keyword...Passed
Testing Units/c-sample...Passed
Testing Units/verilog-2001...FAILED: differences left in Units/verilog-2001.d/DIFF
Testing Units/verilog-basic...FAILED: differences left in Units/verilog-basic.d/DIFF
$ head Units/verilog-2001.d/DIFF
--- Units/verilog-2001.d/EXPECTED   2014-05-08 11:52:24.538887360 +0900
+++ Units/verilog-2001.d/OUTPUT 2014-05-08 11:52:24.536887337 +0900
@@ -2,11 +2,11 @@
-PARAM  Units/verilog-2001.d/input.v    /^parameter PARAM = 1;$/;"  c
-a  Units/verilog-2001.d/input.v    /^    input wire a,$/;" p
-add    Units/verilog-2001.d/input.v    /^task add ($/;"    t
-b  Units/verilog-2001.d/input.v    /^    b,c,$/;"  p
-c  Units/verilog-2001.d/input.v    /^    b,c,$/;"  p
-d  Units/verilog-2001.d/input.v    /^    d ,$/;"   p
-e  Units/verilog-2001.d/input.v    /^    output wire e ,$/;"   p

masatake · 2014-05-29T18:12:39Z

vhda, How do you do?

The next branch of mine is merged into deploy branch of fishiman. So you can use the deploy branch of fishiman as base.

vhda · 2014-05-29T18:51:30Z

sorry, I still did not have time to review this. I'll try to look into it
tonight
On 29 May 2014 19:12, "Masatake YAMATO" [email protected] wrote:

vhda, How do you do?

The next branch of mine is merged into deploy branch of fishiman. So you
can use the deploy branch of fishiman as base.

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#23 (comment).

vhda · 2014-05-30T00:43:04Z

Hi Masatake,

Hope everything is ok with you :)

I've reviewed the code and I think the NULL assignment you added is the only one that is needed. Thank you for help spotting this issue and for the suggested fix.

As you requested, I have rebased my work over fishman/deploy. The following branches are currently available:

testcase - Contains only the two simple verilog testcases I created.
verilog - Updates to the verilog parser.
systemverilog - Extension of the verilog parser to support SystemVerilog.

In my opinion the first two are ready for merge, so I'll go ahead and create the respective pull requests.

Starting from version 2001, the Verilog standard allows module declaration in the following format: module module_name ( input wire a, output reg b ); This patch adds a check to confirm if the name of the port is not a keyword, guaranteeing that the port net type is not added as a port by mistake. Note: when using this format only the port declaration is listed with the assumption that the respective net type is not important. Although this concept true in my workflow, this might not be so in all situations and is open to further discussion.

Add tokenInfo structure and required helper functions to implement a push/pop stack containing the current context of the tags being found.

fishman · 2014-05-30T01:12:57Z

it looks good to me though.

acked from me

masatake · 2014-05-30T14:55:11Z

Hi, vhda.

I'm confused because you open multiple pull requests.
As far as reading #33 of pull requests you want more comprehensive
discussion about SystemVerilog and Verilog with experts before merging.

Yes, I love your approach. However, you have to be the coordinator of
discussion because fishman and I don't know well about SystemVerilog and Verilog.

Please, tell me the commit ids of your changes which you want us to pull now.
I guess c05c957 01acca6 94d3294 1730980 are ready for merge. However, if
you think more discussions are needed, tell me. I'll suspend pulling.
Tell me the commit ids in this pull request thread.
If you are interested in more comprehensive discussion, could you join the discussion of Draft text for announcement #30?
ctags-devel may be good place to find people who are interested in SystemVerilog ctags support. We have a plane to submit an article which declares we are working on reactivating
ctags development at https://github.com/fishman/ctags. Once submitting the article, it becomes easier for you to invite people at ctags-devel list to here.

vhda · 2014-06-02T11:31:14Z

Hi Masatake,

I guess I should read some documentation regarding github development flows. I was trying to mimic what I've done in the past by email with git format-patch, but I can see I was not very successful :)

From what I can see the all the commit ids are already associated with this pull request, so you can go along and pull the for commit ids you mentioned.
Ok, let's do this. I've tried to get Vikram's contact information through Sourceforge, but wasn't very successful.

Vitor

masatake · 2014-06-04T13:30:56Z

Maybe my English is wrong. Sorry.

Let's forget the work flow on github here. I don't know well, too:-P

I make my question simpler.

Do you want me to merge your c05c957 01acca6 94d3294 1730980 to fishiman tree now?
Or more discussion is needed before merging?

vhda · 2014-06-04T13:53:00Z

Merge them! :D

On Wed, Jun 4, 2014 at 2:30 PM, Masatake YAMATO [email protected]
wrote:

Maybe my English is wrong. Sorry.

Let's forget the work flow on github here. I don't know well, too:-P

I make my question simpler.

Do you want me to merge your c05c957
c05c957 01acca6
01acca6 94d3294
94d3294 1730980
1730980 to fishiman tree now?
Or more discussion is needed before merging?

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#23 (comment).

masatake · 2014-06-04T15:33:23Z

To avoid introduce unexpected modifications, I use cherry-pick. Could you look at fishman's deploy branch wheter your patches are merged expectedly? If they are, please close this thread.

Ok, let's do this. I've tried to get Vikram's contact information through Sourceforge, but wasn't very successful.

O.K. Let's try again after posting the ANNOUNCEMENT. I think we should be popular more.

Tests output:

$ PATH=/usr/bin make -f testing.mak
Testing tag inclusion...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing extension fields...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing extra tags...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing line directives...Passed
Testing TAGS output...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
No Eiffel library source found for testing
No Linux kernel source found for testing
Testing Units/cpp-type-alias-with-using-keyword...Passed
Testing Units/c-sample...Passed
Testing Units/verilog-2001...Passed
Testing Units/verilog-basic...Passed

Thanks.

vhda · 2014-06-04T15:51:09Z

Hi Masatake,

I've rebased my verilog branch on top of your commits and no unexpected
changes were detected.
But you should really have merged the branches instead... please do try to
do that next time.

Regarding the SF area, I've already updated issue #17 sharing my work and
fishman's repository in order to get more feedback on my changes.

Thanks,
Vitor

On Wed, Jun 4, 2014 at 4:33 PM, Masatake YAMATO [email protected]
wrote:

To avoid introduce unexpected modifications, I use cherry-pick. Could you
look at fishman's deploy branch wheter your patches are merged expectedly?
If they are, please close this thread.

Ok, let's do this. I've tried to get Vikram's contact information through
Sourceforge, but wasn't very successful.

O.K. Let's try again after posting the ANNOUNCEMENT. I think we should be
popular more.

Tests output:

$ PATH=/usr/bin make -f testing.mak
Testing tag inclusion...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing extension fields...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing extra tags...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
Testing line directives...Passed
Testing TAGS output...ctags.ref: Warning: ignoring null tag in Test/1878155.js
ctags: Warning: ignoring null tag in Test/1878155.js
Passed
No Eiffel library source found for testing
No Linux kernel source found for testing
Testing Units/cpp-type-alias-with-using-keyword...Passed
Testing Units/c-sample...Passed
Testing Units/verilog-2001...Passed
Testing Units/verilog-basic...Passed

Thanks.

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#23 (comment).

masatake · 2014-06-04T17:20:05Z

I'm sorry. Now I understand I should just merge.
I think we can use #33 for the rest of discussion.

Add ‘ifndef … endif’ guard around thread locking macros

6c289b79 Merge pull request universal-ctags#23 from masatake/github-issue-21 8536bc8e tagsOpen: propagate errno from readTagLineRaw to tagsOpen instead of calling perror a526cc93 Close FILE when failing to initialize tagFile git-subtree-dir: libreadtags git-subtree-split: 6c289b793ef6a06b90f288c48be869f1d56826dd

vhda added 2 commits May 30, 2014 01:07

verilog: Add basic unit test case

c05c957

verilog: Add test for 2001 port declaration format

01acca6

vhda closed this May 30, 2014

vhda added 2 commits May 30, 2014 01:46

verilog: Add scope information extraction

1730980

Add tokenInfo structure and required helper functions to implement a push/pop stack containing the current context of the tags being found.

fishman reopened this May 30, 2014

masatake mentioned this pull request Jun 4, 2014

Simple Verilog test cases #31

Closed

Merge remote-tracking branch 'fishman/deploy' into verilog

6f830b5

masatake closed this Jun 4, 2014

masatake pushed a commit to masatake/ctags that referenced this pull request Mar 12, 2020

Merge pull request universal-ctags#23 from textmate/master

754f936

Add ‘ifndef … endif’ guard around thread locking macros

nachose mentioned this pull request Sep 1, 2022

Rake: crash and core dump. #3474

Closed

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Verilog #23

Verilog #23

vhda commented Apr 11, 2014

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Verilog #23

Verilog #23

Conversation

vhda commented Apr 11, 2014

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vhda commented Apr 14, 2014

masatake commented Apr 17, 2014

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vhda commented May 7, 2014

masatake commented May 8, 2014

How to reproduce

My fix

Re run the test

masatake commented May 29, 2014

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